2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/bootmem.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/pci.h>
35 #include <linux/msi.h>
36 #include <linux/htirq.h>
37 #include <linux/freezer.h>
38 #include <linux/kthread.h>
39 #include <linux/jiffies.h> /* time_after() */
44 #include <asm/timer.h>
45 #include <asm/i8259.h>
47 #include <asm/msidef.h>
48 #include <asm/hypertransport.h>
49 #include <asm/setup.h>
51 #include <mach_apic.h>
52 #include <mach_apicdef.h>
54 #define __apicdebuginit(type) static type __init
56 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
57 atomic_t irq_mis_count
;
59 /* Where if anywhere is the i8259 connect in external int mode */
60 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
62 static DEFINE_SPINLOCK(ioapic_lock
);
63 DEFINE_SPINLOCK(vector_lock
);
65 int timer_through_8259 __initdata
;
68 * Is the SiS APIC rmw bug present ?
69 * -1 = don't know, 0 = no, 1 = yes
71 int sis_apic_bug
= -1;
75 * # of IRQ routing registers
77 int nr_ioapic_registers
[MAX_IO_APICS
];
79 /* I/O APIC entries */
80 struct mp_config_ioapic mp_ioapics
[MAX_IO_APICS
];
83 /* MP IRQ source entries */
84 struct mp_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
86 /* # of MP IRQ source entries */
89 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
90 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
93 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
95 static int disable_timer_pin_1 __initdata
;
98 * Rough estimation of how many shared IRQs there are, can
104 * This is performance-critical, we want to do it O(1)
106 * the indexing order of this array favors 1:1 mappings
107 * between pins and IRQs.
110 static struct irq_pin_list
{
114 DEFINE_DYN_ARRAY(irq_2_pin
, sizeof(struct irq_pin_list
), pin_map_size
, 16, NULL
);
118 unsigned int unused
[3];
122 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
124 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
125 + (mp_ioapics
[idx
].mp_apicaddr
& ~PAGE_MASK
);
128 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
130 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
131 writel(reg
, &io_apic
->index
);
132 return readl(&io_apic
->data
);
135 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
137 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
138 writel(reg
, &io_apic
->index
);
139 writel(value
, &io_apic
->data
);
143 * Re-write a value: to be used for read-modify-write
144 * cycles where the read already set up the index register.
146 * Older SiS APIC requires we rewrite the index register
148 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
150 volatile struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
152 writel(reg
, &io_apic
->index
);
153 writel(value
, &io_apic
->data
);
157 struct { u32 w1
, w2
; };
158 struct IO_APIC_route_entry entry
;
161 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
163 union entry_union eu
;
165 spin_lock_irqsave(&ioapic_lock
, flags
);
166 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
167 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
168 spin_unlock_irqrestore(&ioapic_lock
, flags
);
173 * When we write a new IO APIC routing entry, we need to write the high
174 * word first! If the mask bit in the low word is clear, we will enable
175 * the interrupt, and we need to make sure the entry is fully populated
176 * before that happens.
179 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
181 union entry_union eu
;
183 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
184 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
187 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
190 spin_lock_irqsave(&ioapic_lock
, flags
);
191 __ioapic_write_entry(apic
, pin
, e
);
192 spin_unlock_irqrestore(&ioapic_lock
, flags
);
196 * When we mask an IO APIC routing entry, we need to write the low
197 * word first, in order to set the mask bit before we change the
200 static void ioapic_mask_entry(int apic
, int pin
)
203 union entry_union eu
= { .entry
.mask
= 1 };
205 spin_lock_irqsave(&ioapic_lock
, flags
);
206 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
207 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
208 spin_unlock_irqrestore(&ioapic_lock
, flags
);
212 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
213 * shared ISA-space IRQs, so we have to support them. We are super
214 * fast in the common case, and fast for shared ISA-space IRQs.
216 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
218 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
221 entry
= irq_2_pin
+ entry
->next
;
223 if (entry
->pin
!= -1) {
224 entry
->next
= first_free_entry
;
225 entry
= irq_2_pin
+ entry
->next
;
226 if (++first_free_entry
>= pin_map_size
)
227 panic("io_apic.c: whoops");
234 * Reroute an IRQ to a different pin.
236 static void __init
replace_pin_at_irq(unsigned int irq
,
237 int oldapic
, int oldpin
,
238 int newapic
, int newpin
)
240 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
243 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
244 entry
->apic
= newapic
;
249 entry
= irq_2_pin
+ entry
->next
;
253 static void __modify_IO_APIC_irq(unsigned int irq
, unsigned long enable
, unsigned long disable
)
255 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
256 unsigned int pin
, reg
;
262 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
265 io_apic_modify(entry
->apic
, 0x10 + pin
*2, reg
);
268 entry
= irq_2_pin
+ entry
->next
;
273 static void __mask_IO_APIC_irq(unsigned int irq
)
275 __modify_IO_APIC_irq(irq
, IO_APIC_REDIR_MASKED
, 0);
279 static void __unmask_IO_APIC_irq(unsigned int irq
)
281 __modify_IO_APIC_irq(irq
, 0, IO_APIC_REDIR_MASKED
);
284 /* mask = 1, trigger = 0 */
285 static void __mask_and_edge_IO_APIC_irq(unsigned int irq
)
287 __modify_IO_APIC_irq(irq
, IO_APIC_REDIR_MASKED
,
288 IO_APIC_REDIR_LEVEL_TRIGGER
);
291 /* mask = 0, trigger = 1 */
292 static void __unmask_and_level_IO_APIC_irq(unsigned int irq
)
294 __modify_IO_APIC_irq(irq
, IO_APIC_REDIR_LEVEL_TRIGGER
,
295 IO_APIC_REDIR_MASKED
);
298 static void mask_IO_APIC_irq(unsigned int irq
)
302 spin_lock_irqsave(&ioapic_lock
, flags
);
303 __mask_IO_APIC_irq(irq
);
304 spin_unlock_irqrestore(&ioapic_lock
, flags
);
307 static void unmask_IO_APIC_irq(unsigned int irq
)
311 spin_lock_irqsave(&ioapic_lock
, flags
);
312 __unmask_IO_APIC_irq(irq
);
313 spin_unlock_irqrestore(&ioapic_lock
, flags
);
316 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
318 struct IO_APIC_route_entry entry
;
320 /* Check delivery_mode to be sure we're not clearing an SMI pin */
321 entry
= ioapic_read_entry(apic
, pin
);
322 if (entry
.delivery_mode
== dest_SMI
)
326 * Disable it in the IO-APIC irq-routing table:
328 ioapic_mask_entry(apic
, pin
);
331 static void clear_IO_APIC(void)
335 for (apic
= 0; apic
< nr_ioapics
; apic
++)
336 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
337 clear_IO_APIC_pin(apic
, pin
);
341 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t cpumask
)
345 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
346 unsigned int apicid_value
;
349 cpus_and(tmp
, cpumask
, cpu_online_map
);
353 cpus_and(cpumask
, tmp
, CPU_MASK_ALL
);
355 apicid_value
= cpu_mask_to_apicid(cpumask
);
356 /* Prepare to do the io_apic_write */
357 apicid_value
= apicid_value
<< 24;
358 spin_lock_irqsave(&ioapic_lock
, flags
);
363 io_apic_write(entry
->apic
, 0x10 + 1 + pin
*2, apicid_value
);
366 entry
= irq_2_pin
+ entry
->next
;
368 irq_desc
[irq
].affinity
= cpumask
;
369 spin_unlock_irqrestore(&ioapic_lock
, flags
);
372 #if defined(CONFIG_IRQBALANCE)
373 # include <asm/processor.h> /* kernel_thread() */
374 # include <linux/kernel_stat.h> /* kstat */
375 # include <linux/slab.h> /* kmalloc() */
376 # include <linux/timer.h>
378 #define IRQBALANCE_CHECK_ARCH -999
379 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
380 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
381 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
382 #define BALANCED_IRQ_LESS_DELTA (HZ)
384 static int irqbalance_disabled __read_mostly
= IRQBALANCE_CHECK_ARCH
;
385 static int physical_balance __read_mostly
;
386 static long balanced_irq_interval __read_mostly
= MAX_BALANCED_IRQ_INTERVAL
;
388 static struct irq_cpu_info
{
389 unsigned long *last_irq
;
390 unsigned long *irq_delta
;
392 } irq_cpu_data
[NR_CPUS
];
394 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
395 #define LAST_CPU_IRQ(cpu, irq) (irq_cpu_data[cpu].last_irq[irq])
396 #define IRQ_DELTA(cpu, irq) (irq_cpu_data[cpu].irq_delta[irq])
398 #define IDLE_ENOUGH(cpu,now) \
399 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
401 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
403 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
405 static cpumask_t balance_irq_affinity_init __initdata
= CPU_MASK_ALL
;
407 static cpumask_t
*balance_irq_affinity
;
410 static void __init
irq_affinity_init_work(void *data
)
412 struct dyn_array
*da
= data
;
415 struct balance_irq_affinity
*affinity
;
417 affinity
= *da
->name
;
419 for (i
= 0; i
< *da
->nr
; i
++)
420 memcpy(&affinity
[i
], &balance_irq_affinity_init
,
421 sizeof(struct balance_irq_affinity
));
425 DEFINE_DYN_ARRAY(balance_irq_affinity
, sizeof(struct balance_irq_affinity
), nr_irqs
, PAGE_SIZE
, irq_affinity_init_work
);
428 void set_balance_irq_affinity(unsigned int irq
, cpumask_t mask
)
430 balance_irq_affinity
[irq
] = mask
;
433 static unsigned long move(int curr_cpu
, cpumask_t allowed_mask
,
434 unsigned long now
, int direction
)
442 if (unlikely(cpu
== curr_cpu
))
445 if (direction
== 1) {
454 } while (!cpu_online(cpu
) || !IRQ_ALLOWED(cpu
, allowed_mask
) ||
455 (search_idle
&& !IDLE_ENOUGH(cpu
, now
)));
460 static inline void balance_irq(int cpu
, int irq
)
462 unsigned long now
= jiffies
;
463 cpumask_t allowed_mask
;
464 unsigned int new_cpu
;
466 if (irqbalance_disabled
)
469 cpus_and(allowed_mask
, cpu_online_map
, balance_irq_affinity
[irq
]);
470 new_cpu
= move(cpu
, allowed_mask
, now
, 1);
472 set_pending_irq(irq
, cpumask_of_cpu(new_cpu
));
475 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold
)
479 for_each_online_cpu(i
) {
480 for (j
= 0; j
< nr_irqs
; j
++) {
481 if (!irq_desc
[j
].action
)
483 /* Is it a significant load ? */
484 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i
), j
) <
485 useful_load_threshold
)
490 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
491 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
495 static void do_irq_balance(void)
498 unsigned long max_cpu_irq
= 0, min_cpu_irq
= (~0);
499 unsigned long move_this_load
= 0;
500 int max_loaded
= 0, min_loaded
= 0;
502 unsigned long useful_load_threshold
= balanced_irq_interval
+ 10;
504 int tmp_loaded
, first_attempt
= 1;
505 unsigned long tmp_cpu_irq
;
506 unsigned long imbalance
= 0;
507 cpumask_t allowed_mask
, target_cpu_mask
, tmp
;
509 for_each_possible_cpu(i
) {
514 package_index
= CPU_TO_PACKAGEINDEX(i
);
515 for (j
= 0; j
< nr_irqs
; j
++) {
516 unsigned long value_now
, delta
;
517 /* Is this an active IRQ or balancing disabled ? */
518 if (!irq_desc
[j
].action
|| irq_balancing_disabled(j
))
520 if (package_index
== i
)
521 IRQ_DELTA(package_index
, j
) = 0;
522 /* Determine the total count per processor per IRQ */
523 value_now
= (unsigned long) kstat_cpu(i
).irqs
[j
];
525 /* Determine the activity per processor per IRQ */
526 delta
= value_now
- LAST_CPU_IRQ(i
, j
);
528 /* Update last_cpu_irq[][] for the next time */
529 LAST_CPU_IRQ(i
, j
) = value_now
;
531 /* Ignore IRQs whose rate is less than the clock */
532 if (delta
< useful_load_threshold
)
534 /* update the load for the processor or package total */
535 IRQ_DELTA(package_index
, j
) += delta
;
537 /* Keep track of the higher numbered sibling as well */
538 if (i
!= package_index
)
541 * We have sibling A and sibling B in the package
543 * cpu_irq[A] = load for cpu A + load for cpu B
544 * cpu_irq[B] = load for cpu B
546 CPU_IRQ(package_index
) += delta
;
549 /* Find the least loaded processor package */
550 for_each_online_cpu(i
) {
551 if (i
!= CPU_TO_PACKAGEINDEX(i
))
553 if (min_cpu_irq
> CPU_IRQ(i
)) {
554 min_cpu_irq
= CPU_IRQ(i
);
558 max_cpu_irq
= ULONG_MAX
;
562 * Look for heaviest loaded processor.
563 * We may come back to get the next heaviest loaded processor.
564 * Skip processors with trivial loads.
568 for_each_online_cpu(i
) {
569 if (i
!= CPU_TO_PACKAGEINDEX(i
))
571 if (max_cpu_irq
<= CPU_IRQ(i
))
573 if (tmp_cpu_irq
< CPU_IRQ(i
)) {
574 tmp_cpu_irq
= CPU_IRQ(i
);
579 if (tmp_loaded
== -1) {
581 * In the case of small number of heavy interrupt sources,
582 * loading some of the cpus too much. We use Ingo's original
583 * approach to rotate them around.
585 if (!first_attempt
&& imbalance
>= useful_load_threshold
) {
586 rotate_irqs_among_cpus(useful_load_threshold
);
589 goto not_worth_the_effort
;
592 first_attempt
= 0; /* heaviest search */
593 max_cpu_irq
= tmp_cpu_irq
; /* load */
594 max_loaded
= tmp_loaded
; /* processor */
595 imbalance
= (max_cpu_irq
- min_cpu_irq
) / 2;
598 * if imbalance is less than approx 10% of max load, then
599 * observe diminishing returns action. - quit
601 if (imbalance
< (max_cpu_irq
>> 3))
602 goto not_worth_the_effort
;
605 /* if we select an IRQ to move that can't go where we want, then
606 * see if there is another one to try.
610 for (j
= 0; j
< nr_irqs
; j
++) {
611 /* Is this an active IRQ? */
612 if (!irq_desc
[j
].action
)
614 if (imbalance
<= IRQ_DELTA(max_loaded
, j
))
616 /* Try to find the IRQ that is closest to the imbalance
617 * without going over.
619 if (move_this_load
< IRQ_DELTA(max_loaded
, j
)) {
620 move_this_load
= IRQ_DELTA(max_loaded
, j
);
624 if (selected_irq
== -1)
627 imbalance
= move_this_load
;
629 /* For physical_balance case, we accumulated both load
630 * values in the one of the siblings cpu_irq[],
631 * to use the same code for physical and logical processors
632 * as much as possible.
634 * NOTE: the cpu_irq[] array holds the sum of the load for
635 * sibling A and sibling B in the slot for the lowest numbered
636 * sibling (A), _AND_ the load for sibling B in the slot for
637 * the higher numbered sibling.
639 * We seek the least loaded sibling by making the comparison
642 load
= CPU_IRQ(min_loaded
) >> 1;
643 for_each_cpu_mask(j
, per_cpu(cpu_sibling_map
, min_loaded
)) {
644 if (load
> CPU_IRQ(j
)) {
645 /* This won't change cpu_sibling_map[min_loaded] */
651 cpus_and(allowed_mask
,
653 balance_irq_affinity
[selected_irq
]);
654 target_cpu_mask
= cpumask_of_cpu(min_loaded
);
655 cpus_and(tmp
, target_cpu_mask
, allowed_mask
);
657 if (!cpus_empty(tmp
)) {
658 /* mark for change destination */
659 set_pending_irq(selected_irq
, cpumask_of_cpu(min_loaded
));
661 /* Since we made a change, come back sooner to
662 * check for more variation.
664 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
665 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
670 not_worth_the_effort
:
672 * if we did not find an IRQ to move, then adjust the time interval
675 balanced_irq_interval
= min((long)MAX_BALANCED_IRQ_INTERVAL
,
676 balanced_irq_interval
+ BALANCED_IRQ_MORE_DELTA
);
680 static int balanced_irq(void *unused
)
683 unsigned long prev_balance_time
= jiffies
;
684 long time_remaining
= balanced_irq_interval
;
686 /* push everything to CPU 0 to give us a starting point. */
687 for (i
= 0 ; i
< nr_irqs
; i
++) {
688 irq_desc
[i
].pending_mask
= cpumask_of_cpu(0);
689 set_pending_irq(i
, cpumask_of_cpu(0));
694 time_remaining
= schedule_timeout_interruptible(time_remaining
);
696 if (time_after(jiffies
,
697 prev_balance_time
+balanced_irq_interval
)) {
700 prev_balance_time
= jiffies
;
701 time_remaining
= balanced_irq_interval
;
708 static int __init
balanced_irq_init(void)
711 struct cpuinfo_x86
*c
;
714 cpus_shift_right(tmp
, cpu_online_map
, 2);
716 /* When not overwritten by the command line ask subarchitecture. */
717 if (irqbalance_disabled
== IRQBALANCE_CHECK_ARCH
)
718 irqbalance_disabled
= NO_BALANCE_IRQ
;
719 if (irqbalance_disabled
)
722 /* disable irqbalance completely if there is only one processor online */
723 if (num_online_cpus() < 2) {
724 irqbalance_disabled
= 1;
728 * Enable physical balance only if more than 1 physical processor
731 if (smp_num_siblings
> 1 && !cpus_empty(tmp
))
732 physical_balance
= 1;
734 for_each_online_cpu(i
) {
735 irq_cpu_data
[i
].irq_delta
= kzalloc(sizeof(unsigned long) * nr_irqs
, GFP_KERNEL
);
736 irq_cpu_data
[i
].last_irq
= kzalloc(sizeof(unsigned long) * nr_irqs
, GFP_KERNEL
);
737 if (irq_cpu_data
[i
].irq_delta
== NULL
|| irq_cpu_data
[i
].last_irq
== NULL
) {
738 printk(KERN_ERR
"balanced_irq_init: out of memory");
743 printk(KERN_INFO
"Starting balanced_irq\n");
744 if (!IS_ERR(kthread_run(balanced_irq
, NULL
, "kirqd")))
746 printk(KERN_ERR
"balanced_irq_init: failed to spawn balanced_irq");
748 for_each_possible_cpu(i
) {
749 kfree(irq_cpu_data
[i
].irq_delta
);
750 irq_cpu_data
[i
].irq_delta
= NULL
;
751 kfree(irq_cpu_data
[i
].last_irq
);
752 irq_cpu_data
[i
].last_irq
= NULL
;
757 int __devinit
irqbalance_disable(char *str
)
759 irqbalance_disabled
= 1;
763 __setup("noirqbalance", irqbalance_disable
);
765 late_initcall(balanced_irq_init
);
766 #endif /* CONFIG_IRQBALANCE */
767 #endif /* CONFIG_SMP */
770 void send_IPI_self(int vector
)
777 apic_wait_icr_idle();
778 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
780 * Send the IPI. The write to APIC_ICR fires this off.
782 apic_write(APIC_ICR
, cfg
);
784 #endif /* !CONFIG_SMP */
788 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
789 * specific CPU-side IRQs.
793 static int pirq_entries
[MAX_PIRQS
];
794 static int pirqs_enabled
;
795 int skip_ioapic_setup
;
797 static int __init
ioapic_pirq_setup(char *str
)
800 int ints
[MAX_PIRQS
+1];
802 get_options(str
, ARRAY_SIZE(ints
), ints
);
804 for (i
= 0; i
< MAX_PIRQS
; i
++)
805 pirq_entries
[i
] = -1;
808 apic_printk(APIC_VERBOSE
, KERN_INFO
809 "PIRQ redirection, working around broken MP-BIOS.\n");
811 if (ints
[0] < MAX_PIRQS
)
814 for (i
= 0; i
< max
; i
++) {
815 apic_printk(APIC_VERBOSE
, KERN_DEBUG
816 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
818 * PIRQs are mapped upside down, usually.
820 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
825 __setup("pirq=", ioapic_pirq_setup
);
828 * Find the IRQ entry number of a certain pin.
830 static int find_irq_entry(int apic
, int pin
, int type
)
834 for (i
= 0; i
< mp_irq_entries
; i
++)
835 if (mp_irqs
[i
].mp_irqtype
== type
&&
836 (mp_irqs
[i
].mp_dstapic
== mp_ioapics
[apic
].mp_apicid
||
837 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
) &&
838 mp_irqs
[i
].mp_dstirq
== pin
)
845 * Find the pin to which IRQ[irq] (ISA) is connected
847 static int __init
find_isa_irq_pin(int irq
, int type
)
851 for (i
= 0; i
< mp_irq_entries
; i
++) {
852 int lbus
= mp_irqs
[i
].mp_srcbus
;
854 if (test_bit(lbus
, mp_bus_not_pci
) &&
855 (mp_irqs
[i
].mp_irqtype
== type
) &&
856 (mp_irqs
[i
].mp_srcbusirq
== irq
))
858 return mp_irqs
[i
].mp_dstirq
;
863 static int __init
find_isa_irq_apic(int irq
, int type
)
867 for (i
= 0; i
< mp_irq_entries
; i
++) {
868 int lbus
= mp_irqs
[i
].mp_srcbus
;
870 if (test_bit(lbus
, mp_bus_not_pci
) &&
871 (mp_irqs
[i
].mp_irqtype
== type
) &&
872 (mp_irqs
[i
].mp_srcbusirq
== irq
))
875 if (i
< mp_irq_entries
) {
877 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
878 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
)
887 * Find a specific PCI IRQ entry.
888 * Not an __init, possibly needed by modules
890 static int pin_2_irq(int idx
, int apic
, int pin
);
892 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
894 int apic
, i
, best_guess
= -1;
896 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, "
897 "slot:%d, pin:%d.\n", bus
, slot
, pin
);
898 if (test_bit(bus
, mp_bus_not_pci
)) {
899 printk(KERN_WARNING
"PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
902 for (i
= 0; i
< mp_irq_entries
; i
++) {
903 int lbus
= mp_irqs
[i
].mp_srcbus
;
905 for (apic
= 0; apic
< nr_ioapics
; apic
++)
906 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
||
907 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
)
910 if (!test_bit(lbus
, mp_bus_not_pci
) &&
911 !mp_irqs
[i
].mp_irqtype
&&
913 (slot
== ((mp_irqs
[i
].mp_srcbusirq
>> 2) & 0x1f))) {
914 int irq
= pin_2_irq(i
, apic
, mp_irqs
[i
].mp_dstirq
);
916 if (!(apic
|| IO_APIC_IRQ(irq
)))
919 if (pin
== (mp_irqs
[i
].mp_srcbusirq
& 3))
922 * Use the first all-but-pin matching entry as a
923 * best-guess fuzzy result for broken mptables.
931 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
934 * This function currently is only a helper for the i386 smp boot process where
935 * we need to reprogram the ioredtbls to cater for the cpus which have come online
936 * so mask in all cases should simply be TARGET_CPUS
939 void __init
setup_ioapic_dest(void)
941 int pin
, ioapic
, irq
, irq_entry
;
943 if (skip_ioapic_setup
== 1)
946 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
947 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
948 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
951 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
952 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
959 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
961 * EISA Edge/Level control register, ELCR
963 static int EISA_ELCR(unsigned int irq
)
966 unsigned int port
= 0x4d0 + (irq
>> 3);
967 return (inb(port
) >> (irq
& 7)) & 1;
969 apic_printk(APIC_VERBOSE
, KERN_INFO
970 "Broken MPtable reports ISA irq %d\n", irq
);
975 /* ISA interrupts are always polarity zero edge triggered,
976 * when listed as conforming in the MP table. */
978 #define default_ISA_trigger(idx) (0)
979 #define default_ISA_polarity(idx) (0)
981 /* EISA interrupts are always polarity zero and can be edge or level
982 * trigger depending on the ELCR value. If an interrupt is listed as
983 * EISA conforming in the MP table, that means its trigger type must
984 * be read in from the ELCR */
986 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
987 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
989 /* PCI interrupts are always polarity one level triggered,
990 * when listed as conforming in the MP table. */
992 #define default_PCI_trigger(idx) (1)
993 #define default_PCI_polarity(idx) (1)
995 /* MCA interrupts are always polarity zero level triggered,
996 * when listed as conforming in the MP table. */
998 #define default_MCA_trigger(idx) (1)
999 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
1001 static int MPBIOS_polarity(int idx
)
1003 int bus
= mp_irqs
[idx
].mp_srcbus
;
1007 * Determine IRQ line polarity (high active or low active):
1009 switch (mp_irqs
[idx
].mp_irqflag
& 3) {
1010 case 0: /* conforms, ie. bus-type dependent polarity */
1012 polarity
= test_bit(bus
, mp_bus_not_pci
)?
1013 default_ISA_polarity(idx
):
1014 default_PCI_polarity(idx
);
1017 case 1: /* high active */
1022 case 2: /* reserved */
1024 printk(KERN_WARNING
"broken BIOS!!\n");
1028 case 3: /* low active */
1033 default: /* invalid */
1035 printk(KERN_WARNING
"broken BIOS!!\n");
1043 static int MPBIOS_trigger(int idx
)
1045 int bus
= mp_irqs
[idx
].mp_srcbus
;
1049 * Determine IRQ trigger mode (edge or level sensitive):
1051 switch ((mp_irqs
[idx
].mp_irqflag
>>2) & 3) {
1052 case 0: /* conforms, ie. bus-type dependent */
1054 trigger
= test_bit(bus
, mp_bus_not_pci
)?
1055 default_ISA_trigger(idx
):
1056 default_PCI_trigger(idx
);
1057 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1058 switch (mp_bus_id_to_type
[bus
]) {
1059 case MP_BUS_ISA
: /* ISA pin */
1061 /* set before the switch */
1064 case MP_BUS_EISA
: /* EISA pin */
1066 trigger
= default_EISA_trigger(idx
);
1069 case MP_BUS_PCI
: /* PCI pin */
1071 /* set before the switch */
1074 case MP_BUS_MCA
: /* MCA pin */
1076 trigger
= default_MCA_trigger(idx
);
1081 printk(KERN_WARNING
"broken BIOS!!\n");
1094 case 2: /* reserved */
1096 printk(KERN_WARNING
"broken BIOS!!\n");
1105 default: /* invalid */
1107 printk(KERN_WARNING
"broken BIOS!!\n");
1115 static inline int irq_polarity(int idx
)
1117 return MPBIOS_polarity(idx
);
1120 static inline int irq_trigger(int idx
)
1122 return MPBIOS_trigger(idx
);
1125 static int pin_2_irq(int idx
, int apic
, int pin
)
1128 int bus
= mp_irqs
[idx
].mp_srcbus
;
1131 * Debugging check, we are in big trouble if this message pops up!
1133 if (mp_irqs
[idx
].mp_dstirq
!= pin
)
1134 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1136 if (test_bit(bus
, mp_bus_not_pci
))
1137 irq
= mp_irqs
[idx
].mp_srcbusirq
;
1140 * PCI IRQs are mapped in order
1144 irq
+= nr_ioapic_registers
[i
++];
1148 * For MPS mode, so far only needed by ES7000 platform
1150 if (ioapic_renumber_irq
)
1151 irq
= ioapic_renumber_irq(apic
, irq
);
1155 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1157 if ((pin
>= 16) && (pin
<= 23)) {
1158 if (pirq_entries
[pin
-16] != -1) {
1159 if (!pirq_entries
[pin
-16]) {
1160 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1161 "disabling PIRQ%d\n", pin
-16);
1163 irq
= pirq_entries
[pin
-16];
1164 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1165 "using PIRQ%d -> IRQ %d\n",
1173 static inline int IO_APIC_irq_trigger(int irq
)
1177 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1178 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1179 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1180 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1181 return irq_trigger(idx
);
1185 * nonexistent IRQs are edge default
1190 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1191 static u8 irq_vector_init_first __initdata
= FIRST_DEVICE_VECTOR
;
1192 static u8
*irq_vector
;
1194 static void __init
irq_vector_init_work(void *data
)
1196 struct dyn_array
*da
= data
;
1200 irq_vec
= *da
->name
;
1202 irq_vec
[0] = irq_vector_init_first
;
1205 DEFINE_DYN_ARRAY(irq_vector
, sizeof(u8
), nr_irqs
, PAGE_SIZE
, irq_vector_init_work
);
1207 static int __assign_irq_vector(int irq
)
1209 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
;
1212 BUG_ON((unsigned)irq
>= nr_irqs
);
1214 if (irq_vector
[irq
] > 0)
1215 return irq_vector
[irq
];
1217 vector
= current_vector
;
1218 offset
= current_offset
;
1221 if (vector
>= first_system_vector
) {
1222 offset
= (offset
+ 1) % 8;
1223 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1225 if (vector
== current_vector
)
1227 if (test_and_set_bit(vector
, used_vectors
))
1230 current_vector
= vector
;
1231 current_offset
= offset
;
1232 irq_vector
[irq
] = vector
;
1237 static int assign_irq_vector(int irq
)
1239 unsigned long flags
;
1242 spin_lock_irqsave(&vector_lock
, flags
);
1243 vector
= __assign_irq_vector(irq
);
1244 spin_unlock_irqrestore(&vector_lock
, flags
);
1249 static struct irq_chip ioapic_chip
;
1251 #define IOAPIC_AUTO -1
1252 #define IOAPIC_EDGE 0
1253 #define IOAPIC_LEVEL 1
1255 static void ioapic_register_intr(int irq
, int vector
, unsigned long trigger
)
1257 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1258 trigger
== IOAPIC_LEVEL
) {
1259 irq_desc
[irq
].status
|= IRQ_LEVEL
;
1260 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1261 handle_fasteoi_irq
, "fasteoi");
1263 irq_desc
[irq
].status
&= ~IRQ_LEVEL
;
1264 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1265 handle_edge_irq
, "edge");
1267 set_intr_gate(vector
, interrupt
[irq
]);
1270 static void __init
setup_IO_APIC_irqs(void)
1272 struct IO_APIC_route_entry entry
;
1273 int apic
, pin
, idx
, irq
, first_notcon
= 1, vector
;
1275 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1277 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1278 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1281 * add it to the IO-APIC irq-routing table:
1283 memset(&entry
, 0, sizeof(entry
));
1285 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1286 entry
.dest_mode
= INT_DEST_MODE
;
1287 entry
.mask
= 0; /* enable IRQ */
1288 entry
.dest
.logical
.logical_dest
=
1289 cpu_mask_to_apicid(TARGET_CPUS
);
1291 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1294 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1295 " IO-APIC (apicid-pin) %d-%d",
1296 mp_ioapics
[apic
].mp_apicid
,
1300 apic_printk(APIC_VERBOSE
, ", %d-%d",
1301 mp_ioapics
[apic
].mp_apicid
, pin
);
1305 if (!first_notcon
) {
1306 apic_printk(APIC_VERBOSE
, " not connected.\n");
1310 entry
.trigger
= irq_trigger(idx
);
1311 entry
.polarity
= irq_polarity(idx
);
1313 if (irq_trigger(idx
)) {
1318 irq
= pin_2_irq(idx
, apic
, pin
);
1320 * skip adding the timer int on secondary nodes, which causes
1321 * a small but painful rift in the time-space continuum
1323 if (multi_timer_check(apic
, irq
))
1326 add_pin_to_irq(irq
, apic
, pin
);
1328 if (!apic
&& !IO_APIC_IRQ(irq
))
1331 if (IO_APIC_IRQ(irq
)) {
1332 vector
= assign_irq_vector(irq
);
1333 entry
.vector
= vector
;
1334 ioapic_register_intr(irq
, vector
, IOAPIC_AUTO
);
1336 if (!apic
&& (irq
< 16))
1337 disable_8259A_irq(irq
);
1339 ioapic_write_entry(apic
, pin
, entry
);
1344 apic_printk(APIC_VERBOSE
, " not connected.\n");
1348 * Set up the timer pin, possibly with the 8259A-master behind.
1350 static void __init
setup_timer_IRQ0_pin(unsigned int apic
, unsigned int pin
,
1353 struct IO_APIC_route_entry entry
;
1355 memset(&entry
, 0, sizeof(entry
));
1358 * We use logical delivery to get the timer IRQ
1361 entry
.dest_mode
= INT_DEST_MODE
;
1362 entry
.mask
= 1; /* mask IRQ now */
1363 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1364 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1367 entry
.vector
= vector
;
1370 * The timer IRQ doesn't have to know that behind the
1371 * scene we may have a 8259A-master in AEOI mode ...
1373 ioapic_register_intr(0, vector
, IOAPIC_EDGE
);
1376 * Add it to the IO-APIC irq-routing table:
1378 ioapic_write_entry(apic
, pin
, entry
);
1382 __apicdebuginit(void) print_IO_APIC(void)
1385 union IO_APIC_reg_00 reg_00
;
1386 union IO_APIC_reg_01 reg_01
;
1387 union IO_APIC_reg_02 reg_02
;
1388 union IO_APIC_reg_03 reg_03
;
1389 unsigned long flags
;
1391 if (apic_verbosity
== APIC_QUIET
)
1394 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1395 for (i
= 0; i
< nr_ioapics
; i
++)
1396 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1397 mp_ioapics
[i
].mp_apicid
, nr_ioapic_registers
[i
]);
1400 * We are a bit conservative about what we expect. We have to
1401 * know about every hardware change ASAP.
1403 printk(KERN_INFO
"testing the IO APIC.......................\n");
1405 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1407 spin_lock_irqsave(&ioapic_lock
, flags
);
1408 reg_00
.raw
= io_apic_read(apic
, 0);
1409 reg_01
.raw
= io_apic_read(apic
, 1);
1410 if (reg_01
.bits
.version
>= 0x10)
1411 reg_02
.raw
= io_apic_read(apic
, 2);
1412 if (reg_01
.bits
.version
>= 0x20)
1413 reg_03
.raw
= io_apic_read(apic
, 3);
1414 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1416 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mp_apicid
);
1417 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1418 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1419 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1420 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1422 printk(KERN_DEBUG
".... register #01: %08X\n", reg_01
.raw
);
1423 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1425 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1426 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1429 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1430 * but the value of reg_02 is read as the previous read register
1431 * value, so ignore it if reg_02 == reg_01.
1433 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1434 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1435 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1439 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1440 * or reg_03, but the value of reg_0[23] is read as the previous read
1441 * register value, so ignore it if reg_03 == reg_0[12].
1443 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1444 reg_03
.raw
!= reg_01
.raw
) {
1445 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1446 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1449 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1451 printk(KERN_DEBUG
" NR Log Phy Mask Trig IRR Pol"
1452 " Stat Dest Deli Vect: \n");
1454 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1455 struct IO_APIC_route_entry entry
;
1457 entry
= ioapic_read_entry(apic
, i
);
1459 printk(KERN_DEBUG
" %02x %03X %02X ",
1461 entry
.dest
.logical
.logical_dest
,
1462 entry
.dest
.physical
.physical_dest
1465 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1470 entry
.delivery_status
,
1472 entry
.delivery_mode
,
1477 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1478 for (i
= 0; i
< nr_irqs
; i
++) {
1479 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
1482 printk(KERN_DEBUG
"IRQ%d ", i
);
1484 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1487 entry
= irq_2_pin
+ entry
->next
;
1492 printk(KERN_INFO
".................................... done.\n");
1497 __apicdebuginit(void) print_APIC_bitfield(int base
)
1502 if (apic_verbosity
== APIC_QUIET
)
1505 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1506 for (i
= 0; i
< 8; i
++) {
1507 v
= apic_read(base
+ i
*0x10);
1508 for (j
= 0; j
< 32; j
++) {
1518 __apicdebuginit(void) print_local_APIC(void *dummy
)
1520 unsigned int v
, ver
, maxlvt
;
1523 if (apic_verbosity
== APIC_QUIET
)
1526 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1527 smp_processor_id(), hard_smp_processor_id());
1528 v
= apic_read(APIC_ID
);
1529 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
,
1531 v
= apic_read(APIC_LVR
);
1532 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1533 ver
= GET_APIC_VERSION(v
);
1534 maxlvt
= lapic_get_maxlvt();
1536 v
= apic_read(APIC_TASKPRI
);
1537 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1539 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1540 v
= apic_read(APIC_ARBPRI
);
1541 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1542 v
& APIC_ARBPRI_MASK
);
1543 v
= apic_read(APIC_PROCPRI
);
1544 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1547 v
= apic_read(APIC_EOI
);
1548 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1549 v
= apic_read(APIC_RRR
);
1550 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1551 v
= apic_read(APIC_LDR
);
1552 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1553 v
= apic_read(APIC_DFR
);
1554 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1555 v
= apic_read(APIC_SPIV
);
1556 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1558 printk(KERN_DEBUG
"... APIC ISR field:\n");
1559 print_APIC_bitfield(APIC_ISR
);
1560 printk(KERN_DEBUG
"... APIC TMR field:\n");
1561 print_APIC_bitfield(APIC_TMR
);
1562 printk(KERN_DEBUG
"... APIC IRR field:\n");
1563 print_APIC_bitfield(APIC_IRR
);
1565 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1566 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1567 apic_write(APIC_ESR
, 0);
1568 v
= apic_read(APIC_ESR
);
1569 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1572 icr
= apic_icr_read();
1573 printk(KERN_DEBUG
"... APIC ICR: %08x\n", icr
);
1574 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", icr
>> 32);
1576 v
= apic_read(APIC_LVTT
);
1577 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1579 if (maxlvt
> 3) { /* PC is LVT#4. */
1580 v
= apic_read(APIC_LVTPC
);
1581 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1583 v
= apic_read(APIC_LVT0
);
1584 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1585 v
= apic_read(APIC_LVT1
);
1586 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1588 if (maxlvt
> 2) { /* ERR is LVT#3. */
1589 v
= apic_read(APIC_LVTERR
);
1590 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1593 v
= apic_read(APIC_TMICT
);
1594 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1595 v
= apic_read(APIC_TMCCT
);
1596 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1597 v
= apic_read(APIC_TDCR
);
1598 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1602 __apicdebuginit(void) print_all_local_APICs(void)
1604 on_each_cpu(print_local_APIC
, NULL
, 1);
1607 __apicdebuginit(void) print_PIC(void)
1610 unsigned long flags
;
1612 if (apic_verbosity
== APIC_QUIET
)
1615 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1617 spin_lock_irqsave(&i8259A_lock
, flags
);
1619 v
= inb(0xa1) << 8 | inb(0x21);
1620 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1622 v
= inb(0xa0) << 8 | inb(0x20);
1623 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1627 v
= inb(0xa0) << 8 | inb(0x20);
1631 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1633 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1635 v
= inb(0x4d1) << 8 | inb(0x4d0);
1636 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1639 __apicdebuginit(int) print_all_ICs(void)
1642 print_all_local_APICs();
1648 fs_initcall(print_all_ICs
);
1651 static void __init
enable_IO_APIC(void)
1653 union IO_APIC_reg_01 reg_01
;
1654 int i8259_apic
, i8259_pin
;
1656 unsigned long flags
;
1658 for (i
= 0; i
< pin_map_size
; i
++) {
1659 irq_2_pin
[i
].pin
= -1;
1660 irq_2_pin
[i
].next
= 0;
1663 for (i
= 0; i
< MAX_PIRQS
; i
++)
1664 pirq_entries
[i
] = -1;
1667 * The number of IO-APIC IRQ registers (== #pins):
1669 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1670 spin_lock_irqsave(&ioapic_lock
, flags
);
1671 reg_01
.raw
= io_apic_read(apic
, 1);
1672 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1673 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1675 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1677 /* See if any of the pins is in ExtINT mode */
1678 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1679 struct IO_APIC_route_entry entry
;
1680 entry
= ioapic_read_entry(apic
, pin
);
1683 /* If the interrupt line is enabled and in ExtInt mode
1684 * I have found the pin where the i8259 is connected.
1686 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1687 ioapic_i8259
.apic
= apic
;
1688 ioapic_i8259
.pin
= pin
;
1694 /* Look to see what if the MP table has reported the ExtINT */
1695 /* If we could not find the appropriate pin by looking at the ioapic
1696 * the i8259 probably is not connected the ioapic but give the
1697 * mptable a chance anyway.
1699 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1700 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1701 /* Trust the MP table if nothing is setup in the hardware */
1702 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1703 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1704 ioapic_i8259
.pin
= i8259_pin
;
1705 ioapic_i8259
.apic
= i8259_apic
;
1707 /* Complain if the MP table and the hardware disagree */
1708 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1709 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1711 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1715 * Do not trust the IO-APIC being empty at bootup
1721 * Not an __init, needed by the reboot code
1723 void disable_IO_APIC(void)
1726 * Clear the IO-APIC before rebooting:
1731 * If the i8259 is routed through an IOAPIC
1732 * Put that IOAPIC in virtual wire mode
1733 * so legacy interrupts can be delivered.
1735 if (ioapic_i8259
.pin
!= -1) {
1736 struct IO_APIC_route_entry entry
;
1738 memset(&entry
, 0, sizeof(entry
));
1739 entry
.mask
= 0; /* Enabled */
1740 entry
.trigger
= 0; /* Edge */
1742 entry
.polarity
= 0; /* High */
1743 entry
.delivery_status
= 0;
1744 entry
.dest_mode
= 0; /* Physical */
1745 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1747 entry
.dest
.physical
.physical_dest
= read_apic_id();
1750 * Add it to the IO-APIC irq-routing table:
1752 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1754 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1758 * function to set the IO-APIC physical IDs based on the
1759 * values stored in the MPC table.
1761 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1764 static void __init
setup_ioapic_ids_from_mpc(void)
1766 union IO_APIC_reg_00 reg_00
;
1767 physid_mask_t phys_id_present_map
;
1770 unsigned char old_id
;
1771 unsigned long flags
;
1773 if (x86_quirks
->setup_ioapic_ids
&& x86_quirks
->setup_ioapic_ids())
1777 * Don't check I/O APIC IDs for xAPIC systems. They have
1778 * no meaning without the serial APIC bus.
1780 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
1781 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
1784 * This is broken; anything with a real cpu count has to
1785 * circumvent this idiocy regardless.
1787 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
1790 * Set the IOAPIC ID to the value stored in the MPC table.
1792 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1794 /* Read the register 0 value */
1795 spin_lock_irqsave(&ioapic_lock
, flags
);
1796 reg_00
.raw
= io_apic_read(apic
, 0);
1797 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1799 old_id
= mp_ioapics
[apic
].mp_apicid
;
1801 if (mp_ioapics
[apic
].mp_apicid
>= get_physical_broadcast()) {
1802 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1803 apic
, mp_ioapics
[apic
].mp_apicid
);
1804 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1806 mp_ioapics
[apic
].mp_apicid
= reg_00
.bits
.ID
;
1810 * Sanity check, is the ID really free? Every APIC in a
1811 * system must have a unique ID or we get lots of nice
1812 * 'stuck on smp_invalidate_needed IPI wait' messages.
1814 if (check_apicid_used(phys_id_present_map
,
1815 mp_ioapics
[apic
].mp_apicid
)) {
1816 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1817 apic
, mp_ioapics
[apic
].mp_apicid
);
1818 for (i
= 0; i
< get_physical_broadcast(); i
++)
1819 if (!physid_isset(i
, phys_id_present_map
))
1821 if (i
>= get_physical_broadcast())
1822 panic("Max APIC ID exceeded!\n");
1823 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1825 physid_set(i
, phys_id_present_map
);
1826 mp_ioapics
[apic
].mp_apicid
= i
;
1829 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mp_apicid
);
1830 apic_printk(APIC_VERBOSE
, "Setting %d in the "
1831 "phys_id_present_map\n",
1832 mp_ioapics
[apic
].mp_apicid
);
1833 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
1838 * We need to adjust the IRQ routing table
1839 * if the ID changed.
1841 if (old_id
!= mp_ioapics
[apic
].mp_apicid
)
1842 for (i
= 0; i
< mp_irq_entries
; i
++)
1843 if (mp_irqs
[i
].mp_dstapic
== old_id
)
1844 mp_irqs
[i
].mp_dstapic
1845 = mp_ioapics
[apic
].mp_apicid
;
1848 * Read the right value from the MPC table and
1849 * write it into the ID register.
1851 apic_printk(APIC_VERBOSE
, KERN_INFO
1852 "...changing IO-APIC physical APIC ID to %d ...",
1853 mp_ioapics
[apic
].mp_apicid
);
1855 reg_00
.bits
.ID
= mp_ioapics
[apic
].mp_apicid
;
1856 spin_lock_irqsave(&ioapic_lock
, flags
);
1857 io_apic_write(apic
, 0, reg_00
.raw
);
1858 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1863 spin_lock_irqsave(&ioapic_lock
, flags
);
1864 reg_00
.raw
= io_apic_read(apic
, 0);
1865 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1866 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mp_apicid
)
1867 printk("could not set ID!\n");
1869 apic_printk(APIC_VERBOSE
, " ok.\n");
1873 int no_timer_check __initdata
;
1875 static int __init
notimercheck(char *s
)
1880 __setup("no_timer_check", notimercheck
);
1883 * There is a nasty bug in some older SMP boards, their mptable lies
1884 * about the timer IRQ. We do the following to work around the situation:
1886 * - timer IRQ defaults to IO-APIC IRQ
1887 * - if this function detects that timer IRQs are defunct, then we fall
1888 * back to ISA timer IRQs
1890 static int __init
timer_irq_works(void)
1892 unsigned long t1
= jiffies
;
1893 unsigned long flags
;
1898 local_save_flags(flags
);
1900 /* Let ten ticks pass... */
1901 mdelay((10 * 1000) / HZ
);
1902 local_irq_restore(flags
);
1905 * Expect a few ticks at least, to be sure some possible
1906 * glue logic does not lock up after one or two first
1907 * ticks in a non-ExtINT mode. Also the local APIC
1908 * might have cached one ExtINT interrupt. Finally, at
1909 * least one tick may be lost due to delays.
1911 if (time_after(jiffies
, t1
+ 4))
1918 * In the SMP+IOAPIC case it might happen that there are an unspecified
1919 * number of pending IRQ events unhandled. These cases are very rare,
1920 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1921 * better to do it this way as thus we do not have to be aware of
1922 * 'pending' interrupts in the IRQ path, except at this point.
1925 * Edge triggered needs to resend any interrupt
1926 * that was delayed but this is now handled in the device
1933 * Starting up a edge-triggered IO-APIC interrupt is
1934 * nasty - we need to make sure that we get the edge.
1935 * If it is already asserted for some reason, we need
1936 * return 1 to indicate that is was pending.
1938 * This is not complete - we should be able to fake
1939 * an edge even if it isn't on the 8259A...
1941 * (We do this for level-triggered IRQs too - it cannot hurt.)
1943 static unsigned int startup_ioapic_irq(unsigned int irq
)
1945 int was_pending
= 0;
1946 unsigned long flags
;
1948 spin_lock_irqsave(&ioapic_lock
, flags
);
1950 disable_8259A_irq(irq
);
1951 if (i8259A_irq_pending(irq
))
1954 __unmask_IO_APIC_irq(irq
);
1955 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1960 static void ack_ioapic_irq(unsigned int irq
)
1962 move_native_irq(irq
);
1966 static void ack_ioapic_quirk_irq(unsigned int irq
)
1971 move_native_irq(irq
);
1973 * It appears there is an erratum which affects at least version 0x11
1974 * of I/O APIC (that's the 82093AA and cores integrated into various
1975 * chipsets). Under certain conditions a level-triggered interrupt is
1976 * erroneously delivered as edge-triggered one but the respective IRR
1977 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1978 * message but it will never arrive and further interrupts are blocked
1979 * from the source. The exact reason is so far unknown, but the
1980 * phenomenon was observed when two consecutive interrupt requests
1981 * from a given source get delivered to the same CPU and the source is
1982 * temporarily disabled in between.
1984 * A workaround is to simulate an EOI message manually. We achieve it
1985 * by setting the trigger mode to edge and then to level when the edge
1986 * trigger mode gets detected in the TMR of a local APIC for a
1987 * level-triggered interrupt. We mask the source for the time of the
1988 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1989 * The idea is from Manfred Spraul. --macro
1991 i
= irq_vector
[irq
];
1993 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
1997 if (!(v
& (1 << (i
& 0x1f)))) {
1998 atomic_inc(&irq_mis_count
);
1999 spin_lock(&ioapic_lock
);
2000 __mask_and_edge_IO_APIC_irq(irq
);
2001 __unmask_and_level_IO_APIC_irq(irq
);
2002 spin_unlock(&ioapic_lock
);
2006 static int ioapic_retrigger_irq(unsigned int irq
)
2008 send_IPI_self(irq_vector
[irq
]);
2013 static struct irq_chip ioapic_chip __read_mostly
= {
2015 .startup
= startup_ioapic_irq
,
2016 .mask
= mask_IO_APIC_irq
,
2017 .unmask
= unmask_IO_APIC_irq
,
2018 .ack
= ack_ioapic_irq
,
2019 .eoi
= ack_ioapic_quirk_irq
,
2021 .set_affinity
= set_ioapic_affinity_irq
,
2023 .retrigger
= ioapic_retrigger_irq
,
2027 static inline void init_IO_APIC_traps(void)
2032 * NOTE! The local APIC isn't very good at handling
2033 * multiple interrupts at the same interrupt level.
2034 * As the interrupt level is determined by taking the
2035 * vector number and shifting that right by 4, we
2036 * want to spread these out a bit so that they don't
2037 * all fall in the same interrupt level.
2039 * Also, we've got to be careful not to trash gate
2040 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2042 for (irq
= 0; irq
< nr_irqs
; irq
++) {
2043 if (IO_APIC_IRQ(irq
) && !irq_vector
[irq
]) {
2045 * Hmm.. We don't have an entry for this,
2046 * so default to an old-fashioned 8259
2047 * interrupt if we can..
2050 make_8259A_irq(irq
);
2052 /* Strange. Oh, well.. */
2053 irq_desc
[irq
].chip
= &no_irq_chip
;
2059 * The local APIC irq-chip implementation:
2062 static void ack_lapic_irq(unsigned int irq
)
2067 static void mask_lapic_irq(unsigned int irq
)
2071 v
= apic_read(APIC_LVT0
);
2072 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2075 static void unmask_lapic_irq(unsigned int irq
)
2079 v
= apic_read(APIC_LVT0
);
2080 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2083 static struct irq_chip lapic_chip __read_mostly
= {
2084 .name
= "local-APIC",
2085 .mask
= mask_lapic_irq
,
2086 .unmask
= unmask_lapic_irq
,
2087 .ack
= ack_lapic_irq
,
2090 static void lapic_register_intr(int irq
, int vector
)
2092 irq_desc
[irq
].status
&= ~IRQ_LEVEL
;
2093 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2095 set_intr_gate(vector
, interrupt
[irq
]);
2098 static void __init
setup_nmi(void)
2101 * Dirty trick to enable the NMI watchdog ...
2102 * We put the 8259A master into AEOI mode and
2103 * unmask on all local APICs LVT0 as NMI.
2105 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2106 * is from Maciej W. Rozycki - so we do not have to EOI from
2107 * the NMI handler or the timer interrupt.
2109 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2111 enable_NMI_through_LVT0();
2113 apic_printk(APIC_VERBOSE
, " done.\n");
2117 * This looks a bit hackish but it's about the only one way of sending
2118 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2119 * not support the ExtINT mode, unfortunately. We need to send these
2120 * cycles as some i82489DX-based boards have glue logic that keeps the
2121 * 8259A interrupt line asserted until INTA. --macro
2123 static inline void __init
unlock_ExtINT_logic(void)
2126 struct IO_APIC_route_entry entry0
, entry1
;
2127 unsigned char save_control
, save_freq_select
;
2129 pin
= find_isa_irq_pin(8, mp_INT
);
2134 apic
= find_isa_irq_apic(8, mp_INT
);
2140 entry0
= ioapic_read_entry(apic
, pin
);
2141 clear_IO_APIC_pin(apic
, pin
);
2143 memset(&entry1
, 0, sizeof(entry1
));
2145 entry1
.dest_mode
= 0; /* physical delivery */
2146 entry1
.mask
= 0; /* unmask IRQ now */
2147 entry1
.dest
.physical
.physical_dest
= hard_smp_processor_id();
2148 entry1
.delivery_mode
= dest_ExtINT
;
2149 entry1
.polarity
= entry0
.polarity
;
2153 ioapic_write_entry(apic
, pin
, entry1
);
2155 save_control
= CMOS_READ(RTC_CONTROL
);
2156 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2157 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2159 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2164 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2168 CMOS_WRITE(save_control
, RTC_CONTROL
);
2169 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2170 clear_IO_APIC_pin(apic
, pin
);
2172 ioapic_write_entry(apic
, pin
, entry0
);
2176 * This code may look a bit paranoid, but it's supposed to cooperate with
2177 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2178 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2179 * fanatically on his truly buggy board.
2181 static inline void __init
check_timer(void)
2183 int apic1
, pin1
, apic2
, pin2
;
2187 unsigned long flags
;
2189 local_irq_save(flags
);
2191 ver
= apic_read(APIC_LVR
);
2192 ver
= GET_APIC_VERSION(ver
);
2195 * get/set the timer IRQ vector:
2197 disable_8259A_irq(0);
2198 vector
= assign_irq_vector(0);
2199 set_intr_gate(vector
, interrupt
[0]);
2202 * As IRQ0 is to be enabled in the 8259A, the virtual
2203 * wire has to be disabled in the local APIC. Also
2204 * timer interrupts need to be acknowledged manually in
2205 * the 8259A for the i82489DX when using the NMI
2206 * watchdog as that APIC treats NMIs as level-triggered.
2207 * The AEOI mode will finish them in the 8259A
2210 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2212 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2214 pin1
= find_isa_irq_pin(0, mp_INT
);
2215 apic1
= find_isa_irq_apic(0, mp_INT
);
2216 pin2
= ioapic_i8259
.pin
;
2217 apic2
= ioapic_i8259
.apic
;
2219 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2220 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2221 vector
, apic1
, pin1
, apic2
, pin2
);
2224 * Some BIOS writers are clueless and report the ExtINTA
2225 * I/O APIC input from the cascaded 8259A as the timer
2226 * interrupt input. So just in case, if only one pin
2227 * was found above, try it both directly and through the
2234 } else if (pin2
== -1) {
2241 * Ok, does IRQ0 through the IOAPIC work?
2244 add_pin_to_irq(0, apic1
, pin1
);
2245 setup_timer_IRQ0_pin(apic1
, pin1
, vector
);
2247 unmask_IO_APIC_irq(0);
2248 if (timer_irq_works()) {
2249 if (nmi_watchdog
== NMI_IO_APIC
) {
2251 enable_8259A_irq(0);
2253 if (disable_timer_pin_1
> 0)
2254 clear_IO_APIC_pin(0, pin1
);
2257 clear_IO_APIC_pin(apic1
, pin1
);
2259 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2260 "8254 timer not connected to IO-APIC\n");
2262 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2263 "(IRQ0) through the 8259A ...\n");
2264 apic_printk(APIC_QUIET
, KERN_INFO
2265 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2267 * legacy devices should be connected to IO APIC #0
2269 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2270 setup_timer_IRQ0_pin(apic2
, pin2
, vector
);
2271 unmask_IO_APIC_irq(0);
2272 enable_8259A_irq(0);
2273 if (timer_irq_works()) {
2274 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2275 timer_through_8259
= 1;
2276 if (nmi_watchdog
== NMI_IO_APIC
) {
2277 disable_8259A_irq(0);
2279 enable_8259A_irq(0);
2284 * Cleanup, just in case ...
2286 disable_8259A_irq(0);
2287 clear_IO_APIC_pin(apic2
, pin2
);
2288 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2291 if (nmi_watchdog
== NMI_IO_APIC
) {
2292 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2293 "through the IO-APIC - disabling NMI Watchdog!\n");
2294 nmi_watchdog
= NMI_NONE
;
2298 apic_printk(APIC_QUIET
, KERN_INFO
2299 "...trying to set up timer as Virtual Wire IRQ...\n");
2301 lapic_register_intr(0, vector
);
2302 apic_write(APIC_LVT0
, APIC_DM_FIXED
| vector
); /* Fixed mode */
2303 enable_8259A_irq(0);
2305 if (timer_irq_works()) {
2306 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2309 disable_8259A_irq(0);
2310 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| vector
);
2311 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2313 apic_printk(APIC_QUIET
, KERN_INFO
2314 "...trying to set up timer as ExtINT IRQ...\n");
2318 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2320 unlock_ExtINT_logic();
2322 if (timer_irq_works()) {
2323 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2326 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
2327 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2328 "report. Then try booting with the 'noapic' option.\n");
2330 local_irq_restore(flags
);
2334 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2335 * to devices. However there may be an I/O APIC pin available for
2336 * this interrupt regardless. The pin may be left unconnected, but
2337 * typically it will be reused as an ExtINT cascade interrupt for
2338 * the master 8259A. In the MPS case such a pin will normally be
2339 * reported as an ExtINT interrupt in the MP table. With ACPI
2340 * there is no provision for ExtINT interrupts, and in the absence
2341 * of an override it would be treated as an ordinary ISA I/O APIC
2342 * interrupt, that is edge-triggered and unmasked by default. We
2343 * used to do this, but it caused problems on some systems because
2344 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2345 * the same ExtINT cascade interrupt to drive the local APIC of the
2346 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2347 * the I/O APIC in all cases now. No actual device should request
2348 * it anyway. --macro
2350 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2352 void __init
setup_IO_APIC(void)
2356 /* Reserve all the system vectors. */
2357 for (i
= first_system_vector
; i
< NR_VECTORS
; i
++)
2358 set_bit(i
, used_vectors
);
2362 io_apic_irqs
= ~PIC_IRQS
;
2364 printk("ENABLING IO-APIC IRQs\n");
2367 * Set up IO-APIC IRQ routing.
2370 setup_ioapic_ids_from_mpc();
2372 setup_IO_APIC_irqs();
2373 init_IO_APIC_traps();
2378 * Called after all the initialization is done. If we didnt find any
2379 * APIC bugs then we can allow the modify fast path
2382 static int __init
io_apic_bug_finalize(void)
2384 if (sis_apic_bug
== -1)
2389 late_initcall(io_apic_bug_finalize
);
2391 struct sysfs_ioapic_data
{
2392 struct sys_device dev
;
2393 struct IO_APIC_route_entry entry
[0];
2395 static struct sysfs_ioapic_data
*mp_ioapic_data
[MAX_IO_APICS
];
2397 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2399 struct IO_APIC_route_entry
*entry
;
2400 struct sysfs_ioapic_data
*data
;
2403 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2404 entry
= data
->entry
;
2405 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2406 entry
[i
] = ioapic_read_entry(dev
->id
, i
);
2411 static int ioapic_resume(struct sys_device
*dev
)
2413 struct IO_APIC_route_entry
*entry
;
2414 struct sysfs_ioapic_data
*data
;
2415 unsigned long flags
;
2416 union IO_APIC_reg_00 reg_00
;
2419 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2420 entry
= data
->entry
;
2422 spin_lock_irqsave(&ioapic_lock
, flags
);
2423 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2424 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mp_apicid
) {
2425 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mp_apicid
;
2426 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2428 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2429 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2430 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
2435 static struct sysdev_class ioapic_sysdev_class
= {
2437 .suspend
= ioapic_suspend
,
2438 .resume
= ioapic_resume
,
2441 static int __init
ioapic_init_sysfs(void)
2443 struct sys_device
*dev
;
2444 int i
, size
, error
= 0;
2446 error
= sysdev_class_register(&ioapic_sysdev_class
);
2450 for (i
= 0; i
< nr_ioapics
; i
++) {
2451 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2452 * sizeof(struct IO_APIC_route_entry
);
2453 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
2454 if (!mp_ioapic_data
[i
]) {
2455 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2458 dev
= &mp_ioapic_data
[i
]->dev
;
2460 dev
->cls
= &ioapic_sysdev_class
;
2461 error
= sysdev_register(dev
);
2463 kfree(mp_ioapic_data
[i
]);
2464 mp_ioapic_data
[i
] = NULL
;
2465 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2473 device_initcall(ioapic_init_sysfs
);
2476 * Dynamic irq allocate and deallocation
2478 int create_irq(void)
2480 /* Allocate an unused irq */
2481 int irq
, new, vector
= 0;
2482 unsigned long flags
;
2485 spin_lock_irqsave(&vector_lock
, flags
);
2486 for (new = (nr_irqs
- 1); new >= 0; new--) {
2487 if (platform_legacy_irq(new))
2489 if (irq_vector
[new] != 0)
2491 vector
= __assign_irq_vector(new);
2492 if (likely(vector
> 0))
2496 spin_unlock_irqrestore(&vector_lock
, flags
);
2499 set_intr_gate(vector
, interrupt
[irq
]);
2500 dynamic_irq_init(irq
);
2505 void destroy_irq(unsigned int irq
)
2507 unsigned long flags
;
2509 dynamic_irq_cleanup(irq
);
2511 spin_lock_irqsave(&vector_lock
, flags
);
2512 clear_bit(irq_vector
[irq
], used_vectors
);
2513 irq_vector
[irq
] = 0;
2514 spin_unlock_irqrestore(&vector_lock
, flags
);
2518 * MSI message composition
2520 #ifdef CONFIG_PCI_MSI
2521 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
2526 vector
= assign_irq_vector(irq
);
2528 dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2530 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2533 ((INT_DEST_MODE
== 0) ?
2534 MSI_ADDR_DEST_MODE_PHYSICAL
:
2535 MSI_ADDR_DEST_MODE_LOGICAL
) |
2536 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2537 MSI_ADDR_REDIRECTION_CPU
:
2538 MSI_ADDR_REDIRECTION_LOWPRI
) |
2539 MSI_ADDR_DEST_ID(dest
);
2542 MSI_DATA_TRIGGER_EDGE
|
2543 MSI_DATA_LEVEL_ASSERT
|
2544 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2545 MSI_DATA_DELIVERY_FIXED
:
2546 MSI_DATA_DELIVERY_LOWPRI
) |
2547 MSI_DATA_VECTOR(vector
);
2553 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
2560 cpus_and(tmp
, mask
, cpu_online_map
);
2561 if (cpus_empty(tmp
))
2564 vector
= assign_irq_vector(irq
);
2568 dest
= cpu_mask_to_apicid(mask
);
2570 read_msi_msg(irq
, &msg
);
2572 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2573 msg
.data
|= MSI_DATA_VECTOR(vector
);
2574 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2575 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2577 write_msi_msg(irq
, &msg
);
2578 irq_desc
[irq
].affinity
= mask
;
2580 #endif /* CONFIG_SMP */
2583 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2584 * which implement the MSI or MSI-X Capability Structure.
2586 static struct irq_chip msi_chip
= {
2588 .unmask
= unmask_msi_irq
,
2589 .mask
= mask_msi_irq
,
2590 .ack
= ack_ioapic_irq
,
2592 .set_affinity
= set_msi_irq_affinity
,
2594 .retrigger
= ioapic_retrigger_irq
,
2597 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
2605 ret
= msi_compose_msg(dev
, irq
, &msg
);
2611 set_irq_msi(irq
, desc
);
2612 write_msi_msg(irq
, &msg
);
2614 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
,
2620 void arch_teardown_msi_irq(unsigned int irq
)
2625 #endif /* CONFIG_PCI_MSI */
2628 * Hypertransport interrupt support
2630 #ifdef CONFIG_HT_IRQ
2634 static void target_ht_irq(unsigned int irq
, unsigned int dest
)
2636 struct ht_irq_msg msg
;
2637 fetch_ht_irq_msg(irq
, &msg
);
2639 msg
.address_lo
&= ~(HT_IRQ_LOW_DEST_ID_MASK
);
2640 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
2642 msg
.address_lo
|= HT_IRQ_LOW_DEST_ID(dest
);
2643 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
2645 write_ht_irq_msg(irq
, &msg
);
2648 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
2653 cpus_and(tmp
, mask
, cpu_online_map
);
2654 if (cpus_empty(tmp
))
2657 cpus_and(mask
, tmp
, CPU_MASK_ALL
);
2659 dest
= cpu_mask_to_apicid(mask
);
2661 target_ht_irq(irq
, dest
);
2662 irq_desc
[irq
].affinity
= mask
;
2666 static struct irq_chip ht_irq_chip
= {
2668 .mask
= mask_ht_irq
,
2669 .unmask
= unmask_ht_irq
,
2670 .ack
= ack_ioapic_irq
,
2672 .set_affinity
= set_ht_irq_affinity
,
2674 .retrigger
= ioapic_retrigger_irq
,
2677 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
2681 vector
= assign_irq_vector(irq
);
2683 struct ht_irq_msg msg
;
2688 cpu_set(vector
>> 8, tmp
);
2689 dest
= cpu_mask_to_apicid(tmp
);
2691 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
2695 HT_IRQ_LOW_DEST_ID(dest
) |
2696 HT_IRQ_LOW_VECTOR(vector
) |
2697 ((INT_DEST_MODE
== 0) ?
2698 HT_IRQ_LOW_DM_PHYSICAL
:
2699 HT_IRQ_LOW_DM_LOGICAL
) |
2700 HT_IRQ_LOW_RQEOI_EDGE
|
2701 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2702 HT_IRQ_LOW_MT_FIXED
:
2703 HT_IRQ_LOW_MT_ARBITRATED
) |
2704 HT_IRQ_LOW_IRQ_MASKED
;
2706 write_ht_irq_msg(irq
, &msg
);
2708 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
2709 handle_edge_irq
, "edge");
2713 #endif /* CONFIG_HT_IRQ */
2715 /* --------------------------------------------------------------------------
2716 ACPI-based IOAPIC Configuration
2717 -------------------------------------------------------------------------- */
2721 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
2723 union IO_APIC_reg_00 reg_00
;
2724 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
2726 unsigned long flags
;
2730 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2731 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2732 * supports up to 16 on one shared APIC bus.
2734 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2735 * advantage of new APIC bus architecture.
2738 if (physids_empty(apic_id_map
))
2739 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
2741 spin_lock_irqsave(&ioapic_lock
, flags
);
2742 reg_00
.raw
= io_apic_read(ioapic
, 0);
2743 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2745 if (apic_id
>= get_physical_broadcast()) {
2746 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
2747 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
2748 apic_id
= reg_00
.bits
.ID
;
2752 * Every APIC in a system must have a unique ID or we get lots of nice
2753 * 'stuck on smp_invalidate_needed IPI wait' messages.
2755 if (check_apicid_used(apic_id_map
, apic_id
)) {
2757 for (i
= 0; i
< get_physical_broadcast(); i
++) {
2758 if (!check_apicid_used(apic_id_map
, i
))
2762 if (i
== get_physical_broadcast())
2763 panic("Max apic_id exceeded!\n");
2765 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
2766 "trying %d\n", ioapic
, apic_id
, i
);
2771 tmp
= apicid_to_cpu_present(apic_id
);
2772 physids_or(apic_id_map
, apic_id_map
, tmp
);
2774 if (reg_00
.bits
.ID
!= apic_id
) {
2775 reg_00
.bits
.ID
= apic_id
;
2777 spin_lock_irqsave(&ioapic_lock
, flags
);
2778 io_apic_write(ioapic
, 0, reg_00
.raw
);
2779 reg_00
.raw
= io_apic_read(ioapic
, 0);
2780 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2783 if (reg_00
.bits
.ID
!= apic_id
) {
2784 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
2789 apic_printk(APIC_VERBOSE
, KERN_INFO
2790 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
2796 int __init
io_apic_get_version(int ioapic
)
2798 union IO_APIC_reg_01 reg_01
;
2799 unsigned long flags
;
2801 spin_lock_irqsave(&ioapic_lock
, flags
);
2802 reg_01
.raw
= io_apic_read(ioapic
, 1);
2803 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2805 return reg_01
.bits
.version
;
2809 int __init
io_apic_get_redir_entries(int ioapic
)
2811 union IO_APIC_reg_01 reg_01
;
2812 unsigned long flags
;
2814 spin_lock_irqsave(&ioapic_lock
, flags
);
2815 reg_01
.raw
= io_apic_read(ioapic
, 1);
2816 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2818 return reg_01
.bits
.entries
;
2822 int io_apic_set_pci_routing(int ioapic
, int pin
, int irq
, int edge_level
, int active_high_low
)
2824 struct IO_APIC_route_entry entry
;
2826 if (!IO_APIC_IRQ(irq
)) {
2827 printk(KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2833 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2834 * Note that we mask (disable) IRQs now -- these get enabled when the
2835 * corresponding device driver registers for this IRQ.
2838 memset(&entry
, 0, sizeof(entry
));
2840 entry
.delivery_mode
= INT_DELIVERY_MODE
;
2841 entry
.dest_mode
= INT_DEST_MODE
;
2842 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2843 entry
.trigger
= edge_level
;
2844 entry
.polarity
= active_high_low
;
2848 * IRQs < 16 are already in the irq_2_pin[] map
2851 add_pin_to_irq(irq
, ioapic
, pin
);
2853 entry
.vector
= assign_irq_vector(irq
);
2855 apic_printk(APIC_DEBUG
, KERN_DEBUG
"IOAPIC[%d]: Set PCI routing entry "
2856 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic
,
2857 mp_ioapics
[ioapic
].mp_apicid
, pin
, entry
.vector
, irq
,
2858 edge_level
, active_high_low
);
2860 ioapic_register_intr(irq
, entry
.vector
, edge_level
);
2862 if (!ioapic
&& (irq
< 16))
2863 disable_8259A_irq(irq
);
2865 ioapic_write_entry(ioapic
, pin
, entry
);
2870 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
2874 if (skip_ioapic_setup
)
2877 for (i
= 0; i
< mp_irq_entries
; i
++)
2878 if (mp_irqs
[i
].mp_irqtype
== mp_INT
&&
2879 mp_irqs
[i
].mp_srcbusirq
== bus_irq
)
2881 if (i
>= mp_irq_entries
)
2884 *trigger
= irq_trigger(i
);
2885 *polarity
= irq_polarity(i
);
2889 #endif /* CONFIG_ACPI */
2891 static int __init
parse_disable_timer_pin_1(char *arg
)
2893 disable_timer_pin_1
= 1;
2896 early_param("disable_timer_pin_1", parse_disable_timer_pin_1
);
2898 static int __init
parse_enable_timer_pin_1(char *arg
)
2900 disable_timer_pin_1
= -1;
2903 early_param("enable_timer_pin_1", parse_enable_timer_pin_1
);
2905 static int __init
parse_noapic(char *arg
)
2907 /* disable IO-APIC */
2908 disable_ioapic_setup();
2911 early_param("noapic", parse_noapic
);
2913 void __init
ioapic_init_mappings(void)
2915 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
2918 for (i
= 0; i
< nr_ioapics
; i
++) {
2919 if (smp_found_config
) {
2920 ioapic_phys
= mp_ioapics
[i
].mp_apicaddr
;
2923 "WARNING: bogus zero IO-APIC "
2924 "address found in MPTABLE, "
2925 "disabling IO/APIC support!\n");
2926 smp_found_config
= 0;
2927 skip_ioapic_setup
= 1;
2928 goto fake_ioapic_page
;
2932 ioapic_phys
= (unsigned long)
2933 alloc_bootmem_pages(PAGE_SIZE
);
2934 ioapic_phys
= __pa(ioapic_phys
);
2936 set_fixmap_nocache(idx
, ioapic_phys
);
2937 printk(KERN_DEBUG
"mapped IOAPIC to %08lx (%08lx)\n",
2938 __fix_to_virt(idx
), ioapic_phys
);