?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
drm/radeon/kms: adjust quirk for acer laptop
[linux-2.6.git] / drivers / gpu / drm / radeon / radeon_atombios.c
blob6317d2c9e6d93b766b56a377a4b2ed7e85edf1a4
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "radeon_drm.h"
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include "atom-bits.h"
32
33 /* from radeon_encoder.c */
34 extern uint32_t
35 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37 extern void radeon_link_encoder_connector(struct drm_device *dev);
38 extern void
39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
40 uint32_t supported_device);
41
42 /* from radeon_connector.c */
43 extern void
44 radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 uint32_t igp_lane_info,
50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd,
52 struct radeon_router *router);
53
54 /* from radeon_legacy_encoder.c */
55 extern void
56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
57 uint32_t supported_device);
58
59 union atom_supported_devices {
60 struct _ATOM_SUPPORTED_DEVICES_INFO info;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
62 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
63 };
64
65 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
66 uint8_t id)
67 {
68 struct atom_context *ctx = rdev->mode_info.atom_context;
69 ATOM_GPIO_I2C_ASSIGMENT *gpio;
70 struct radeon_i2c_bus_rec i2c;
71 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
72 struct _ATOM_GPIO_I2C_INFO *i2c_info;
73 uint16_t data_offset, size;
74 int i, num_indices;
75
76 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
77 i2c.valid = false;
78
79 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
80 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
81
82 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
83 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
84
85 for (i = 0; i < num_indices; i++) {
86 gpio = &i2c_info->asGPIO_Info[i];
87
88 /* some evergreen boards have bad data for this entry */
89 if (ASIC_IS_DCE4(rdev)) {
90 if ((i == 7) &&
91 (gpio->usClkMaskRegisterIndex == 0x1936) &&
92 (gpio->sucI2cId.ucAccess == 0)) {
93 gpio->sucI2cId.ucAccess = 0x97;
94 gpio->ucDataMaskShift = 8;
95 gpio->ucDataEnShift = 8;
96 gpio->ucDataY_Shift = 8;
97 gpio->ucDataA_Shift = 8;
98 }
99 }
100
101 /* some DCE3 boards have bad data for this entry */
102 if (ASIC_IS_DCE3(rdev)) {
103 if ((i == 4) &&
104 (gpio->usClkMaskRegisterIndex == 0x1fda) &&
105 (gpio->sucI2cId.ucAccess == 0x94))
106 gpio->sucI2cId.ucAccess = 0x14;
107 }
108
109 if (gpio->sucI2cId.ucAccess == id) {
110 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
111 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
112 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
113 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
114 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
115 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
116 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
117 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
118 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
119 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
120 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
121 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
122 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
123 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
124 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
125 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
126
127 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
128 i2c.hw_capable = true;
129 else
130 i2c.hw_capable = false;
131
132 if (gpio->sucI2cId.ucAccess == 0xa0)
133 i2c.mm_i2c = true;
134 else
135 i2c.mm_i2c = false;
136
137 i2c.i2c_id = gpio->sucI2cId.ucAccess;
138
139 if (i2c.mask_clk_reg)
140 i2c.valid = true;
141 break;
142 }
143 }
144 }
145
146 return i2c;
147 }
148
149 void radeon_atombios_i2c_init(struct radeon_device *rdev)
150 {
151 struct atom_context *ctx = rdev->mode_info.atom_context;
152 ATOM_GPIO_I2C_ASSIGMENT *gpio;
153 struct radeon_i2c_bus_rec i2c;
154 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
155 struct _ATOM_GPIO_I2C_INFO *i2c_info;
156 uint16_t data_offset, size;
157 int i, num_indices;
158 char stmp[32];
159
160 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
161
162 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
163 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
164
165 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
166 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
167
168 for (i = 0; i < num_indices; i++) {
169 gpio = &i2c_info->asGPIO_Info[i];
170 i2c.valid = false;
171
172 /* some evergreen boards have bad data for this entry */
173 if (ASIC_IS_DCE4(rdev)) {
174 if ((i == 7) &&
175 (gpio->usClkMaskRegisterIndex == 0x1936) &&
176 (gpio->sucI2cId.ucAccess == 0)) {
177 gpio->sucI2cId.ucAccess = 0x97;
178 gpio->ucDataMaskShift = 8;
179 gpio->ucDataEnShift = 8;
180 gpio->ucDataY_Shift = 8;
181 gpio->ucDataA_Shift = 8;
182 }
183 }
184
185 /* some DCE3 boards have bad data for this entry */
186 if (ASIC_IS_DCE3(rdev)) {
187 if ((i == 4) &&
188 (gpio->usClkMaskRegisterIndex == 0x1fda) &&
189 (gpio->sucI2cId.ucAccess == 0x94))
190 gpio->sucI2cId.ucAccess = 0x14;
191 }
192
193 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
194 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
195 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
196 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
197 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
198 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
199 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
200 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
201 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
202 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
203 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
204 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
205 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
206 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
207 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
208 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
209
210 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
211 i2c.hw_capable = true;
212 else
213 i2c.hw_capable = false;
214
215 if (gpio->sucI2cId.ucAccess == 0xa0)
216 i2c.mm_i2c = true;
217 else
218 i2c.mm_i2c = false;
219
220 i2c.i2c_id = gpio->sucI2cId.ucAccess;
221
222 if (i2c.mask_clk_reg) {
223 i2c.valid = true;
224 sprintf(stmp, "0x%x", i2c.i2c_id);
225 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
226 }
227 }
228 }
229 }
230
231 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
232 u8 id)
233 {
234 struct atom_context *ctx = rdev->mode_info.atom_context;
235 struct radeon_gpio_rec gpio;
236 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
237 struct _ATOM_GPIO_PIN_LUT *gpio_info;
238 ATOM_GPIO_PIN_ASSIGNMENT *pin;
239 u16 data_offset, size;
240 int i, num_indices;
241
242 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
243 gpio.valid = false;
244
245 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
246 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
247
248 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
249 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
250
251 for (i = 0; i < num_indices; i++) {
252 pin = &gpio_info->asGPIO_Pin[i];
253 if (id == pin->ucGPIO_ID) {
254 gpio.id = pin->ucGPIO_ID;
255 gpio.reg = pin->usGpioPin_AIndex * 4;
256 gpio.mask = (1 << pin->ucGpioPinBitShift);
257 gpio.valid = true;
258 break;
259 }
260 }
261 }
262
263 return gpio;
264 }
265
266 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
267 struct radeon_gpio_rec *gpio)
268 {
269 struct radeon_hpd hpd;
270 u32 reg;
271
272 memset(&hpd, 0, sizeof(struct radeon_hpd));
273
274 if (ASIC_IS_DCE4(rdev))
275 reg = EVERGREEN_DC_GPIO_HPD_A;
276 else
277 reg = AVIVO_DC_GPIO_HPD_A;
278
279 hpd.gpio = *gpio;
280 if (gpio->reg == reg) {
281 switch(gpio->mask) {
282 case (1 << 0):
283 hpd.hpd = RADEON_HPD_1;
284 break;
285 case (1 << 8):
286 hpd.hpd = RADEON_HPD_2;
287 break;
288 case (1 << 16):
289 hpd.hpd = RADEON_HPD_3;
290 break;
291 case (1 << 24):
292 hpd.hpd = RADEON_HPD_4;
293 break;
294 case (1 << 26):
295 hpd.hpd = RADEON_HPD_5;
296 break;
297 case (1 << 28):
298 hpd.hpd = RADEON_HPD_6;
299 break;
300 default:
301 hpd.hpd = RADEON_HPD_NONE;
302 break;
303 }
304 } else
305 hpd.hpd = RADEON_HPD_NONE;
306 return hpd;
307 }
308
309 static bool radeon_atom_apply_quirks(struct drm_device *dev,
310 uint32_t supported_device,
311 int *connector_type,
312 struct radeon_i2c_bus_rec *i2c_bus,
313 uint16_t *line_mux,
314 struct radeon_hpd *hpd)
315 {
316
317 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
318 if ((dev->pdev->device == 0x791e) &&
319 (dev->pdev->subsystem_vendor == 0x1043) &&
320 (dev->pdev->subsystem_device == 0x826d)) {
321 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
322 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
323 *connector_type = DRM_MODE_CONNECTOR_DVID;
324 }
325
326 /* Asrock RS600 board lists the DVI port as HDMI */
327 if ((dev->pdev->device == 0x7941) &&
328 (dev->pdev->subsystem_vendor == 0x1849) &&
329 (dev->pdev->subsystem_device == 0x7941)) {
330 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
331 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
332 *connector_type = DRM_MODE_CONNECTOR_DVID;
333 }
334
335 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
336 if ((dev->pdev->device == 0x796e) &&
337 (dev->pdev->subsystem_vendor == 0x1462) &&
338 (dev->pdev->subsystem_device == 0x7302)) {
339 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
340 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
341 return false;
342 }
343
344 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
345 if ((dev->pdev->device == 0x7941) &&
346 (dev->pdev->subsystem_vendor == 0x147b) &&
347 (dev->pdev->subsystem_device == 0x2412)) {
348 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
349 return false;
350 }
351
352 /* Falcon NW laptop lists vga ddc line for LVDS */
353 if ((dev->pdev->device == 0x5653) &&
354 (dev->pdev->subsystem_vendor == 0x1462) &&
355 (dev->pdev->subsystem_device == 0x0291)) {
356 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
357 i2c_bus->valid = false;
358 *line_mux = 53;
359 }
360 }
361
362 /* HIS X1300 is DVI+VGA, not DVI+DVI */
363 if ((dev->pdev->device == 0x7146) &&
364 (dev->pdev->subsystem_vendor == 0x17af) &&
365 (dev->pdev->subsystem_device == 0x2058)) {
366 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
367 return false;
368 }
369
370 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
371 if ((dev->pdev->device == 0x7142) &&
372 (dev->pdev->subsystem_vendor == 0x1458) &&
373 (dev->pdev->subsystem_device == 0x2134)) {
374 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
375 return false;
376 }
377
378
379 /* Funky macbooks */
380 if ((dev->pdev->device == 0x71C5) &&
381 (dev->pdev->subsystem_vendor == 0x106b) &&
382 (dev->pdev->subsystem_device == 0x0080)) {
383 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
384 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
385 return false;
386 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
387 *line_mux = 0x90;
388 }
389
390 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
391 if ((dev->pdev->device == 0x9598) &&
392 (dev->pdev->subsystem_vendor == 0x1043) &&
393 (dev->pdev->subsystem_device == 0x01da)) {
394 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
395 *connector_type = DRM_MODE_CONNECTOR_DVII;
396 }
397 }
398
399 /* ASUS HD 3600 board lists the DVI port as HDMI */
400 if ((dev->pdev->device == 0x9598) &&
401 (dev->pdev->subsystem_vendor == 0x1043) &&
402 (dev->pdev->subsystem_device == 0x01e4)) {
403 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
404 *connector_type = DRM_MODE_CONNECTOR_DVII;
405 }
406 }
407
408 /* ASUS HD 3450 board lists the DVI port as HDMI */
409 if ((dev->pdev->device == 0x95C5) &&
410 (dev->pdev->subsystem_vendor == 0x1043) &&
411 (dev->pdev->subsystem_device == 0x01e2)) {
412 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
413 *connector_type = DRM_MODE_CONNECTOR_DVII;
414 }
415 }
416
417 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
418 * HDMI + VGA reporting as HDMI
419 */
420 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
421 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
422 *connector_type = DRM_MODE_CONNECTOR_VGA;
423 *line_mux = 0;
424 }
425 }
426
427 /* Acer laptop (Acer TravelMate 5730G) has an HDMI port
428 * on the laptop and a DVI port on the docking station and
429 * both share the same encoder, hpd pin, and ddc line.
430 * So while the bios table is technically correct,
431 * we drop the DVI port here since xrandr has no concept of
432 * encoders and will try and drive both connectors
433 * with different crtcs which isn't possible on the hardware
434 * side and leaves no crtcs for LVDS or VGA.
435 */
436 if ((dev->pdev->device == 0x95c4) &&
437 (dev->pdev->subsystem_vendor == 0x1025) &&
438 (dev->pdev->subsystem_device == 0x013c)) {
439 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
440 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
441 /* actually it's a DVI-D port not DVI-I */
442 *connector_type = DRM_MODE_CONNECTOR_DVID;
443 return false;
444 }
445 }
446
447 /* XFX Pine Group device rv730 reports no VGA DDC lines
448 * even though they are wired up to record 0x93
449 */
450 if ((dev->pdev->device == 0x9498) &&
451 (dev->pdev->subsystem_vendor == 0x1682) &&
452 (dev->pdev->subsystem_device == 0x2452)) {
453 struct radeon_device *rdev = dev->dev_private;
454 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
455 }
456 return true;
457 }
458
459 const int supported_devices_connector_convert[] = {
460 DRM_MODE_CONNECTOR_Unknown,
461 DRM_MODE_CONNECTOR_VGA,
462 DRM_MODE_CONNECTOR_DVII,
463 DRM_MODE_CONNECTOR_DVID,
464 DRM_MODE_CONNECTOR_DVIA,
465 DRM_MODE_CONNECTOR_SVIDEO,
466 DRM_MODE_CONNECTOR_Composite,
467 DRM_MODE_CONNECTOR_LVDS,
468 DRM_MODE_CONNECTOR_Unknown,
469 DRM_MODE_CONNECTOR_Unknown,
470 DRM_MODE_CONNECTOR_HDMIA,
471 DRM_MODE_CONNECTOR_HDMIB,
472 DRM_MODE_CONNECTOR_Unknown,
473 DRM_MODE_CONNECTOR_Unknown,
474 DRM_MODE_CONNECTOR_9PinDIN,
475 DRM_MODE_CONNECTOR_DisplayPort
476 };
477
478 const uint16_t supported_devices_connector_object_id_convert[] = {
479 CONNECTOR_OBJECT_ID_NONE,
480 CONNECTOR_OBJECT_ID_VGA,
481 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
482 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
483 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
484 CONNECTOR_OBJECT_ID_COMPOSITE,
485 CONNECTOR_OBJECT_ID_SVIDEO,
486 CONNECTOR_OBJECT_ID_LVDS,
487 CONNECTOR_OBJECT_ID_9PIN_DIN,
488 CONNECTOR_OBJECT_ID_9PIN_DIN,
489 CONNECTOR_OBJECT_ID_DISPLAYPORT,
490 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
491 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
492 CONNECTOR_OBJECT_ID_SVIDEO
493 };
494
495 const int object_connector_convert[] = {
496 DRM_MODE_CONNECTOR_Unknown,
497 DRM_MODE_CONNECTOR_DVII,
498 DRM_MODE_CONNECTOR_DVII,
499 DRM_MODE_CONNECTOR_DVID,
500 DRM_MODE_CONNECTOR_DVID,
501 DRM_MODE_CONNECTOR_VGA,
502 DRM_MODE_CONNECTOR_Composite,
503 DRM_MODE_CONNECTOR_SVIDEO,
504 DRM_MODE_CONNECTOR_Unknown,
505 DRM_MODE_CONNECTOR_Unknown,
506 DRM_MODE_CONNECTOR_9PinDIN,
507 DRM_MODE_CONNECTOR_Unknown,
508 DRM_MODE_CONNECTOR_HDMIA,
509 DRM_MODE_CONNECTOR_HDMIB,
510 DRM_MODE_CONNECTOR_LVDS,
511 DRM_MODE_CONNECTOR_9PinDIN,
512 DRM_MODE_CONNECTOR_Unknown,
513 DRM_MODE_CONNECTOR_Unknown,
514 DRM_MODE_CONNECTOR_Unknown,
515 DRM_MODE_CONNECTOR_DisplayPort,
516 DRM_MODE_CONNECTOR_eDP,
517 DRM_MODE_CONNECTOR_Unknown
518 };
519
520 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
521 {
522 struct radeon_device *rdev = dev->dev_private;
523 struct radeon_mode_info *mode_info = &rdev->mode_info;
524 struct atom_context *ctx = mode_info->atom_context;
525 int index = GetIndexIntoMasterTable(DATA, Object_Header);
526 u16 size, data_offset;
527 u8 frev, crev;
528 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
529 ATOM_OBJECT_TABLE *router_obj;
530 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
531 ATOM_OBJECT_HEADER *obj_header;
532 int i, j, k, path_size, device_support;
533 int connector_type;
534 u16 igp_lane_info, conn_id, connector_object_id;
535 struct radeon_i2c_bus_rec ddc_bus;
536 struct radeon_router router;
537 struct radeon_gpio_rec gpio;
538 struct radeon_hpd hpd;
539
540 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
541 return false;
542
543 if (crev < 2)
544 return false;
545
546 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
547 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
548 (ctx->bios + data_offset +
549 le16_to_cpu(obj_header->usDisplayPathTableOffset));
550 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
551 (ctx->bios + data_offset +
552 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
553 router_obj = (ATOM_OBJECT_TABLE *)
554 (ctx->bios + data_offset +
555 le16_to_cpu(obj_header->usRouterObjectTableOffset));
556 device_support = le16_to_cpu(obj_header->usDeviceSupport);
557
558 path_size = 0;
559 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
560 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
561 ATOM_DISPLAY_OBJECT_PATH *path;
562 addr += path_size;
563 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
564 path_size += le16_to_cpu(path->usSize);
565
566 if (device_support & le16_to_cpu(path->usDeviceTag)) {
567 uint8_t con_obj_id, con_obj_num, con_obj_type;
568
569 con_obj_id =
570 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
571 >> OBJECT_ID_SHIFT;
572 con_obj_num =
573 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
574 >> ENUM_ID_SHIFT;
575 con_obj_type =
576 (le16_to_cpu(path->usConnObjectId) &
577 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
578
579 /* TODO CV support */
580 if (le16_to_cpu(path->usDeviceTag) ==
581 ATOM_DEVICE_CV_SUPPORT)
582 continue;
583
584 /* IGP chips */
585 if ((rdev->flags & RADEON_IS_IGP) &&
586 (con_obj_id ==
587 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
588 uint16_t igp_offset = 0;
589 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
590
591 index =
592 GetIndexIntoMasterTable(DATA,
593 IntegratedSystemInfo);
594
595 if (atom_parse_data_header(ctx, index, &size, &frev,
596 &crev, &igp_offset)) {
597
598 if (crev >= 2) {
599 igp_obj =
600 (ATOM_INTEGRATED_SYSTEM_INFO_V2
601 *) (ctx->bios + igp_offset);
602
603 if (igp_obj) {
604 uint32_t slot_config, ct;
605
606 if (con_obj_num == 1)
607 slot_config =
608 igp_obj->
609 ulDDISlot1Config;
610 else
611 slot_config =
612 igp_obj->
613 ulDDISlot2Config;
614
615 ct = (slot_config >> 16) & 0xff;
616 connector_type =
617 object_connector_convert
618 [ct];
619 connector_object_id = ct;
620 igp_lane_info =
621 slot_config & 0xffff;
622 } else
623 continue;
624 } else
625 continue;
626 } else {
627 igp_lane_info = 0;
628 connector_type =
629 object_connector_convert[con_obj_id];
630 connector_object_id = con_obj_id;
631 }
632 } else {
633 igp_lane_info = 0;
634 connector_type =
635 object_connector_convert[con_obj_id];
636 connector_object_id = con_obj_id;
637 }
638
639 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
640 continue;
641
642 router.ddc_valid = false;
643 router.cd_valid = false;
644 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
645 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
646
647 grph_obj_id =
648 (le16_to_cpu(path->usGraphicObjIds[j]) &
649 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
650 grph_obj_num =
651 (le16_to_cpu(path->usGraphicObjIds[j]) &
652 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
653 grph_obj_type =
654 (le16_to_cpu(path->usGraphicObjIds[j]) &
655 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
656
657 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
658 u16 encoder_obj = le16_to_cpu(path->usGraphicObjIds[j]);
659
660 radeon_add_atom_encoder(dev,
661 encoder_obj,
662 le16_to_cpu
663 (path->
664 usDeviceTag));
665
666 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
667 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
668 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
669 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
670 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
671 (ctx->bios + data_offset +
672 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
673 ATOM_I2C_RECORD *i2c_record;
674 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
675 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
676 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
677 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
678 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
679 (ctx->bios + data_offset +
680 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
681 int enum_id;
682
683 router.router_id = router_obj_id;
684 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
685 enum_id++) {
686 if (le16_to_cpu(path->usConnObjectId) ==
687 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
688 break;
689 }
690
691 while (record->ucRecordType > 0 &&
692 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
693 switch (record->ucRecordType) {
694 case ATOM_I2C_RECORD_TYPE:
695 i2c_record =
696 (ATOM_I2C_RECORD *)
697 record;
698 i2c_config =
699 (ATOM_I2C_ID_CONFIG_ACCESS *)
700 &i2c_record->sucI2cId;
701 router.i2c_info =
702 radeon_lookup_i2c_gpio(rdev,
703 i2c_config->
704 ucAccess);
705 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
706 break;
707 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
708 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
709 record;
710 router.ddc_valid = true;
711 router.ddc_mux_type = ddc_path->ucMuxType;
712 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
713 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
714 break;
715 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
716 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
717 record;
718 router.cd_valid = true;
719 router.cd_mux_type = cd_path->ucMuxType;
720 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
721 router.cd_mux_state = cd_path->ucMuxState[enum_id];
722 break;
723 }
724 record = (ATOM_COMMON_RECORD_HEADER *)
725 ((char *)record + record->ucRecordSize);
726 }
727 }
728 }
729 }
730 }
731
732 /* look up gpio for ddc, hpd */
733 ddc_bus.valid = false;
734 hpd.hpd = RADEON_HPD_NONE;
735 if ((le16_to_cpu(path->usDeviceTag) &
736 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
737 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
738 if (le16_to_cpu(path->usConnObjectId) ==
739 le16_to_cpu(con_obj->asObjects[j].
740 usObjectID)) {
741 ATOM_COMMON_RECORD_HEADER
742 *record =
743 (ATOM_COMMON_RECORD_HEADER
744 *)
745 (ctx->bios + data_offset +
746 le16_to_cpu(con_obj->
747 asObjects[j].
748 usRecordOffset));
749 ATOM_I2C_RECORD *i2c_record;
750 ATOM_HPD_INT_RECORD *hpd_record;
751 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
752
753 while (record->ucRecordType > 0
754 && record->
755 ucRecordType <=
756 ATOM_MAX_OBJECT_RECORD_NUMBER) {
757 switch (record->ucRecordType) {
758 case ATOM_I2C_RECORD_TYPE:
759 i2c_record =
760 (ATOM_I2C_RECORD *)
761 record;
762 i2c_config =
763 (ATOM_I2C_ID_CONFIG_ACCESS *)
764 &i2c_record->sucI2cId;
765 ddc_bus = radeon_lookup_i2c_gpio(rdev,
766 i2c_config->
767 ucAccess);
768 break;
769 case ATOM_HPD_INT_RECORD_TYPE:
770 hpd_record =
771 (ATOM_HPD_INT_RECORD *)
772 record;
773 gpio = radeon_lookup_gpio(rdev,
774 hpd_record->ucHPDIntGPIOID);
775 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
776 hpd.plugged_state = hpd_record->ucPlugged_PinState;
777 break;
778 }
779 record =
780 (ATOM_COMMON_RECORD_HEADER
781 *) ((char *)record
782 +
783 record->
784 ucRecordSize);
785 }
786 break;
787 }
788 }
789 }
790
791 /* needed for aux chan transactions */
792 ddc_bus.hpd = hpd.hpd;
793
794 conn_id = le16_to_cpu(path->usConnObjectId);
795
796 if (!radeon_atom_apply_quirks
797 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
798 &ddc_bus, &conn_id, &hpd))
799 continue;
800
801 radeon_add_atom_connector(dev,
802 conn_id,
803 le16_to_cpu(path->
804 usDeviceTag),
805 connector_type, &ddc_bus,
806 igp_lane_info,
807 connector_object_id,
808 &hpd,
809 &router);
810
811 }
812 }
813
814 radeon_link_encoder_connector(dev);
815
816 return true;
817 }
818
819 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
820 int connector_type,
821 uint16_t devices)
822 {
823 struct radeon_device *rdev = dev->dev_private;
824
825 if (rdev->flags & RADEON_IS_IGP) {
826 return supported_devices_connector_object_id_convert
827 [connector_type];
828 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
829 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
830 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
831 struct radeon_mode_info *mode_info = &rdev->mode_info;
832 struct atom_context *ctx = mode_info->atom_context;
833 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
834 uint16_t size, data_offset;
835 uint8_t frev, crev;
836 ATOM_XTMDS_INFO *xtmds;
837
838 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
839 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
840
841 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
842 if (connector_type == DRM_MODE_CONNECTOR_DVII)
843 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
844 else
845 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
846 } else {
847 if (connector_type == DRM_MODE_CONNECTOR_DVII)
848 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
849 else
850 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
851 }
852 } else
853 return supported_devices_connector_object_id_convert
854 [connector_type];
855 } else {
856 return supported_devices_connector_object_id_convert
857 [connector_type];
858 }
859 }
860
861 struct bios_connector {
862 bool valid;
863 uint16_t line_mux;
864 uint16_t devices;
865 int connector_type;
866 struct radeon_i2c_bus_rec ddc_bus;
867 struct radeon_hpd hpd;
868 };
869
870 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
871 drm_device
872 *dev)
873 {
874 struct radeon_device *rdev = dev->dev_private;
875 struct radeon_mode_info *mode_info = &rdev->mode_info;
876 struct atom_context *ctx = mode_info->atom_context;
877 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
878 uint16_t size, data_offset;
879 uint8_t frev, crev;
880 uint16_t device_support;
881 uint8_t dac;
882 union atom_supported_devices *supported_devices;
883 int i, j, max_device;
884 struct bios_connector *bios_connectors;
885 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
886 struct radeon_router router;
887
888 router.ddc_valid = false;
889 router.cd_valid = false;
890
891 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
892 if (!bios_connectors)
893 return false;
894
895 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
896 &data_offset)) {
897 kfree(bios_connectors);
898 return false;
899 }
900
901 supported_devices =
902 (union atom_supported_devices *)(ctx->bios + data_offset);
903
904 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
905
906 if (frev > 1)
907 max_device = ATOM_MAX_SUPPORTED_DEVICE;
908 else
909 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
910
911 for (i = 0; i < max_device; i++) {
912 ATOM_CONNECTOR_INFO_I2C ci =
913 supported_devices->info.asConnInfo[i];
914
915 bios_connectors[i].valid = false;
916
917 if (!(device_support & (1 << i))) {
918 continue;
919 }
920
921 if (i == ATOM_DEVICE_CV_INDEX) {
922 DRM_DEBUG_KMS("Skipping Component Video\n");
923 continue;
924 }
925
926 bios_connectors[i].connector_type =
927 supported_devices_connector_convert[ci.sucConnectorInfo.
928 sbfAccess.
929 bfConnectorType];
930
931 if (bios_connectors[i].connector_type ==
932 DRM_MODE_CONNECTOR_Unknown)
933 continue;
934
935 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
936
937 bios_connectors[i].line_mux =
938 ci.sucI2cId.ucAccess;
939
940 /* give tv unique connector ids */
941 if (i == ATOM_DEVICE_TV1_INDEX) {
942 bios_connectors[i].ddc_bus.valid = false;
943 bios_connectors[i].line_mux = 50;
944 } else if (i == ATOM_DEVICE_TV2_INDEX) {
945 bios_connectors[i].ddc_bus.valid = false;
946 bios_connectors[i].line_mux = 51;
947 } else if (i == ATOM_DEVICE_CV_INDEX) {
948 bios_connectors[i].ddc_bus.valid = false;
949 bios_connectors[i].line_mux = 52;
950 } else
951 bios_connectors[i].ddc_bus =
952 radeon_lookup_i2c_gpio(rdev,
953 bios_connectors[i].line_mux);
954
955 if ((crev > 1) && (frev > 1)) {
956 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
957 switch (isb) {
958 case 0x4:
959 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
960 break;
961 case 0xa:
962 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
963 break;
964 default:
965 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
966 break;
967 }
968 } else {
969 if (i == ATOM_DEVICE_DFP1_INDEX)
970 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
971 else if (i == ATOM_DEVICE_DFP2_INDEX)
972 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
973 else
974 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
975 }
976
977 /* Always set the connector type to VGA for CRT1/CRT2. if they are
978 * shared with a DVI port, we'll pick up the DVI connector when we
979 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
980 */
981 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
982 bios_connectors[i].connector_type =
983 DRM_MODE_CONNECTOR_VGA;
984
985 if (!radeon_atom_apply_quirks
986 (dev, (1 << i), &bios_connectors[i].connector_type,
987 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
988 &bios_connectors[i].hpd))
989 continue;
990
991 bios_connectors[i].valid = true;
992 bios_connectors[i].devices = (1 << i);
993
994 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
995 radeon_add_atom_encoder(dev,
996 radeon_get_encoder_enum(dev,
997 (1 << i),
998 dac),
999 (1 << i));
1000 else
1001 radeon_add_legacy_encoder(dev,
1002 radeon_get_encoder_enum(dev,
1003 (1 << i),
1004 dac),
1005 (1 << i));
1006 }
1007
1008 /* combine shared connectors */
1009 for (i = 0; i < max_device; i++) {
1010 if (bios_connectors[i].valid) {
1011 for (j = 0; j < max_device; j++) {
1012 if (bios_connectors[j].valid && (i != j)) {
1013 if (bios_connectors[i].line_mux ==
1014 bios_connectors[j].line_mux) {
1015 /* make sure not to combine LVDS */
1016 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1017 bios_connectors[i].line_mux = 53;
1018 bios_connectors[i].ddc_bus.valid = false;
1019 continue;
1020 }
1021 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1022 bios_connectors[j].line_mux = 53;
1023 bios_connectors[j].ddc_bus.valid = false;
1024 continue;
1025 }
1026 /* combine analog and digital for DVI-I */
1027 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1028 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1029 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1030 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1031 bios_connectors[i].devices |=
1032 bios_connectors[j].devices;
1033 bios_connectors[i].connector_type =
1034 DRM_MODE_CONNECTOR_DVII;
1035 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1036 bios_connectors[i].hpd =
1037 bios_connectors[j].hpd;
1038 bios_connectors[j].valid = false;
1039 }
1040 }
1041 }
1042 }
1043 }
1044 }
1045
1046 /* add the connectors */
1047 for (i = 0; i < max_device; i++) {
1048 if (bios_connectors[i].valid) {
1049 uint16_t connector_object_id =
1050 atombios_get_connector_object_id(dev,
1051 bios_connectors[i].connector_type,
1052 bios_connectors[i].devices);
1053 radeon_add_atom_connector(dev,
1054 bios_connectors[i].line_mux,
1055 bios_connectors[i].devices,
1056 bios_connectors[i].
1057 connector_type,
1058 &bios_connectors[i].ddc_bus,
1059 0,
1060 connector_object_id,
1061 &bios_connectors[i].hpd,
1062 &router);
1063 }
1064 }
1065
1066 radeon_link_encoder_connector(dev);
1067
1068 kfree(bios_connectors);
1069 return true;
1070 }
1071
1072 union firmware_info {
1073 ATOM_FIRMWARE_INFO info;
1074 ATOM_FIRMWARE_INFO_V1_2 info_12;
1075 ATOM_FIRMWARE_INFO_V1_3 info_13;
1076 ATOM_FIRMWARE_INFO_V1_4 info_14;
1077 ATOM_FIRMWARE_INFO_V2_1 info_21;
1078 };
1079
1080 bool radeon_atom_get_clock_info(struct drm_device *dev)
1081 {
1082 struct radeon_device *rdev = dev->dev_private;
1083 struct radeon_mode_info *mode_info = &rdev->mode_info;
1084 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1085 union firmware_info *firmware_info;
1086 uint8_t frev, crev;
1087 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1088 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1089 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1090 struct radeon_pll *spll = &rdev->clock.spll;
1091 struct radeon_pll *mpll = &rdev->clock.mpll;
1092 uint16_t data_offset;
1093
1094 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1095 &frev, &crev, &data_offset)) {
1096 firmware_info =
1097 (union firmware_info *)(mode_info->atom_context->bios +
1098 data_offset);
1099 /* pixel clocks */
1100 p1pll->reference_freq =
1101 le16_to_cpu(firmware_info->info.usReferenceClock);
1102 p1pll->reference_div = 0;
1103
1104 if (crev < 2)
1105 p1pll->pll_out_min =
1106 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1107 else
1108 p1pll->pll_out_min =
1109 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1110 p1pll->pll_out_max =
1111 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1112
1113 if (crev >= 4) {
1114 p1pll->lcd_pll_out_min =
1115 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1116 if (p1pll->lcd_pll_out_min == 0)
1117 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1118 p1pll->lcd_pll_out_max =
1119 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1120 if (p1pll->lcd_pll_out_max == 0)
1121 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1122 } else {
1123 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1124 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1125 }
1126
1127 if (p1pll->pll_out_min == 0) {
1128 if (ASIC_IS_AVIVO(rdev))
1129 p1pll->pll_out_min = 64800;
1130 else
1131 p1pll->pll_out_min = 20000;
1132 } else if (p1pll->pll_out_min > 64800) {
1133 /* Limiting the pll output range is a good thing generally as
1134 * it limits the number of possible pll combinations for a given
1135 * frequency presumably to the ones that work best on each card.
1136 * However, certain duallink DVI monitors seem to like
1137 * pll combinations that would be limited by this at least on
1138 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
1139 * family.
1140 */
1141 p1pll->pll_out_min = 64800;
1142 }
1143
1144 p1pll->pll_in_min =
1145 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1146 p1pll->pll_in_max =
1147 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1148
1149 *p2pll = *p1pll;
1150
1151 /* system clock */
1152 spll->reference_freq =
1153 le16_to_cpu(firmware_info->info.usReferenceClock);
1154 spll->reference_div = 0;
1155
1156 spll->pll_out_min =
1157 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1158 spll->pll_out_max =
1159 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1160
1161 /* ??? */
1162 if (spll->pll_out_min == 0) {
1163 if (ASIC_IS_AVIVO(rdev))
1164 spll->pll_out_min = 64800;
1165 else
1166 spll->pll_out_min = 20000;
1167 }
1168
1169 spll->pll_in_min =
1170 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1171 spll->pll_in_max =
1172 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1173
1174 /* memory clock */
1175 mpll->reference_freq =
1176 le16_to_cpu(firmware_info->info.usReferenceClock);
1177 mpll->reference_div = 0;
1178
1179 mpll->pll_out_min =
1180 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1181 mpll->pll_out_max =
1182 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1183
1184 /* ??? */
1185 if (mpll->pll_out_min == 0) {
1186 if (ASIC_IS_AVIVO(rdev))
1187 mpll->pll_out_min = 64800;
1188 else
1189 mpll->pll_out_min = 20000;
1190 }
1191
1192 mpll->pll_in_min =
1193 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1194 mpll->pll_in_max =
1195 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1196
1197 rdev->clock.default_sclk =
1198 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1199 rdev->clock.default_mclk =
1200 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1201
1202 if (ASIC_IS_DCE4(rdev)) {
1203 rdev->clock.default_dispclk =
1204 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1205 if (rdev->clock.default_dispclk == 0)
1206 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1207 rdev->clock.dp_extclk =
1208 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1209 }
1210 *dcpll = *p1pll;
1211
1212 return true;
1213 }
1214
1215 return false;
1216 }
1217
1218 union igp_info {
1219 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1220 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1221 };
1222
1223 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1224 {
1225 struct radeon_mode_info *mode_info = &rdev->mode_info;
1226 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1227 union igp_info *igp_info;
1228 u8 frev, crev;
1229 u16 data_offset;
1230
1231 /* sideport is AMD only */
1232 if (rdev->family == CHIP_RS600)
1233 return false;
1234
1235 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1236 &frev, &crev, &data_offset)) {
1237 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1238 data_offset);
1239 switch (crev) {
1240 case 1:
1241 if (igp_info->info.ulBootUpMemoryClock)
1242 return true;
1243 break;
1244 case 2:
1245 if (igp_info->info_2.ulBootUpSidePortClock)
1246 return true;
1247 break;
1248 default:
1249 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1250 break;
1251 }
1252 }
1253 return false;
1254 }
1255
1256 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1257 struct radeon_encoder_int_tmds *tmds)
1258 {
1259 struct drm_device *dev = encoder->base.dev;
1260 struct radeon_device *rdev = dev->dev_private;
1261 struct radeon_mode_info *mode_info = &rdev->mode_info;
1262 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1263 uint16_t data_offset;
1264 struct _ATOM_TMDS_INFO *tmds_info;
1265 uint8_t frev, crev;
1266 uint16_t maxfreq;
1267 int i;
1268
1269 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1270 &frev, &crev, &data_offset)) {
1271 tmds_info =
1272 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1273 data_offset);
1274
1275 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1276 for (i = 0; i < 4; i++) {
1277 tmds->tmds_pll[i].freq =
1278 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1279 tmds->tmds_pll[i].value =
1280 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1281 tmds->tmds_pll[i].value |=
1282 (tmds_info->asMiscInfo[i].
1283 ucPLL_VCO_Gain & 0x3f) << 6;
1284 tmds->tmds_pll[i].value |=
1285 (tmds_info->asMiscInfo[i].
1286 ucPLL_DutyCycle & 0xf) << 12;
1287 tmds->tmds_pll[i].value |=
1288 (tmds_info->asMiscInfo[i].
1289 ucPLL_VoltageSwing & 0xf) << 16;
1290
1291 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1292 tmds->tmds_pll[i].freq,
1293 tmds->tmds_pll[i].value);
1294
1295 if (maxfreq == tmds->tmds_pll[i].freq) {
1296 tmds->tmds_pll[i].freq = 0xffffffff;
1297 break;
1298 }
1299 }
1300 return true;
1301 }
1302 return false;
1303 }
1304
1305 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1306 struct radeon_atom_ss *ss,
1307 int id)
1308 {
1309 struct radeon_mode_info *mode_info = &rdev->mode_info;
1310 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1311 uint16_t data_offset, size;
1312 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1313 uint8_t frev, crev;
1314 int i, num_indices;
1315
1316 memset(ss, 0, sizeof(struct radeon_atom_ss));
1317 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1318 &frev, &crev, &data_offset)) {
1319 ss_info =
1320 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1321
1322 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1323 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1324
1325 for (i = 0; i < num_indices; i++) {
1326 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1327 ss->percentage =
1328 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1329 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1330 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1331 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1332 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1333 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1334 return true;
1335 }
1336 }
1337 }
1338 return false;
1339 }
1340
1341 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1342 struct radeon_atom_ss *ss,
1343 int id)
1344 {
1345 struct radeon_mode_info *mode_info = &rdev->mode_info;
1346 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1347 u16 data_offset, size;
1348 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info;
1349 u8 frev, crev;
1350 u16 percentage = 0, rate = 0;
1351
1352 /* get any igp specific overrides */
1353 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1354 &frev, &crev, &data_offset)) {
1355 igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *)
1356 (mode_info->atom_context->bios + data_offset);
1357 switch (id) {
1358 case ASIC_INTERNAL_SS_ON_TMDS:
1359 percentage = le16_to_cpu(igp_info->usDVISSPercentage);
1360 rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz);
1361 break;
1362 case ASIC_INTERNAL_SS_ON_HDMI:
1363 percentage = le16_to_cpu(igp_info->usHDMISSPercentage);
1364 rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz);
1365 break;
1366 case ASIC_INTERNAL_SS_ON_LVDS:
1367 percentage = le16_to_cpu(igp_info->usLvdsSSPercentage);
1368 rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz);
1369 break;
1370 }
1371 if (percentage)
1372 ss->percentage = percentage;
1373 if (rate)
1374 ss->rate = rate;
1375 }
1376 }
1377
1378 union asic_ss_info {
1379 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1380 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1381 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1382 };
1383
1384 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1385 struct radeon_atom_ss *ss,
1386 int id, u32 clock)
1387 {
1388 struct radeon_mode_info *mode_info = &rdev->mode_info;
1389 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1390 uint16_t data_offset, size;
1391 union asic_ss_info *ss_info;
1392 uint8_t frev, crev;
1393 int i, num_indices;
1394
1395 memset(ss, 0, sizeof(struct radeon_atom_ss));
1396 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1397 &frev, &crev, &data_offset)) {
1398
1399 ss_info =
1400 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1401
1402 switch (frev) {
1403 case 1:
1404 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1405 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1406
1407 for (i = 0; i < num_indices; i++) {
1408 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1409 (clock <= ss_info->info.asSpreadSpectrum[i].ulTargetClockRange)) {
1410 ss->percentage =
1411 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1412 ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1413 ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1414 return true;
1415 }
1416 }
1417 break;
1418 case 2:
1419 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1420 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1421 for (i = 0; i < num_indices; i++) {
1422 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1423 (clock <= ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange)) {
1424 ss->percentage =
1425 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1426 ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1427 ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1428 return true;
1429 }
1430 }
1431 break;
1432 case 3:
1433 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1434 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1435 for (i = 0; i < num_indices; i++) {
1436 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1437 (clock <= ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange)) {
1438 ss->percentage =
1439 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1440 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1441 ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1442 if (rdev->flags & RADEON_IS_IGP)
1443 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1444 return true;
1445 }
1446 }
1447 break;
1448 default:
1449 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1450 break;
1451 }
1452
1453 }
1454 return false;
1455 }
1456
1457 union lvds_info {
1458 struct _ATOM_LVDS_INFO info;
1459 struct _ATOM_LVDS_INFO_V12 info_12;
1460 };
1461
1462 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1463 radeon_encoder
1464 *encoder)
1465 {
1466 struct drm_device *dev = encoder->base.dev;
1467 struct radeon_device *rdev = dev->dev_private;
1468 struct radeon_mode_info *mode_info = &rdev->mode_info;
1469 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1470 uint16_t data_offset, misc;
1471 union lvds_info *lvds_info;
1472 uint8_t frev, crev;
1473 struct radeon_encoder_atom_dig *lvds = NULL;
1474 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1475
1476 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1477 &frev, &crev, &data_offset)) {
1478 lvds_info =
1479 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1480 lvds =
1481 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1482
1483 if (!lvds)
1484 return NULL;
1485
1486 lvds->native_mode.clock =
1487 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1488 lvds->native_mode.hdisplay =
1489 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1490 lvds->native_mode.vdisplay =
1491 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1492 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1493 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1494 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1495 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1496 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1497 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1498 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1499 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1500 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1501 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1502 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1503 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1504 lvds->panel_pwr_delay =
1505 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1506 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1507
1508 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1509 if (misc & ATOM_VSYNC_POLARITY)
1510 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1511 if (misc & ATOM_HSYNC_POLARITY)
1512 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1513 if (misc & ATOM_COMPOSITESYNC)
1514 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1515 if (misc & ATOM_INTERLACE)
1516 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1517 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1518 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1519
1520 lvds->native_mode.width_mm = lvds_info->info.sLCDTiming.usImageHSize;
1521 lvds->native_mode.height_mm = lvds_info->info.sLCDTiming.usImageVSize;
1522
1523 /* set crtc values */
1524 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1525
1526 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1527
1528 encoder->native_mode = lvds->native_mode;
1529
1530 if (encoder_enum == 2)
1531 lvds->linkb = true;
1532 else
1533 lvds->linkb = false;
1534
1535 /* parse the lcd record table */
1536 if (lvds_info->info.usModePatchTableOffset) {
1537 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1538 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1539 bool bad_record = false;
1540 u8 *record = (u8 *)(mode_info->atom_context->bios +
1541 data_offset +
1542 lvds_info->info.usModePatchTableOffset);
1543 while (*record != ATOM_RECORD_END_TYPE) {
1544 switch (*record) {
1545 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1546 record += sizeof(ATOM_PATCH_RECORD_MODE);
1547 break;
1548 case LCD_RTS_RECORD_TYPE:
1549 record += sizeof(ATOM_LCD_RTS_RECORD);
1550 break;
1551 case LCD_CAP_RECORD_TYPE:
1552 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1553 break;
1554 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1555 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1556 if (fake_edid_record->ucFakeEDIDLength) {
1557 struct edid *edid;
1558 int edid_size =
1559 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1560 edid = kmalloc(edid_size, GFP_KERNEL);
1561 if (edid) {
1562 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1563 fake_edid_record->ucFakeEDIDLength);
1564
1565 if (drm_edid_is_valid(edid))
1566 rdev->mode_info.bios_hardcoded_edid = edid;
1567 else
1568 kfree(edid);
1569 }
1570 }
1571 record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1572 break;
1573 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1574 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1575 lvds->native_mode.width_mm = panel_res_record->usHSize;
1576 lvds->native_mode.height_mm = panel_res_record->usVSize;
1577 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1578 break;
1579 default:
1580 DRM_ERROR("Bad LCD record %d\n", *record);
1581 bad_record = true;
1582 break;
1583 }
1584 if (bad_record)
1585 break;
1586 }
1587 }
1588 }
1589 return lvds;
1590 }
1591
1592 struct radeon_encoder_primary_dac *
1593 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1594 {
1595 struct drm_device *dev = encoder->base.dev;
1596 struct radeon_device *rdev = dev->dev_private;
1597 struct radeon_mode_info *mode_info = &rdev->mode_info;
1598 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1599 uint16_t data_offset;
1600 struct _COMPASSIONATE_DATA *dac_info;
1601 uint8_t frev, crev;
1602 uint8_t bg, dac;
1603 struct radeon_encoder_primary_dac *p_dac = NULL;
1604
1605 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1606 &frev, &crev, &data_offset)) {
1607 dac_info = (struct _COMPASSIONATE_DATA *)
1608 (mode_info->atom_context->bios + data_offset);
1609
1610 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1611
1612 if (!p_dac)
1613 return NULL;
1614
1615 bg = dac_info->ucDAC1_BG_Adjustment;
1616 dac = dac_info->ucDAC1_DAC_Adjustment;
1617 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1618
1619 }
1620 return p_dac;
1621 }
1622
1623 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1624 struct drm_display_mode *mode)
1625 {
1626 struct radeon_mode_info *mode_info = &rdev->mode_info;
1627 ATOM_ANALOG_TV_INFO *tv_info;
1628 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1629 ATOM_DTD_FORMAT *dtd_timings;
1630 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1631 u8 frev, crev;
1632 u16 data_offset, misc;
1633
1634 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1635 &frev, &crev, &data_offset))
1636 return false;
1637
1638 switch (crev) {
1639 case 1:
1640 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1641 if (index >= MAX_SUPPORTED_TV_TIMING)
1642 return false;
1643
1644 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1645 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1646 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1647 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1648 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1649
1650 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1651 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1652 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1653 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1654 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1655
1656 mode->flags = 0;
1657 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1658 if (misc & ATOM_VSYNC_POLARITY)
1659 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1660 if (misc & ATOM_HSYNC_POLARITY)
1661 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1662 if (misc & ATOM_COMPOSITESYNC)
1663 mode->flags |= DRM_MODE_FLAG_CSYNC;
1664 if (misc & ATOM_INTERLACE)
1665 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1666 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1667 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1668
1669 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1670
1671 if (index == 1) {
1672 /* PAL timings appear to have wrong values for totals */
1673 mode->crtc_htotal -= 1;
1674 mode->crtc_vtotal -= 1;
1675 }
1676 break;
1677 case 2:
1678 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1679 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1680 return false;
1681
1682 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1683 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1684 le16_to_cpu(dtd_timings->usHBlanking_Time);
1685 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1686 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1687 le16_to_cpu(dtd_timings->usHSyncOffset);
1688 mode->crtc_hsync_end = mode->crtc_hsync_start +
1689 le16_to_cpu(dtd_timings->usHSyncWidth);
1690
1691 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1692 le16_to_cpu(dtd_timings->usVBlanking_Time);
1693 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1694 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1695 le16_to_cpu(dtd_timings->usVSyncOffset);
1696 mode->crtc_vsync_end = mode->crtc_vsync_start +
1697 le16_to_cpu(dtd_timings->usVSyncWidth);
1698
1699 mode->flags = 0;
1700 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1701 if (misc & ATOM_VSYNC_POLARITY)
1702 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1703 if (misc & ATOM_HSYNC_POLARITY)
1704 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1705 if (misc & ATOM_COMPOSITESYNC)
1706 mode->flags |= DRM_MODE_FLAG_CSYNC;
1707 if (misc & ATOM_INTERLACE)
1708 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1709 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1710 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1711
1712 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1713 break;
1714 }
1715 return true;
1716 }
1717
1718 enum radeon_tv_std
1719 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1720 {
1721 struct radeon_mode_info *mode_info = &rdev->mode_info;
1722 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1723 uint16_t data_offset;
1724 uint8_t frev, crev;
1725 struct _ATOM_ANALOG_TV_INFO *tv_info;
1726 enum radeon_tv_std tv_std = TV_STD_NTSC;
1727
1728 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1729 &frev, &crev, &data_offset)) {
1730
1731 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1732 (mode_info->atom_context->bios + data_offset);
1733
1734 switch (tv_info->ucTV_BootUpDefaultStandard) {
1735 case ATOM_TV_NTSC:
1736 tv_std = TV_STD_NTSC;
1737 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1738 break;
1739 case ATOM_TV_NTSCJ:
1740 tv_std = TV_STD_NTSC_J;
1741 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1742 break;
1743 case ATOM_TV_PAL:
1744 tv_std = TV_STD_PAL;
1745 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1746 break;
1747 case ATOM_TV_PALM:
1748 tv_std = TV_STD_PAL_M;
1749 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1750 break;
1751 case ATOM_TV_PALN:
1752 tv_std = TV_STD_PAL_N;
1753 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1754 break;
1755 case ATOM_TV_PALCN:
1756 tv_std = TV_STD_PAL_CN;
1757 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1758 break;
1759 case ATOM_TV_PAL60:
1760 tv_std = TV_STD_PAL_60;
1761 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1762 break;
1763 case ATOM_TV_SECAM:
1764 tv_std = TV_STD_SECAM;
1765 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1766 break;
1767 default:
1768 tv_std = TV_STD_NTSC;
1769 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1770 break;
1771 }
1772 }
1773 return tv_std;
1774 }
1775
1776 struct radeon_encoder_tv_dac *
1777 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1778 {
1779 struct drm_device *dev = encoder->base.dev;
1780 struct radeon_device *rdev = dev->dev_private;
1781 struct radeon_mode_info *mode_info = &rdev->mode_info;
1782 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1783 uint16_t data_offset;
1784 struct _COMPASSIONATE_DATA *dac_info;
1785 uint8_t frev, crev;
1786 uint8_t bg, dac;
1787 struct radeon_encoder_tv_dac *tv_dac = NULL;
1788
1789 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1790 &frev, &crev, &data_offset)) {
1791
1792 dac_info = (struct _COMPASSIONATE_DATA *)
1793 (mode_info->atom_context->bios + data_offset);
1794
1795 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1796
1797 if (!tv_dac)
1798 return NULL;
1799
1800 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1801 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1802 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1803
1804 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1805 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1806 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1807
1808 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1809 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1810 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1811
1812 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1813 }
1814 return tv_dac;
1815 }
1816
1817 static const char *thermal_controller_names[] = {
1818 "NONE",
1819 "lm63",
1820 "adm1032",
1821 "adm1030",
1822 "max6649",
1823 "lm64",
1824 "f75375",
1825 "asc7xxx",
1826 };
1827
1828 static const char *pp_lib_thermal_controller_names[] = {
1829 "NONE",
1830 "lm63",
1831 "adm1032",
1832 "adm1030",
1833 "max6649",
1834 "lm64",
1835 "f75375",
1836 "RV6xx",
1837 "RV770",
1838 "adt7473",
1839 "NONE",
1840 "External GPIO",
1841 "Evergreen",
1842 "emc2103",
1843 "Sumo",
1844 };
1845
1846 union power_info {
1847 struct _ATOM_POWERPLAY_INFO info;
1848 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1849 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1850 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1851 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1852 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1853 };
1854
1855 union pplib_clock_info {
1856 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1857 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1858 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1859 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1860 };
1861
1862 union pplib_power_state {
1863 struct _ATOM_PPLIB_STATE v1;
1864 struct _ATOM_PPLIB_STATE_V2 v2;
1865 };
1866
1867 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1868 int state_index,
1869 u32 misc, u32 misc2)
1870 {
1871 rdev->pm.power_state[state_index].misc = misc;
1872 rdev->pm.power_state[state_index].misc2 = misc2;
1873 /* order matters! */
1874 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1875 rdev->pm.power_state[state_index].type =
1876 POWER_STATE_TYPE_POWERSAVE;
1877 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1878 rdev->pm.power_state[state_index].type =
1879 POWER_STATE_TYPE_BATTERY;
1880 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1881 rdev->pm.power_state[state_index].type =
1882 POWER_STATE_TYPE_BATTERY;
1883 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1884 rdev->pm.power_state[state_index].type =
1885 POWER_STATE_TYPE_BALANCED;
1886 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1887 rdev->pm.power_state[state_index].type =
1888 POWER_STATE_TYPE_PERFORMANCE;
1889 rdev->pm.power_state[state_index].flags &=
1890 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1891 }
1892 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1893 rdev->pm.power_state[state_index].type =
1894 POWER_STATE_TYPE_BALANCED;
1895 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1896 rdev->pm.power_state[state_index].type =
1897 POWER_STATE_TYPE_DEFAULT;
1898 rdev->pm.default_power_state_index = state_index;
1899 rdev->pm.power_state[state_index].default_clock_mode =
1900 &rdev->pm.power_state[state_index].clock_info[0];
1901 } else if (state_index == 0) {
1902 rdev->pm.power_state[state_index].clock_info[0].flags |=
1903 RADEON_PM_MODE_NO_DISPLAY;
1904 }
1905 }
1906
1907 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
1908 {
1909 struct radeon_mode_info *mode_info = &rdev->mode_info;
1910 u32 misc, misc2 = 0;
1911 int num_modes = 0, i;
1912 int state_index = 0;
1913 struct radeon_i2c_bus_rec i2c_bus;
1914 union power_info *power_info;
1915 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1916 u16 data_offset;
1917 u8 frev, crev;
1918
1919 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1920 &frev, &crev, &data_offset))
1921 return state_index;
1922 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1923
1924 /* add the i2c bus for thermal/fan chip */
1925 if (power_info->info.ucOverdriveThermalController > 0) {
1926 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1927 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1928 power_info->info.ucOverdriveControllerAddress >> 1);
1929 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1930 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1931 if (rdev->pm.i2c_bus) {
1932 struct i2c_board_info info = { };
1933 const char *name = thermal_controller_names[power_info->info.
1934 ucOverdriveThermalController];
1935 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1936 strlcpy(info.type, name, sizeof(info.type));
1937 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1938 }
1939 }
1940 num_modes = power_info->info.ucNumOfPowerModeEntries;
1941 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1942 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1943 /* last mode is usually default, array is low to high */
1944 for (i = 0; i < num_modes; i++) {
1945 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1946 switch (frev) {
1947 case 1:
1948 rdev->pm.power_state[state_index].num_clock_modes = 1;
1949 rdev->pm.power_state[state_index].clock_info[0].mclk =
1950 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1951 rdev->pm.power_state[state_index].clock_info[0].sclk =
1952 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1953 /* skip invalid modes */
1954 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1955 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1956 continue;
1957 rdev->pm.power_state[state_index].pcie_lanes =
1958 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1959 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1960 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1961 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1962 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1963 VOLTAGE_GPIO;
1964 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1965 radeon_lookup_gpio(rdev,
1966 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1967 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1968 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1969 true;
1970 else
1971 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1972 false;
1973 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1974 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1975 VOLTAGE_VDDC;
1976 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1977 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1978 }
1979 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1980 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
1981 state_index++;
1982 break;
1983 case 2:
1984 rdev->pm.power_state[state_index].num_clock_modes = 1;
1985 rdev->pm.power_state[state_index].clock_info[0].mclk =
1986 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1987 rdev->pm.power_state[state_index].clock_info[0].sclk =
1988 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1989 /* skip invalid modes */
1990 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1991 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1992 continue;
1993 rdev->pm.power_state[state_index].pcie_lanes =
1994 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1995 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1996 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1997 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1998 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1999 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2000 VOLTAGE_GPIO;
2001 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2002 radeon_lookup_gpio(rdev,
2003 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2004 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2005 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2006 true;
2007 else
2008 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2009 false;
2010 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2011 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2012 VOLTAGE_VDDC;
2013 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2014 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2015 }
2016 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2017 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2018 state_index++;
2019 break;
2020 case 3:
2021 rdev->pm.power_state[state_index].num_clock_modes = 1;
2022 rdev->pm.power_state[state_index].clock_info[0].mclk =
2023 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2024 rdev->pm.power_state[state_index].clock_info[0].sclk =
2025 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2026 /* skip invalid modes */
2027 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2028 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2029 continue;
2030 rdev->pm.power_state[state_index].pcie_lanes =
2031 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2032 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2033 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2034 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2035 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2036 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2037 VOLTAGE_GPIO;
2038 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2039 radeon_lookup_gpio(rdev,
2040 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2041 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2042 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2043 true;
2044 else
2045 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2046 false;
2047 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2048 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2049 VOLTAGE_VDDC;
2050 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2051 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2052 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2053 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2054 true;
2055 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2056 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2057 }
2058 }
2059 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2060 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2061 state_index++;
2062 break;
2063 }
2064 }
2065 /* last mode is usually default */
2066 if (rdev->pm.default_power_state_index == -1) {
2067 rdev->pm.power_state[state_index - 1].type =
2068 POWER_STATE_TYPE_DEFAULT;
2069 rdev->pm.default_power_state_index = state_index - 1;
2070 rdev->pm.power_state[state_index - 1].default_clock_mode =
2071 &rdev->pm.power_state[state_index - 1].clock_info[0];
2072 rdev->pm.power_state[state_index].flags &=
2073 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2074 rdev->pm.power_state[state_index].misc = 0;
2075 rdev->pm.power_state[state_index].misc2 = 0;
2076 }
2077 return state_index;
2078 }
2079
2080 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2081 ATOM_PPLIB_THERMALCONTROLLER *controller)
2082 {
2083 struct radeon_i2c_bus_rec i2c_bus;
2084
2085 /* add the i2c bus for thermal/fan chip */
2086 if (controller->ucType > 0) {
2087 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2088 DRM_INFO("Internal thermal controller %s fan control\n",
2089 (controller->ucFanParameters &
2090 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2091 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2092 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2093 DRM_INFO("Internal thermal controller %s fan control\n",
2094 (controller->ucFanParameters &
2095 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2096 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2097 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2098 DRM_INFO("Internal thermal controller %s fan control\n",
2099 (controller->ucFanParameters &
2100 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2101 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2102 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2103 DRM_INFO("Internal thermal controller %s fan control\n",
2104 (controller->ucFanParameters &
2105 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2106 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2107 } else if ((controller->ucType ==
2108 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2109 (controller->ucType ==
2110 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2111 (controller->ucType ==
2112 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2113 DRM_INFO("Special thermal controller config\n");
2114 } else {
2115 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2116 pp_lib_thermal_controller_names[controller->ucType],
2117 controller->ucI2cAddress >> 1,
2118 (controller->ucFanParameters &
2119 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2120 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2121 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2122 if (rdev->pm.i2c_bus) {
2123 struct i2c_board_info info = { };
2124 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2125 info.addr = controller->ucI2cAddress >> 1;
2126 strlcpy(info.type, name, sizeof(info.type));
2127 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2128 }
2129 }
2130 }
2131 }
2132
2133 static u16 radeon_atombios_get_default_vddc(struct radeon_device *rdev)
2134 {
2135 struct radeon_mode_info *mode_info = &rdev->mode_info;
2136 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2137 u8 frev, crev;
2138 u16 data_offset;
2139 union firmware_info *firmware_info;
2140 u16 vddc = 0;
2141
2142 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2143 &frev, &crev, &data_offset)) {
2144 firmware_info =
2145 (union firmware_info *)(mode_info->atom_context->bios +
2146 data_offset);
2147 vddc = firmware_info->info_14.usBootUpVDDCVoltage;
2148 }
2149
2150 return vddc;
2151 }
2152
2153 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2154 int state_index, int mode_index,
2155 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2156 {
2157 int j;
2158 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2159 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2160 u16 vddc = radeon_atombios_get_default_vddc(rdev);
2161
2162 rdev->pm.power_state[state_index].misc = misc;
2163 rdev->pm.power_state[state_index].misc2 = misc2;
2164 rdev->pm.power_state[state_index].pcie_lanes =
2165 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2166 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2167 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2168 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2169 rdev->pm.power_state[state_index].type =
2170 POWER_STATE_TYPE_BATTERY;
2171 break;
2172 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2173 rdev->pm.power_state[state_index].type =
2174 POWER_STATE_TYPE_BALANCED;
2175 break;
2176 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2177 rdev->pm.power_state[state_index].type =
2178 POWER_STATE_TYPE_PERFORMANCE;
2179 break;
2180 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2181 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2182 rdev->pm.power_state[state_index].type =
2183 POWER_STATE_TYPE_PERFORMANCE;
2184 break;
2185 }
2186 rdev->pm.power_state[state_index].flags = 0;
2187 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2188 rdev->pm.power_state[state_index].flags |=
2189 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2190 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2191 rdev->pm.power_state[state_index].type =
2192 POWER_STATE_TYPE_DEFAULT;
2193 rdev->pm.default_power_state_index = state_index;
2194 rdev->pm.power_state[state_index].default_clock_mode =
2195 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2196 /* patch the table values with the default slck/mclk from firmware info */
2197 for (j = 0; j < mode_index; j++) {
2198 rdev->pm.power_state[state_index].clock_info[j].mclk =
2199 rdev->clock.default_mclk;
2200 rdev->pm.power_state[state_index].clock_info[j].sclk =
2201 rdev->clock.default_sclk;
2202 if (vddc)
2203 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2204 vddc;
2205 }
2206 }
2207 }
2208
2209 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2210 int state_index, int mode_index,
2211 union pplib_clock_info *clock_info)
2212 {
2213 u32 sclk, mclk;
2214
2215 if (rdev->flags & RADEON_IS_IGP) {
2216 if (rdev->family >= CHIP_PALM) {
2217 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2218 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2219 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2220 } else {
2221 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2222 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2223 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2224 }
2225 } else if (ASIC_IS_DCE4(rdev)) {
2226 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2227 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2228 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2229 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2230 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2231 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2232 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2233 VOLTAGE_SW;
2234 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2235 clock_info->evergreen.usVDDC;
2236 } else {
2237 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2238 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2239 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2240 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2241 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2242 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2243 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2244 VOLTAGE_SW;
2245 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2246 clock_info->r600.usVDDC;
2247 }
2248
2249 if (rdev->flags & RADEON_IS_IGP) {
2250 /* skip invalid modes */
2251 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2252 return false;
2253 } else {
2254 /* skip invalid modes */
2255 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2256 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2257 return false;
2258 }
2259 return true;
2260 }
2261
2262 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2263 {
2264 struct radeon_mode_info *mode_info = &rdev->mode_info;
2265 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2266 union pplib_power_state *power_state;
2267 int i, j;
2268 int state_index = 0, mode_index = 0;
2269 union pplib_clock_info *clock_info;
2270 bool valid;
2271 union power_info *power_info;
2272 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2273 u16 data_offset;
2274 u8 frev, crev;
2275
2276 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2277 &frev, &crev, &data_offset))
2278 return state_index;
2279 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2280
2281 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2282 /* first mode is usually default, followed by low to high */
2283 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2284 mode_index = 0;
2285 power_state = (union pplib_power_state *)
2286 (mode_info->atom_context->bios + data_offset +
2287 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2288 i * power_info->pplib.ucStateEntrySize);
2289 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2290 (mode_info->atom_context->bios + data_offset +
2291 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2292 (power_state->v1.ucNonClockStateIndex *
2293 power_info->pplib.ucNonClockSize));
2294 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2295 clock_info = (union pplib_clock_info *)
2296 (mode_info->atom_context->bios + data_offset +
2297 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2298 (power_state->v1.ucClockStateIndices[j] *
2299 power_info->pplib.ucClockInfoSize));
2300 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2301 state_index, mode_index,
2302 clock_info);
2303 if (valid)
2304 mode_index++;
2305 }
2306 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2307 if (mode_index) {
2308 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2309 non_clock_info);
2310 state_index++;
2311 }
2312 }
2313 /* if multiple clock modes, mark the lowest as no display */
2314 for (i = 0; i < state_index; i++) {
2315 if (rdev->pm.power_state[i].num_clock_modes > 1)
2316 rdev->pm.power_state[i].clock_info[0].flags |=
2317 RADEON_PM_MODE_NO_DISPLAY;
2318 }
2319 /* first mode is usually default */
2320 if (rdev->pm.default_power_state_index == -1) {
2321 rdev->pm.power_state[0].type =
2322 POWER_STATE_TYPE_DEFAULT;
2323 rdev->pm.default_power_state_index = 0;
2324 rdev->pm.power_state[0].default_clock_mode =
2325 &rdev->pm.power_state[0].clock_info[0];
2326 }
2327 return state_index;
2328 }
2329
2330 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2331 {
2332 struct radeon_mode_info *mode_info = &rdev->mode_info;
2333 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2334 union pplib_power_state *power_state;
2335 int i, j, non_clock_array_index, clock_array_index;
2336 int state_index = 0, mode_index = 0;
2337 union pplib_clock_info *clock_info;
2338 struct StateArray *state_array;
2339 struct ClockInfoArray *clock_info_array;
2340 struct NonClockInfoArray *non_clock_info_array;
2341 bool valid;
2342 union power_info *power_info;
2343 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2344 u16 data_offset;
2345 u8 frev, crev;
2346
2347 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2348 &frev, &crev, &data_offset))
2349 return state_index;
2350 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2351
2352 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2353 state_array = (struct StateArray *)
2354 (mode_info->atom_context->bios + data_offset +
2355 power_info->pplib.usStateArrayOffset);
2356 clock_info_array = (struct ClockInfoArray *)
2357 (mode_info->atom_context->bios + data_offset +
2358 power_info->pplib.usClockInfoArrayOffset);
2359 non_clock_info_array = (struct NonClockInfoArray *)
2360 (mode_info->atom_context->bios + data_offset +
2361 power_info->pplib.usNonClockInfoArrayOffset);
2362 for (i = 0; i < state_array->ucNumEntries; i++) {
2363 mode_index = 0;
2364 power_state = (union pplib_power_state *)&state_array->states[i];
2365 /* XXX this might be an inagua bug... */
2366 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
2367 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2368 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2369 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2370 clock_array_index = power_state->v2.clockInfoIndex[j];
2371 /* XXX this might be an inagua bug... */
2372 if (clock_array_index >= clock_info_array->ucNumEntries)
2373 continue;
2374 clock_info = (union pplib_clock_info *)
2375 &clock_info_array->clockInfo[clock_array_index];
2376 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2377 state_index, mode_index,
2378 clock_info);
2379 if (valid)
2380 mode_index++;
2381 }
2382 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2383 if (mode_index) {
2384 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2385 non_clock_info);
2386 state_index++;
2387 }
2388 }
2389 /* if multiple clock modes, mark the lowest as no display */
2390 for (i = 0; i < state_index; i++) {
2391 if (rdev->pm.power_state[i].num_clock_modes > 1)
2392 rdev->pm.power_state[i].clock_info[0].flags |=
2393 RADEON_PM_MODE_NO_DISPLAY;
2394 }
2395 /* first mode is usually default */
2396 if (rdev->pm.default_power_state_index == -1) {
2397 rdev->pm.power_state[0].type =
2398 POWER_STATE_TYPE_DEFAULT;
2399 rdev->pm.default_power_state_index = 0;
2400 rdev->pm.power_state[0].default_clock_mode =
2401 &rdev->pm.power_state[0].clock_info[0];
2402 }
2403 return state_index;
2404 }
2405
2406 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2407 {
2408 struct radeon_mode_info *mode_info = &rdev->mode_info;
2409 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2410 u16 data_offset;
2411 u8 frev, crev;
2412 int state_index = 0;
2413
2414 rdev->pm.default_power_state_index = -1;
2415
2416 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2417 &frev, &crev, &data_offset)) {
2418 switch (frev) {
2419 case 1:
2420 case 2:
2421 case 3:
2422 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2423 break;
2424 case 4:
2425 case 5:
2426 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2427 break;
2428 case 6:
2429 state_index = radeon_atombios_parse_power_table_6(rdev);
2430 break;
2431 default:
2432 break;
2433 }
2434 } else {
2435 /* add the default mode */
2436 rdev->pm.power_state[state_index].type =
2437 POWER_STATE_TYPE_DEFAULT;
2438 rdev->pm.power_state[state_index].num_clock_modes = 1;
2439 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2440 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2441 rdev->pm.power_state[state_index].default_clock_mode =
2442 &rdev->pm.power_state[state_index].clock_info[0];
2443 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2444 rdev->pm.power_state[state_index].pcie_lanes = 16;
2445 rdev->pm.default_power_state_index = state_index;
2446 rdev->pm.power_state[state_index].flags = 0;
2447 state_index++;
2448 }
2449
2450 rdev->pm.num_power_states = state_index;
2451
2452 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2453 rdev->pm.current_clock_mode_index = 0;
2454 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2455 }
2456
2457 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2458 {
2459 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2460 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2461
2462 args.ucEnable = enable;
2463
2464 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2465 }
2466
2467 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2468 {
2469 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2470 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2471
2472 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2473 return args.ulReturnEngineClock;
2474 }
2475
2476 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2477 {
2478 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2479 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2480
2481 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2482 return args.ulReturnMemoryClock;
2483 }
2484
2485 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2486 uint32_t eng_clock)
2487 {
2488 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2489 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2490
2491 args.ulTargetEngineClock = eng_clock; /* 10 khz */
2492
2493 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2494 }
2495
2496 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2497 uint32_t mem_clock)
2498 {
2499 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2500 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2501
2502 if (rdev->flags & RADEON_IS_IGP)
2503 return;
2504
2505 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
2506
2507 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2508 }
2509
2510 union set_voltage {
2511 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2512 struct _SET_VOLTAGE_PARAMETERS v1;
2513 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2514 };
2515
2516 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level)
2517 {
2518 union set_voltage args;
2519 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2520 u8 frev, crev, volt_index = level;
2521
2522 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2523 return;
2524
2525 switch (crev) {
2526 case 1:
2527 args.v1.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2528 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2529 args.v1.ucVoltageIndex = volt_index;
2530 break;
2531 case 2:
2532 args.v2.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2533 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2534 args.v2.usVoltageLevel = cpu_to_le16(level);
2535 break;
2536 default:
2537 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2538 return;
2539 }
2540
2541 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2542 }
2543
2544
2545
2546 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2547 {
2548 struct radeon_device *rdev = dev->dev_private;
2549 uint32_t bios_2_scratch, bios_6_scratch;
2550
2551 if (rdev->family >= CHIP_R600) {
2552 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2553 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2554 } else {
2555 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2556 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2557 }
2558
2559 /* let the bios control the backlight */
2560 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2561
2562 /* tell the bios not to handle mode switching */
2563 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
2564
2565 if (rdev->family >= CHIP_R600) {
2566 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2567 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2568 } else {
2569 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2570 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2571 }
2572
2573 }
2574
2575 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2576 {
2577 uint32_t scratch_reg;
2578 int i;
2579
2580 if (rdev->family >= CHIP_R600)
2581 scratch_reg = R600_BIOS_0_SCRATCH;
2582 else
2583 scratch_reg = RADEON_BIOS_0_SCRATCH;
2584
2585 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2586 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2587 }
2588
2589 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2590 {
2591 uint32_t scratch_reg;
2592 int i;
2593
2594 if (rdev->family >= CHIP_R600)
2595 scratch_reg = R600_BIOS_0_SCRATCH;
2596 else
2597 scratch_reg = RADEON_BIOS_0_SCRATCH;
2598
2599 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2600 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2601 }
2602
2603 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2604 {
2605 struct drm_device *dev = encoder->dev;
2606 struct radeon_device *rdev = dev->dev_private;
2607 uint32_t bios_6_scratch;
2608
2609 if (rdev->family >= CHIP_R600)
2610 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2611 else
2612 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2613
2614 if (lock)
2615 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2616 else
2617 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2618
2619 if (rdev->family >= CHIP_R600)
2620 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2621 else
2622 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2623 }
2624
2625 /* at some point we may want to break this out into individual functions */
2626 void
2627 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2628 struct drm_encoder *encoder,
2629 bool connected)
2630 {
2631 struct drm_device *dev = connector->dev;
2632 struct radeon_device *rdev = dev->dev_private;
2633 struct radeon_connector *radeon_connector =
2634 to_radeon_connector(connector);
2635 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2636 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2637
2638 if (rdev->family >= CHIP_R600) {
2639 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2640 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2641 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2642 } else {
2643 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2644 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2645 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2646 }
2647
2648 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2649 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2650 if (connected) {
2651 DRM_DEBUG_KMS("TV1 connected\n");
2652 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2653 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2654 } else {
2655 DRM_DEBUG_KMS("TV1 disconnected\n");
2656 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2657 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2658 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2659 }
2660 }
2661 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2662 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2663 if (connected) {
2664 DRM_DEBUG_KMS("CV connected\n");
2665 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2666 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2667 } else {
2668 DRM_DEBUG_KMS("CV disconnected\n");
2669 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2670 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2671 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2672 }
2673 }
2674 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2675 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2676 if (connected) {
2677 DRM_DEBUG_KMS("LCD1 connected\n");
2678 bios_0_scratch |= ATOM_S0_LCD1;
2679 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2680 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2681 } else {
2682 DRM_DEBUG_KMS("LCD1 disconnected\n");
2683 bios_0_scratch &= ~ATOM_S0_LCD1;
2684 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2685 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2686 }
2687 }
2688 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2689 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2690 if (connected) {
2691 DRM_DEBUG_KMS("CRT1 connected\n");
2692 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2693 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2694 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2695 } else {
2696 DRM_DEBUG_KMS("CRT1 disconnected\n");
2697 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2698 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2699 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2700 }
2701 }
2702 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2703 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2704 if (connected) {
2705 DRM_DEBUG_KMS("CRT2 connected\n");
2706 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2707 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2708 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2709 } else {
2710 DRM_DEBUG_KMS("CRT2 disconnected\n");
2711 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2712 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2713 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2714 }
2715 }
2716 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2717 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2718 if (connected) {
2719 DRM_DEBUG_KMS("DFP1 connected\n");
2720 bios_0_scratch |= ATOM_S0_DFP1;
2721 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2722 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2723 } else {
2724 DRM_DEBUG_KMS("DFP1 disconnected\n");
2725 bios_0_scratch &= ~ATOM_S0_DFP1;
2726 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2727 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2728 }
2729 }
2730 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2731 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2732 if (connected) {
2733 DRM_DEBUG_KMS("DFP2 connected\n");
2734 bios_0_scratch |= ATOM_S0_DFP2;
2735 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2736 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2737 } else {
2738 DRM_DEBUG_KMS("DFP2 disconnected\n");
2739 bios_0_scratch &= ~ATOM_S0_DFP2;
2740 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2741 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2742 }
2743 }
2744 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2745 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2746 if (connected) {
2747 DRM_DEBUG_KMS("DFP3 connected\n");
2748 bios_0_scratch |= ATOM_S0_DFP3;
2749 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2750 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2751 } else {
2752 DRM_DEBUG_KMS("DFP3 disconnected\n");
2753 bios_0_scratch &= ~ATOM_S0_DFP3;
2754 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2755 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2756 }
2757 }
2758 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2759 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2760 if (connected) {
2761 DRM_DEBUG_KMS("DFP4 connected\n");
2762 bios_0_scratch |= ATOM_S0_DFP4;
2763 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2764 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2765 } else {
2766 DRM_DEBUG_KMS("DFP4 disconnected\n");
2767 bios_0_scratch &= ~ATOM_S0_DFP4;
2768 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2769 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2770 }
2771 }
2772 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2773 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2774 if (connected) {
2775 DRM_DEBUG_KMS("DFP5 connected\n");
2776 bios_0_scratch |= ATOM_S0_DFP5;
2777 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2778 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2779 } else {
2780 DRM_DEBUG_KMS("DFP5 disconnected\n");
2781 bios_0_scratch &= ~ATOM_S0_DFP5;
2782 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2783 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2784 }
2785 }
2786
2787 if (rdev->family >= CHIP_R600) {
2788 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2789 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2790 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2791 } else {
2792 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2793 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2794 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2795 }
2796 }
2797
2798 void
2799 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2800 {
2801 struct drm_device *dev = encoder->dev;
2802 struct radeon_device *rdev = dev->dev_private;
2803 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2804 uint32_t bios_3_scratch;
2805
2806 if (rdev->family >= CHIP_R600)
2807 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2808 else
2809 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2810
2811 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2812 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2813 bios_3_scratch |= (crtc << 18);
2814 }
2815 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2816 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2817 bios_3_scratch |= (crtc << 24);
2818 }
2819 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2820 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2821 bios_3_scratch |= (crtc << 16);
2822 }
2823 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2824 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2825 bios_3_scratch |= (crtc << 20);
2826 }
2827 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2828 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2829 bios_3_scratch |= (crtc << 17);
2830 }
2831 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2832 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2833 bios_3_scratch |= (crtc << 19);
2834 }
2835 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2836 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2837 bios_3_scratch |= (crtc << 23);
2838 }
2839 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2840 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2841 bios_3_scratch |= (crtc << 25);
2842 }
2843
2844 if (rdev->family >= CHIP_R600)
2845 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2846 else
2847 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2848 }
2849
2850 void
2851 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2852 {
2853 struct drm_device *dev = encoder->dev;
2854 struct radeon_device *rdev = dev->dev_private;
2855 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2856 uint32_t bios_2_scratch;
2857
2858 if (rdev->family >= CHIP_R600)
2859 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2860 else
2861 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2862
2863 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2864 if (on)
2865 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2866 else
2867 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2868 }
2869 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2870 if (on)
2871 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2872 else
2873 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2874 }
2875 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2876 if (on)
2877 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2878 else
2879 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2880 }
2881 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2882 if (on)
2883 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2884 else
2885 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2886 }
2887 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2888 if (on)
2889 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2890 else
2891 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2892 }
2893 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2894 if (on)
2895 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2896 else
2897 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2898 }
2899 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2900 if (on)
2901 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2902 else
2903 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2904 }
2905 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2906 if (on)
2907 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2908 else
2909 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2910 }
2911 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2912 if (on)
2913 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2914 else
2915 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2916 }
2917 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2918 if (on)
2919 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2920 else
2921 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2922 }
2923
2924 if (rdev->family >= CHIP_R600)
2925 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2926 else
2927 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2928 }
Linus' kernel tree