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Staging: et131x: Clean up number fields
[linux-2.6.git] / drivers / staging / et131x / et1310_address_map.h
blob019588d131274d1c5eb33a1e5c46d4d343cac705
1 /*
2 * Agere Systems Inc.
3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
4 *
5 * Copyright © 2005 Agere Systems Inc.
6 * All rights reserved.
7 * http://www.agere.com
8 *
9 *------------------------------------------------------------------------------
10 *
11 * et1310_address_map.h - Contains the register mapping for the ET1310
12 *
13 *------------------------------------------------------------------------------
14 *
15 * SOFTWARE LICENSE
16 *
17 * This software is provided subject to the following terms and conditions,
18 * which you should read carefully before using the software. Using this
19 * software indicates your acceptance of these terms and conditions. If you do
20 * not agree with these terms and conditions, do not use the software.
21 *
22 * Copyright © 2005 Agere Systems Inc.
23 * All rights reserved.
24 *
25 * Redistribution and use in source or binary forms, with or without
26 * modifications, are permitted provided that the following conditions are met:
27 *
28 * . Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following Disclaimer as comments in the code as
30 * well as in the documentation and/or other materials provided with the
31 * distribution.
32 *
33 * . Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following Disclaimer in the documentation
35 * and/or other materials provided with the distribution.
36 *
37 * . Neither the name of Agere Systems Inc. nor the names of the contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
40 *
41 * Disclaimer
42 *
43 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
44 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
46 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
47 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
48 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
49 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
51 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
54 * DAMAGE.
55 *
56 */
57
58 #ifndef _ET1310_ADDRESS_MAP_H_
59 #define _ET1310_ADDRESS_MAP_H_
60
61
62 /* START OF GLOBAL REGISTER ADDRESS MAP */
63
64 /*
65 * 10bit registers
66 *
67 * Tx queue start address reg in global address map at address 0x0000
68 * tx queue end address reg in global address map at address 0x0004
69 * rx queue start address reg in global address map at address 0x0008
70 * rx queue end address reg in global address map at address 0x000C
71 */
72
73 /*
74 * structure for power management control status reg in global address map
75 * located at address 0x0010
76 * jagcore_rx_rdy bit 9
77 * jagcore_tx_rdy bit 8
78 * phy_lped_en bit 7
79 * phy_sw_coma bit 6
80 * rxclk_gate bit 5
81 * txclk_gate bit 4
82 * sysclk_gate bit 3
83 * jagcore_rx_en bit 2
84 * jagcore_tx_en bit 1
85 * gigephy_en bit 0
86 */
87
88 #define ET_PM_PHY_SW_COMA 0x40
89 #define ET_PMCSR_INIT 0x38
90
91 /*
92 * Interrupt status reg at address 0x0018
93 */
94
95 #define ET_INTR_TXDMA_ISR 0x00000008
96 #define ET_INTR_TXDMA_ERR 0x00000010
97 #define ET_INTR_RXDMA_XFR_DONE 0x00000020
98 #define ET_INTR_RXDMA_FB_R0_LOW 0x00000040
99 #define ET_INTR_RXDMA_FB_R1_LOW 0x00000080
100 #define ET_INTR_RXDMA_STAT_LOW 0x00000100
101 #define ET_INTR_RXDMA_ERR 0x00000200
102 #define ET_INTR_WATCHDOG 0x00004000
103 #define ET_INTR_WOL 0x00008000
104 #define ET_INTR_PHY 0x00010000
105 #define ET_INTR_TXMAC 0x00020000
106 #define ET_INTR_RXMAC 0x00040000
107 #define ET_INTR_MAC_STAT 0x00080000
108 #define ET_INTR_SLV_TIMEOUT 0x00100000
109
110 /*
111 * Interrupt mask register at address 0x001C
112 * Interrupt alias clear mask reg at address 0x0020
113 * Interrupt status alias reg at address 0x0024
114 *
115 * Same masks as above
116 */
117
118 /*
119 * Software reset reg at address 0x0028
120 * 0: txdma_sw_reset
121 * 1: rxdma_sw_reset
122 * 2: txmac_sw_reset
123 * 3: rxmac_sw_reset
124 * 4: mac_sw_reset
125 * 5: mac_stat_sw_reset
126 * 6: mmc_sw_reset
127 *31: selfclr_disable
128 */
129
130 /*
131 * SLV Timer reg at address 0x002C (low 24 bits)
132 */
133
134 /*
135 * MSI Configuration reg at address 0x0030
136 */
137
138 #define ET_MSI_VECTOR 0x0000001F
139 #define ET_MSI_TC 0x00070000
140
141 /*
142 * Loopback reg located at address 0x0034
143 */
144
145 #define ET_LOOP_MAC 0x00000001
146 #define ET_LOOP_DMA 0x00000002
147
148 /*
149 * GLOBAL Module of JAGCore Address Mapping
150 * Located at address 0x0000
151 */
152 typedef struct _GLOBAL_t { /* Location: */
153 u32 txq_start_addr; /* 0x0000 */
154 u32 txq_end_addr; /* 0x0004 */
155 u32 rxq_start_addr; /* 0x0008 */
156 u32 rxq_end_addr; /* 0x000C */
157 u32 pm_csr; /* 0x0010 */
158 u32 unused; /* 0x0014 */
159 u32 int_status; /* 0x0018 */
160 u32 int_mask; /* 0x001C */
161 u32 int_alias_clr_en; /* 0x0020 */
162 u32 int_status_alias; /* 0x0024 */
163 u32 sw_reset; /* 0x0028 */
164 u32 slv_timer; /* 0x002C */
165 u32 msi_config; /* 0x0030 */
166 u32 loopback; /* 0x0034 */
167 u32 watchdog_timer; /* 0x0038 */
168 } GLOBAL_t, *PGLOBAL_t;
169
170 /* END OF GLOBAL REGISTER ADDRESS MAP */
171
172
173 /* START OF TXDMA REGISTER ADDRESS MAP */
174
175 /*
176 * txdma control status reg at address 0x1000
177 */
178
179 #define ET_TXDMA_CSR_HALT 0x00000001
180 #define ET_TXDMA_DROP_TLP 0x00000002
181 #define ET_TXDMA_CACHE_THRS 0x000000F0
182 #define ET_TXDMA_CACHE_SHIFT 4
183 #define ET_TXDMA_SNGL_EPKT 0x00000100
184 #define ET_TXDMA_CLASS 0x00001E00
185
186 /*
187 * structure for txdma packet ring base address hi reg in txdma address map
188 * located at address 0x1004
189 * Defined earlier (u32)
190 */
191
192 /*
193 * structure for txdma packet ring base address low reg in txdma address map
194 * located at address 0x1008
195 * Defined earlier (u32)
196 */
197
198 /*
199 * structure for txdma packet ring number of descriptor reg in txdma address
200 * map. Located at address 0x100C
201 *
202 * 31-10: unused
203 * 9-0: pr ndes
204 */
205
206 #define ET_DMA10_MASK 0x3FF /* 10 bit mask for DMA10W types */
207 #define ET_DMA10_WRAP 0x400
208 #define ET_DMA4_MASK 0x00F /* 4 bit mask for DMA4W types */
209 #define ET_DMA4_WRAP 0x010
210
211 #define INDEX10(x) ((x) & ET_DMA10_MASK)
212 #define INDEX4(x) ((x) & ET_DMA4_MASK)
213
214 extern inline void add_10bit(u32 *v, int n)
215 {
216 *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
217 }
218
219 /*
220 * 10bit DMA with wrap
221 * txdma tx queue write address reg in txdma address map at 0x1010
222 * txdma tx queue write address external reg in txdma address map at 0x1014
223 * txdma tx queue read address reg in txdma address map at 0x1018
224 *
225 * u32
226 * txdma status writeback address hi reg in txdma address map at0x101C
227 * txdma status writeback address lo reg in txdma address map at 0x1020
228 *
229 * 10bit DMA with wrap
230 * txdma service request reg in txdma address map at 0x1024
231 * structure for txdma service complete reg in txdma address map at 0x1028
232 *
233 * 4bit DMA with wrap
234 * txdma tx descriptor cache read index reg in txdma address map at 0x102C
235 * txdma tx descriptor cache write index reg in txdma address map at 0x1030
236 *
237 * txdma error reg in txdma address map at address 0x1034
238 * 0: PyldResend
239 * 1: PyldRewind
240 * 4: DescrResend
241 * 5: DescrRewind
242 * 8: WrbkResend
243 * 9: WrbkRewind
244 */
245
246 /*
247 * Tx DMA Module of JAGCore Address Mapping
248 * Located at address 0x1000
249 */
250 typedef struct _TXDMA_t { /* Location: */
251 u32 csr; /* 0x1000 */
252 u32 pr_base_hi; /* 0x1004 */
253 u32 pr_base_lo; /* 0x1008 */
254 u32 pr_num_des; /* 0x100C */
255 u32 txq_wr_addr; /* 0x1010 */
256 u32 txq_wr_addr_ext; /* 0x1014 */
257 u32 txq_rd_addr; /* 0x1018 */
258 u32 dma_wb_base_hi; /* 0x101C */
259 u32 dma_wb_base_lo; /* 0x1020 */
260 u32 service_request; /* 0x1024 */
261 u32 service_complete; /* 0x1028 */
262 u32 cache_rd_index; /* 0x102C */
263 u32 cache_wr_index; /* 0x1030 */
264 u32 TxDmaError; /* 0x1034 */
265 u32 DescAbortCount; /* 0x1038 */
266 u32 PayloadAbortCnt; /* 0x103c */
267 u32 WriteBackAbortCnt; /* 0x1040 */
268 u32 DescTimeoutCnt; /* 0x1044 */
269 u32 PayloadTimeoutCnt; /* 0x1048 */
270 u32 WriteBackTimeoutCnt; /* 0x104c */
271 u32 DescErrorCount; /* 0x1050 */
272 u32 PayloadErrorCnt; /* 0x1054 */
273 u32 WriteBackErrorCnt; /* 0x1058 */
274 u32 DroppedTLPCount; /* 0x105c */
275 u32 NewServiceComplete; /* 0x1060 */
276 u32 EthernetPacketCount; /* 0x1064 */
277 } TXDMA_t, *PTXDMA_t;
278
279 /* END OF TXDMA REGISTER ADDRESS MAP */
280
281
282 /* START OF RXDMA REGISTER ADDRESS MAP */
283
284 /*
285 * structure for control status reg in rxdma address map
286 * Located at address 0x2000
287 */
288 typedef union _RXDMA_CSR_t {
289 u32 value;
290 struct {
291 #ifdef _BIT_FIELDS_HTOL
292 u32 unused2:14; /* bits 18-31 */
293 u32 halt_status:1; /* bit 17 */
294 u32 pkt_done_flush:1; /* bit 16 */
295 u32 pkt_drop_disable:1; /* bit 15 */
296 u32 unused1:1; /* bit 14 */
297 u32 fbr1_enable:1; /* bit 13 */
298 u32 fbr1_size:2; /* bits 11-12 */
299 u32 fbr0_enable:1; /* bit 10 */
300 u32 fbr0_size:2; /* bits 8-9 */
301 u32 dma_big_endian:1; /* bit 7 */
302 u32 pkt_big_endian:1; /* bit 6 */
303 u32 psr_big_endian:1; /* bit 5 */
304 u32 fbr_big_endian:1; /* bit 4 */
305 u32 tc:3; /* bits 1-3 */
306 u32 halt:1; /* bit 0 */
307 #else
308 u32 halt:1; /* bit 0 */
309 u32 tc:3; /* bits 1-3 */
310 u32 fbr_big_endian:1; /* bit 4 */
311 u32 psr_big_endian:1; /* bit 5 */
312 u32 pkt_big_endian:1; /* bit 6 */
313 u32 dma_big_endian:1; /* bit 7 */
314 u32 fbr0_size:2; /* bits 8-9 */
315 u32 fbr0_enable:1; /* bit 10 */
316 u32 fbr1_size:2; /* bits 11-12 */
317 u32 fbr1_enable:1; /* bit 13 */
318 u32 unused1:1; /* bit 14 */
319 u32 pkt_drop_disable:1; /* bit 15 */
320 u32 pkt_done_flush:1; /* bit 16 */
321 u32 halt_status:1; /* bit 17 */
322 u32 unused2:14; /* bits 18-31 */
323 #endif
324 } bits;
325 } RXDMA_CSR_t, *PRXDMA_CSR_t;
326
327 /*
328 * structure for dma writeback lo reg in rxdma address map
329 * located at address 0x2004
330 * Defined earlier (u32)
331 */
332
333 /*
334 * structure for dma writeback hi reg in rxdma address map
335 * located at address 0x2008
336 * Defined earlier (u32)
337 */
338
339 /*
340 * structure for number of packets done reg in rxdma address map
341 * located at address 0x200C
342 *
343 * 31-8: unused
344 * 7-0: num done
345 */
346
347 /*
348 * structure for max packet time reg in rxdma address map
349 * located at address 0x2010
350 *
351 * 31-18: unused
352 * 17-0: time done
353 */
354
355 /*
356 * structure for rx queue read address reg in rxdma address map
357 * located at address 0x2014
358 * Defined earlier (u32)
359 */
360
361 /*
362 * structure for rx queue read address external reg in rxdma address map
363 * located at address 0x2018
364 * Defined earlier (u32)
365 */
366
367 /*
368 * structure for rx queue write address reg in rxdma address map
369 * located at address 0x201C
370 * Defined earlier (u32)
371 */
372
373 /*
374 * structure for packet status ring base address lo reg in rxdma address map
375 * located at address 0x2020
376 * Defined earlier (u32)
377 */
378
379 /*
380 * structure for packet status ring base address hi reg in rxdma address map
381 * located at address 0x2024
382 * Defined earlier (u32)
383 */
384
385 /*
386 * structure for packet status ring number of descriptors reg in rxdma address
387 * map. Located at address 0x2028
388 *
389 * 31-12: unused
390 * 11-0: psr ndes
391 */
392
393 /*
394 * structure for packet status ring available offset reg in rxdma address map
395 * located at address 0x202C
396 */
397 typedef union _RXDMA_PSR_AVAIL_OFFSET_t {
398 u32 value;
399 struct {
400 #ifdef _BIT_FIELDS_HTOL
401 u32 unused:19; /* bits 13-31 */
402 u32 psr_avail_wrap:1; /* bit 12 */
403 u32 psr_avail:12; /* bit 0-11 */
404 #else
405 u32 psr_avail:12; /* bit 0-11 */
406 u32 psr_avail_wrap:1; /* bit 12 */
407 u32 unused:19; /* bits 13-31 */
408 #endif
409 } bits;
410 } RXDMA_PSR_AVAIL_OFFSET_t, *PRXDMA_PSR_AVAIL_OFFSET_t;
411
412 /*
413 * structure for packet status ring full offset reg in rxdma address map
414 * located at address 0x2030
415 */
416 typedef union _RXDMA_PSR_FULL_OFFSET_t {
417 u32 value;
418 struct {
419 #ifdef _BIT_FIELDS_HTOL
420 u32 unused:19; /* bits 13-31 */
421 u32 psr_full_wrap:1; /* bit 12 */
422 u32 psr_full:12; /* bit 0-11 */
423 #else
424 u32 psr_full:12; /* bit 0-11 */
425 u32 psr_full_wrap:1; /* bit 12 */
426 u32 unused:19; /* bits 13-31 */
427 #endif
428 } bits;
429 } RXDMA_PSR_FULL_OFFSET_t, *PRXDMA_PSR_FULL_OFFSET_t;
430
431 /*
432 * structure for packet status ring access index reg in rxdma address map
433 * located at address 0x2034
434 *
435 * 31-5: unused
436 * 4-0: psr_ai
437 */
438
439 /*
440 * structure for packet status ring minimum descriptors reg in rxdma address
441 * map. Located at address 0x2038
442 *
443 * 31-12: unused
444 * 11-0: psr_min
445 */
446
447 /*
448 * structure for free buffer ring base lo address reg in rxdma address map
449 * located at address 0x203C
450 * Defined earlier (u32)
451 */
452
453 /*
454 * structure for free buffer ring base hi address reg in rxdma address map
455 * located at address 0x2040
456 * Defined earlier (u32)
457 */
458
459 /*
460 * structure for free buffer ring number of descriptors reg in rxdma address
461 * map. Located at address 0x2044
462 *
463 * 31-10: unused
464 * 9-0: fbr ndesc
465 */
466 typedef union _RXDMA_FBR_NUM_DES_t {
467 u32 value;
468 struct {
469 #ifdef _BIT_FIELDS_HTOL
470 u32 unused:22; /* bits 10-31 */
471 u32 fbr_ndesc:10; /* bits 0-9 */
472 #else
473 u32 fbr_ndesc:10; /* bits 0-9 */
474 u32 unused:22; /* bits 10-31 */
475 #endif
476 } bits;
477 } RXDMA_FBR_NUM_DES_t, *PRXDMA_FBR_NUM_DES_t;
478
479 /*
480 * structure for free buffer ring 0 available offset reg in rxdma address map
481 * located at address 0x2048
482 * Defined earlier (u32)
483 */
484
485 /*
486 * structure for free buffer ring 0 full offset reg in rxdma address map
487 * located at address 0x204C
488 * Defined earlier (u32)
489 */
490
491 /*
492 * structure for free buffer cache 0 full offset reg in rxdma address map
493 * located at address 0x2050
494 *
495 * 31-5: unused
496 * 4-0: fbc rdi
497 */
498
499 /*
500 * structure for free buffer ring 0 minimum descriptor reg in rxdma address map
501 * located at address 0x2054
502 *
503 * 31-10: unused
504 * 9-0: fbr min
505 */
506
507 /*
508 * structure for free buffer ring 1 base address lo reg in rxdma address map
509 * located at address 0x2058 - 0x205C
510 * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t)
511 */
512
513 /*
514 * structure for free buffer ring 1 number of descriptors reg in rxdma address
515 * map. Located at address 0x2060
516 * Defined earlier (RXDMA_FBR_NUM_DES_t)
517 */
518
519 /*
520 * structure for free buffer ring 1 available offset reg in rxdma address map
521 * located at address 0x2064
522 * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t)
523 */
524
525 /*
526 * structure for free buffer ring 1 full offset reg in rxdma address map
527 * located at address 0x2068
528 * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t)
529 */
530
531 /*
532 * structure for free buffer cache 1 read index reg in rxdma address map
533 * located at address 0x206C
534 * Defined Earlier (RXDMA_FBC_RD_INDEX_t)
535 */
536
537 /*
538 * structure for free buffer ring 1 minimum descriptor reg in rxdma address map
539 * located at address 0x2070
540 * Defined Earlier (RXDMA_FBR_MIN_DES_t)
541 */
542
543 /*
544 * Rx DMA Module of JAGCore Address Mapping
545 * Located at address 0x2000
546 */
547 typedef struct _RXDMA_t { /* Location: */
548 RXDMA_CSR_t csr; /* 0x2000 */
549 u32 dma_wb_base_lo; /* 0x2004 */
550 u32 dma_wb_base_hi; /* 0x2008 */
551 u32 num_pkt_done; /* 0x200C */
552 u32 max_pkt_time; /* 0x2010 */
553 u32 rxq_rd_addr; /* 0x2014 */
554 u32 rxq_rd_addr_ext; /* 0x2018 */
555 u32 rxq_wr_addr; /* 0x201C */
556 u32 psr_base_lo; /* 0x2020 */
557 u32 psr_base_hi; /* 0x2024 */
558 u32 psr_num_des; /* 0x2028 */
559 RXDMA_PSR_AVAIL_OFFSET_t psr_avail_offset; /* 0x202C */
560 RXDMA_PSR_FULL_OFFSET_t psr_full_offset; /* 0x2030 */
561 u32 psr_access_index; /* 0x2034 */
562 u32 psr_min_des; /* 0x2038 */
563 u32 fbr0_base_lo; /* 0x203C */
564 u32 fbr0_base_hi; /* 0x2040 */
565 u32 fbr0_num_des; /* 0x2044 */
566 u32 fbr0_avail_offset; /* 0x2048 */
567 u32 fbr0_full_offset; /* 0x204C */
568 u32 fbr0_rd_index; /* 0x2050 */
569 u32 fbr0_min_des; /* 0x2054 */
570 u32 fbr1_base_lo; /* 0x2058 */
571 u32 fbr1_base_hi; /* 0x205C */
572 u32 fbr1_num_des; /* 0x2060 */
573 u32 fbr1_avail_offset; /* 0x2064 */
574 u32 fbr1_full_offset; /* 0x2068 */
575 u32 fbr1_rd_index; /* 0x206C */
576 u32 fbr1_min_des; /* 0x2070 */
577 } RXDMA_t, *PRXDMA_t;
578
579 /* END OF RXDMA REGISTER ADDRESS MAP */
580
581
582 /* START OF TXMAC REGISTER ADDRESS MAP */
583
584 /*
585 * structure for control reg in txmac address map
586 * located at address 0x3000
587 */
588 typedef union _TXMAC_CTL_t {
589 u32 value;
590 struct {
591 #ifdef _BIT_FIELDS_HTOL
592 u32 unused:24; /* bits 8-31 */
593 u32 cklseg_diable:1; /* bit 7 */
594 u32 ckbcnt_disable:1; /* bit 6 */
595 u32 cksegnum:1; /* bit 5 */
596 u32 async_disable:1; /* bit 4 */
597 u32 fc_disable:1; /* bit 3 */
598 u32 mcif_disable:1; /* bit 2 */
599 u32 mif_disable:1; /* bit 1 */
600 u32 txmac_en:1; /* bit 0 */
601 #else
602 u32 txmac_en:1; /* bit 0 */
603 u32 mif_disable:1; /* bit 1 mac interface */
604 u32 mcif_disable:1; /* bit 2 mem. contr. interface */
605 u32 fc_disable:1; /* bit 3 */
606 u32 async_disable:1; /* bit 4 */
607 u32 cksegnum:1; /* bit 5 */
608 u32 ckbcnt_disable:1; /* bit 6 */
609 u32 cklseg_diable:1; /* bit 7 */
610 u32 unused:24; /* bits 8-31 */
611 #endif
612 } bits;
613 } TXMAC_CTL_t, *PTXMAC_CTL_t;
614
615 /*
616 * structure for shadow pointer reg in txmac address map
617 * located at address 0x3004
618 * 31-27: reserved
619 * 26-16: txq rd ptr
620 * 15-11: reserved
621 * 10-0: txq wr ptr
622 */
623
624 /*
625 * structure for error count reg in txmac address map
626 * located at address 0x3008
627 */
628 typedef union _TXMAC_ERR_CNT_t {
629 u32 value;
630 struct {
631 #ifdef _BIT_FIELDS_HTOL
632 u32 unused:20; /* bits 12-31 */
633 u32 reserved:4; /* bits 8-11 */
634 u32 txq_underrun:4; /* bits 4-7 */
635 u32 fifo_underrun:4; /* bits 0-3 */
636 #else
637 u32 fifo_underrun:4; /* bits 0-3 */
638 u32 txq_underrun:4; /* bits 4-7 */
639 u32 reserved:4; /* bits 8-11 */
640 u32 unused:20; /* bits 12-31 */
641 #endif
642 } bits;
643 } TXMAC_ERR_CNT_t, *PTXMAC_ERR_CNT_t;
644
645 /*
646 * structure for max fill reg in txmac address map
647 * located at address 0x300C
648 * 31-12: unused
649 * 11-0: max fill
650 */
651
652 /*
653 * structure for cf parameter reg in txmac address map
654 * located at address 0x3010
655 * 31-16: cfep
656 * 15-0: cfpt
657 */
658
659 /*
660 * structure for tx test reg in txmac address map
661 * located at address 0x3014
662 * 31-17: unused
663 * 16: reserved1
664 * 15: txtest_en
665 * 14-11: unused
666 * 10-0: txq test pointer
667 */
668
669 /*
670 * structure for error reg in txmac address map
671 * located at address 0x3018
672 */
673 typedef union _TXMAC_ERR_t {
674 u32 value;
675 struct {
676 #ifdef _BIT_FIELDS_HTOL
677 u32 unused2:23; /* bits 9-31 */
678 u32 fifo_underrun:1; /* bit 8 */
679 u32 unused1:2; /* bits 6-7 */
680 u32 ctrl2_err:1; /* bit 5 */
681 u32 txq_underrun:1; /* bit 4 */
682 u32 bcnt_err:1; /* bit 3 */
683 u32 lseg_err:1; /* bit 2 */
684 u32 segnum_err:1; /* bit 1 */
685 u32 seg0_err:1; /* bit 0 */
686 #else
687 u32 seg0_err:1; /* bit 0 */
688 u32 segnum_err:1; /* bit 1 */
689 u32 lseg_err:1; /* bit 2 */
690 u32 bcnt_err:1; /* bit 3 */
691 u32 txq_underrun:1; /* bit 4 */
692 u32 ctrl2_err:1; /* bit 5 */
693 u32 unused1:2; /* bits 6-7 */
694 u32 fifo_underrun:1; /* bit 8 */
695 u32 unused2:23; /* bits 9-31 */
696 #endif
697 } bits;
698 } TXMAC_ERR_t, *PTXMAC_ERR_t;
699
700 /*
701 * structure for error interrupt reg in txmac address map
702 * located at address 0x301C
703 */
704 typedef union _TXMAC_ERR_INT_t {
705 u32 value;
706 struct {
707 #ifdef _BIT_FIELDS_HTOL
708 u32 unused2:23; /* bits 9-31 */
709 u32 fifo_underrun:1; /* bit 8 */
710 u32 unused1:2; /* bits 6-7 */
711 u32 ctrl2_err:1; /* bit 5 */
712 u32 txq_underrun:1; /* bit 4 */
713 u32 bcnt_err:1; /* bit 3 */
714 u32 lseg_err:1; /* bit 2 */
715 u32 segnum_err:1; /* bit 1 */
716 u32 seg0_err:1; /* bit 0 */
717 #else
718 u32 seg0_err:1; /* bit 0 */
719 u32 segnum_err:1; /* bit 1 */
720 u32 lseg_err:1; /* bit 2 */
721 u32 bcnt_err:1; /* bit 3 */
722 u32 txq_underrun:1; /* bit 4 */
723 u32 ctrl2_err:1; /* bit 5 */
724 u32 unused1:2; /* bits 6-7 */
725 u32 fifo_underrun:1; /* bit 8 */
726 u32 unused2:23; /* bits 9-31 */
727 #endif
728 } bits;
729 } TXMAC_ERR_INT_t, *PTXMAC_ERR_INT_t;
730
731 /*
732 * structure for error interrupt reg in txmac address map
733 * located at address 0x3020
734 *
735 * 31-2: unused
736 * 1: bp_req
737 * 0: bp_xonxoff
738 */
739
740 /*
741 * Tx MAC Module of JAGCore Address Mapping
742 */
743 typedef struct _TXMAC_t { /* Location: */
744 TXMAC_CTL_t ctl; /* 0x3000 */
745 u32 shadow_ptr; /* 0x3004 */
746 TXMAC_ERR_CNT_t err_cnt; /* 0x3008 */
747 u32 max_fill; /* 0x300C */
748 u32 cf_param; /* 0x3010 */
749 u32 tx_test; /* 0x3014 */
750 TXMAC_ERR_t err; /* 0x3018 */
751 TXMAC_ERR_INT_t err_int; /* 0x301C */
752 u32 bp_ctrl; /* 0x3020 */
753 } TXMAC_t, *PTXMAC_t;
754
755 /* END OF TXMAC REGISTER ADDRESS MAP */
756
757 /* START OF RXMAC REGISTER ADDRESS MAP */
758
759 /*
760 * structure for rxmac control reg in rxmac address map
761 * located at address 0x4000
762 */
763 typedef union _RXMAC_CTRL_t {
764 u32 value;
765 struct {
766 #ifdef _BIT_FIELDS_HTOL
767 u32 reserved:25; /* bits 7-31 */
768 u32 rxmac_int_disable:1; /* bit 6 */
769 u32 async_disable:1; /* bit 5 */
770 u32 mif_disable:1; /* bit 4 */
771 u32 wol_disable:1; /* bit 3 */
772 u32 pkt_filter_disable:1; /* bit 2 */
773 u32 mcif_disable:1; /* bit 1 */
774 u32 rxmac_en:1; /* bit 0 */
775 #else
776 u32 rxmac_en:1; /* bit 0 */
777 u32 mcif_disable:1; /* bit 1 */
778 u32 pkt_filter_disable:1; /* bit 2 */
779 u32 wol_disable:1; /* bit 3 */
780 u32 mif_disable:1; /* bit 4 */
781 u32 async_disable:1; /* bit 5 */
782 u32 rxmac_int_disable:1; /* bit 6 */
783 u32 reserved:25; /* bits 7-31 */
784 #endif
785 } bits;
786 } RXMAC_CTRL_t, *PRXMAC_CTRL_t;
787
788 /*
789 * structure for Wake On Lan Control and CRC 0 reg in rxmac address map
790 * located at address 0x4004
791 */
792 typedef union _RXMAC_WOL_CTL_CRC0_t {
793 u32 value;
794 struct {
795 #ifdef _BIT_FIELDS_HTOL
796 u32 crc0:16; /* bits 16-31 */
797 u32 reserve:4; /* bits 12-15 */
798 u32 ignore_pp:1; /* bit 11 */
799 u32 ignore_mp:1; /* bit 10 */
800 u32 clr_intr:1; /* bit 9 */
801 u32 ignore_link_chg:1; /* bit 8 */
802 u32 ignore_uni:1; /* bit 7 */
803 u32 ignore_multi:1; /* bit 6 */
804 u32 ignore_broad:1; /* bit 5 */
805 u32 valid_crc4:1; /* bit 4 */
806 u32 valid_crc3:1; /* bit 3 */
807 u32 valid_crc2:1; /* bit 2 */
808 u32 valid_crc1:1; /* bit 1 */
809 u32 valid_crc0:1; /* bit 0 */
810 #else
811 u32 valid_crc0:1; /* bit 0 */
812 u32 valid_crc1:1; /* bit 1 */
813 u32 valid_crc2:1; /* bit 2 */
814 u32 valid_crc3:1; /* bit 3 */
815 u32 valid_crc4:1; /* bit 4 */
816 u32 ignore_broad:1; /* bit 5 */
817 u32 ignore_multi:1; /* bit 6 */
818 u32 ignore_uni:1; /* bit 7 */
819 u32 ignore_link_chg:1; /* bit 8 */
820 u32 clr_intr:1; /* bit 9 */
821 u32 ignore_mp:1; /* bit 10 */
822 u32 ignore_pp:1; /* bit 11 */
823 u32 reserve:4; /* bits 12-15 */
824 u32 crc0:16; /* bits 16-31 */
825 #endif
826 } bits;
827 } RXMAC_WOL_CTL_CRC0_t, *PRXMAC_WOL_CTL_CRC0_t;
828
829 /*
830 * structure for CRC 1 and CRC 2 reg in rxmac address map
831 * located at address 0x4008
832 */
833 typedef union _RXMAC_WOL_CRC12_t {
834 u32 value;
835 struct {
836 #ifdef _BIT_FIELDS_HTOL
837 u32 crc2:16; /* bits 16-31 */
838 u32 crc1:16; /* bits 0-15 */
839 #else
840 u32 crc1:16; /* bits 0-15 */
841 u32 crc2:16; /* bits 16-31 */
842 #endif
843 } bits;
844 } RXMAC_WOL_CRC12_t, *PRXMAC_WOL_CRC12_t;
845
846 /*
847 * structure for CRC 3 and CRC 4 reg in rxmac address map
848 * located at address 0x400C
849 */
850 typedef union _RXMAC_WOL_CRC34_t {
851 u32 value;
852 struct {
853 #ifdef _BIT_FIELDS_HTOL
854 u32 crc4:16; /* bits 16-31 */
855 u32 crc3:16; /* bits 0-15 */
856 #else
857 u32 crc3:16; /* bits 0-15 */
858 u32 crc4:16; /* bits 16-31 */
859 #endif
860 } bits;
861 } RXMAC_WOL_CRC34_t, *PRXMAC_WOL_CRC34_t;
862
863 /*
864 * structure for Wake On Lan Source Address Lo reg in rxmac address map
865 * located at address 0x4010
866 */
867 typedef union _RXMAC_WOL_SA_LO_t {
868 u32 value;
869 struct {
870 #ifdef _BIT_FIELDS_HTOL
871 u32 sa3:8; /* bits 24-31 */
872 u32 sa4:8; /* bits 16-23 */
873 u32 sa5:8; /* bits 8-15 */
874 u32 sa6:8; /* bits 0-7 */
875 #else
876 u32 sa6:8; /* bits 0-7 */
877 u32 sa5:8; /* bits 8-15 */
878 u32 sa4:8; /* bits 16-23 */
879 u32 sa3:8; /* bits 24-31 */
880 #endif
881 } bits;
882 } RXMAC_WOL_SA_LO_t, *PRXMAC_WOL_SA_LO_t;
883
884 /*
885 * structure for Wake On Lan Source Address Hi reg in rxmac address map
886 * located at address 0x4014
887 */
888 typedef union _RXMAC_WOL_SA_HI_t {
889 u32 value;
890 struct {
891 #ifdef _BIT_FIELDS_HTOL
892 u32 reserved:16; /* bits 16-31 */
893 u32 sa1:8; /* bits 8-15 */
894 u32 sa2:8; /* bits 0-7 */
895 #else
896 u32 sa2:8; /* bits 0-7 */
897 u32 sa1:8; /* bits 8-15 */
898 u32 reserved:16; /* bits 16-31 */
899 #endif
900 } bits;
901 } RXMAC_WOL_SA_HI_t, *PRXMAC_WOL_SA_HI_t;
902
903 /*
904 * structure for Wake On Lan mask reg in rxmac address map
905 * located at address 0x4018 - 0x4064
906 * Defined earlier (u32)
907 */
908
909 /*
910 * structure for Unicast Paket Filter Address 1 reg in rxmac address map
911 * located at address 0x4068
912 */
913 typedef union _RXMAC_UNI_PF_ADDR1_t {
914 u32 value;
915 struct {
916 #ifdef _BIT_FIELDS_HTOL
917 u32 addr1_3:8; /* bits 24-31 */
918 u32 addr1_4:8; /* bits 16-23 */
919 u32 addr1_5:8; /* bits 8-15 */
920 u32 addr1_6:8; /* bits 0-7 */
921 #else
922 u32 addr1_6:8; /* bits 0-7 */
923 u32 addr1_5:8; /* bits 8-15 */
924 u32 addr1_4:8; /* bits 16-23 */
925 u32 addr1_3:8; /* bits 24-31 */
926 #endif
927 } bits;
928 } RXMAC_UNI_PF_ADDR1_t, *PRXMAC_UNI_PF_ADDR1_t;
929
930 /*
931 * structure for Unicast Paket Filter Address 2 reg in rxmac address map
932 * located at address 0x406C
933 */
934 typedef union _RXMAC_UNI_PF_ADDR2_t {
935 u32 value;
936 struct {
937 #ifdef _BIT_FIELDS_HTOL
938 u32 addr2_3:8; /* bits 24-31 */
939 u32 addr2_4:8; /* bits 16-23 */
940 u32 addr2_5:8; /* bits 8-15 */
941 u32 addr2_6:8; /* bits 0-7 */
942 #else
943 u32 addr2_6:8; /* bits 0-7 */
944 u32 addr2_5:8; /* bits 8-15 */
945 u32 addr2_4:8; /* bits 16-23 */
946 u32 addr2_3:8; /* bits 24-31 */
947 #endif
948 } bits;
949 } RXMAC_UNI_PF_ADDR2_t, *PRXMAC_UNI_PF_ADDR2_t;
950
951 /*
952 * structure for Unicast Paket Filter Address 1 & 2 reg in rxmac address map
953 * located at address 0x4070
954 */
955 typedef union _RXMAC_UNI_PF_ADDR3_t {
956 u32 value;
957 struct {
958 #ifdef _BIT_FIELDS_HTOL
959 u32 addr2_1:8; /* bits 24-31 */
960 u32 addr2_2:8; /* bits 16-23 */
961 u32 addr1_1:8; /* bits 8-15 */
962 u32 addr1_2:8; /* bits 0-7 */
963 #else
964 u32 addr1_2:8; /* bits 0-7 */
965 u32 addr1_1:8; /* bits 8-15 */
966 u32 addr2_2:8; /* bits 16-23 */
967 u32 addr2_1:8; /* bits 24-31 */
968 #endif
969 } bits;
970 } RXMAC_UNI_PF_ADDR3_t, *PRXMAC_UNI_PF_ADDR3_t;
971
972 /*
973 * structure for Multicast Hash reg in rxmac address map
974 * located at address 0x4074 - 0x4080
975 * Defined earlier (u32)
976 */
977
978 /*
979 * structure for Packet Filter Control reg in rxmac address map
980 * located at address 0x4084
981 */
982 typedef union _RXMAC_PF_CTRL_t {
983 u32 value;
984 struct {
985 #ifdef _BIT_FIELDS_HTOL
986 u32 unused2:9; /* bits 23-31 */
987 u32 min_pkt_size:7; /* bits 16-22 */
988 u32 unused1:12; /* bits 4-15 */
989 u32 filter_frag_en:1; /* bit 3 */
990 u32 filter_uni_en:1; /* bit 2 */
991 u32 filter_multi_en:1; /* bit 1 */
992 u32 filter_broad_en:1; /* bit 0 */
993 #else
994 u32 filter_broad_en:1; /* bit 0 */
995 u32 filter_multi_en:1; /* bit 1 */
996 u32 filter_uni_en:1; /* bit 2 */
997 u32 filter_frag_en:1; /* bit 3 */
998 u32 unused1:12; /* bits 4-15 */
999 u32 min_pkt_size:7; /* bits 16-22 */
1000 u32 unused2:9; /* bits 23-31 */
1001 #endif
1002 } bits;
1003 } RXMAC_PF_CTRL_t, *PRXMAC_PF_CTRL_t;
1004
1005 /*
1006 * structure for Memory Controller Interface Control Max Segment reg in rxmac
1007 * address map. Located at address 0x4088
1008 */
1009 typedef union _RXMAC_MCIF_CTRL_MAX_SEG_t {
1010 u32 value;
1011 struct {
1012 #ifdef _BIT_FIELDS_HTOL
1013 u32 reserved:22; /* bits 10-31 */
1014 u32 max_size:8; /* bits 2-9 */
1015 u32 fc_en:1; /* bit 1 */
1016 u32 seg_en:1; /* bit 0 */
1017 #else
1018 u32 seg_en:1; /* bit 0 */
1019 u32 fc_en:1; /* bit 1 */
1020 u32 max_size:8; /* bits 2-9 */
1021 u32 reserved:22; /* bits 10-31 */
1022 #endif
1023 } bits;
1024 } RXMAC_MCIF_CTRL_MAX_SEG_t, *PRXMAC_MCIF_CTRL_MAX_SEG_t;
1025
1026 /*
1027 * structure for Memory Controller Interface Water Mark reg in rxmac address
1028 * map. Located at address 0x408C
1029 */
1030 typedef union _RXMAC_MCIF_WATER_MARK_t {
1031 u32 value;
1032 struct {
1033 #ifdef _BIT_FIELDS_HTOL
1034 u32 reserved2:6; /* bits 26-31 */
1035 u32 mark_hi:10; /* bits 16-25 */
1036 u32 reserved1:6; /* bits 10-15 */
1037 u32 mark_lo:10; /* bits 0-9 */
1038 #else
1039 u32 mark_lo:10; /* bits 0-9 */
1040 u32 reserved1:6; /* bits 10-15 */
1041 u32 mark_hi:10; /* bits 16-25 */
1042 u32 reserved2:6; /* bits 26-31 */
1043 #endif
1044 } bits;
1045 } RXMAC_MCIF_WATER_MARK_t, *PRXMAC_MCIF_WATER_MARK_t;
1046
1047 /*
1048 * structure for Rx Queue Dialog reg in rxmac address map.
1049 * located at address 0x4090
1050 */
1051 typedef union _RXMAC_RXQ_DIAG_t {
1052 u32 value;
1053 struct {
1054 #ifdef _BIT_FIELDS_HTOL
1055 u32 reserved2:6; /* bits 26-31 */
1056 u32 rd_ptr:10; /* bits 16-25 */
1057 u32 reserved1:6; /* bits 10-15 */
1058 u32 wr_ptr:10; /* bits 0-9 */
1059 #else
1060 u32 wr_ptr:10; /* bits 0-9 */
1061 u32 reserved1:6; /* bits 10-15 */
1062 u32 rd_ptr:10; /* bits 16-25 */
1063 u32 reserved2:6; /* bits 26-31 */
1064 #endif
1065 } bits;
1066 } RXMAC_RXQ_DIAG_t, *PRXMAC_RXQ_DIAG_t;
1067
1068 /*
1069 * structure for space availiable reg in rxmac address map.
1070 * located at address 0x4094
1071 */
1072 typedef union _RXMAC_SPACE_AVAIL_t {
1073 u32 value;
1074 struct {
1075 #ifdef _BIT_FIELDS_HTOL
1076 u32 reserved2:15; /* bits 17-31 */
1077 u32 space_avail_en:1; /* bit 16 */
1078 u32 reserved1:6; /* bits 10-15 */
1079 u32 space_avail:10; /* bits 0-9 */
1080 #else
1081 u32 space_avail:10; /* bits 0-9 */
1082 u32 reserved1:6; /* bits 10-15 */
1083 u32 space_avail_en:1; /* bit 16 */
1084 u32 reserved2:15; /* bits 17-31 */
1085 #endif
1086 } bits;
1087 } RXMAC_SPACE_AVAIL_t, *PRXMAC_SPACE_AVAIL_t;
1088
1089 /*
1090 * structure for management interface reg in rxmac address map.
1091 * located at address 0x4098
1092 */
1093 typedef union _RXMAC_MIF_CTL_t {
1094 u32 value;
1095 struct {
1096 #ifdef _BIT_FIELDS_HTOL
1097 u32 reserve:14; /* bits 18-31 */
1098 u32 drop_pkt_en:1; /* bit 17 */
1099 u32 drop_pkt_mask:17; /* bits 0-16 */
1100 #else
1101 u32 drop_pkt_mask:17; /* bits 0-16 */
1102 u32 drop_pkt_en:1; /* bit 17 */
1103 u32 reserve:14; /* bits 18-31 */
1104 #endif
1105 } bits;
1106 } RXMAC_MIF_CTL_t, *PRXMAC_MIF_CTL_t;
1107
1108 /*
1109 * structure for Error reg in rxmac address map.
1110 * located at address 0x409C
1111 */
1112 typedef union _RXMAC_ERROR_REG_t {
1113 u32 value;
1114 struct {
1115 #ifdef _BIT_FIELDS_HTOL
1116 u32 reserve:28; /* bits 4-31 */
1117 u32 mif:1; /* bit 3 */
1118 u32 async:1; /* bit 2 */
1119 u32 pkt_filter:1; /* bit 1 */
1120 u32 mcif:1; /* bit 0 */
1121 #else
1122 u32 mcif:1; /* bit 0 */
1123 u32 pkt_filter:1; /* bit 1 */
1124 u32 async:1; /* bit 2 */
1125 u32 mif:1; /* bit 3 */
1126 u32 reserve:28; /* bits 4-31 */
1127 #endif
1128 } bits;
1129 } RXMAC_ERROR_REG_t, *PRXMAC_ERROR_REG_t;
1130
1131 /*
1132 * Rx MAC Module of JAGCore Address Mapping
1133 */
1134 typedef struct _RXMAC_t { /* Location: */
1135 RXMAC_CTRL_t ctrl; /* 0x4000 */
1136 RXMAC_WOL_CTL_CRC0_t crc0; /* 0x4004 */
1137 RXMAC_WOL_CRC12_t crc12; /* 0x4008 */
1138 RXMAC_WOL_CRC34_t crc34; /* 0x400C */
1139 RXMAC_WOL_SA_LO_t sa_lo; /* 0x4010 */
1140 RXMAC_WOL_SA_HI_t sa_hi; /* 0x4014 */
1141 u32 mask0_word0; /* 0x4018 */
1142 u32 mask0_word1; /* 0x401C */
1143 u32 mask0_word2; /* 0x4020 */
1144 u32 mask0_word3; /* 0x4024 */
1145 u32 mask1_word0; /* 0x4028 */
1146 u32 mask1_word1; /* 0x402C */
1147 u32 mask1_word2; /* 0x4030 */
1148 u32 mask1_word3; /* 0x4034 */
1149 u32 mask2_word0; /* 0x4038 */
1150 u32 mask2_word1; /* 0x403C */
1151 u32 mask2_word2; /* 0x4040 */
1152 u32 mask2_word3; /* 0x4044 */
1153 u32 mask3_word0; /* 0x4048 */
1154 u32 mask3_word1; /* 0x404C */
1155 u32 mask3_word2; /* 0x4050 */
1156 u32 mask3_word3; /* 0x4054 */
1157 u32 mask4_word0; /* 0x4058 */
1158 u32 mask4_word1; /* 0x405C */
1159 u32 mask4_word2; /* 0x4060 */
1160 u32 mask4_word3; /* 0x4064 */
1161 RXMAC_UNI_PF_ADDR1_t uni_pf_addr1; /* 0x4068 */
1162 RXMAC_UNI_PF_ADDR2_t uni_pf_addr2; /* 0x406C */
1163 RXMAC_UNI_PF_ADDR3_t uni_pf_addr3; /* 0x4070 */
1164 u32 multi_hash1; /* 0x4074 */
1165 u32 multi_hash2; /* 0x4078 */
1166 u32 multi_hash3; /* 0x407C */
1167 u32 multi_hash4; /* 0x4080 */
1168 RXMAC_PF_CTRL_t pf_ctrl; /* 0x4084 */
1169 RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg; /* 0x4088 */
1170 RXMAC_MCIF_WATER_MARK_t mcif_water_mark; /* 0x408C */
1171 RXMAC_RXQ_DIAG_t rxq_diag; /* 0x4090 */
1172 RXMAC_SPACE_AVAIL_t space_avail; /* 0x4094 */
1173
1174 RXMAC_MIF_CTL_t mif_ctrl; /* 0x4098 */
1175 RXMAC_ERROR_REG_t err_reg; /* 0x409C */
1176 } RXMAC_t, *PRXMAC_t;
1177
1178 /* END OF TXMAC REGISTER ADDRESS MAP */
1179
1180
1181 /* START OF MAC REGISTER ADDRESS MAP */
1182
1183 /*
1184 * structure for configuration #1 reg in mac address map.
1185 * located at address 0x5000
1186 *
1187 * 31: soft reset
1188 * 30: sim reset
1189 * 29-20: reserved
1190 * 19: reset rx mc
1191 * 18: reset tx mc
1192 * 17: reset rx func
1193 * 16: reset tx fnc
1194 * 15-9: reserved
1195 * 8: loopback
1196 * 7-6: reserved
1197 * 5: rx flow
1198 * 4: tx flow
1199 * 3: syncd rx en
1200 * 2: rx enable
1201 * 1: syncd tx en
1202 * 0: tx enable
1203 */
1204
1205 #define CFG1_LOOPBACK 0x00000100
1206 #define CFG1_RX_FLOW 0x00000020
1207 #define CFG1_TX_FLOW 0x00000010
1208 #define CFG1_RX_ENABLE 0x00000004
1209 #define CFG1_TX_ENABLE 0x00000001
1210 #define CFG1_WAIT 0x0000000A /* RX & TX syncd */
1211
1212 /*
1213 * structure for configuration #2 reg in mac address map.
1214 * located at address 0x5004
1215 * 31-16: reserved
1216 * 15-12: preamble
1217 * 11-10: reserved
1218 * 9-8: if mode
1219 * 7-6: reserved
1220 * 5: huge frame
1221 * 4: length check
1222 * 3: undefined
1223 * 2: pad crc
1224 * 1: crc enable
1225 * 0: full duplex
1226 */
1227
1228
1229 /*
1230 * structure for Interpacket gap reg in mac address map.
1231 * located at address 0x5008
1232 *
1233 * 31: reserved
1234 * 30-24: non B2B ipg 1
1235 * 23: undefined
1236 * 22-16: non B2B ipg 2
1237 * 15-8: Min ifg enforce
1238 * 7-0: B2B ipg
1239 *
1240 * structure for half duplex reg in mac address map.
1241 * located at address 0x500C
1242 * 31-24: reserved
1243 * 23-20: Alt BEB trunc
1244 * 19: Alt BEB enable
1245 * 18: BP no backoff
1246 * 17: no backoff
1247 * 16: excess defer
1248 * 15-12: re-xmit max
1249 * 11-10: reserved
1250 * 9-0: collision window
1251 */
1252
1253 /*
1254 * structure for Maximum Frame Length reg in mac address map.
1255 * located at address 0x5010: bits 0-15 hold the length.
1256 */
1257
1258 /*
1259 * structure for Reserve 1 reg in mac address map.
1260 * located at address 0x5014 - 0x5018
1261 * Defined earlier (u32)
1262 */
1263
1264 /*
1265 * structure for Test reg in mac address map.
1266 * located at address 0x501C
1267 * test: bits 0-2, rest unused
1268 */
1269
1270 /*
1271 * structure for MII Management Configuration reg in mac address map.
1272 * located at address 0x5020
1273 *
1274 * 31: reset MII mgmt
1275 * 30-6: unused
1276 * 5: scan auto increment
1277 * 4: preamble supress
1278 * 3: undefined
1279 * 2-0: mgmt clock reset
1280 */
1281
1282 /*
1283 * structure for MII Management Command reg in mac address map.
1284 * located at address 0x5024
1285 * bit 1: scan cycle
1286 * bit 0: read cycle
1287 */
1288
1289 /*
1290 * structure for MII Management Address reg in mac address map.
1291 * located at address 0x5028
1292 * 31-13: reserved
1293 * 12-8: phy addr
1294 * 7-5: reserved
1295 * 4-0: register
1296 */
1297
1298 #define MII_ADDR(phy,reg) ((phy) << 8 | (reg))
1299
1300 /*
1301 * structure for MII Management Control reg in mac address map.
1302 * located at address 0x502C
1303 * 31-16: reserved
1304 * 15-0: phy control
1305 */
1306
1307 /*
1308 * structure for MII Management Status reg in mac address map.
1309 * located at address 0x5030
1310 * 31-16: reserved
1311 * 15-0: phy control
1312 */
1313
1314 /*
1315 * structure for MII Management Indicators reg in mac address map.
1316 * located at address 0x5034
1317 * 31-3: reserved
1318 * 2: not valid
1319 * 1: scanning
1320 * 0: busy
1321 */
1322
1323 #define MGMT_BUSY 0x00000001 /* busy */
1324 #define MGMT_WAIT 0x00000005 /* busy | not valid */
1325
1326 /*
1327 * structure for Interface Control reg in mac address map.
1328 * located at address 0x5038
1329 *
1330 * 31: reset if module
1331 * 30-28: reserved
1332 * 27: tbi mode
1333 * 26: ghd mode
1334 * 25: lhd mode
1335 * 24: phy mode
1336 * 23: reset per mii
1337 * 22-17: reserved
1338 * 16: speed
1339 * 15: reset pe100x
1340 * 14-11: reserved
1341 * 10: force quiet
1342 * 9: no cipher
1343 * 8: disable link fail
1344 * 7: reset gpsi
1345 * 6-1: reserved
1346 * 0: enable jabber protection
1347 */
1348
1349 /*
1350 * structure for Interface Status reg in mac address map.
1351 * located at address 0x503C
1352 */
1353 typedef union _MAC_IF_STAT_t {
1354 u32 value;
1355 struct {
1356 #ifdef _BIT_FIELDS_HTOL
1357 u32 reserved:22; /* bits 10-31 */
1358 u32 excess_defer:1; /* bit 9 */
1359 u32 clash:1; /* bit 8 */
1360 u32 phy_jabber:1; /* bit 7 */
1361 u32 phy_link_ok:1; /* bit 6 */
1362 u32 phy_full_duplex:1; /* bit 5 */
1363 u32 phy_speed:1; /* bit 4 */
1364 u32 pe100x_link_fail:1; /* bit 3 */
1365 u32 pe10t_loss_carrie:1; /* bit 2 */
1366 u32 pe10t_sqe_error:1; /* bit 1 */
1367 u32 pe10t_jabber:1; /* bit 0 */
1368 #else
1369 u32 pe10t_jabber:1; /* bit 0 */
1370 u32 pe10t_sqe_error:1; /* bit 1 */
1371 u32 pe10t_loss_carrie:1; /* bit 2 */
1372 u32 pe100x_link_fail:1; /* bit 3 */
1373 u32 phy_speed:1; /* bit 4 */
1374 u32 phy_full_duplex:1; /* bit 5 */
1375 u32 phy_link_ok:1; /* bit 6 */
1376 u32 phy_jabber:1; /* bit 7 */
1377 u32 clash:1; /* bit 8 */
1378 u32 excess_defer:1; /* bit 9 */
1379 u32 reserved:22; /* bits 10-31 */
1380 #endif
1381 } bits;
1382 } MAC_IF_STAT_t, *PMAC_IF_STAT_t;
1383
1384 /*
1385 * structure for Mac Station Address, Part 1 reg in mac address map.
1386 * located at address 0x5040
1387 */
1388 typedef union _MAC_STATION_ADDR1_t {
1389 u32 value;
1390 struct {
1391 #ifdef _BIT_FIELDS_HTOL
1392 u32 Octet6:8; /* bits 24-31 */
1393 u32 Octet5:8; /* bits 16-23 */
1394 u32 Octet4:8; /* bits 8-15 */
1395 u32 Octet3:8; /* bits 0-7 */
1396 #else
1397 u32 Octet3:8; /* bits 0-7 */
1398 u32 Octet4:8; /* bits 8-15 */
1399 u32 Octet5:8; /* bits 16-23 */
1400 u32 Octet6:8; /* bits 24-31 */
1401 #endif
1402 } bits;
1403 } MAC_STATION_ADDR1_t, *PMAC_STATION_ADDR1_t;
1404
1405 /*
1406 * structure for Mac Station Address, Part 2 reg in mac address map.
1407 * located at address 0x5044
1408 */
1409 typedef union _MAC_STATION_ADDR2_t {
1410 u32 value;
1411 struct {
1412 #ifdef _BIT_FIELDS_HTOL
1413 u32 Octet2:8; /* bits 24-31 */
1414 u32 Octet1:8; /* bits 16-23 */
1415 u32 reserved:16; /* bits 0-15 */
1416 #else
1417 u32 reserved:16; /* bit 0-15 */
1418 u32 Octet1:8; /* bits 16-23 */
1419 u32 Octet2:8; /* bits 24-31 */
1420 #endif
1421 } bits;
1422 } MAC_STATION_ADDR2_t, *PMAC_STATION_ADDR2_t;
1423
1424 /*
1425 * MAC Module of JAGCore Address Mapping
1426 */
1427 typedef struct _MAC_t { /* Location: */
1428 u32 cfg1; /* 0x5000 */
1429 u32 cfg2; /* 0x5004 */
1430 u32 ipg; /* 0x5008 */
1431 u32 hfdp; /* 0x500C */
1432 u32 max_fm_len; /* 0x5010 */
1433 u32 rsv1; /* 0x5014 */
1434 u32 rsv2; /* 0x5018 */
1435 u32 mac_test; /* 0x501C */
1436 u32 mii_mgmt_cfg; /* 0x5020 */
1437 u32 mii_mgmt_cmd; /* 0x5024 */
1438 u32 mii_mgmt_addr; /* 0x5028 */
1439 u32 mii_mgmt_ctrl; /* 0x502C */
1440 u32 mii_mgmt_stat; /* 0x5030 */
1441 u32 mii_mgmt_indicator; /* 0x5034 */
1442 u32 if_ctrl; /* 0x5038 */
1443 MAC_IF_STAT_t if_stat; /* 0x503C */
1444 MAC_STATION_ADDR1_t station_addr_1; /* 0x5040 */
1445 MAC_STATION_ADDR2_t station_addr_2; /* 0x5044 */
1446 } MAC_t, *PMAC_t;
1447
1448 /* END OF MAC REGISTER ADDRESS MAP */
1449
1450 /* START OF MAC STAT REGISTER ADDRESS MAP */
1451
1452 /*
1453 * structure for Carry Register One and it's Mask Register reg located in mac
1454 * stat address map address 0x6130 and 0x6138.
1455 *
1456 * 31: tr64
1457 * 30: tr127
1458 * 29: tr255
1459 * 28: tr511
1460 * 27: tr1k
1461 * 26: trmax
1462 * 25: trmgv
1463 * 24-17: unused
1464 * 16: rbyt
1465 * 15: rpkt
1466 * 14: rfcs
1467 * 13: rmca
1468 * 12: rbca
1469 * 11: rxcf
1470 * 10: rxpf
1471 * 9: rxuo
1472 * 8: raln
1473 * 7: rflr
1474 * 6: rcde
1475 * 5: rcse
1476 * 4: rund
1477 * 3: rovr
1478 * 2: rfrg
1479 * 1: rjbr
1480 * 0: rdrp
1481 */
1482
1483 /*
1484 * structure for Carry Register Two Mask Register reg in mac stat address map.
1485 * located at address 0x613C
1486 *
1487 * 31-20: unused
1488 * 19: tjbr
1489 * 18: tfcs
1490 * 17: txcf
1491 * 16: tovr
1492 * 15: tund
1493 * 14: trfg
1494 * 13: tbyt
1495 * 12: tpkt
1496 * 11: tmca
1497 * 10: tbca
1498 * 9: txpf
1499 * 8: tdfr
1500 * 7: tedf
1501 * 6: tscl
1502 * 5: tmcl
1503 * 4: tlcl
1504 * 3: txcl
1505 * 2: tncl
1506 * 1: tpfh
1507 * 0: tdrp
1508 */
1509
1510 /*
1511 * MAC STATS Module of JAGCore Address Mapping
1512 */
1513 typedef struct _MAC_STAT_t { /* Location: */
1514 u32 pad[32]; /* 0x6000 - 607C */
1515
1516 /* Tx/Rx 0-64 Byte Frame Counter */
1517 u32 TR64; /* 0x6080 */
1518
1519 /* Tx/Rx 65-127 Byte Frame Counter */
1520 u32 TR127; /* 0x6084 */
1521
1522 /* Tx/Rx 128-255 Byte Frame Counter */
1523 u32 TR255; /* 0x6088 */
1524
1525 /* Tx/Rx 256-511 Byte Frame Counter */
1526 u32 TR511; /* 0x608C */
1527
1528 /* Tx/Rx 512-1023 Byte Frame Counter */
1529 u32 TR1K; /* 0x6090 */
1530
1531 /* Tx/Rx 1024-1518 Byte Frame Counter */
1532 u32 TRMax; /* 0x6094 */
1533
1534 /* Tx/Rx 1519-1522 Byte Good VLAN Frame Count */
1535 u32 TRMgv; /* 0x6098 */
1536
1537 /* Rx Byte Counter */
1538 u32 RByt; /* 0x609C */
1539
1540 /* Rx Packet Counter */
1541 u32 RPkt; /* 0x60A0 */
1542
1543 /* Rx FCS Error Counter */
1544 u32 RFcs; /* 0x60A4 */
1545
1546 /* Rx Multicast Packet Counter */
1547 u32 RMca; /* 0x60A8 */
1548
1549 /* Rx Broadcast Packet Counter */
1550 u32 RBca; /* 0x60AC */
1551
1552 /* Rx Control Frame Packet Counter */
1553 u32 RxCf; /* 0x60B0 */
1554
1555 /* Rx Pause Frame Packet Counter */
1556 u32 RxPf; /* 0x60B4 */
1557
1558 /* Rx Unknown OP Code Counter */
1559 u32 RxUo; /* 0x60B8 */
1560
1561 /* Rx Alignment Error Counter */
1562 u32 RAln; /* 0x60BC */
1563
1564 /* Rx Frame Length Error Counter */
1565 u32 RFlr; /* 0x60C0 */
1566
1567 /* Rx Code Error Counter */
1568 u32 RCde; /* 0x60C4 */
1569
1570 /* Rx Carrier Sense Error Counter */
1571 u32 RCse; /* 0x60C8 */
1572
1573 /* Rx Undersize Packet Counter */
1574 u32 RUnd; /* 0x60CC */
1575
1576 /* Rx Oversize Packet Counter */
1577 u32 ROvr; /* 0x60D0 */
1578
1579 /* Rx Fragment Counter */
1580 u32 RFrg; /* 0x60D4 */
1581
1582 /* Rx Jabber Counter */
1583 u32 RJbr; /* 0x60D8 */
1584
1585 /* Rx Drop */
1586 u32 RDrp; /* 0x60DC */
1587
1588 /* Tx Byte Counter */
1589 u32 TByt; /* 0x60E0 */
1590
1591 /* Tx Packet Counter */
1592 u32 TPkt; /* 0x60E4 */
1593
1594 /* Tx Multicast Packet Counter */
1595 u32 TMca; /* 0x60E8 */
1596
1597 /* Tx Broadcast Packet Counter */
1598 u32 TBca; /* 0x60EC */
1599
1600 /* Tx Pause Control Frame Counter */
1601 u32 TxPf; /* 0x60F0 */
1602
1603 /* Tx Deferral Packet Counter */
1604 u32 TDfr; /* 0x60F4 */
1605
1606 /* Tx Excessive Deferral Packet Counter */
1607 u32 TEdf; /* 0x60F8 */
1608
1609 /* Tx Single Collision Packet Counter */
1610 u32 TScl; /* 0x60FC */
1611
1612 /* Tx Multiple Collision Packet Counter */
1613 u32 TMcl; /* 0x6100 */
1614
1615 /* Tx Late Collision Packet Counter */
1616 u32 TLcl; /* 0x6104 */
1617
1618 /* Tx Excessive Collision Packet Counter */
1619 u32 TXcl; /* 0x6108 */
1620
1621 /* Tx Total Collision Packet Counter */
1622 u32 TNcl; /* 0x610C */
1623
1624 /* Tx Pause Frame Honored Counter */
1625 u32 TPfh; /* 0x6110 */
1626
1627 /* Tx Drop Frame Counter */
1628 u32 TDrp; /* 0x6114 */
1629
1630 /* Tx Jabber Frame Counter */
1631 u32 TJbr; /* 0x6118 */
1632
1633 /* Tx FCS Error Counter */
1634 u32 TFcs; /* 0x611C */
1635
1636 /* Tx Control Frame Counter */
1637 u32 TxCf; /* 0x6120 */
1638
1639 /* Tx Oversize Frame Counter */
1640 u32 TOvr; /* 0x6124 */
1641
1642 /* Tx Undersize Frame Counter */
1643 u32 TUnd; /* 0x6128 */
1644
1645 /* Tx Fragments Frame Counter */
1646 u32 TFrg; /* 0x612C */
1647
1648 /* Carry Register One Register */
1649 u32 Carry1; /* 0x6130 */
1650
1651 /* Carry Register Two Register */
1652 u32 Carry2; /* 0x6134 */
1653
1654 /* Carry Register One Mask Register */
1655 u32 Carry1M; /* 0x6138 */
1656
1657 /* Carry Register Two Mask Register */
1658 u32 Carry2M; /* 0x613C */
1659 } MAC_STAT_t, *PMAC_STAT_t;
1660
1661 /* END OF MAC STAT REGISTER ADDRESS MAP */
1662
1663
1664 /* START OF MMC REGISTER ADDRESS MAP */
1665
1666 /*
1667 * Main Memory Controller Control reg in mmc address map.
1668 * located at address 0x7000
1669 */
1670
1671 #define ET_MMC_ENABLE 1
1672 #define ET_MMC_ARB_DISABLE 2
1673 #define ET_MMC_RXMAC_DISABLE 4
1674 #define ET_MMC_TXMAC_DISABLE 8
1675 #define ET_MMC_TXDMA_DISABLE 16
1676 #define ET_MMC_RXDMA_DISABLE 32
1677 #define ET_MMC_FORCE_CE 64
1678
1679 /*
1680 * Main Memory Controller Host Memory Access Address reg in mmc
1681 * address map. Located at address 0x7004. Top 16 bits hold the address bits
1682 */
1683
1684 #define ET_SRAM_REQ_ACCESS 1
1685 #define ET_SRAM_WR_ACCESS 2
1686 #define ET_SRAM_IS_CTRL 4
1687
1688 /*
1689 * structure for Main Memory Controller Host Memory Access Data reg in mmc
1690 * address map. Located at address 0x7008 - 0x7014
1691 * Defined earlier (u32)
1692 */
1693
1694 /*
1695 * Memory Control Module of JAGCore Address Mapping
1696 */
1697 typedef struct _MMC_t { /* Location: */
1698 u32 mmc_ctrl; /* 0x7000 */
1699 u32 sram_access; /* 0x7004 */
1700 u32 sram_word1; /* 0x7008 */
1701 u32 sram_word2; /* 0x700C */
1702 u32 sram_word3; /* 0x7010 */
1703 u32 sram_word4; /* 0x7014 */
1704 } MMC_t, *PMMC_t;
1705
1706 /* END OF MMC REGISTER ADDRESS MAP */
1707
1708
1709 /* START OF EXP ROM REGISTER ADDRESS MAP */
1710
1711 /*
1712 * Expansion ROM Module of JAGCore Address Mapping
1713 */
1714
1715 /* Take this out until it is not empty */
1716 #if 0
1717 typedef struct _EXP_ROM_t {
1718
1719 } EXP_ROM_t, *PEXP_ROM_t;
1720 #endif
1721
1722 /* END OF EXP ROM REGISTER ADDRESS MAP */
1723
1724
1725 /*
1726 * JAGCore Address Mapping
1727 */
1728 typedef struct _ADDRESS_MAP_t {
1729 GLOBAL_t global;
1730 /* unused section of global address map */
1731 u8 unused_global[4096 - sizeof(GLOBAL_t)];
1732 TXDMA_t txdma;
1733 /* unused section of txdma address map */
1734 u8 unused_txdma[4096 - sizeof(TXDMA_t)];
1735 RXDMA_t rxdma;
1736 /* unused section of rxdma address map */
1737 u8 unused_rxdma[4096 - sizeof(RXDMA_t)];
1738 TXMAC_t txmac;
1739 /* unused section of txmac address map */
1740 u8 unused_txmac[4096 - sizeof(TXMAC_t)];
1741 RXMAC_t rxmac;
1742 /* unused section of rxmac address map */
1743 u8 unused_rxmac[4096 - sizeof(RXMAC_t)];
1744 MAC_t mac;
1745 /* unused section of mac address map */
1746 u8 unused_mac[4096 - sizeof(MAC_t)];
1747 MAC_STAT_t macStat;
1748 /* unused section of mac stat address map */
1749 u8 unused_mac_stat[4096 - sizeof(MAC_STAT_t)];
1750 MMC_t mmc;
1751 /* unused section of mmc address map */
1752 u8 unused_mmc[4096 - sizeof(MMC_t)];
1753 /* unused section of address map */
1754 u8 unused_[1015808];
1755
1756 /* Take this out until it is not empty */
1757 #if 0
1758 EXP_ROM_t exp_rom;
1759 #endif
1760
1761 u8 unused_exp_rom[4096]; /* MGS-size TBD */
1762 u8 unused__[524288]; /* unused section of address map */
1763 } ADDRESS_MAP_t, *PADDRESS_MAP_t;
1764
1765 #endif /* _ET1310_ADDRESS_MAP_H_ */
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