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bnx2x: Semantic renovation
[linux-2.6.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
blob502cea13aa2eff59bd28d13f126c4f323cd4e00d
1 /* bnx2x_main.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/device.h> /* for dev_info() */
24 #include <linux/timer.h>
25 #include <linux/errno.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/bitops.h>
36 #include <linux/irq.h>
37 #include <linux/delay.h>
38 #include <asm/byteorder.h>
39 #include <linux/time.h>
40 #include <linux/ethtool.h>
41 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
43 #include <net/ip.h>
44 #include <net/ipv6.h>
45 #include <net/tcp.h>
46 #include <net/checksum.h>
47 #include <net/ip6_checksum.h>
48 #include <linux/workqueue.h>
49 #include <linux/crc32.h>
50 #include <linux/crc32c.h>
51 #include <linux/prefetch.h>
52 #include <linux/zlib.h>
53 #include <linux/io.h>
54 #include <linux/semaphore.h>
55 #include <linux/stringify.h>
56 #include <linux/vmalloc.h>
57
58 #include "bnx2x.h"
59 #include "bnx2x_init.h"
60 #include "bnx2x_init_ops.h"
61 #include "bnx2x_cmn.h"
62 #include "bnx2x_vfpf.h"
63 #include "bnx2x_dcb.h"
64 #include "bnx2x_sp.h"
65
66 #include <linux/firmware.h>
67 #include "bnx2x_fw_file_hdr.h"
68 /* FW files */
69 #define FW_FILE_VERSION \
70 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
71 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
72 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
73 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
74 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
75 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
76 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
77
78 #define MAC_LEADING_ZERO_CNT (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN)
79
80 /* Time in jiffies before concluding the transmitter is hung */
81 #define TX_TIMEOUT (5*HZ)
82
83 static char version[] =
84 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
85 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
86
87 MODULE_AUTHOR("Eliezer Tamir");
88 MODULE_DESCRIPTION("Broadcom NetXtreme II "
89 "BCM57710/57711/57711E/"
90 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
91 "57840/57840_MF Driver");
92 MODULE_LICENSE("GPL");
93 MODULE_VERSION(DRV_MODULE_VERSION);
94 MODULE_FIRMWARE(FW_FILE_NAME_E1);
95 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
96 MODULE_FIRMWARE(FW_FILE_NAME_E2);
97
98
99 int num_queues;
100 module_param(num_queues, int, 0);
101 MODULE_PARM_DESC(num_queues,
102 " Set number of queues (default is as a number of CPUs)");
103
104 static int disable_tpa;
105 module_param(disable_tpa, int, 0);
106 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
107
108 #define INT_MODE_INTx 1
109 #define INT_MODE_MSI 2
110 int int_mode;
111 module_param(int_mode, int, 0);
112 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
113 "(1 INT#x; 2 MSI)");
114
115 static int dropless_fc;
116 module_param(dropless_fc, int, 0);
117 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
118
119 static int mrrs = -1;
120 module_param(mrrs, int, 0);
121 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
122
123 static int debug;
124 module_param(debug, int, 0);
125 MODULE_PARM_DESC(debug, " Default debug msglevel");
126
127
128
129 struct workqueue_struct *bnx2x_wq;
130
131 struct bnx2x_mac_vals {
132 u32 xmac_addr;
133 u32 xmac_val;
134 u32 emac_addr;
135 u32 emac_val;
136 u32 umac_addr;
137 u32 umac_val;
138 u32 bmac_addr;
139 u32 bmac_val[2];
140 };
141
142 enum bnx2x_board_type {
143 BCM57710 = 0,
144 BCM57711,
145 BCM57711E,
146 BCM57712,
147 BCM57712_MF,
148 BCM57712_VF,
149 BCM57800,
150 BCM57800_MF,
151 BCM57800_VF,
152 BCM57810,
153 BCM57810_MF,
154 BCM57810_VF,
155 BCM57840_4_10,
156 BCM57840_2_20,
157 BCM57840_MF,
158 BCM57840_VF,
159 BCM57811,
160 BCM57811_MF,
161 BCM57840_O,
162 BCM57840_MFO,
163 BCM57811_VF
164 };
165
166 /* indexed by board_type, above */
167 static struct {
168 char *name;
169 } board_info[] = {
170 [BCM57710] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
171 [BCM57711] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
172 [BCM57711E] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
173 [BCM57712] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
174 [BCM57712_MF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
175 [BCM57712_VF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
176 [BCM57800] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
177 [BCM57800_MF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
178 [BCM57800_VF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
179 [BCM57810] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
180 [BCM57810_MF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
181 [BCM57810_VF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
182 [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
183 [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
184 [BCM57840_MF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
185 [BCM57840_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
186 [BCM57811] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
187 [BCM57811_MF] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
188 [BCM57840_O] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
189 [BCM57840_MFO] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
190 [BCM57811_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
191 };
192
193 #ifndef PCI_DEVICE_ID_NX2_57710
194 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
195 #endif
196 #ifndef PCI_DEVICE_ID_NX2_57711
197 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
198 #endif
199 #ifndef PCI_DEVICE_ID_NX2_57711E
200 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
201 #endif
202 #ifndef PCI_DEVICE_ID_NX2_57712
203 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
204 #endif
205 #ifndef PCI_DEVICE_ID_NX2_57712_MF
206 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
207 #endif
208 #ifndef PCI_DEVICE_ID_NX2_57712_VF
209 #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
210 #endif
211 #ifndef PCI_DEVICE_ID_NX2_57800
212 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
213 #endif
214 #ifndef PCI_DEVICE_ID_NX2_57800_MF
215 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
216 #endif
217 #ifndef PCI_DEVICE_ID_NX2_57800_VF
218 #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
219 #endif
220 #ifndef PCI_DEVICE_ID_NX2_57810
221 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
222 #endif
223 #ifndef PCI_DEVICE_ID_NX2_57810_MF
224 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
225 #endif
226 #ifndef PCI_DEVICE_ID_NX2_57840_O
227 #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
228 #endif
229 #ifndef PCI_DEVICE_ID_NX2_57810_VF
230 #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
231 #endif
232 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
233 #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
234 #endif
235 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
236 #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
237 #endif
238 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
239 #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
240 #endif
241 #ifndef PCI_DEVICE_ID_NX2_57840_MF
242 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
243 #endif
244 #ifndef PCI_DEVICE_ID_NX2_57840_VF
245 #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
246 #endif
247 #ifndef PCI_DEVICE_ID_NX2_57811
248 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
249 #endif
250 #ifndef PCI_DEVICE_ID_NX2_57811_MF
251 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
252 #endif
253 #ifndef PCI_DEVICE_ID_NX2_57811_VF
254 #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
255 #endif
256
257 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
258 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
259 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
260 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
261 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
268 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
269 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
270 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
271 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
272 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
273 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
274 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
275 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
276 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
277 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
278 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
279 { 0 }
280 };
281
282 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
283
284 /* Global resources for unloading a previously loaded device */
285 #define BNX2X_PREV_WAIT_NEEDED 1
286 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
287 static LIST_HEAD(bnx2x_prev_list);
288 /****************************************************************************
289 * General service functions
290 ****************************************************************************/
291
292 static void __storm_memset_dma_mapping(struct bnx2x *bp,
293 u32 addr, dma_addr_t mapping)
294 {
295 REG_WR(bp, addr, U64_LO(mapping));
296 REG_WR(bp, addr + 4, U64_HI(mapping));
297 }
298
299 static void storm_memset_spq_addr(struct bnx2x *bp,
300 dma_addr_t mapping, u16 abs_fid)
301 {
302 u32 addr = XSEM_REG_FAST_MEMORY +
303 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
304
305 __storm_memset_dma_mapping(bp, addr, mapping);
306 }
307
308 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
309 u16 pf_id)
310 {
311 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
312 pf_id);
313 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
314 pf_id);
315 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
316 pf_id);
317 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
318 pf_id);
319 }
320
321 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
322 u8 enable)
323 {
324 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
325 enable);
326 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
327 enable);
328 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
329 enable);
330 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
331 enable);
332 }
333
334 static void storm_memset_eq_data(struct bnx2x *bp,
335 struct event_ring_data *eq_data,
336 u16 pfid)
337 {
338 size_t size = sizeof(struct event_ring_data);
339
340 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
341
342 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
343 }
344
345 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
346 u16 pfid)
347 {
348 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
349 REG_WR16(bp, addr, eq_prod);
350 }
351
352 /* used only at init
353 * locking is done by mcp
354 */
355 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
356 {
357 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
358 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
359 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
360 PCICFG_VENDOR_ID_OFFSET);
361 }
362
363 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
364 {
365 u32 val;
366
367 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
368 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
369 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
370 PCICFG_VENDOR_ID_OFFSET);
371
372 return val;
373 }
374
375 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
376 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
377 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
378 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
379 #define DMAE_DP_DST_NONE "dst_addr [none]"
380
381 void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, int msglvl)
382 {
383 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
384
385 switch (dmae->opcode & DMAE_COMMAND_DST) {
386 case DMAE_CMD_DST_PCI:
387 if (src_type == DMAE_CMD_SRC_PCI)
388 DP(msglvl, "DMAE: opcode 0x%08x\n"
389 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
390 "comp_addr [%x:%08x], comp_val 0x%08x\n",
391 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
392 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
393 dmae->comp_addr_hi, dmae->comp_addr_lo,
394 dmae->comp_val);
395 else
396 DP(msglvl, "DMAE: opcode 0x%08x\n"
397 "src [%08x], len [%d*4], dst [%x:%08x]\n"
398 "comp_addr [%x:%08x], comp_val 0x%08x\n",
399 dmae->opcode, dmae->src_addr_lo >> 2,
400 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
401 dmae->comp_addr_hi, dmae->comp_addr_lo,
402 dmae->comp_val);
403 break;
404 case DMAE_CMD_DST_GRC:
405 if (src_type == DMAE_CMD_SRC_PCI)
406 DP(msglvl, "DMAE: opcode 0x%08x\n"
407 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
408 "comp_addr [%x:%08x], comp_val 0x%08x\n",
409 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
410 dmae->len, dmae->dst_addr_lo >> 2,
411 dmae->comp_addr_hi, dmae->comp_addr_lo,
412 dmae->comp_val);
413 else
414 DP(msglvl, "DMAE: opcode 0x%08x\n"
415 "src [%08x], len [%d*4], dst [%08x]\n"
416 "comp_addr [%x:%08x], comp_val 0x%08x\n",
417 dmae->opcode, dmae->src_addr_lo >> 2,
418 dmae->len, dmae->dst_addr_lo >> 2,
419 dmae->comp_addr_hi, dmae->comp_addr_lo,
420 dmae->comp_val);
421 break;
422 default:
423 if (src_type == DMAE_CMD_SRC_PCI)
424 DP(msglvl, "DMAE: opcode 0x%08x\n"
425 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
426 "comp_addr [%x:%08x] comp_val 0x%08x\n",
427 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
428 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
429 dmae->comp_val);
430 else
431 DP(msglvl, "DMAE: opcode 0x%08x\n"
432 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
433 "comp_addr [%x:%08x] comp_val 0x%08x\n",
434 dmae->opcode, dmae->src_addr_lo >> 2,
435 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
436 dmae->comp_val);
437 break;
438 }
439 }
440
441 /* copy command into DMAE command memory and set DMAE command go */
442 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
443 {
444 u32 cmd_offset;
445 int i;
446
447 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
448 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
449 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
450 }
451 REG_WR(bp, dmae_reg_go_c[idx], 1);
452 }
453
454 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
455 {
456 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
457 DMAE_CMD_C_ENABLE);
458 }
459
460 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
461 {
462 return opcode & ~DMAE_CMD_SRC_RESET;
463 }
464
465 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
466 bool with_comp, u8 comp_type)
467 {
468 u32 opcode = 0;
469
470 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
471 (dst_type << DMAE_COMMAND_DST_SHIFT));
472
473 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
474
475 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
476 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
477 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
478 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
479
480 #ifdef __BIG_ENDIAN
481 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
482 #else
483 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
484 #endif
485 if (with_comp)
486 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
487 return opcode;
488 }
489
490 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
491 struct dmae_command *dmae,
492 u8 src_type, u8 dst_type)
493 {
494 memset(dmae, 0, sizeof(struct dmae_command));
495
496 /* set the opcode */
497 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
498 true, DMAE_COMP_PCI);
499
500 /* fill in the completion parameters */
501 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
502 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
503 dmae->comp_val = DMAE_COMP_VAL;
504 }
505
506 /* issue a dmae command over the init-channel and wait for completion */
507 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae)
508 {
509 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
510 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
511 int rc = 0;
512
513 /*
514 * Lock the dmae channel. Disable BHs to prevent a dead-lock
515 * as long as this code is called both from syscall context and
516 * from ndo_set_rx_mode() flow that may be called from BH.
517 */
518 spin_lock_bh(&bp->dmae_lock);
519
520 /* reset completion */
521 *wb_comp = 0;
522
523 /* post the command on the channel used for initializations */
524 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
525
526 /* wait for completion */
527 udelay(5);
528 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
529
530 if (!cnt ||
531 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
532 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
533 BNX2X_ERR("DMAE timeout!\n");
534 rc = DMAE_TIMEOUT;
535 goto unlock;
536 }
537 cnt--;
538 udelay(50);
539 }
540 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
541 BNX2X_ERR("DMAE PCI error!\n");
542 rc = DMAE_PCI_ERROR;
543 }
544
545 unlock:
546 spin_unlock_bh(&bp->dmae_lock);
547 return rc;
548 }
549
550 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
551 u32 len32)
552 {
553 struct dmae_command dmae;
554
555 if (!bp->dmae_ready) {
556 u32 *data = bnx2x_sp(bp, wb_data[0]);
557
558 if (CHIP_IS_E1(bp))
559 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
560 else
561 bnx2x_init_str_wr(bp, dst_addr, data, len32);
562 return;
563 }
564
565 /* set opcode and fixed command fields */
566 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
567
568 /* fill in addresses and len */
569 dmae.src_addr_lo = U64_LO(dma_addr);
570 dmae.src_addr_hi = U64_HI(dma_addr);
571 dmae.dst_addr_lo = dst_addr >> 2;
572 dmae.dst_addr_hi = 0;
573 dmae.len = len32;
574
575 /* issue the command and wait for completion */
576 bnx2x_issue_dmae_with_comp(bp, &dmae);
577 }
578
579 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
580 {
581 struct dmae_command dmae;
582
583 if (!bp->dmae_ready) {
584 u32 *data = bnx2x_sp(bp, wb_data[0]);
585 int i;
586
587 if (CHIP_IS_E1(bp))
588 for (i = 0; i < len32; i++)
589 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
590 else
591 for (i = 0; i < len32; i++)
592 data[i] = REG_RD(bp, src_addr + i*4);
593
594 return;
595 }
596
597 /* set opcode and fixed command fields */
598 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
599
600 /* fill in addresses and len */
601 dmae.src_addr_lo = src_addr >> 2;
602 dmae.src_addr_hi = 0;
603 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
604 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
605 dmae.len = len32;
606
607 /* issue the command and wait for completion */
608 bnx2x_issue_dmae_with_comp(bp, &dmae);
609 }
610
611 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
612 u32 addr, u32 len)
613 {
614 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
615 int offset = 0;
616
617 while (len > dmae_wr_max) {
618 bnx2x_write_dmae(bp, phys_addr + offset,
619 addr + offset, dmae_wr_max);
620 offset += dmae_wr_max * 4;
621 len -= dmae_wr_max;
622 }
623
624 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
625 }
626
627 static int bnx2x_mc_assert(struct bnx2x *bp)
628 {
629 char last_idx;
630 int i, rc = 0;
631 u32 row0, row1, row2, row3;
632
633 /* XSTORM */
634 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
635 XSTORM_ASSERT_LIST_INDEX_OFFSET);
636 if (last_idx)
637 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
638
639 /* print the asserts */
640 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
641
642 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
643 XSTORM_ASSERT_LIST_OFFSET(i));
644 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
645 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
646 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
647 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
648 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
649 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
650
651 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
652 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
653 i, row3, row2, row1, row0);
654 rc++;
655 } else {
656 break;
657 }
658 }
659
660 /* TSTORM */
661 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
662 TSTORM_ASSERT_LIST_INDEX_OFFSET);
663 if (last_idx)
664 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
665
666 /* print the asserts */
667 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
668
669 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
670 TSTORM_ASSERT_LIST_OFFSET(i));
671 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
672 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
673 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
674 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
675 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
676 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
677
678 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
679 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
680 i, row3, row2, row1, row0);
681 rc++;
682 } else {
683 break;
684 }
685 }
686
687 /* CSTORM */
688 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
689 CSTORM_ASSERT_LIST_INDEX_OFFSET);
690 if (last_idx)
691 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
692
693 /* print the asserts */
694 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
695
696 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
697 CSTORM_ASSERT_LIST_OFFSET(i));
698 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
699 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
700 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
701 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
702 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
703 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
704
705 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
706 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
707 i, row3, row2, row1, row0);
708 rc++;
709 } else {
710 break;
711 }
712 }
713
714 /* USTORM */
715 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
716 USTORM_ASSERT_LIST_INDEX_OFFSET);
717 if (last_idx)
718 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
719
720 /* print the asserts */
721 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
722
723 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
724 USTORM_ASSERT_LIST_OFFSET(i));
725 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
726 USTORM_ASSERT_LIST_OFFSET(i) + 4);
727 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
728 USTORM_ASSERT_LIST_OFFSET(i) + 8);
729 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
730 USTORM_ASSERT_LIST_OFFSET(i) + 12);
731
732 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
733 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
734 i, row3, row2, row1, row0);
735 rc++;
736 } else {
737 break;
738 }
739 }
740
741 return rc;
742 }
743
744 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
745 {
746 u32 addr, val;
747 u32 mark, offset;
748 __be32 data[9];
749 int word;
750 u32 trace_shmem_base;
751 if (BP_NOMCP(bp)) {
752 BNX2X_ERR("NO MCP - can not dump\n");
753 return;
754 }
755 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
756 (bp->common.bc_ver & 0xff0000) >> 16,
757 (bp->common.bc_ver & 0xff00) >> 8,
758 (bp->common.bc_ver & 0xff));
759
760 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
761 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
762 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
763
764 if (BP_PATH(bp) == 0)
765 trace_shmem_base = bp->common.shmem_base;
766 else
767 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
768 addr = trace_shmem_base - 0x800;
769
770 /* validate TRCB signature */
771 mark = REG_RD(bp, addr);
772 if (mark != MFW_TRACE_SIGNATURE) {
773 BNX2X_ERR("Trace buffer signature is missing.");
774 return ;
775 }
776
777 /* read cyclic buffer pointer */
778 addr += 4;
779 mark = REG_RD(bp, addr);
780 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
781 + ((mark + 0x3) & ~0x3) - 0x08000000;
782 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
783
784 printk("%s", lvl);
785
786 /* dump buffer after the mark */
787 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
788 for (word = 0; word < 8; word++)
789 data[word] = htonl(REG_RD(bp, offset + 4*word));
790 data[8] = 0x0;
791 pr_cont("%s", (char *)data);
792 }
793
794 /* dump buffer before the mark */
795 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
796 for (word = 0; word < 8; word++)
797 data[word] = htonl(REG_RD(bp, offset + 4*word));
798 data[8] = 0x0;
799 pr_cont("%s", (char *)data);
800 }
801 printk("%s" "end of fw dump\n", lvl);
802 }
803
804 static void bnx2x_fw_dump(struct bnx2x *bp)
805 {
806 bnx2x_fw_dump_lvl(bp, KERN_ERR);
807 }
808
809 static void bnx2x_hc_int_disable(struct bnx2x *bp)
810 {
811 int port = BP_PORT(bp);
812 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
813 u32 val = REG_RD(bp, addr);
814
815 /* in E1 we must use only PCI configuration space to disable
816 * MSI/MSIX capablility
817 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
818 */
819 if (CHIP_IS_E1(bp)) {
820 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
821 * Use mask register to prevent from HC sending interrupts
822 * after we exit the function
823 */
824 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
825
826 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
827 HC_CONFIG_0_REG_INT_LINE_EN_0 |
828 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
829 } else
830 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
831 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
832 HC_CONFIG_0_REG_INT_LINE_EN_0 |
833 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
834
835 DP(NETIF_MSG_IFDOWN,
836 "write %x to HC %d (addr 0x%x)\n",
837 val, port, addr);
838
839 /* flush all outstanding writes */
840 mmiowb();
841
842 REG_WR(bp, addr, val);
843 if (REG_RD(bp, addr) != val)
844 BNX2X_ERR("BUG! proper val not read from IGU!\n");
845 }
846
847 static void bnx2x_igu_int_disable(struct bnx2x *bp)
848 {
849 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
850
851 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
852 IGU_PF_CONF_INT_LINE_EN |
853 IGU_PF_CONF_ATTN_BIT_EN);
854
855 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
856
857 /* flush all outstanding writes */
858 mmiowb();
859
860 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
861 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
862 BNX2X_ERR("BUG! proper val not read from IGU!\n");
863 }
864
865 static void bnx2x_int_disable(struct bnx2x *bp)
866 {
867 if (bp->common.int_block == INT_BLOCK_HC)
868 bnx2x_hc_int_disable(bp);
869 else
870 bnx2x_igu_int_disable(bp);
871 }
872
873 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
874 {
875 int i;
876 u16 j;
877 struct hc_sp_status_block_data sp_sb_data;
878 int func = BP_FUNC(bp);
879 #ifdef BNX2X_STOP_ON_ERROR
880 u16 start = 0, end = 0;
881 u8 cos;
882 #endif
883 if (disable_int)
884 bnx2x_int_disable(bp);
885
886 bp->stats_state = STATS_STATE_DISABLED;
887 bp->eth_stats.unrecoverable_error++;
888 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
889
890 BNX2X_ERR("begin crash dump -----------------\n");
891
892 /* Indices */
893 /* Common */
894 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
895 bp->def_idx, bp->def_att_idx, bp->attn_state,
896 bp->spq_prod_idx, bp->stats_counter);
897 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
898 bp->def_status_blk->atten_status_block.attn_bits,
899 bp->def_status_blk->atten_status_block.attn_bits_ack,
900 bp->def_status_blk->atten_status_block.status_block_id,
901 bp->def_status_blk->atten_status_block.attn_bits_index);
902 BNX2X_ERR(" def (");
903 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
904 pr_cont("0x%x%s",
905 bp->def_status_blk->sp_sb.index_values[i],
906 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
907
908 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
909 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
910 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
911 i*sizeof(u32));
912
913 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
914 sp_sb_data.igu_sb_id,
915 sp_sb_data.igu_seg_id,
916 sp_sb_data.p_func.pf_id,
917 sp_sb_data.p_func.vnic_id,
918 sp_sb_data.p_func.vf_id,
919 sp_sb_data.p_func.vf_valid,
920 sp_sb_data.state);
921
922
923 for_each_eth_queue(bp, i) {
924 struct bnx2x_fastpath *fp = &bp->fp[i];
925 int loop;
926 struct hc_status_block_data_e2 sb_data_e2;
927 struct hc_status_block_data_e1x sb_data_e1x;
928 struct hc_status_block_sm *hc_sm_p =
929 CHIP_IS_E1x(bp) ?
930 sb_data_e1x.common.state_machine :
931 sb_data_e2.common.state_machine;
932 struct hc_index_data *hc_index_p =
933 CHIP_IS_E1x(bp) ?
934 sb_data_e1x.index_data :
935 sb_data_e2.index_data;
936 u8 data_size, cos;
937 u32 *sb_data_p;
938 struct bnx2x_fp_txdata txdata;
939
940 /* Rx */
941 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
942 i, fp->rx_bd_prod, fp->rx_bd_cons,
943 fp->rx_comp_prod,
944 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
945 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
946 fp->rx_sge_prod, fp->last_max_sge,
947 le16_to_cpu(fp->fp_hc_idx));
948
949 /* Tx */
950 for_each_cos_in_tx_queue(fp, cos)
951 {
952 txdata = *fp->txdata_ptr[cos];
953 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
954 i, txdata.tx_pkt_prod,
955 txdata.tx_pkt_cons, txdata.tx_bd_prod,
956 txdata.tx_bd_cons,
957 le16_to_cpu(*txdata.tx_cons_sb));
958 }
959
960 loop = CHIP_IS_E1x(bp) ?
961 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
962
963 /* host sb data */
964
965 if (IS_FCOE_FP(fp))
966 continue;
967
968 BNX2X_ERR(" run indexes (");
969 for (j = 0; j < HC_SB_MAX_SM; j++)
970 pr_cont("0x%x%s",
971 fp->sb_running_index[j],
972 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
973
974 BNX2X_ERR(" indexes (");
975 for (j = 0; j < loop; j++)
976 pr_cont("0x%x%s",
977 fp->sb_index_values[j],
978 (j == loop - 1) ? ")" : " ");
979 /* fw sb data */
980 data_size = CHIP_IS_E1x(bp) ?
981 sizeof(struct hc_status_block_data_e1x) :
982 sizeof(struct hc_status_block_data_e2);
983 data_size /= sizeof(u32);
984 sb_data_p = CHIP_IS_E1x(bp) ?
985 (u32 *)&sb_data_e1x :
986 (u32 *)&sb_data_e2;
987 /* copy sb data in here */
988 for (j = 0; j < data_size; j++)
989 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
990 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
991 j * sizeof(u32));
992
993 if (!CHIP_IS_E1x(bp)) {
994 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
995 sb_data_e2.common.p_func.pf_id,
996 sb_data_e2.common.p_func.vf_id,
997 sb_data_e2.common.p_func.vf_valid,
998 sb_data_e2.common.p_func.vnic_id,
999 sb_data_e2.common.same_igu_sb_1b,
1000 sb_data_e2.common.state);
1001 } else {
1002 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1003 sb_data_e1x.common.p_func.pf_id,
1004 sb_data_e1x.common.p_func.vf_id,
1005 sb_data_e1x.common.p_func.vf_valid,
1006 sb_data_e1x.common.p_func.vnic_id,
1007 sb_data_e1x.common.same_igu_sb_1b,
1008 sb_data_e1x.common.state);
1009 }
1010
1011 /* SB_SMs data */
1012 for (j = 0; j < HC_SB_MAX_SM; j++) {
1013 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1014 j, hc_sm_p[j].__flags,
1015 hc_sm_p[j].igu_sb_id,
1016 hc_sm_p[j].igu_seg_id,
1017 hc_sm_p[j].time_to_expire,
1018 hc_sm_p[j].timer_value);
1019 }
1020
1021 /* Indecies data */
1022 for (j = 0; j < loop; j++) {
1023 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1024 hc_index_p[j].flags,
1025 hc_index_p[j].timeout);
1026 }
1027 }
1028
1029 #ifdef BNX2X_STOP_ON_ERROR
1030 /* Rings */
1031 /* Rx */
1032 for_each_valid_rx_queue(bp, i) {
1033 struct bnx2x_fastpath *fp = &bp->fp[i];
1034
1035 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1036 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1037 for (j = start; j != end; j = RX_BD(j + 1)) {
1038 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1039 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1040
1041 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
1042 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1043 }
1044
1045 start = RX_SGE(fp->rx_sge_prod);
1046 end = RX_SGE(fp->last_max_sge);
1047 for (j = start; j != end; j = RX_SGE(j + 1)) {
1048 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1049 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1050
1051 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1052 i, j, rx_sge[1], rx_sge[0], sw_page->page);
1053 }
1054
1055 start = RCQ_BD(fp->rx_comp_cons - 10);
1056 end = RCQ_BD(fp->rx_comp_cons + 503);
1057 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1058 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1059
1060 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1061 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1062 }
1063 }
1064
1065 /* Tx */
1066 for_each_valid_tx_queue(bp, i) {
1067 struct bnx2x_fastpath *fp = &bp->fp[i];
1068 for_each_cos_in_tx_queue(fp, cos) {
1069 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1070
1071 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1072 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1073 for (j = start; j != end; j = TX_BD(j + 1)) {
1074 struct sw_tx_bd *sw_bd =
1075 &txdata->tx_buf_ring[j];
1076
1077 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1078 i, cos, j, sw_bd->skb,
1079 sw_bd->first_bd);
1080 }
1081
1082 start = TX_BD(txdata->tx_bd_cons - 10);
1083 end = TX_BD(txdata->tx_bd_cons + 254);
1084 for (j = start; j != end; j = TX_BD(j + 1)) {
1085 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1086
1087 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1088 i, cos, j, tx_bd[0], tx_bd[1],
1089 tx_bd[2], tx_bd[3]);
1090 }
1091 }
1092 }
1093 #endif
1094 bnx2x_fw_dump(bp);
1095 bnx2x_mc_assert(bp);
1096 BNX2X_ERR("end crash dump -----------------\n");
1097 }
1098
1099 /*
1100 * FLR Support for E2
1101 *
1102 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1103 * initialization.
1104 */
1105 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */
1106 #define FLR_WAIT_INTERVAL 50 /* usec */
1107 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1108
1109 struct pbf_pN_buf_regs {
1110 int pN;
1111 u32 init_crd;
1112 u32 crd;
1113 u32 crd_freed;
1114 };
1115
1116 struct pbf_pN_cmd_regs {
1117 int pN;
1118 u32 lines_occup;
1119 u32 lines_freed;
1120 };
1121
1122 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1123 struct pbf_pN_buf_regs *regs,
1124 u32 poll_count)
1125 {
1126 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1127 u32 cur_cnt = poll_count;
1128
1129 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1130 crd = crd_start = REG_RD(bp, regs->crd);
1131 init_crd = REG_RD(bp, regs->init_crd);
1132
1133 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1134 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1135 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1136
1137 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1138 (init_crd - crd_start))) {
1139 if (cur_cnt--) {
1140 udelay(FLR_WAIT_INTERVAL);
1141 crd = REG_RD(bp, regs->crd);
1142 crd_freed = REG_RD(bp, regs->crd_freed);
1143 } else {
1144 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1145 regs->pN);
1146 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1147 regs->pN, crd);
1148 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1149 regs->pN, crd_freed);
1150 break;
1151 }
1152 }
1153 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1154 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1155 }
1156
1157 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1158 struct pbf_pN_cmd_regs *regs,
1159 u32 poll_count)
1160 {
1161 u32 occup, to_free, freed, freed_start;
1162 u32 cur_cnt = poll_count;
1163
1164 occup = to_free = REG_RD(bp, regs->lines_occup);
1165 freed = freed_start = REG_RD(bp, regs->lines_freed);
1166
1167 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1168 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1169
1170 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1171 if (cur_cnt--) {
1172 udelay(FLR_WAIT_INTERVAL);
1173 occup = REG_RD(bp, regs->lines_occup);
1174 freed = REG_RD(bp, regs->lines_freed);
1175 } else {
1176 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1177 regs->pN);
1178 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1179 regs->pN, occup);
1180 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1181 regs->pN, freed);
1182 break;
1183 }
1184 }
1185 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1186 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1187 }
1188
1189 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1190 u32 expected, u32 poll_count)
1191 {
1192 u32 cur_cnt = poll_count;
1193 u32 val;
1194
1195 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1196 udelay(FLR_WAIT_INTERVAL);
1197
1198 return val;
1199 }
1200
1201 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1202 char *msg, u32 poll_cnt)
1203 {
1204 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1205 if (val != 0) {
1206 BNX2X_ERR("%s usage count=%d\n", msg, val);
1207 return 1;
1208 }
1209 return 0;
1210 }
1211
1212 /* Common routines with VF FLR cleanup */
1213 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1214 {
1215 /* adjust polling timeout */
1216 if (CHIP_REV_IS_EMUL(bp))
1217 return FLR_POLL_CNT * 2000;
1218
1219 if (CHIP_REV_IS_FPGA(bp))
1220 return FLR_POLL_CNT * 120;
1221
1222 return FLR_POLL_CNT;
1223 }
1224
1225 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1226 {
1227 struct pbf_pN_cmd_regs cmd_regs[] = {
1228 {0, (CHIP_IS_E3B0(bp)) ?
1229 PBF_REG_TQ_OCCUPANCY_Q0 :
1230 PBF_REG_P0_TQ_OCCUPANCY,
1231 (CHIP_IS_E3B0(bp)) ?
1232 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1233 PBF_REG_P0_TQ_LINES_FREED_CNT},
1234 {1, (CHIP_IS_E3B0(bp)) ?
1235 PBF_REG_TQ_OCCUPANCY_Q1 :
1236 PBF_REG_P1_TQ_OCCUPANCY,
1237 (CHIP_IS_E3B0(bp)) ?
1238 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1239 PBF_REG_P1_TQ_LINES_FREED_CNT},
1240 {4, (CHIP_IS_E3B0(bp)) ?
1241 PBF_REG_TQ_OCCUPANCY_LB_Q :
1242 PBF_REG_P4_TQ_OCCUPANCY,
1243 (CHIP_IS_E3B0(bp)) ?
1244 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1245 PBF_REG_P4_TQ_LINES_FREED_CNT}
1246 };
1247
1248 struct pbf_pN_buf_regs buf_regs[] = {
1249 {0, (CHIP_IS_E3B0(bp)) ?
1250 PBF_REG_INIT_CRD_Q0 :
1251 PBF_REG_P0_INIT_CRD ,
1252 (CHIP_IS_E3B0(bp)) ?
1253 PBF_REG_CREDIT_Q0 :
1254 PBF_REG_P0_CREDIT,
1255 (CHIP_IS_E3B0(bp)) ?
1256 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1257 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1258 {1, (CHIP_IS_E3B0(bp)) ?
1259 PBF_REG_INIT_CRD_Q1 :
1260 PBF_REG_P1_INIT_CRD,
1261 (CHIP_IS_E3B0(bp)) ?
1262 PBF_REG_CREDIT_Q1 :
1263 PBF_REG_P1_CREDIT,
1264 (CHIP_IS_E3B0(bp)) ?
1265 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1266 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1267 {4, (CHIP_IS_E3B0(bp)) ?
1268 PBF_REG_INIT_CRD_LB_Q :
1269 PBF_REG_P4_INIT_CRD,
1270 (CHIP_IS_E3B0(bp)) ?
1271 PBF_REG_CREDIT_LB_Q :
1272 PBF_REG_P4_CREDIT,
1273 (CHIP_IS_E3B0(bp)) ?
1274 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1275 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1276 };
1277
1278 int i;
1279
1280 /* Verify the command queues are flushed P0, P1, P4 */
1281 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1282 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1283
1284
1285 /* Verify the transmission buffers are flushed P0, P1, P4 */
1286 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1287 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1288 }
1289
1290 #define OP_GEN_PARAM(param) \
1291 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1292
1293 #define OP_GEN_TYPE(type) \
1294 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1295
1296 #define OP_GEN_AGG_VECT(index) \
1297 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1298
1299
1300 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1301 {
1302 struct sdm_op_gen op_gen = {0};
1303
1304 u32 comp_addr = BAR_CSTRORM_INTMEM +
1305 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1306 int ret = 0;
1307
1308 if (REG_RD(bp, comp_addr)) {
1309 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1310 return 1;
1311 }
1312
1313 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1314 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1315 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1316 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1317
1318 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1319 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1320
1321 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1322 BNX2X_ERR("FW final cleanup did not succeed\n");
1323 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1324 (REG_RD(bp, comp_addr)));
1325 bnx2x_panic();
1326 return 1;
1327 }
1328 /* Zero completion for nxt FLR */
1329 REG_WR(bp, comp_addr, 0);
1330
1331 return ret;
1332 }
1333
1334 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1335 {
1336 u16 status;
1337
1338 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1339 return status & PCI_EXP_DEVSTA_TRPND;
1340 }
1341
1342 /* PF FLR specific routines
1343 */
1344 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1345 {
1346
1347 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1348 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1349 CFC_REG_NUM_LCIDS_INSIDE_PF,
1350 "CFC PF usage counter timed out",
1351 poll_cnt))
1352 return 1;
1353
1354
1355 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1356 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1357 DORQ_REG_PF_USAGE_CNT,
1358 "DQ PF usage counter timed out",
1359 poll_cnt))
1360 return 1;
1361
1362 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1363 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1364 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1365 "QM PF usage counter timed out",
1366 poll_cnt))
1367 return 1;
1368
1369 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1370 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1371 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1372 "Timers VNIC usage counter timed out",
1373 poll_cnt))
1374 return 1;
1375 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1376 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1377 "Timers NUM_SCANS usage counter timed out",
1378 poll_cnt))
1379 return 1;
1380
1381 /* Wait DMAE PF usage counter to zero */
1382 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1383 dmae_reg_go_c[INIT_DMAE_C(bp)],
1384 "DMAE dommand register timed out",
1385 poll_cnt))
1386 return 1;
1387
1388 return 0;
1389 }
1390
1391 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1392 {
1393 u32 val;
1394
1395 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1396 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1397
1398 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1399 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1400
1401 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1402 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1403
1404 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1405 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1406
1407 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1408 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1409
1410 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1411 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1412
1413 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1414 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1415
1416 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1417 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1418 val);
1419 }
1420
1421 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1422 {
1423 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1424
1425 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1426
1427 /* Re-enable PF target read access */
1428 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1429
1430 /* Poll HW usage counters */
1431 DP(BNX2X_MSG_SP, "Polling usage counters\n");
1432 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1433 return -EBUSY;
1434
1435 /* Zero the igu 'trailing edge' and 'leading edge' */
1436
1437 /* Send the FW cleanup command */
1438 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1439 return -EBUSY;
1440
1441 /* ATC cleanup */
1442
1443 /* Verify TX hw is flushed */
1444 bnx2x_tx_hw_flushed(bp, poll_cnt);
1445
1446 /* Wait 100ms (not adjusted according to platform) */
1447 msleep(100);
1448
1449 /* Verify no pending pci transactions */
1450 if (bnx2x_is_pcie_pending(bp->pdev))
1451 BNX2X_ERR("PCIE Transactions still pending\n");
1452
1453 /* Debug */
1454 bnx2x_hw_enable_status(bp);
1455
1456 /*
1457 * Master enable - Due to WB DMAE writes performed before this
1458 * register is re-initialized as part of the regular function init
1459 */
1460 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1461
1462 return 0;
1463 }
1464
1465 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1466 {
1467 int port = BP_PORT(bp);
1468 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1469 u32 val = REG_RD(bp, addr);
1470 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1471 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1472 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1473
1474 if (msix) {
1475 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1476 HC_CONFIG_0_REG_INT_LINE_EN_0);
1477 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1478 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1479 if (single_msix)
1480 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1481 } else if (msi) {
1482 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1483 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1484 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1485 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1486 } else {
1487 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1488 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1489 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1490 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1491
1492 if (!CHIP_IS_E1(bp)) {
1493 DP(NETIF_MSG_IFUP,
1494 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1495
1496 REG_WR(bp, addr, val);
1497
1498 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1499 }
1500 }
1501
1502 if (CHIP_IS_E1(bp))
1503 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1504
1505 DP(NETIF_MSG_IFUP,
1506 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1507 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1508
1509 REG_WR(bp, addr, val);
1510 /*
1511 * Ensure that HC_CONFIG is written before leading/trailing edge config
1512 */
1513 mmiowb();
1514 barrier();
1515
1516 if (!CHIP_IS_E1(bp)) {
1517 /* init leading/trailing edge */
1518 if (IS_MF(bp)) {
1519 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1520 if (bp->port.pmf)
1521 /* enable nig and gpio3 attention */
1522 val |= 0x1100;
1523 } else
1524 val = 0xffff;
1525
1526 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1527 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1528 }
1529
1530 /* Make sure that interrupts are indeed enabled from here on */
1531 mmiowb();
1532 }
1533
1534 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1535 {
1536 u32 val;
1537 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1538 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1539 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1540
1541 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1542
1543 if (msix) {
1544 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1545 IGU_PF_CONF_SINGLE_ISR_EN);
1546 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1547 IGU_PF_CONF_ATTN_BIT_EN);
1548
1549 if (single_msix)
1550 val |= IGU_PF_CONF_SINGLE_ISR_EN;
1551 } else if (msi) {
1552 val &= ~IGU_PF_CONF_INT_LINE_EN;
1553 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1554 IGU_PF_CONF_ATTN_BIT_EN |
1555 IGU_PF_CONF_SINGLE_ISR_EN);
1556 } else {
1557 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1558 val |= (IGU_PF_CONF_INT_LINE_EN |
1559 IGU_PF_CONF_ATTN_BIT_EN |
1560 IGU_PF_CONF_SINGLE_ISR_EN);
1561 }
1562
1563 /* Clean previous status - need to configure igu prior to ack*/
1564 if ((!msix) || single_msix) {
1565 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1566 bnx2x_ack_int(bp);
1567 }
1568
1569 val |= IGU_PF_CONF_FUNC_EN;
1570
1571 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
1572 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1573
1574 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1575
1576 if (val & IGU_PF_CONF_INT_LINE_EN)
1577 pci_intx(bp->pdev, true);
1578
1579 barrier();
1580
1581 /* init leading/trailing edge */
1582 if (IS_MF(bp)) {
1583 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1584 if (bp->port.pmf)
1585 /* enable nig and gpio3 attention */
1586 val |= 0x1100;
1587 } else
1588 val = 0xffff;
1589
1590 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1591 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1592
1593 /* Make sure that interrupts are indeed enabled from here on */
1594 mmiowb();
1595 }
1596
1597 void bnx2x_int_enable(struct bnx2x *bp)
1598 {
1599 if (bp->common.int_block == INT_BLOCK_HC)
1600 bnx2x_hc_int_enable(bp);
1601 else
1602 bnx2x_igu_int_enable(bp);
1603 }
1604
1605 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1606 {
1607 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1608 int i, offset;
1609
1610 if (disable_hw)
1611 /* prevent the HW from sending interrupts */
1612 bnx2x_int_disable(bp);
1613
1614 /* make sure all ISRs are done */
1615 if (msix) {
1616 synchronize_irq(bp->msix_table[0].vector);
1617 offset = 1;
1618 if (CNIC_SUPPORT(bp))
1619 offset++;
1620 for_each_eth_queue(bp, i)
1621 synchronize_irq(bp->msix_table[offset++].vector);
1622 } else
1623 synchronize_irq(bp->pdev->irq);
1624
1625 /* make sure sp_task is not running */
1626 cancel_delayed_work(&bp->sp_task);
1627 cancel_delayed_work(&bp->period_task);
1628 flush_workqueue(bnx2x_wq);
1629 }
1630
1631 /* fast path */
1632
1633 /*
1634 * General service functions
1635 */
1636
1637 /* Return true if succeeded to acquire the lock */
1638 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1639 {
1640 u32 lock_status;
1641 u32 resource_bit = (1 << resource);
1642 int func = BP_FUNC(bp);
1643 u32 hw_lock_control_reg;
1644
1645 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1646 "Trying to take a lock on resource %d\n", resource);
1647
1648 /* Validating that the resource is within range */
1649 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1650 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1651 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1652 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1653 return false;
1654 }
1655
1656 if (func <= 5)
1657 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1658 else
1659 hw_lock_control_reg =
1660 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1661
1662 /* Try to acquire the lock */
1663 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1664 lock_status = REG_RD(bp, hw_lock_control_reg);
1665 if (lock_status & resource_bit)
1666 return true;
1667
1668 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1669 "Failed to get a lock on resource %d\n", resource);
1670 return false;
1671 }
1672
1673 /**
1674 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1675 *
1676 * @bp: driver handle
1677 *
1678 * Returns the recovery leader resource id according to the engine this function
1679 * belongs to. Currently only only 2 engines is supported.
1680 */
1681 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1682 {
1683 if (BP_PATH(bp))
1684 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1685 else
1686 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1687 }
1688
1689 /**
1690 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1691 *
1692 * @bp: driver handle
1693 *
1694 * Tries to acquire a leader lock for current engine.
1695 */
1696 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1697 {
1698 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1699 }
1700
1701 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1702
1703 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1704 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1705 {
1706 /* Set the interrupt occurred bit for the sp-task to recognize it
1707 * must ack the interrupt and transition according to the IGU
1708 * state machine.
1709 */
1710 atomic_set(&bp->interrupt_occurred, 1);
1711
1712 /* The sp_task must execute only after this bit
1713 * is set, otherwise we will get out of sync and miss all
1714 * further interrupts. Hence, the barrier.
1715 */
1716 smp_wmb();
1717
1718 /* schedule sp_task to workqueue */
1719 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1720 }
1721
1722 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1723 {
1724 struct bnx2x *bp = fp->bp;
1725 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1726 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1727 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1728 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1729
1730 DP(BNX2X_MSG_SP,
1731 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1732 fp->index, cid, command, bp->state,
1733 rr_cqe->ramrod_cqe.ramrod_type);
1734
1735 /* If cid is within VF range, replace the slowpath object with the
1736 * one corresponding to this VF
1737 */
1738 if (cid >= BNX2X_FIRST_VF_CID &&
1739 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1740 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1741
1742 switch (command) {
1743 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1744 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1745 drv_cmd = BNX2X_Q_CMD_UPDATE;
1746 break;
1747
1748 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1749 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1750 drv_cmd = BNX2X_Q_CMD_SETUP;
1751 break;
1752
1753 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1754 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1755 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1756 break;
1757
1758 case (RAMROD_CMD_ID_ETH_HALT):
1759 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1760 drv_cmd = BNX2X_Q_CMD_HALT;
1761 break;
1762
1763 case (RAMROD_CMD_ID_ETH_TERMINATE):
1764 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
1765 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1766 break;
1767
1768 case (RAMROD_CMD_ID_ETH_EMPTY):
1769 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1770 drv_cmd = BNX2X_Q_CMD_EMPTY;
1771 break;
1772
1773 default:
1774 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1775 command, fp->index);
1776 return;
1777 }
1778
1779 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1780 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1781 /* q_obj->complete_cmd() failure means that this was
1782 * an unexpected completion.
1783 *
1784 * In this case we don't want to increase the bp->spq_left
1785 * because apparently we haven't sent this command the first
1786 * place.
1787 */
1788 #ifdef BNX2X_STOP_ON_ERROR
1789 bnx2x_panic();
1790 #else
1791 return;
1792 #endif
1793 /* SRIOV: reschedule any 'in_progress' operations */
1794 bnx2x_iov_sp_event(bp, cid, true);
1795
1796 smp_mb__before_atomic_inc();
1797 atomic_inc(&bp->cq_spq_left);
1798 /* push the change in bp->spq_left and towards the memory */
1799 smp_mb__after_atomic_inc();
1800
1801 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1802
1803 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1804 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1805 /* if Q update ramrod is completed for last Q in AFEX vif set
1806 * flow, then ACK MCP at the end
1807 *
1808 * mark pending ACK to MCP bit.
1809 * prevent case that both bits are cleared.
1810 * At the end of load/unload driver checks that
1811 * sp_state is cleared, and this order prevents
1812 * races
1813 */
1814 smp_mb__before_clear_bit();
1815 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1816 wmb();
1817 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1818 smp_mb__after_clear_bit();
1819
1820 /* schedule the sp task as mcp ack is required */
1821 bnx2x_schedule_sp_task(bp);
1822 }
1823
1824 return;
1825 }
1826
1827 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1828 {
1829 struct bnx2x *bp = netdev_priv(dev_instance);
1830 u16 status = bnx2x_ack_int(bp);
1831 u16 mask;
1832 int i;
1833 u8 cos;
1834
1835 /* Return here if interrupt is shared and it's not for us */
1836 if (unlikely(status == 0)) {
1837 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1838 return IRQ_NONE;
1839 }
1840 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1841
1842 #ifdef BNX2X_STOP_ON_ERROR
1843 if (unlikely(bp->panic))
1844 return IRQ_HANDLED;
1845 #endif
1846
1847 for_each_eth_queue(bp, i) {
1848 struct bnx2x_fastpath *fp = &bp->fp[i];
1849
1850 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1851 if (status & mask) {
1852 /* Handle Rx or Tx according to SB id */
1853 prefetch(fp->rx_cons_sb);
1854 for_each_cos_in_tx_queue(fp, cos)
1855 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1856 prefetch(&fp->sb_running_index[SM_RX_ID]);
1857 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1858 status &= ~mask;
1859 }
1860 }
1861
1862 if (CNIC_SUPPORT(bp)) {
1863 mask = 0x2;
1864 if (status & (mask | 0x1)) {
1865 struct cnic_ops *c_ops = NULL;
1866
1867 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1868 rcu_read_lock();
1869 c_ops = rcu_dereference(bp->cnic_ops);
1870 if (c_ops)
1871 c_ops->cnic_handler(bp->cnic_data,
1872 NULL);
1873 rcu_read_unlock();
1874 }
1875
1876 status &= ~mask;
1877 }
1878 }
1879
1880 if (unlikely(status & 0x1)) {
1881
1882 /* schedule sp task to perform default status block work, ack
1883 * attentions and enable interrupts.
1884 */
1885 bnx2x_schedule_sp_task(bp);
1886
1887 status &= ~0x1;
1888 if (!status)
1889 return IRQ_HANDLED;
1890 }
1891
1892 if (unlikely(status))
1893 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1894 status);
1895
1896 return IRQ_HANDLED;
1897 }
1898
1899 /* Link */
1900
1901 /*
1902 * General service functions
1903 */
1904
1905 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1906 {
1907 u32 lock_status;
1908 u32 resource_bit = (1 << resource);
1909 int func = BP_FUNC(bp);
1910 u32 hw_lock_control_reg;
1911 int cnt;
1912
1913 /* Validating that the resource is within range */
1914 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1915 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1916 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1917 return -EINVAL;
1918 }
1919
1920 if (func <= 5) {
1921 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1922 } else {
1923 hw_lock_control_reg =
1924 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1925 }
1926
1927 /* Validating that the resource is not already taken */
1928 lock_status = REG_RD(bp, hw_lock_control_reg);
1929 if (lock_status & resource_bit) {
1930 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
1931 lock_status, resource_bit);
1932 return -EEXIST;
1933 }
1934
1935 /* Try for 5 second every 5ms */
1936 for (cnt = 0; cnt < 1000; cnt++) {
1937 /* Try to acquire the lock */
1938 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1939 lock_status = REG_RD(bp, hw_lock_control_reg);
1940 if (lock_status & resource_bit)
1941 return 0;
1942
1943 msleep(5);
1944 }
1945 BNX2X_ERR("Timeout\n");
1946 return -EAGAIN;
1947 }
1948
1949 int bnx2x_release_leader_lock(struct bnx2x *bp)
1950 {
1951 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1952 }
1953
1954 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1955 {
1956 u32 lock_status;
1957 u32 resource_bit = (1 << resource);
1958 int func = BP_FUNC(bp);
1959 u32 hw_lock_control_reg;
1960
1961 /* Validating that the resource is within range */
1962 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1963 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1964 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1965 return -EINVAL;
1966 }
1967
1968 if (func <= 5) {
1969 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1970 } else {
1971 hw_lock_control_reg =
1972 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1973 }
1974
1975 /* Validating that the resource is currently taken */
1976 lock_status = REG_RD(bp, hw_lock_control_reg);
1977 if (!(lock_status & resource_bit)) {
1978 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n",
1979 lock_status, resource_bit);
1980 return -EFAULT;
1981 }
1982
1983 REG_WR(bp, hw_lock_control_reg, resource_bit);
1984 return 0;
1985 }
1986
1987
1988 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1989 {
1990 /* The GPIO should be swapped if swap register is set and active */
1991 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1992 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1993 int gpio_shift = gpio_num +
1994 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1995 u32 gpio_mask = (1 << gpio_shift);
1996 u32 gpio_reg;
1997 int value;
1998
1999 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2000 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2001 return -EINVAL;
2002 }
2003
2004 /* read GPIO value */
2005 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2006
2007 /* get the requested pin value */
2008 if ((gpio_reg & gpio_mask) == gpio_mask)
2009 value = 1;
2010 else
2011 value = 0;
2012
2013 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
2014
2015 return value;
2016 }
2017
2018 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2019 {
2020 /* The GPIO should be swapped if swap register is set and active */
2021 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2022 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2023 int gpio_shift = gpio_num +
2024 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2025 u32 gpio_mask = (1 << gpio_shift);
2026 u32 gpio_reg;
2027
2028 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2029 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2030 return -EINVAL;
2031 }
2032
2033 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2034 /* read GPIO and mask except the float bits */
2035 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2036
2037 switch (mode) {
2038 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2039 DP(NETIF_MSG_LINK,
2040 "Set GPIO %d (shift %d) -> output low\n",
2041 gpio_num, gpio_shift);
2042 /* clear FLOAT and set CLR */
2043 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2044 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2045 break;
2046
2047 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2048 DP(NETIF_MSG_LINK,
2049 "Set GPIO %d (shift %d) -> output high\n",
2050 gpio_num, gpio_shift);
2051 /* clear FLOAT and set SET */
2052 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2053 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2054 break;
2055
2056 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2057 DP(NETIF_MSG_LINK,
2058 "Set GPIO %d (shift %d) -> input\n",
2059 gpio_num, gpio_shift);
2060 /* set FLOAT */
2061 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2062 break;
2063
2064 default:
2065 break;
2066 }
2067
2068 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2069 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2070
2071 return 0;
2072 }
2073
2074 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2075 {
2076 u32 gpio_reg = 0;
2077 int rc = 0;
2078
2079 /* Any port swapping should be handled by caller. */
2080
2081 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2082 /* read GPIO and mask except the float bits */
2083 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2084 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2085 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2086 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2087
2088 switch (mode) {
2089 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2090 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2091 /* set CLR */
2092 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2093 break;
2094
2095 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2096 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2097 /* set SET */
2098 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2099 break;
2100
2101 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2102 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2103 /* set FLOAT */
2104 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2105 break;
2106
2107 default:
2108 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2109 rc = -EINVAL;
2110 break;
2111 }
2112
2113 if (rc == 0)
2114 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2115
2116 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2117
2118 return rc;
2119 }
2120
2121 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2122 {
2123 /* The GPIO should be swapped if swap register is set and active */
2124 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2125 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2126 int gpio_shift = gpio_num +
2127 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2128 u32 gpio_mask = (1 << gpio_shift);
2129 u32 gpio_reg;
2130
2131 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2132 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2133 return -EINVAL;
2134 }
2135
2136 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2137 /* read GPIO int */
2138 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2139
2140 switch (mode) {
2141 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2142 DP(NETIF_MSG_LINK,
2143 "Clear GPIO INT %d (shift %d) -> output low\n",
2144 gpio_num, gpio_shift);
2145 /* clear SET and set CLR */
2146 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2147 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2148 break;
2149
2150 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2151 DP(NETIF_MSG_LINK,
2152 "Set GPIO INT %d (shift %d) -> output high\n",
2153 gpio_num, gpio_shift);
2154 /* clear CLR and set SET */
2155 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2156 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2157 break;
2158
2159 default:
2160 break;
2161 }
2162
2163 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2164 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2165
2166 return 0;
2167 }
2168
2169 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2170 {
2171 u32 spio_reg;
2172
2173 /* Only 2 SPIOs are configurable */
2174 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2175 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2176 return -EINVAL;
2177 }
2178
2179 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2180 /* read SPIO and mask except the float bits */
2181 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2182
2183 switch (mode) {
2184 case MISC_SPIO_OUTPUT_LOW:
2185 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2186 /* clear FLOAT and set CLR */
2187 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2188 spio_reg |= (spio << MISC_SPIO_CLR_POS);
2189 break;
2190
2191 case MISC_SPIO_OUTPUT_HIGH:
2192 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2193 /* clear FLOAT and set SET */
2194 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2195 spio_reg |= (spio << MISC_SPIO_SET_POS);
2196 break;
2197
2198 case MISC_SPIO_INPUT_HI_Z:
2199 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2200 /* set FLOAT */
2201 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2202 break;
2203
2204 default:
2205 break;
2206 }
2207
2208 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2209 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2210
2211 return 0;
2212 }
2213
2214 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2215 {
2216 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2217 switch (bp->link_vars.ieee_fc &
2218 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2219 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2220 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2221 ADVERTISED_Pause);
2222 break;
2223
2224 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2225 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2226 ADVERTISED_Pause);
2227 break;
2228
2229 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2230 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2231 break;
2232
2233 default:
2234 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2235 ADVERTISED_Pause);
2236 break;
2237 }
2238 }
2239
2240 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2241 {
2242 /* Initialize link parameters structure variables
2243 * It is recommended to turn off RX FC for jumbo frames
2244 * for better performance
2245 */
2246 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2247 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2248 else
2249 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2250 }
2251
2252 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2253 {
2254 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2255 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2256
2257 if (!BP_NOMCP(bp)) {
2258 bnx2x_set_requested_fc(bp);
2259 bnx2x_acquire_phy_lock(bp);
2260
2261 if (load_mode == LOAD_DIAG) {
2262 struct link_params *lp = &bp->link_params;
2263 lp->loopback_mode = LOOPBACK_XGXS;
2264 /* do PHY loopback at 10G speed, if possible */
2265 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2266 if (lp->speed_cap_mask[cfx_idx] &
2267 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2268 lp->req_line_speed[cfx_idx] =
2269 SPEED_10000;
2270 else
2271 lp->req_line_speed[cfx_idx] =
2272 SPEED_1000;
2273 }
2274 }
2275
2276 if (load_mode == LOAD_LOOPBACK_EXT) {
2277 struct link_params *lp = &bp->link_params;
2278 lp->loopback_mode = LOOPBACK_EXT;
2279 }
2280
2281 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2282
2283 bnx2x_release_phy_lock(bp);
2284
2285 bnx2x_calc_fc_adv(bp);
2286
2287 if (bp->link_vars.link_up) {
2288 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2289 bnx2x_link_report(bp);
2290 }
2291 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2292 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2293 return rc;
2294 }
2295 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2296 return -EINVAL;
2297 }
2298
2299 void bnx2x_link_set(struct bnx2x *bp)
2300 {
2301 if (!BP_NOMCP(bp)) {
2302 bnx2x_acquire_phy_lock(bp);
2303 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2304 bnx2x_release_phy_lock(bp);
2305
2306 bnx2x_calc_fc_adv(bp);
2307 } else
2308 BNX2X_ERR("Bootcode is missing - can not set link\n");
2309 }
2310
2311 static void bnx2x__link_reset(struct bnx2x *bp)
2312 {
2313 if (!BP_NOMCP(bp)) {
2314 bnx2x_acquire_phy_lock(bp);
2315 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2316 bnx2x_release_phy_lock(bp);
2317 } else
2318 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2319 }
2320
2321 void bnx2x_force_link_reset(struct bnx2x *bp)
2322 {
2323 bnx2x_acquire_phy_lock(bp);
2324 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2325 bnx2x_release_phy_lock(bp);
2326 }
2327
2328 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2329 {
2330 u8 rc = 0;
2331
2332 if (!BP_NOMCP(bp)) {
2333 bnx2x_acquire_phy_lock(bp);
2334 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2335 is_serdes);
2336 bnx2x_release_phy_lock(bp);
2337 } else
2338 BNX2X_ERR("Bootcode is missing - can not test link\n");
2339
2340 return rc;
2341 }
2342
2343
2344 /* Calculates the sum of vn_min_rates.
2345 It's needed for further normalizing of the min_rates.
2346 Returns:
2347 sum of vn_min_rates.
2348 or
2349 0 - if all the min_rates are 0.
2350 In the later case fainess algorithm should be deactivated.
2351 If not all min_rates are zero then those that are zeroes will be set to 1.
2352 */
2353 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2354 struct cmng_init_input *input)
2355 {
2356 int all_zero = 1;
2357 int vn;
2358
2359 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2360 u32 vn_cfg = bp->mf_config[vn];
2361 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2362 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2363
2364 /* Skip hidden vns */
2365 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2366 vn_min_rate = 0;
2367 /* If min rate is zero - set it to 1 */
2368 else if (!vn_min_rate)
2369 vn_min_rate = DEF_MIN_RATE;
2370 else
2371 all_zero = 0;
2372
2373 input->vnic_min_rate[vn] = vn_min_rate;
2374 }
2375
2376 /* if ETS or all min rates are zeros - disable fairness */
2377 if (BNX2X_IS_ETS_ENABLED(bp)) {
2378 input->flags.cmng_enables &=
2379 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2380 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2381 } else if (all_zero) {
2382 input->flags.cmng_enables &=
2383 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2384 DP(NETIF_MSG_IFUP,
2385 "All MIN values are zeroes fairness will be disabled\n");
2386 } else
2387 input->flags.cmng_enables |=
2388 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2389 }
2390
2391 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2392 struct cmng_init_input *input)
2393 {
2394 u16 vn_max_rate;
2395 u32 vn_cfg = bp->mf_config[vn];
2396
2397 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2398 vn_max_rate = 0;
2399 else {
2400 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2401
2402 if (IS_MF_SI(bp)) {
2403 /* maxCfg in percents of linkspeed */
2404 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2405 } else /* SD modes */
2406 /* maxCfg is absolute in 100Mb units */
2407 vn_max_rate = maxCfg * 100;
2408 }
2409
2410 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2411
2412 input->vnic_max_rate[vn] = vn_max_rate;
2413 }
2414
2415
2416 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2417 {
2418 if (CHIP_REV_IS_SLOW(bp))
2419 return CMNG_FNS_NONE;
2420 if (IS_MF(bp))
2421 return CMNG_FNS_MINMAX;
2422
2423 return CMNG_FNS_NONE;
2424 }
2425
2426 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2427 {
2428 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2429
2430 if (BP_NOMCP(bp))
2431 return; /* what should be the default bvalue in this case */
2432
2433 /* For 2 port configuration the absolute function number formula
2434 * is:
2435 * abs_func = 2 * vn + BP_PORT + BP_PATH
2436 *
2437 * and there are 4 functions per port
2438 *
2439 * For 4 port configuration it is
2440 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2441 *
2442 * and there are 2 functions per port
2443 */
2444 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2445 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2446
2447 if (func >= E1H_FUNC_MAX)
2448 break;
2449
2450 bp->mf_config[vn] =
2451 MF_CFG_RD(bp, func_mf_config[func].config);
2452 }
2453 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2454 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2455 bp->flags |= MF_FUNC_DIS;
2456 } else {
2457 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2458 bp->flags &= ~MF_FUNC_DIS;
2459 }
2460 }
2461
2462 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2463 {
2464 struct cmng_init_input input;
2465 memset(&input, 0, sizeof(struct cmng_init_input));
2466
2467 input.port_rate = bp->link_vars.line_speed;
2468
2469 if (cmng_type == CMNG_FNS_MINMAX) {
2470 int vn;
2471
2472 /* read mf conf from shmem */
2473 if (read_cfg)
2474 bnx2x_read_mf_cfg(bp);
2475
2476 /* vn_weight_sum and enable fairness if not 0 */
2477 bnx2x_calc_vn_min(bp, &input);
2478
2479 /* calculate and set min-max rate for each vn */
2480 if (bp->port.pmf)
2481 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2482 bnx2x_calc_vn_max(bp, vn, &input);
2483
2484 /* always enable rate shaping and fairness */
2485 input.flags.cmng_enables |=
2486 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2487
2488 bnx2x_init_cmng(&input, &bp->cmng);
2489 return;
2490 }
2491
2492 /* rate shaping and fairness are disabled */
2493 DP(NETIF_MSG_IFUP,
2494 "rate shaping and fairness are disabled\n");
2495 }
2496
2497 static void storm_memset_cmng(struct bnx2x *bp,
2498 struct cmng_init *cmng,
2499 u8 port)
2500 {
2501 int vn;
2502 size_t size = sizeof(struct cmng_struct_per_port);
2503
2504 u32 addr = BAR_XSTRORM_INTMEM +
2505 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2506
2507 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2508
2509 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2510 int func = func_by_vn(bp, vn);
2511
2512 addr = BAR_XSTRORM_INTMEM +
2513 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2514 size = sizeof(struct rate_shaping_vars_per_vn);
2515 __storm_memset_struct(bp, addr, size,
2516 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2517
2518 addr = BAR_XSTRORM_INTMEM +
2519 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2520 size = sizeof(struct fairness_vars_per_vn);
2521 __storm_memset_struct(bp, addr, size,
2522 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2523 }
2524 }
2525
2526 /* This function is called upon link interrupt */
2527 static void bnx2x_link_attn(struct bnx2x *bp)
2528 {
2529 /* Make sure that we are synced with the current statistics */
2530 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2531
2532 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2533
2534 if (bp->link_vars.link_up) {
2535
2536 /* dropless flow control */
2537 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2538 int port = BP_PORT(bp);
2539 u32 pause_enabled = 0;
2540
2541 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2542 pause_enabled = 1;
2543
2544 REG_WR(bp, BAR_USTRORM_INTMEM +
2545 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2546 pause_enabled);
2547 }
2548
2549 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2550 struct host_port_stats *pstats;
2551
2552 pstats = bnx2x_sp(bp, port_stats);
2553 /* reset old mac stats */
2554 memset(&(pstats->mac_stx[0]), 0,
2555 sizeof(struct mac_stx));
2556 }
2557 if (bp->state == BNX2X_STATE_OPEN)
2558 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2559 }
2560
2561 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2562 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2563
2564 if (cmng_fns != CMNG_FNS_NONE) {
2565 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2566 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2567 } else
2568 /* rate shaping and fairness are disabled */
2569 DP(NETIF_MSG_IFUP,
2570 "single function mode without fairness\n");
2571 }
2572
2573 __bnx2x_link_report(bp);
2574
2575 if (IS_MF(bp))
2576 bnx2x_link_sync_notify(bp);
2577 }
2578
2579 void bnx2x__link_status_update(struct bnx2x *bp)
2580 {
2581 if (bp->state != BNX2X_STATE_OPEN)
2582 return;
2583
2584 /* read updated dcb configuration */
2585 if (IS_PF(bp)) {
2586 bnx2x_dcbx_pmf_update(bp);
2587 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2588 if (bp->link_vars.link_up)
2589 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2590 else
2591 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2592 /* indicate link status */
2593 bnx2x_link_report(bp);
2594
2595 } else { /* VF */
2596 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2597 SUPPORTED_10baseT_Full |
2598 SUPPORTED_100baseT_Half |
2599 SUPPORTED_100baseT_Full |
2600 SUPPORTED_1000baseT_Full |
2601 SUPPORTED_2500baseX_Full |
2602 SUPPORTED_10000baseT_Full |
2603 SUPPORTED_TP |
2604 SUPPORTED_FIBRE |
2605 SUPPORTED_Autoneg |
2606 SUPPORTED_Pause |
2607 SUPPORTED_Asym_Pause);
2608 bp->port.advertising[0] = bp->port.supported[0];
2609
2610 bp->link_params.bp = bp;
2611 bp->link_params.port = BP_PORT(bp);
2612 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2613 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2614 bp->link_params.req_line_speed[0] = SPEED_10000;
2615 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2616 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2617 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2618 bp->link_vars.line_speed = SPEED_10000;
2619 bp->link_vars.link_status =
2620 (LINK_STATUS_LINK_UP |
2621 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2622 bp->link_vars.link_up = 1;
2623 bp->link_vars.duplex = DUPLEX_FULL;
2624 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2625 __bnx2x_link_report(bp);
2626 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2627 }
2628 }
2629
2630 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2631 u16 vlan_val, u8 allowed_prio)
2632 {
2633 struct bnx2x_func_state_params func_params = {0};
2634 struct bnx2x_func_afex_update_params *f_update_params =
2635 &func_params.params.afex_update;
2636
2637 func_params.f_obj = &bp->func_obj;
2638 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2639
2640 /* no need to wait for RAMROD completion, so don't
2641 * set RAMROD_COMP_WAIT flag
2642 */
2643
2644 f_update_params->vif_id = vifid;
2645 f_update_params->afex_default_vlan = vlan_val;
2646 f_update_params->allowed_priorities = allowed_prio;
2647
2648 /* if ramrod can not be sent, response to MCP immediately */
2649 if (bnx2x_func_state_change(bp, &func_params) < 0)
2650 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2651
2652 return 0;
2653 }
2654
2655 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2656 u16 vif_index, u8 func_bit_map)
2657 {
2658 struct bnx2x_func_state_params func_params = {0};
2659 struct bnx2x_func_afex_viflists_params *update_params =
2660 &func_params.params.afex_viflists;
2661 int rc;
2662 u32 drv_msg_code;
2663
2664 /* validate only LIST_SET and LIST_GET are received from switch */
2665 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2666 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2667 cmd_type);
2668
2669 func_params.f_obj = &bp->func_obj;
2670 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2671
2672 /* set parameters according to cmd_type */
2673 update_params->afex_vif_list_command = cmd_type;
2674 update_params->vif_list_index = cpu_to_le16(vif_index);
2675 update_params->func_bit_map =
2676 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2677 update_params->func_to_clear = 0;
2678 drv_msg_code =
2679 (cmd_type == VIF_LIST_RULE_GET) ?
2680 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2681 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2682
2683 /* if ramrod can not be sent, respond to MCP immediately for
2684 * SET and GET requests (other are not triggered from MCP)
2685 */
2686 rc = bnx2x_func_state_change(bp, &func_params);
2687 if (rc < 0)
2688 bnx2x_fw_command(bp, drv_msg_code, 0);
2689
2690 return 0;
2691 }
2692
2693 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2694 {
2695 struct afex_stats afex_stats;
2696 u32 func = BP_ABS_FUNC(bp);
2697 u32 mf_config;
2698 u16 vlan_val;
2699 u32 vlan_prio;
2700 u16 vif_id;
2701 u8 allowed_prio;
2702 u8 vlan_mode;
2703 u32 addr_to_write, vifid, addrs, stats_type, i;
2704
2705 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2706 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2707 DP(BNX2X_MSG_MCP,
2708 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2709 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2710 }
2711
2712 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2713 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2714 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2715 DP(BNX2X_MSG_MCP,
2716 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2717 vifid, addrs);
2718 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2719 addrs);
2720 }
2721
2722 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2723 addr_to_write = SHMEM2_RD(bp,
2724 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2725 stats_type = SHMEM2_RD(bp,
2726 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2727
2728 DP(BNX2X_MSG_MCP,
2729 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2730 addr_to_write);
2731
2732 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2733
2734 /* write response to scratchpad, for MCP */
2735 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2736 REG_WR(bp, addr_to_write + i*sizeof(u32),
2737 *(((u32 *)(&afex_stats))+i));
2738
2739 /* send ack message to MCP */
2740 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2741 }
2742
2743 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2744 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2745 bp->mf_config[BP_VN(bp)] = mf_config;
2746 DP(BNX2X_MSG_MCP,
2747 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2748 mf_config);
2749
2750 /* if VIF_SET is "enabled" */
2751 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2752 /* set rate limit directly to internal RAM */
2753 struct cmng_init_input cmng_input;
2754 struct rate_shaping_vars_per_vn m_rs_vn;
2755 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2756 u32 addr = BAR_XSTRORM_INTMEM +
2757 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2758
2759 bp->mf_config[BP_VN(bp)] = mf_config;
2760
2761 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2762 m_rs_vn.vn_counter.rate =
2763 cmng_input.vnic_max_rate[BP_VN(bp)];
2764 m_rs_vn.vn_counter.quota =
2765 (m_rs_vn.vn_counter.rate *
2766 RS_PERIODIC_TIMEOUT_USEC) / 8;
2767
2768 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2769
2770 /* read relevant values from mf_cfg struct in shmem */
2771 vif_id =
2772 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2773 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2774 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2775 vlan_val =
2776 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2777 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2778 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2779 vlan_prio = (mf_config &
2780 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2781 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2782 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2783 vlan_mode =
2784 (MF_CFG_RD(bp,
2785 func_mf_config[func].afex_config) &
2786 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2787 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2788 allowed_prio =
2789 (MF_CFG_RD(bp,
2790 func_mf_config[func].afex_config) &
2791 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2792 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2793
2794 /* send ramrod to FW, return in case of failure */
2795 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2796 allowed_prio))
2797 return;
2798
2799 bp->afex_def_vlan_tag = vlan_val;
2800 bp->afex_vlan_mode = vlan_mode;
2801 } else {
2802 /* notify link down because BP->flags is disabled */
2803 bnx2x_link_report(bp);
2804
2805 /* send INVALID VIF ramrod to FW */
2806 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2807
2808 /* Reset the default afex VLAN */
2809 bp->afex_def_vlan_tag = -1;
2810 }
2811 }
2812 }
2813
2814 static void bnx2x_pmf_update(struct bnx2x *bp)
2815 {
2816 int port = BP_PORT(bp);
2817 u32 val;
2818
2819 bp->port.pmf = 1;
2820 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2821
2822 /*
2823 * We need the mb() to ensure the ordering between the writing to
2824 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2825 */
2826 smp_mb();
2827
2828 /* queue a periodic task */
2829 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2830
2831 bnx2x_dcbx_pmf_update(bp);
2832
2833 /* enable nig attention */
2834 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2835 if (bp->common.int_block == INT_BLOCK_HC) {
2836 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2837 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2838 } else if (!CHIP_IS_E1x(bp)) {
2839 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2840 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2841 }
2842
2843 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2844 }
2845
2846 /* end of Link */
2847
2848 /* slow path */
2849
2850 /*
2851 * General service functions
2852 */
2853
2854 /* send the MCP a request, block until there is a reply */
2855 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2856 {
2857 int mb_idx = BP_FW_MB_IDX(bp);
2858 u32 seq;
2859 u32 rc = 0;
2860 u32 cnt = 1;
2861 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2862
2863 mutex_lock(&bp->fw_mb_mutex);
2864 seq = ++bp->fw_seq;
2865 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2866 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2867
2868 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2869 (command | seq), param);
2870
2871 do {
2872 /* let the FW do it's magic ... */
2873 msleep(delay);
2874
2875 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2876
2877 /* Give the FW up to 5 second (500*10ms) */
2878 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2879
2880 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2881 cnt*delay, rc, seq);
2882
2883 /* is this a reply to our command? */
2884 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2885 rc &= FW_MSG_CODE_MASK;
2886 else {
2887 /* FW BUG! */
2888 BNX2X_ERR("FW failed to respond!\n");
2889 bnx2x_fw_dump(bp);
2890 rc = 0;
2891 }
2892 mutex_unlock(&bp->fw_mb_mutex);
2893
2894 return rc;
2895 }
2896
2897
2898 static void storm_memset_func_cfg(struct bnx2x *bp,
2899 struct tstorm_eth_function_common_config *tcfg,
2900 u16 abs_fid)
2901 {
2902 size_t size = sizeof(struct tstorm_eth_function_common_config);
2903
2904 u32 addr = BAR_TSTRORM_INTMEM +
2905 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2906
2907 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2908 }
2909
2910 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2911 {
2912 if (CHIP_IS_E1x(bp)) {
2913 struct tstorm_eth_function_common_config tcfg = {0};
2914
2915 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2916 }
2917
2918 /* Enable the function in the FW */
2919 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2920 storm_memset_func_en(bp, p->func_id, 1);
2921
2922 /* spq */
2923 if (p->func_flgs & FUNC_FLG_SPQ) {
2924 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2925 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2926 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2927 }
2928 }
2929
2930 /**
2931 * bnx2x_get_tx_only_flags - Return common flags
2932 *
2933 * @bp device handle
2934 * @fp queue handle
2935 * @zero_stats TRUE if statistics zeroing is needed
2936 *
2937 * Return the flags that are common for the Tx-only and not normal connections.
2938 */
2939 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2940 struct bnx2x_fastpath *fp,
2941 bool zero_stats)
2942 {
2943 unsigned long flags = 0;
2944
2945 /* PF driver will always initialize the Queue to an ACTIVE state */
2946 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2947
2948 /* tx only connections collect statistics (on the same index as the
2949 * parent connection). The statistics are zeroed when the parent
2950 * connection is initialized.
2951 */
2952
2953 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2954 if (zero_stats)
2955 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2956
2957
2958 #ifdef BNX2X_STOP_ON_ERROR
2959 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
2960 #endif
2961
2962 return flags;
2963 }
2964
2965 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2966 struct bnx2x_fastpath *fp,
2967 bool leading)
2968 {
2969 unsigned long flags = 0;
2970
2971 /* calculate other queue flags */
2972 if (IS_MF_SD(bp))
2973 __set_bit(BNX2X_Q_FLG_OV, &flags);
2974
2975 if (IS_FCOE_FP(fp)) {
2976 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2977 /* For FCoE - force usage of default priority (for afex) */
2978 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
2979 }
2980
2981 if (!fp->disable_tpa) {
2982 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2983 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2984 if (fp->mode == TPA_MODE_GRO)
2985 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
2986 }
2987
2988 if (leading) {
2989 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2990 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2991 }
2992
2993 /* Always set HW VLAN stripping */
2994 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
2995
2996 /* configure silent vlan removal */
2997 if (IS_MF_AFEX(bp))
2998 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
2999
3000
3001 return flags | bnx2x_get_common_flags(bp, fp, true);
3002 }
3003
3004 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3005 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3006 u8 cos)
3007 {
3008 gen_init->stat_id = bnx2x_stats_id(fp);
3009 gen_init->spcl_id = fp->cl_id;
3010
3011 /* Always use mini-jumbo MTU for FCoE L2 ring */
3012 if (IS_FCOE_FP(fp))
3013 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3014 else
3015 gen_init->mtu = bp->dev->mtu;
3016
3017 gen_init->cos = cos;
3018 }
3019
3020 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3021 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3022 struct bnx2x_rxq_setup_params *rxq_init)
3023 {
3024 u8 max_sge = 0;
3025 u16 sge_sz = 0;
3026 u16 tpa_agg_size = 0;
3027
3028 if (!fp->disable_tpa) {
3029 pause->sge_th_lo = SGE_TH_LO(bp);
3030 pause->sge_th_hi = SGE_TH_HI(bp);
3031
3032 /* validate SGE ring has enough to cross high threshold */
3033 WARN_ON(bp->dropless_fc &&
3034 pause->sge_th_hi + FW_PREFETCH_CNT >
3035 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3036
3037 tpa_agg_size = min_t(u32,
3038 (min_t(u32, 8, MAX_SKB_FRAGS) *
3039 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
3040 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3041 SGE_PAGE_SHIFT;
3042 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3043 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3044 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
3045 0xffff);
3046 }
3047
3048 /* pause - not for e1 */
3049 if (!CHIP_IS_E1(bp)) {
3050 pause->bd_th_lo = BD_TH_LO(bp);
3051 pause->bd_th_hi = BD_TH_HI(bp);
3052
3053 pause->rcq_th_lo = RCQ_TH_LO(bp);
3054 pause->rcq_th_hi = RCQ_TH_HI(bp);
3055 /*
3056 * validate that rings have enough entries to cross
3057 * high thresholds
3058 */
3059 WARN_ON(bp->dropless_fc &&
3060 pause->bd_th_hi + FW_PREFETCH_CNT >
3061 bp->rx_ring_size);
3062 WARN_ON(bp->dropless_fc &&
3063 pause->rcq_th_hi + FW_PREFETCH_CNT >
3064 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3065
3066 pause->pri_map = 1;
3067 }
3068
3069 /* rxq setup */
3070 rxq_init->dscr_map = fp->rx_desc_mapping;
3071 rxq_init->sge_map = fp->rx_sge_mapping;
3072 rxq_init->rcq_map = fp->rx_comp_mapping;
3073 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3074
3075 /* This should be a maximum number of data bytes that may be
3076 * placed on the BD (not including paddings).
3077 */
3078 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3079 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3080
3081 rxq_init->cl_qzone_id = fp->cl_qzone_id;
3082 rxq_init->tpa_agg_sz = tpa_agg_size;
3083 rxq_init->sge_buf_sz = sge_sz;
3084 rxq_init->max_sges_pkt = max_sge;
3085 rxq_init->rss_engine_id = BP_FUNC(bp);
3086 rxq_init->mcast_engine_id = BP_FUNC(bp);
3087
3088 /* Maximum number or simultaneous TPA aggregation for this Queue.
3089 *
3090 * For PF Clients it should be the maximum available number.
3091 * VF driver(s) may want to define it to a smaller value.
3092 */
3093 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3094
3095 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3096 rxq_init->fw_sb_id = fp->fw_sb_id;
3097
3098 if (IS_FCOE_FP(fp))
3099 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3100 else
3101 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3102 /* configure silent vlan removal
3103 * if multi function mode is afex, then mask default vlan
3104 */
3105 if (IS_MF_AFEX(bp)) {
3106 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3107 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3108 }
3109 }
3110
3111 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3112 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3113 u8 cos)
3114 {
3115 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3116 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3117 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3118 txq_init->fw_sb_id = fp->fw_sb_id;
3119
3120 /*
3121 * set the tss leading client id for TX classfication ==
3122 * leading RSS client id
3123 */
3124 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3125
3126 if (IS_FCOE_FP(fp)) {
3127 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3128 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3129 }
3130 }
3131
3132 static void bnx2x_pf_init(struct bnx2x *bp)
3133 {
3134 struct bnx2x_func_init_params func_init = {0};
3135 struct event_ring_data eq_data = { {0} };
3136 u16 flags;
3137
3138 if (!CHIP_IS_E1x(bp)) {
3139 /* reset IGU PF statistics: MSIX + ATTN */
3140 /* PF */
3141 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3142 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3143 (CHIP_MODE_IS_4_PORT(bp) ?
3144 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3145 /* ATTN */
3146 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3147 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3148 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3149 (CHIP_MODE_IS_4_PORT(bp) ?
3150 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3151 }
3152
3153 /* function setup flags */
3154 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3155
3156 /* This flag is relevant for E1x only.
3157 * E2 doesn't have a TPA configuration in a function level.
3158 */
3159 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
3160
3161 func_init.func_flgs = flags;
3162 func_init.pf_id = BP_FUNC(bp);
3163 func_init.func_id = BP_FUNC(bp);
3164 func_init.spq_map = bp->spq_mapping;
3165 func_init.spq_prod = bp->spq_prod_idx;
3166
3167 bnx2x_func_init(bp, &func_init);
3168
3169 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3170
3171 /*
3172 * Congestion management values depend on the link rate
3173 * There is no active link so initial link rate is set to 10 Gbps.
3174 * When the link comes up The congestion management values are
3175 * re-calculated according to the actual link rate.
3176 */
3177 bp->link_vars.line_speed = SPEED_10000;
3178 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3179
3180 /* Only the PMF sets the HW */
3181 if (bp->port.pmf)
3182 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3183
3184 /* init Event Queue */
3185 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3186 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3187 eq_data.producer = bp->eq_prod;
3188 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3189 eq_data.sb_id = DEF_SB_ID;
3190 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3191 }
3192
3193
3194 static void bnx2x_e1h_disable(struct bnx2x *bp)
3195 {
3196 int port = BP_PORT(bp);
3197
3198 bnx2x_tx_disable(bp);
3199
3200 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3201 }
3202
3203 static void bnx2x_e1h_enable(struct bnx2x *bp)
3204 {
3205 int port = BP_PORT(bp);
3206
3207 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3208
3209 /* Tx queue should be only reenabled */
3210 netif_tx_wake_all_queues(bp->dev);
3211
3212 /*
3213 * Should not call netif_carrier_on since it will be called if the link
3214 * is up when checking for link state
3215 */
3216 }
3217
3218 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3219
3220 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3221 {
3222 struct eth_stats_info *ether_stat =
3223 &bp->slowpath->drv_info_to_mcp.ether_stat;
3224
3225 strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3226 ETH_STAT_INFO_VERSION_LEN);
3227
3228 bp->sp_objs[0].mac_obj.get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3229 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3230 ether_stat->mac_local);
3231
3232 ether_stat->mtu_size = bp->dev->mtu;
3233
3234 if (bp->dev->features & NETIF_F_RXCSUM)
3235 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3236 if (bp->dev->features & NETIF_F_TSO)
3237 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3238 ether_stat->feature_flags |= bp->common.boot_mode;
3239
3240 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3241
3242 ether_stat->txq_size = bp->tx_ring_size;
3243 ether_stat->rxq_size = bp->rx_ring_size;
3244 }
3245
3246 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3247 {
3248 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3249 struct fcoe_stats_info *fcoe_stat =
3250 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3251
3252 if (!CNIC_LOADED(bp))
3253 return;
3254
3255 memcpy(fcoe_stat->mac_local + MAC_LEADING_ZERO_CNT,
3256 bp->fip_mac, ETH_ALEN);
3257
3258 fcoe_stat->qos_priority =
3259 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3260
3261 /* insert FCoE stats from ramrod response */
3262 if (!NO_FCOE(bp)) {
3263 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3264 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3265 tstorm_queue_statistics;
3266
3267 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3268 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3269 xstorm_queue_statistics;
3270
3271 struct fcoe_statistics_params *fw_fcoe_stat =
3272 &bp->fw_stats_data->fcoe;
3273
3274 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo,
3275 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3276
3277 ADD_64(fcoe_stat->rx_bytes_hi,
3278 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3279 fcoe_stat->rx_bytes_lo,
3280 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3281
3282 ADD_64(fcoe_stat->rx_bytes_hi,
3283 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3284 fcoe_stat->rx_bytes_lo,
3285 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3286
3287 ADD_64(fcoe_stat->rx_bytes_hi,
3288 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3289 fcoe_stat->rx_bytes_lo,
3290 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3291
3292 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3293 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3294
3295 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3296 fcoe_q_tstorm_stats->rcv_ucast_pkts);
3297
3298 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3299 fcoe_q_tstorm_stats->rcv_bcast_pkts);
3300
3301 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3302 fcoe_q_tstorm_stats->rcv_mcast_pkts);
3303
3304 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo,
3305 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3306
3307 ADD_64(fcoe_stat->tx_bytes_hi,
3308 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3309 fcoe_stat->tx_bytes_lo,
3310 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3311
3312 ADD_64(fcoe_stat->tx_bytes_hi,
3313 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3314 fcoe_stat->tx_bytes_lo,
3315 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3316
3317 ADD_64(fcoe_stat->tx_bytes_hi,
3318 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3319 fcoe_stat->tx_bytes_lo,
3320 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3321
3322 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3323 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3324
3325 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3326 fcoe_q_xstorm_stats->ucast_pkts_sent);
3327
3328 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3329 fcoe_q_xstorm_stats->bcast_pkts_sent);
3330
3331 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3332 fcoe_q_xstorm_stats->mcast_pkts_sent);
3333 }
3334
3335 /* ask L5 driver to add data to the struct */
3336 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3337 }
3338
3339 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3340 {
3341 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3342 struct iscsi_stats_info *iscsi_stat =
3343 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3344
3345 if (!CNIC_LOADED(bp))
3346 return;
3347
3348 memcpy(iscsi_stat->mac_local + MAC_LEADING_ZERO_CNT,
3349 bp->cnic_eth_dev.iscsi_mac, ETH_ALEN);
3350
3351 iscsi_stat->qos_priority =
3352 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3353
3354 /* ask L5 driver to add data to the struct */
3355 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3356 }
3357
3358 /* called due to MCP event (on pmf):
3359 * reread new bandwidth configuration
3360 * configure FW
3361 * notify others function about the change
3362 */
3363 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3364 {
3365 if (bp->link_vars.link_up) {
3366 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3367 bnx2x_link_sync_notify(bp);
3368 }
3369 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3370 }
3371
3372 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3373 {
3374 bnx2x_config_mf_bw(bp);
3375 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3376 }
3377
3378 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3379 {
3380 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3381 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3382 }
3383
3384 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3385 {
3386 enum drv_info_opcode op_code;
3387 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3388
3389 /* if drv_info version supported by MFW doesn't match - send NACK */
3390 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3391 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3392 return;
3393 }
3394
3395 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3396 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3397
3398 memset(&bp->slowpath->drv_info_to_mcp, 0,
3399 sizeof(union drv_info_to_mcp));
3400
3401 switch (op_code) {
3402 case ETH_STATS_OPCODE:
3403 bnx2x_drv_info_ether_stat(bp);
3404 break;
3405 case FCOE_STATS_OPCODE:
3406 bnx2x_drv_info_fcoe_stat(bp);
3407 break;
3408 case ISCSI_STATS_OPCODE:
3409 bnx2x_drv_info_iscsi_stat(bp);
3410 break;
3411 default:
3412 /* if op code isn't supported - send NACK */
3413 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3414 return;
3415 }
3416
3417 /* if we got drv_info attn from MFW then these fields are defined in
3418 * shmem2 for sure
3419 */
3420 SHMEM2_WR(bp, drv_info_host_addr_lo,
3421 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3422 SHMEM2_WR(bp, drv_info_host_addr_hi,
3423 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3424
3425 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3426 }
3427
3428 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3429 {
3430 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3431
3432 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3433
3434 /*
3435 * This is the only place besides the function initialization
3436 * where the bp->flags can change so it is done without any
3437 * locks
3438 */
3439 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3440 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3441 bp->flags |= MF_FUNC_DIS;
3442
3443 bnx2x_e1h_disable(bp);
3444 } else {
3445 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3446 bp->flags &= ~MF_FUNC_DIS;
3447
3448 bnx2x_e1h_enable(bp);
3449 }
3450 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3451 }
3452 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3453 bnx2x_config_mf_bw(bp);
3454 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3455 }
3456
3457 /* Report results to MCP */
3458 if (dcc_event)
3459 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3460 else
3461 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3462 }
3463
3464 /* must be called under the spq lock */
3465 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3466 {
3467 struct eth_spe *next_spe = bp->spq_prod_bd;
3468
3469 if (bp->spq_prod_bd == bp->spq_last_bd) {
3470 bp->spq_prod_bd = bp->spq;
3471 bp->spq_prod_idx = 0;
3472 DP(BNX2X_MSG_SP, "end of spq\n");
3473 } else {
3474 bp->spq_prod_bd++;
3475 bp->spq_prod_idx++;
3476 }
3477 return next_spe;
3478 }
3479
3480 /* must be called under the spq lock */
3481 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3482 {
3483 int func = BP_FUNC(bp);
3484
3485 /*
3486 * Make sure that BD data is updated before writing the producer:
3487 * BD data is written to the memory, the producer is read from the
3488 * memory, thus we need a full memory barrier to ensure the ordering.
3489 */
3490 mb();
3491
3492 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3493 bp->spq_prod_idx);
3494 mmiowb();
3495 }
3496
3497 /**
3498 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3499 *
3500 * @cmd: command to check
3501 * @cmd_type: command type
3502 */
3503 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3504 {
3505 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3506 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3507 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3508 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3509 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3510 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3511 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3512 return true;
3513 else
3514 return false;
3515
3516 }
3517
3518
3519 /**
3520 * bnx2x_sp_post - place a single command on an SP ring
3521 *
3522 * @bp: driver handle
3523 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3524 * @cid: SW CID the command is related to
3525 * @data_hi: command private data address (high 32 bits)
3526 * @data_lo: command private data address (low 32 bits)
3527 * @cmd_type: command type (e.g. NONE, ETH)
3528 *
3529 * SP data is handled as if it's always an address pair, thus data fields are
3530 * not swapped to little endian in upper functions. Instead this function swaps
3531 * data as if it's two u32 fields.
3532 */
3533 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3534 u32 data_hi, u32 data_lo, int cmd_type)
3535 {
3536 struct eth_spe *spe;
3537 u16 type;
3538 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3539
3540 #ifdef BNX2X_STOP_ON_ERROR
3541 if (unlikely(bp->panic)) {
3542 BNX2X_ERR("Can't post SP when there is panic\n");
3543 return -EIO;
3544 }
3545 #endif
3546
3547 spin_lock_bh(&bp->spq_lock);
3548
3549 if (common) {
3550 if (!atomic_read(&bp->eq_spq_left)) {
3551 BNX2X_ERR("BUG! EQ ring full!\n");
3552 spin_unlock_bh(&bp->spq_lock);
3553 bnx2x_panic();
3554 return -EBUSY;
3555 }
3556 } else if (!atomic_read(&bp->cq_spq_left)) {
3557 BNX2X_ERR("BUG! SPQ ring full!\n");
3558 spin_unlock_bh(&bp->spq_lock);
3559 bnx2x_panic();
3560 return -EBUSY;
3561 }
3562
3563 spe = bnx2x_sp_get_next(bp);
3564
3565 /* CID needs port number to be encoded int it */
3566 spe->hdr.conn_and_cmd_data =
3567 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3568 HW_CID(bp, cid));
3569
3570 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3571
3572 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3573 SPE_HDR_FUNCTION_ID);
3574
3575 spe->hdr.type = cpu_to_le16(type);
3576
3577 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3578 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3579
3580 /*
3581 * It's ok if the actual decrement is issued towards the memory
3582 * somewhere between the spin_lock and spin_unlock. Thus no
3583 * more explict memory barrier is needed.
3584 */
3585 if (common)
3586 atomic_dec(&bp->eq_spq_left);
3587 else
3588 atomic_dec(&bp->cq_spq_left);
3589
3590
3591 DP(BNX2X_MSG_SP,
3592 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3593 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3594 (u32)(U64_LO(bp->spq_mapping) +
3595 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3596 HW_CID(bp, cid), data_hi, data_lo, type,
3597 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3598
3599 bnx2x_sp_prod_update(bp);
3600 spin_unlock_bh(&bp->spq_lock);
3601 return 0;
3602 }
3603
3604 /* acquire split MCP access lock register */
3605 static int bnx2x_acquire_alr(struct bnx2x *bp)
3606 {
3607 u32 j, val;
3608 int rc = 0;
3609
3610 might_sleep();
3611 for (j = 0; j < 1000; j++) {
3612 val = (1UL << 31);
3613 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3614 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3615 if (val & (1L << 31))
3616 break;
3617
3618 msleep(5);
3619 }
3620 if (!(val & (1L << 31))) {
3621 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3622 rc = -EBUSY;
3623 }
3624
3625 return rc;
3626 }
3627
3628 /* release split MCP access lock register */
3629 static void bnx2x_release_alr(struct bnx2x *bp)
3630 {
3631 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3632 }
3633
3634 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3635 #define BNX2X_DEF_SB_IDX 0x0002
3636
3637 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3638 {
3639 struct host_sp_status_block *def_sb = bp->def_status_blk;
3640 u16 rc = 0;
3641
3642 barrier(); /* status block is written to by the chip */
3643 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3644 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3645 rc |= BNX2X_DEF_SB_ATT_IDX;
3646 }
3647
3648 if (bp->def_idx != def_sb->sp_sb.running_index) {
3649 bp->def_idx = def_sb->sp_sb.running_index;
3650 rc |= BNX2X_DEF_SB_IDX;
3651 }
3652
3653 /* Do not reorder: indecies reading should complete before handling */
3654 barrier();
3655 return rc;
3656 }
3657
3658 /*
3659 * slow path service functions
3660 */
3661
3662 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3663 {
3664 int port = BP_PORT(bp);
3665 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3666 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3667 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3668 NIG_REG_MASK_INTERRUPT_PORT0;
3669 u32 aeu_mask;
3670 u32 nig_mask = 0;
3671 u32 reg_addr;
3672
3673 if (bp->attn_state & asserted)
3674 BNX2X_ERR("IGU ERROR\n");
3675
3676 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3677 aeu_mask = REG_RD(bp, aeu_addr);
3678
3679 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3680 aeu_mask, asserted);
3681 aeu_mask &= ~(asserted & 0x3ff);
3682 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3683
3684 REG_WR(bp, aeu_addr, aeu_mask);
3685 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3686
3687 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3688 bp->attn_state |= asserted;
3689 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3690
3691 if (asserted & ATTN_HARD_WIRED_MASK) {
3692 if (asserted & ATTN_NIG_FOR_FUNC) {
3693
3694 bnx2x_acquire_phy_lock(bp);
3695
3696 /* save nig interrupt mask */
3697 nig_mask = REG_RD(bp, nig_int_mask_addr);
3698
3699 /* If nig_mask is not set, no need to call the update
3700 * function.
3701 */
3702 if (nig_mask) {
3703 REG_WR(bp, nig_int_mask_addr, 0);
3704
3705 bnx2x_link_attn(bp);
3706 }
3707
3708 /* handle unicore attn? */
3709 }
3710 if (asserted & ATTN_SW_TIMER_4_FUNC)
3711 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3712
3713 if (asserted & GPIO_2_FUNC)
3714 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3715
3716 if (asserted & GPIO_3_FUNC)
3717 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3718
3719 if (asserted & GPIO_4_FUNC)
3720 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3721
3722 if (port == 0) {
3723 if (asserted & ATTN_GENERAL_ATTN_1) {
3724 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3725 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3726 }
3727 if (asserted & ATTN_GENERAL_ATTN_2) {
3728 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3729 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3730 }
3731 if (asserted & ATTN_GENERAL_ATTN_3) {
3732 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3733 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3734 }
3735 } else {
3736 if (asserted & ATTN_GENERAL_ATTN_4) {
3737 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3738 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3739 }
3740 if (asserted & ATTN_GENERAL_ATTN_5) {
3741 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3742 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3743 }
3744 if (asserted & ATTN_GENERAL_ATTN_6) {
3745 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3746 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3747 }
3748 }
3749
3750 } /* if hardwired */
3751
3752 if (bp->common.int_block == INT_BLOCK_HC)
3753 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3754 COMMAND_REG_ATTN_BITS_SET);
3755 else
3756 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3757
3758 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3759 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3760 REG_WR(bp, reg_addr, asserted);
3761
3762 /* now set back the mask */
3763 if (asserted & ATTN_NIG_FOR_FUNC) {
3764 /* Verify that IGU ack through BAR was written before restoring
3765 * NIG mask. This loop should exit after 2-3 iterations max.
3766 */
3767 if (bp->common.int_block != INT_BLOCK_HC) {
3768 u32 cnt = 0, igu_acked;
3769 do {
3770 igu_acked = REG_RD(bp,
3771 IGU_REG_ATTENTION_ACK_BITS);
3772 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3773 (++cnt < MAX_IGU_ATTN_ACK_TO));
3774 if (!igu_acked)
3775 DP(NETIF_MSG_HW,
3776 "Failed to verify IGU ack on time\n");
3777 barrier();
3778 }
3779 REG_WR(bp, nig_int_mask_addr, nig_mask);
3780 bnx2x_release_phy_lock(bp);
3781 }
3782 }
3783
3784 static void bnx2x_fan_failure(struct bnx2x *bp)
3785 {
3786 int port = BP_PORT(bp);
3787 u32 ext_phy_config;
3788 /* mark the failure */
3789 ext_phy_config =
3790 SHMEM_RD(bp,
3791 dev_info.port_hw_config[port].external_phy_config);
3792
3793 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3794 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3795 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3796 ext_phy_config);
3797
3798 /* log the failure */
3799 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3800 "Please contact OEM Support for assistance\n");
3801
3802 /*
3803 * Schedule device reset (unload)
3804 * This is due to some boards consuming sufficient power when driver is
3805 * up to overheat if fan fails.
3806 */
3807 smp_mb__before_clear_bit();
3808 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3809 smp_mb__after_clear_bit();
3810 schedule_delayed_work(&bp->sp_rtnl_task, 0);
3811
3812 }
3813
3814 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3815 {
3816 int port = BP_PORT(bp);
3817 int reg_offset;
3818 u32 val;
3819
3820 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3821 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3822
3823 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3824
3825 val = REG_RD(bp, reg_offset);
3826 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3827 REG_WR(bp, reg_offset, val);
3828
3829 BNX2X_ERR("SPIO5 hw attention\n");
3830
3831 /* Fan failure attention */
3832 bnx2x_hw_reset_phy(&bp->link_params);
3833 bnx2x_fan_failure(bp);
3834 }
3835
3836 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3837 bnx2x_acquire_phy_lock(bp);
3838 bnx2x_handle_module_detect_int(&bp->link_params);
3839 bnx2x_release_phy_lock(bp);
3840 }
3841
3842 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3843
3844 val = REG_RD(bp, reg_offset);
3845 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3846 REG_WR(bp, reg_offset, val);
3847
3848 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3849 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3850 bnx2x_panic();
3851 }
3852 }
3853
3854 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3855 {
3856 u32 val;
3857
3858 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3859
3860 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3861 BNX2X_ERR("DB hw attention 0x%x\n", val);
3862 /* DORQ discard attention */
3863 if (val & 0x2)
3864 BNX2X_ERR("FATAL error from DORQ\n");
3865 }
3866
3867 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3868
3869 int port = BP_PORT(bp);
3870 int reg_offset;
3871
3872 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3873 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3874
3875 val = REG_RD(bp, reg_offset);
3876 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3877 REG_WR(bp, reg_offset, val);
3878
3879 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3880 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3881 bnx2x_panic();
3882 }
3883 }
3884
3885 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3886 {
3887 u32 val;
3888
3889 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3890
3891 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3892 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3893 /* CFC error attention */
3894 if (val & 0x2)
3895 BNX2X_ERR("FATAL error from CFC\n");
3896 }
3897
3898 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3899 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3900 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3901 /* RQ_USDMDP_FIFO_OVERFLOW */
3902 if (val & 0x18000)
3903 BNX2X_ERR("FATAL error from PXP\n");
3904
3905 if (!CHIP_IS_E1x(bp)) {
3906 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3907 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3908 }
3909 }
3910
3911 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3912
3913 int port = BP_PORT(bp);
3914 int reg_offset;
3915
3916 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3917 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3918
3919 val = REG_RD(bp, reg_offset);
3920 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3921 REG_WR(bp, reg_offset, val);
3922
3923 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3924 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3925 bnx2x_panic();
3926 }
3927 }
3928
3929 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3930 {
3931 u32 val;
3932
3933 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3934
3935 if (attn & BNX2X_PMF_LINK_ASSERT) {
3936 int func = BP_FUNC(bp);
3937
3938 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3939 bnx2x_read_mf_cfg(bp);
3940 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3941 func_mf_config[BP_ABS_FUNC(bp)].config);
3942 val = SHMEM_RD(bp,
3943 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3944 if (val & DRV_STATUS_DCC_EVENT_MASK)
3945 bnx2x_dcc_event(bp,
3946 (val & DRV_STATUS_DCC_EVENT_MASK));
3947
3948 if (val & DRV_STATUS_SET_MF_BW)
3949 bnx2x_set_mf_bw(bp);
3950
3951 if (val & DRV_STATUS_DRV_INFO_REQ)
3952 bnx2x_handle_drv_info_req(bp);
3953
3954 if (val & DRV_STATUS_VF_DISABLED)
3955 bnx2x_vf_handle_flr_event(bp);
3956
3957 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3958 bnx2x_pmf_update(bp);
3959
3960 if (bp->port.pmf &&
3961 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3962 bp->dcbx_enabled > 0)
3963 /* start dcbx state machine */
3964 bnx2x_dcbx_set_params(bp,
3965 BNX2X_DCBX_STATE_NEG_RECEIVED);
3966 if (val & DRV_STATUS_AFEX_EVENT_MASK)
3967 bnx2x_handle_afex_cmd(bp,
3968 val & DRV_STATUS_AFEX_EVENT_MASK);
3969 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3970 bnx2x_handle_eee_event(bp);
3971 if (bp->link_vars.periodic_flags &
3972 PERIODIC_FLAGS_LINK_EVENT) {
3973 /* sync with link */
3974 bnx2x_acquire_phy_lock(bp);
3975 bp->link_vars.periodic_flags &=
3976 ~PERIODIC_FLAGS_LINK_EVENT;
3977 bnx2x_release_phy_lock(bp);
3978 if (IS_MF(bp))
3979 bnx2x_link_sync_notify(bp);
3980 bnx2x_link_report(bp);
3981 }
3982 /* Always call it here: bnx2x_link_report() will
3983 * prevent the link indication duplication.
3984 */
3985 bnx2x__link_status_update(bp);
3986 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3987
3988 BNX2X_ERR("MC assert!\n");
3989 bnx2x_mc_assert(bp);
3990 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3991 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3992 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3993 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3994 bnx2x_panic();
3995
3996 } else if (attn & BNX2X_MCP_ASSERT) {
3997
3998 BNX2X_ERR("MCP assert!\n");
3999 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4000 bnx2x_fw_dump(bp);
4001
4002 } else
4003 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4004 }
4005
4006 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4007 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4008 if (attn & BNX2X_GRC_TIMEOUT) {
4009 val = CHIP_IS_E1(bp) ? 0 :
4010 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4011 BNX2X_ERR("GRC time-out 0x%08x\n", val);
4012 }
4013 if (attn & BNX2X_GRC_RSV) {
4014 val = CHIP_IS_E1(bp) ? 0 :
4015 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4016 BNX2X_ERR("GRC reserved 0x%08x\n", val);
4017 }
4018 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4019 }
4020 }
4021
4022 /*
4023 * Bits map:
4024 * 0-7 - Engine0 load counter.
4025 * 8-15 - Engine1 load counter.
4026 * 16 - Engine0 RESET_IN_PROGRESS bit.
4027 * 17 - Engine1 RESET_IN_PROGRESS bit.
4028 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4029 * on the engine
4030 * 19 - Engine1 ONE_IS_LOADED.
4031 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4032 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4033 * just the one belonging to its engine).
4034 *
4035 */
4036 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4037
4038 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4039 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4040 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4041 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4042 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4043 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4044 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
4045
4046 /*
4047 * Set the GLOBAL_RESET bit.
4048 *
4049 * Should be run under rtnl lock
4050 */
4051 void bnx2x_set_reset_global(struct bnx2x *bp)
4052 {
4053 u32 val;
4054 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4055 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4056 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4057 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4058 }
4059
4060 /*
4061 * Clear the GLOBAL_RESET bit.
4062 *
4063 * Should be run under rtnl lock
4064 */
4065 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4066 {
4067 u32 val;
4068 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4069 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4070 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4071 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4072 }
4073
4074 /*
4075 * Checks the GLOBAL_RESET bit.
4076 *
4077 * should be run under rtnl lock
4078 */
4079 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4080 {
4081 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4082
4083 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4084 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4085 }
4086
4087 /*
4088 * Clear RESET_IN_PROGRESS bit for the current engine.
4089 *
4090 * Should be run under rtnl lock
4091 */
4092 static void bnx2x_set_reset_done(struct bnx2x *bp)
4093 {
4094 u32 val;
4095 u32 bit = BP_PATH(bp) ?
4096 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4097 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4098 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4099
4100 /* Clear the bit */
4101 val &= ~bit;
4102 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4103
4104 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4105 }
4106
4107 /*
4108 * Set RESET_IN_PROGRESS for the current engine.
4109 *
4110 * should be run under rtnl lock
4111 */
4112 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4113 {
4114 u32 val;
4115 u32 bit = BP_PATH(bp) ?
4116 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4117 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4118 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4119
4120 /* Set the bit */
4121 val |= bit;
4122 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4123 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4124 }
4125
4126 /*
4127 * Checks the RESET_IN_PROGRESS bit for the given engine.
4128 * should be run under rtnl lock
4129 */
4130 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4131 {
4132 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4133 u32 bit = engine ?
4134 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4135
4136 /* return false if bit is set */
4137 return (val & bit) ? false : true;
4138 }
4139
4140 /*
4141 * set pf load for the current pf.
4142 *
4143 * should be run under rtnl lock
4144 */
4145 void bnx2x_set_pf_load(struct bnx2x *bp)
4146 {
4147 u32 val1, val;
4148 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4149 BNX2X_PATH0_LOAD_CNT_MASK;
4150 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4151 BNX2X_PATH0_LOAD_CNT_SHIFT;
4152
4153 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4154 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4155
4156 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4157
4158 /* get the current counter value */
4159 val1 = (val & mask) >> shift;
4160
4161 /* set bit of that PF */
4162 val1 |= (1 << bp->pf_num);
4163
4164 /* clear the old value */
4165 val &= ~mask;
4166
4167 /* set the new one */
4168 val |= ((val1 << shift) & mask);
4169
4170 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4171 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4172 }
4173
4174 /**
4175 * bnx2x_clear_pf_load - clear pf load mark
4176 *
4177 * @bp: driver handle
4178 *
4179 * Should be run under rtnl lock.
4180 * Decrements the load counter for the current engine. Returns
4181 * whether other functions are still loaded
4182 */
4183 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4184 {
4185 u32 val1, val;
4186 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4187 BNX2X_PATH0_LOAD_CNT_MASK;
4188 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4189 BNX2X_PATH0_LOAD_CNT_SHIFT;
4190
4191 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4192 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4193 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4194
4195 /* get the current counter value */
4196 val1 = (val & mask) >> shift;
4197
4198 /* clear bit of that PF */
4199 val1 &= ~(1 << bp->pf_num);
4200
4201 /* clear the old value */
4202 val &= ~mask;
4203
4204 /* set the new one */
4205 val |= ((val1 << shift) & mask);
4206
4207 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4208 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4209 return val1 != 0;
4210 }
4211
4212 /*
4213 * Read the load status for the current engine.
4214 *
4215 * should be run under rtnl lock
4216 */
4217 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4218 {
4219 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4220 BNX2X_PATH0_LOAD_CNT_MASK);
4221 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4222 BNX2X_PATH0_LOAD_CNT_SHIFT);
4223 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4224
4225 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4226
4227 val = (val & mask) >> shift;
4228
4229 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4230 engine, val);
4231
4232 return val != 0;
4233 }
4234
4235 static void _print_next_block(int idx, const char *blk)
4236 {
4237 pr_cont("%s%s", idx ? ", " : "", blk);
4238 }
4239
4240 static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
4241 bool print)
4242 {
4243 int i = 0;
4244 u32 cur_bit = 0;
4245 for (i = 0; sig; i++) {
4246 cur_bit = ((u32)0x1 << i);
4247 if (sig & cur_bit) {
4248 switch (cur_bit) {
4249 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4250 if (print)
4251 _print_next_block(par_num++, "BRB");
4252 break;
4253 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4254 if (print)
4255 _print_next_block(par_num++, "PARSER");
4256 break;
4257 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4258 if (print)
4259 _print_next_block(par_num++, "TSDM");
4260 break;
4261 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4262 if (print)
4263 _print_next_block(par_num++,
4264 "SEARCHER");
4265 break;
4266 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4267 if (print)
4268 _print_next_block(par_num++, "TCM");
4269 break;
4270 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4271 if (print)
4272 _print_next_block(par_num++, "TSEMI");
4273 break;
4274 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4275 if (print)
4276 _print_next_block(par_num++, "XPB");
4277 break;
4278 }
4279
4280 /* Clear the bit */
4281 sig &= ~cur_bit;
4282 }
4283 }
4284
4285 return par_num;
4286 }
4287
4288 static int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
4289 bool *global, bool print)
4290 {
4291 int i = 0;
4292 u32 cur_bit = 0;
4293 for (i = 0; sig; i++) {
4294 cur_bit = ((u32)0x1 << i);
4295 if (sig & cur_bit) {
4296 switch (cur_bit) {
4297 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4298 if (print)
4299 _print_next_block(par_num++, "PBF");
4300 break;
4301 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4302 if (print)
4303 _print_next_block(par_num++, "QM");
4304 break;
4305 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4306 if (print)
4307 _print_next_block(par_num++, "TM");
4308 break;
4309 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4310 if (print)
4311 _print_next_block(par_num++, "XSDM");
4312 break;
4313 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4314 if (print)
4315 _print_next_block(par_num++, "XCM");
4316 break;
4317 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4318 if (print)
4319 _print_next_block(par_num++, "XSEMI");
4320 break;
4321 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4322 if (print)
4323 _print_next_block(par_num++,
4324 "DOORBELLQ");
4325 break;
4326 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4327 if (print)
4328 _print_next_block(par_num++, "NIG");
4329 break;
4330 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4331 if (print)
4332 _print_next_block(par_num++,
4333 "VAUX PCI CORE");
4334 *global = true;
4335 break;
4336 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4337 if (print)
4338 _print_next_block(par_num++, "DEBUG");
4339 break;
4340 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4341 if (print)
4342 _print_next_block(par_num++, "USDM");
4343 break;
4344 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4345 if (print)
4346 _print_next_block(par_num++, "UCM");
4347 break;
4348 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4349 if (print)
4350 _print_next_block(par_num++, "USEMI");
4351 break;
4352 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4353 if (print)
4354 _print_next_block(par_num++, "UPB");
4355 break;
4356 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4357 if (print)
4358 _print_next_block(par_num++, "CSDM");
4359 break;
4360 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4361 if (print)
4362 _print_next_block(par_num++, "CCM");
4363 break;
4364 }
4365
4366 /* Clear the bit */
4367 sig &= ~cur_bit;
4368 }
4369 }
4370
4371 return par_num;
4372 }
4373
4374 static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
4375 bool print)
4376 {
4377 int i = 0;
4378 u32 cur_bit = 0;
4379 for (i = 0; sig; i++) {
4380 cur_bit = ((u32)0x1 << i);
4381 if (sig & cur_bit) {
4382 switch (cur_bit) {
4383 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4384 if (print)
4385 _print_next_block(par_num++, "CSEMI");
4386 break;
4387 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4388 if (print)
4389 _print_next_block(par_num++, "PXP");
4390 break;
4391 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4392 if (print)
4393 _print_next_block(par_num++,
4394 "PXPPCICLOCKCLIENT");
4395 break;
4396 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4397 if (print)
4398 _print_next_block(par_num++, "CFC");
4399 break;
4400 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4401 if (print)
4402 _print_next_block(par_num++, "CDU");
4403 break;
4404 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4405 if (print)
4406 _print_next_block(par_num++, "DMAE");
4407 break;
4408 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4409 if (print)
4410 _print_next_block(par_num++, "IGU");
4411 break;
4412 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4413 if (print)
4414 _print_next_block(par_num++, "MISC");
4415 break;
4416 }
4417
4418 /* Clear the bit */
4419 sig &= ~cur_bit;
4420 }
4421 }
4422
4423 return par_num;
4424 }
4425
4426 static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4427 bool *global, bool print)
4428 {
4429 int i = 0;
4430 u32 cur_bit = 0;
4431 for (i = 0; sig; i++) {
4432 cur_bit = ((u32)0x1 << i);
4433 if (sig & cur_bit) {
4434 switch (cur_bit) {
4435 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4436 if (print)
4437 _print_next_block(par_num++, "MCP ROM");
4438 *global = true;
4439 break;
4440 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4441 if (print)
4442 _print_next_block(par_num++,
4443 "MCP UMP RX");
4444 *global = true;
4445 break;
4446 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4447 if (print)
4448 _print_next_block(par_num++,
4449 "MCP UMP TX");
4450 *global = true;
4451 break;
4452 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4453 if (print)
4454 _print_next_block(par_num++,
4455 "MCP SCPAD");
4456 *global = true;
4457 break;
4458 }
4459
4460 /* Clear the bit */
4461 sig &= ~cur_bit;
4462 }
4463 }
4464
4465 return par_num;
4466 }
4467
4468 static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
4469 bool print)
4470 {
4471 int i = 0;
4472 u32 cur_bit = 0;
4473 for (i = 0; sig; i++) {
4474 cur_bit = ((u32)0x1 << i);
4475 if (sig & cur_bit) {
4476 switch (cur_bit) {
4477 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4478 if (print)
4479 _print_next_block(par_num++, "PGLUE_B");
4480 break;
4481 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4482 if (print)
4483 _print_next_block(par_num++, "ATC");
4484 break;
4485 }
4486
4487 /* Clear the bit */
4488 sig &= ~cur_bit;
4489 }
4490 }
4491
4492 return par_num;
4493 }
4494
4495 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4496 u32 *sig)
4497 {
4498 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4499 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4500 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4501 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4502 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4503 int par_num = 0;
4504 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4505 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4506 sig[0] & HW_PRTY_ASSERT_SET_0,
4507 sig[1] & HW_PRTY_ASSERT_SET_1,
4508 sig[2] & HW_PRTY_ASSERT_SET_2,
4509 sig[3] & HW_PRTY_ASSERT_SET_3,
4510 sig[4] & HW_PRTY_ASSERT_SET_4);
4511 if (print)
4512 netdev_err(bp->dev,
4513 "Parity errors detected in blocks: ");
4514 par_num = bnx2x_check_blocks_with_parity0(
4515 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4516 par_num = bnx2x_check_blocks_with_parity1(
4517 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4518 par_num = bnx2x_check_blocks_with_parity2(
4519 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4520 par_num = bnx2x_check_blocks_with_parity3(
4521 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4522 par_num = bnx2x_check_blocks_with_parity4(
4523 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4524
4525 if (print)
4526 pr_cont("\n");
4527
4528 return true;
4529 } else
4530 return false;
4531 }
4532
4533 /**
4534 * bnx2x_chk_parity_attn - checks for parity attentions.
4535 *
4536 * @bp: driver handle
4537 * @global: true if there was a global attention
4538 * @print: show parity attention in syslog
4539 */
4540 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4541 {
4542 struct attn_route attn = { {0} };
4543 int port = BP_PORT(bp);
4544
4545 attn.sig[0] = REG_RD(bp,
4546 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4547 port*4);
4548 attn.sig[1] = REG_RD(bp,
4549 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4550 port*4);
4551 attn.sig[2] = REG_RD(bp,
4552 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4553 port*4);
4554 attn.sig[3] = REG_RD(bp,
4555 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4556 port*4);
4557
4558 if (!CHIP_IS_E1x(bp))
4559 attn.sig[4] = REG_RD(bp,
4560 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4561 port*4);
4562
4563 return bnx2x_parity_attn(bp, global, print, attn.sig);
4564 }
4565
4566
4567 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4568 {
4569 u32 val;
4570 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4571
4572 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4573 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4574 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4575 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4576 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4577 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4578 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4579 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4580 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4581 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4582 if (val &
4583 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4584 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4585 if (val &
4586 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4587 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4588 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4589 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4590 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4591 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4592 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4593 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4594 }
4595 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4596 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4597 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4598 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4599 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4600 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4601 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4602 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4603 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4604 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4605 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4606 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4607 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4608 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4609 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4610 }
4611
4612 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4613 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4614 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4615 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4616 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4617 }
4618
4619 }
4620
4621 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4622 {
4623 struct attn_route attn, *group_mask;
4624 int port = BP_PORT(bp);
4625 int index;
4626 u32 reg_addr;
4627 u32 val;
4628 u32 aeu_mask;
4629 bool global = false;
4630
4631 /* need to take HW lock because MCP or other port might also
4632 try to handle this event */
4633 bnx2x_acquire_alr(bp);
4634
4635 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4636 #ifndef BNX2X_STOP_ON_ERROR
4637 bp->recovery_state = BNX2X_RECOVERY_INIT;
4638 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4639 /* Disable HW interrupts */
4640 bnx2x_int_disable(bp);
4641 /* In case of parity errors don't handle attentions so that
4642 * other function would "see" parity errors.
4643 */
4644 #else
4645 bnx2x_panic();
4646 #endif
4647 bnx2x_release_alr(bp);
4648 return;
4649 }
4650
4651 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4652 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4653 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4654 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4655 if (!CHIP_IS_E1x(bp))
4656 attn.sig[4] =
4657 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4658 else
4659 attn.sig[4] = 0;
4660
4661 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4662 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4663
4664 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4665 if (deasserted & (1 << index)) {
4666 group_mask = &bp->attn_group[index];
4667
4668 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4669 index,
4670 group_mask->sig[0], group_mask->sig[1],
4671 group_mask->sig[2], group_mask->sig[3],
4672 group_mask->sig[4]);
4673
4674 bnx2x_attn_int_deasserted4(bp,
4675 attn.sig[4] & group_mask->sig[4]);
4676 bnx2x_attn_int_deasserted3(bp,
4677 attn.sig[3] & group_mask->sig[3]);
4678 bnx2x_attn_int_deasserted1(bp,
4679 attn.sig[1] & group_mask->sig[1]);
4680 bnx2x_attn_int_deasserted2(bp,
4681 attn.sig[2] & group_mask->sig[2]);
4682 bnx2x_attn_int_deasserted0(bp,
4683 attn.sig[0] & group_mask->sig[0]);
4684 }
4685 }
4686
4687 bnx2x_release_alr(bp);
4688
4689 if (bp->common.int_block == INT_BLOCK_HC)
4690 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4691 COMMAND_REG_ATTN_BITS_CLR);
4692 else
4693 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4694
4695 val = ~deasserted;
4696 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4697 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4698 REG_WR(bp, reg_addr, val);
4699
4700 if (~bp->attn_state & deasserted)
4701 BNX2X_ERR("IGU ERROR\n");
4702
4703 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4704 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4705
4706 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4707 aeu_mask = REG_RD(bp, reg_addr);
4708
4709 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4710 aeu_mask, deasserted);
4711 aeu_mask |= (deasserted & 0x3ff);
4712 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4713
4714 REG_WR(bp, reg_addr, aeu_mask);
4715 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4716
4717 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4718 bp->attn_state &= ~deasserted;
4719 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4720 }
4721
4722 static void bnx2x_attn_int(struct bnx2x *bp)
4723 {
4724 /* read local copy of bits */
4725 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4726 attn_bits);
4727 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4728 attn_bits_ack);
4729 u32 attn_state = bp->attn_state;
4730
4731 /* look for changed bits */
4732 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4733 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4734
4735 DP(NETIF_MSG_HW,
4736 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4737 attn_bits, attn_ack, asserted, deasserted);
4738
4739 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4740 BNX2X_ERR("BAD attention state\n");
4741
4742 /* handle bits that were raised */
4743 if (asserted)
4744 bnx2x_attn_int_asserted(bp, asserted);
4745
4746 if (deasserted)
4747 bnx2x_attn_int_deasserted(bp, deasserted);
4748 }
4749
4750 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4751 u16 index, u8 op, u8 update)
4752 {
4753 u32 igu_addr = bp->igu_base_addr;
4754 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4755 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4756 igu_addr);
4757 }
4758
4759 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4760 {
4761 /* No memory barriers */
4762 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4763 mmiowb(); /* keep prod updates ordered */
4764 }
4765
4766 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4767 union event_ring_elem *elem)
4768 {
4769 u8 err = elem->message.error;
4770
4771 if (!bp->cnic_eth_dev.starting_cid ||
4772 (cid < bp->cnic_eth_dev.starting_cid &&
4773 cid != bp->cnic_eth_dev.iscsi_l2_cid))
4774 return 1;
4775
4776 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4777
4778 if (unlikely(err)) {
4779
4780 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4781 cid);
4782 bnx2x_panic_dump(bp, false);
4783 }
4784 bnx2x_cnic_cfc_comp(bp, cid, err);
4785 return 0;
4786 }
4787
4788 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4789 {
4790 struct bnx2x_mcast_ramrod_params rparam;
4791 int rc;
4792
4793 memset(&rparam, 0, sizeof(rparam));
4794
4795 rparam.mcast_obj = &bp->mcast_obj;
4796
4797 netif_addr_lock_bh(bp->dev);
4798
4799 /* Clear pending state for the last command */
4800 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4801
4802 /* If there are pending mcast commands - send them */
4803 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4804 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4805 if (rc < 0)
4806 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4807 rc);
4808 }
4809
4810 netif_addr_unlock_bh(bp->dev);
4811 }
4812
4813 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4814 union event_ring_elem *elem)
4815 {
4816 unsigned long ramrod_flags = 0;
4817 int rc = 0;
4818 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4819 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4820
4821 /* Always push next commands out, don't wait here */
4822 __set_bit(RAMROD_CONT, &ramrod_flags);
4823
4824 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4825 case BNX2X_FILTER_MAC_PENDING:
4826 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
4827 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
4828 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4829 else
4830 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
4831
4832 break;
4833 case BNX2X_FILTER_MCAST_PENDING:
4834 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
4835 /* This is only relevant for 57710 where multicast MACs are
4836 * configured as unicast MACs using the same ramrod.
4837 */
4838 bnx2x_handle_mcast_eqe(bp);
4839 return;
4840 default:
4841 BNX2X_ERR("Unsupported classification command: %d\n",
4842 elem->message.data.eth_event.echo);
4843 return;
4844 }
4845
4846 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4847
4848 if (rc < 0)
4849 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4850 else if (rc > 0)
4851 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4852
4853 }
4854
4855 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4856
4857 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4858 {
4859 netif_addr_lock_bh(bp->dev);
4860
4861 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4862
4863 /* Send rx_mode command again if was requested */
4864 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4865 bnx2x_set_storm_rx_mode(bp);
4866 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4867 &bp->sp_state))
4868 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4869 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4870 &bp->sp_state))
4871 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4872
4873 netif_addr_unlock_bh(bp->dev);
4874 }
4875
4876 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
4877 union event_ring_elem *elem)
4878 {
4879 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
4880 DP(BNX2X_MSG_SP,
4881 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
4882 elem->message.data.vif_list_event.func_bit_map);
4883 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
4884 elem->message.data.vif_list_event.func_bit_map);
4885 } else if (elem->message.data.vif_list_event.echo ==
4886 VIF_LIST_RULE_SET) {
4887 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
4888 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
4889 }
4890 }
4891
4892 /* called with rtnl_lock */
4893 static void bnx2x_after_function_update(struct bnx2x *bp)
4894 {
4895 int q, rc;
4896 struct bnx2x_fastpath *fp;
4897 struct bnx2x_queue_state_params queue_params = {NULL};
4898 struct bnx2x_queue_update_params *q_update_params =
4899 &queue_params.params.update;
4900
4901 /* Send Q update command with afex vlan removal values for all Qs */
4902 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
4903
4904 /* set silent vlan removal values according to vlan mode */
4905 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
4906 &q_update_params->update_flags);
4907 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
4908 &q_update_params->update_flags);
4909 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4910
4911 /* in access mode mark mask and value are 0 to strip all vlans */
4912 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
4913 q_update_params->silent_removal_value = 0;
4914 q_update_params->silent_removal_mask = 0;
4915 } else {
4916 q_update_params->silent_removal_value =
4917 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
4918 q_update_params->silent_removal_mask = VLAN_VID_MASK;
4919 }
4920
4921 for_each_eth_queue(bp, q) {
4922 /* Set the appropriate Queue object */
4923 fp = &bp->fp[q];
4924 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4925
4926 /* send the ramrod */
4927 rc = bnx2x_queue_state_change(bp, &queue_params);
4928 if (rc < 0)
4929 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4930 q);
4931 }
4932
4933 if (!NO_FCOE(bp)) {
4934 fp = &bp->fp[FCOE_IDX(bp)];
4935 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4936
4937 /* clear pending completion bit */
4938 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4939
4940 /* mark latest Q bit */
4941 smp_mb__before_clear_bit();
4942 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4943 smp_mb__after_clear_bit();
4944
4945 /* send Q update ramrod for FCoE Q */
4946 rc = bnx2x_queue_state_change(bp, &queue_params);
4947 if (rc < 0)
4948 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4949 q);
4950 } else {
4951 /* If no FCoE ring - ACK MCP now */
4952 bnx2x_link_report(bp);
4953 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
4954 }
4955 }
4956
4957 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4958 struct bnx2x *bp, u32 cid)
4959 {
4960 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
4961
4962 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
4963 return &bnx2x_fcoe_sp_obj(bp, q_obj);
4964 else
4965 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
4966 }
4967
4968 static void bnx2x_eq_int(struct bnx2x *bp)
4969 {
4970 u16 hw_cons, sw_cons, sw_prod;
4971 union event_ring_elem *elem;
4972 u8 echo;
4973 u32 cid;
4974 u8 opcode;
4975 int rc, spqe_cnt = 0;
4976 struct bnx2x_queue_sp_obj *q_obj;
4977 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4978 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
4979
4980 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4981
4982 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4983 * when we get the the next-page we nned to adjust so the loop
4984 * condition below will be met. The next element is the size of a
4985 * regular element and hence incrementing by 1
4986 */
4987 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4988 hw_cons++;
4989
4990 /* This function may never run in parallel with itself for a
4991 * specific bp, thus there is no need in "paired" read memory
4992 * barrier here.
4993 */
4994 sw_cons = bp->eq_cons;
4995 sw_prod = bp->eq_prod;
4996
4997 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
4998 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
4999
5000 for (; sw_cons != hw_cons;
5001 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5002
5003 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5004
5005 rc = bnx2x_iov_eq_sp_event(bp, elem);
5006 if (!rc) {
5007 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5008 rc);
5009 goto next_spqe;
5010 }
5011 cid = SW_CID(elem->message.data.cfc_del_event.cid);
5012 opcode = elem->message.opcode;
5013
5014
5015 /* handle eq element */
5016 switch (opcode) {
5017 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5018 DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n");
5019 bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event);
5020 continue;
5021
5022 case EVENT_RING_OPCODE_STAT_QUERY:
5023 DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
5024 "got statistics comp event %d\n",
5025 bp->stats_comp++);
5026 /* nothing to do with stats comp */
5027 goto next_spqe;
5028
5029 case EVENT_RING_OPCODE_CFC_DEL:
5030 /* handle according to cid range */
5031 /*
5032 * we may want to verify here that the bp state is
5033 * HALTING
5034 */
5035 DP(BNX2X_MSG_SP,
5036 "got delete ramrod for MULTI[%d]\n", cid);
5037
5038 if (CNIC_LOADED(bp) &&
5039 !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5040 goto next_spqe;
5041
5042 q_obj = bnx2x_cid_to_q_obj(bp, cid);
5043
5044 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5045 break;
5046
5047
5048
5049 goto next_spqe;
5050
5051 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5052 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5053 if (f_obj->complete_cmd(bp, f_obj,
5054 BNX2X_F_CMD_TX_STOP))
5055 break;
5056 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5057 goto next_spqe;
5058
5059 case EVENT_RING_OPCODE_START_TRAFFIC:
5060 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5061 if (f_obj->complete_cmd(bp, f_obj,
5062 BNX2X_F_CMD_TX_START))
5063 break;
5064 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5065 goto next_spqe;
5066
5067 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5068 echo = elem->message.data.function_update_event.echo;
5069 if (echo == SWITCH_UPDATE) {
5070 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5071 "got FUNC_SWITCH_UPDATE ramrod\n");
5072 if (f_obj->complete_cmd(
5073 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5074 break;
5075
5076 } else {
5077 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5078 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5079 f_obj->complete_cmd(bp, f_obj,
5080 BNX2X_F_CMD_AFEX_UPDATE);
5081
5082 /* We will perform the Queues update from
5083 * sp_rtnl task as all Queue SP operations
5084 * should run under rtnl_lock.
5085 */
5086 smp_mb__before_clear_bit();
5087 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
5088 &bp->sp_rtnl_state);
5089 smp_mb__after_clear_bit();
5090
5091 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5092 }
5093
5094 goto next_spqe;
5095
5096 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5097 f_obj->complete_cmd(bp, f_obj,
5098 BNX2X_F_CMD_AFEX_VIFLISTS);
5099 bnx2x_after_afex_vif_lists(bp, elem);
5100 goto next_spqe;
5101 case EVENT_RING_OPCODE_FUNCTION_START:
5102 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5103 "got FUNC_START ramrod\n");
5104 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5105 break;
5106
5107 goto next_spqe;
5108
5109 case EVENT_RING_OPCODE_FUNCTION_STOP:
5110 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5111 "got FUNC_STOP ramrod\n");
5112 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5113 break;
5114
5115 goto next_spqe;
5116 }
5117
5118 switch (opcode | bp->state) {
5119 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5120 BNX2X_STATE_OPEN):
5121 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5122 BNX2X_STATE_OPENING_WAIT4_PORT):
5123 cid = elem->message.data.eth_event.echo &
5124 BNX2X_SWCID_MASK;
5125 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5126 cid);
5127 rss_raw->clear_pending(rss_raw);
5128 break;
5129
5130 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5131 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5132 case (EVENT_RING_OPCODE_SET_MAC |
5133 BNX2X_STATE_CLOSING_WAIT4_HALT):
5134 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5135 BNX2X_STATE_OPEN):
5136 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5137 BNX2X_STATE_DIAG):
5138 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5139 BNX2X_STATE_CLOSING_WAIT4_HALT):
5140 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5141 bnx2x_handle_classification_eqe(bp, elem);
5142 break;
5143
5144 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5145 BNX2X_STATE_OPEN):
5146 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5147 BNX2X_STATE_DIAG):
5148 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5149 BNX2X_STATE_CLOSING_WAIT4_HALT):
5150 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5151 bnx2x_handle_mcast_eqe(bp);
5152 break;
5153
5154 case (EVENT_RING_OPCODE_FILTERS_RULES |
5155 BNX2X_STATE_OPEN):
5156 case (EVENT_RING_OPCODE_FILTERS_RULES |
5157 BNX2X_STATE_DIAG):
5158 case (EVENT_RING_OPCODE_FILTERS_RULES |
5159 BNX2X_STATE_CLOSING_WAIT4_HALT):
5160 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5161 bnx2x_handle_rx_mode_eqe(bp);
5162 break;
5163 default:
5164 /* unknown event log error and continue */
5165 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5166 elem->message.opcode, bp->state);
5167 }
5168 next_spqe:
5169 spqe_cnt++;
5170 } /* for */
5171
5172 smp_mb__before_atomic_inc();
5173 atomic_add(spqe_cnt, &bp->eq_spq_left);
5174
5175 bp->eq_cons = sw_cons;
5176 bp->eq_prod = sw_prod;
5177 /* Make sure that above mem writes were issued towards the memory */
5178 smp_wmb();
5179
5180 /* update producer */
5181 bnx2x_update_eq_prod(bp, bp->eq_prod);
5182 }
5183
5184 static void bnx2x_sp_task(struct work_struct *work)
5185 {
5186 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5187
5188 DP(BNX2X_MSG_SP, "sp task invoked\n");
5189
5190 /* make sure the atomic interupt_occurred has been written */
5191 smp_rmb();
5192 if (atomic_read(&bp->interrupt_occurred)) {
5193
5194 /* what work needs to be performed? */
5195 u16 status = bnx2x_update_dsb_idx(bp);
5196
5197 DP(BNX2X_MSG_SP, "status %x\n", status);
5198 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5199 atomic_set(&bp->interrupt_occurred, 0);
5200
5201 /* HW attentions */
5202 if (status & BNX2X_DEF_SB_ATT_IDX) {
5203 bnx2x_attn_int(bp);
5204 status &= ~BNX2X_DEF_SB_ATT_IDX;
5205 }
5206
5207 /* SP events: STAT_QUERY and others */
5208 if (status & BNX2X_DEF_SB_IDX) {
5209 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5210
5211 if (FCOE_INIT(bp) &&
5212 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5213 /* Prevent local bottom-halves from running as
5214 * we are going to change the local NAPI list.
5215 */
5216 local_bh_disable();
5217 napi_schedule(&bnx2x_fcoe(bp, napi));
5218 local_bh_enable();
5219 }
5220
5221 /* Handle EQ completions */
5222 bnx2x_eq_int(bp);
5223 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5224 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5225
5226 status &= ~BNX2X_DEF_SB_IDX;
5227 }
5228
5229 /* if status is non zero then perhaps something went wrong */
5230 if (unlikely(status))
5231 DP(BNX2X_MSG_SP,
5232 "got an unknown interrupt! (status 0x%x)\n", status);
5233
5234 /* ack status block only if something was actually handled */
5235 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5236 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5237
5238 }
5239
5240 /* must be called after the EQ processing (since eq leads to sriov
5241 * ramrod completion flows).
5242 * This flow may have been scheduled by the arrival of a ramrod
5243 * completion, or by the sriov code rescheduling itself.
5244 */
5245 bnx2x_iov_sp_task(bp);
5246
5247 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5248 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5249 &bp->sp_state)) {
5250 bnx2x_link_report(bp);
5251 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5252 }
5253 }
5254
5255 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5256 {
5257 struct net_device *dev = dev_instance;
5258 struct bnx2x *bp = netdev_priv(dev);
5259
5260 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5261 IGU_INT_DISABLE, 0);
5262
5263 #ifdef BNX2X_STOP_ON_ERROR
5264 if (unlikely(bp->panic))
5265 return IRQ_HANDLED;
5266 #endif
5267
5268 if (CNIC_LOADED(bp)) {
5269 struct cnic_ops *c_ops;
5270
5271 rcu_read_lock();
5272 c_ops = rcu_dereference(bp->cnic_ops);
5273 if (c_ops)
5274 c_ops->cnic_handler(bp->cnic_data, NULL);
5275 rcu_read_unlock();
5276 }
5277
5278 /* schedule sp task to perform default status block work, ack
5279 * attentions and enable interrupts.
5280 */
5281 bnx2x_schedule_sp_task(bp);
5282
5283 return IRQ_HANDLED;
5284 }
5285
5286 /* end of slow path */
5287
5288
5289 void bnx2x_drv_pulse(struct bnx2x *bp)
5290 {
5291 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5292 bp->fw_drv_pulse_wr_seq);
5293 }
5294
5295 static void bnx2x_timer(unsigned long data)
5296 {
5297 struct bnx2x *bp = (struct bnx2x *) data;
5298
5299 if (!netif_running(bp->dev))
5300 return;
5301
5302 if (IS_PF(bp) &&
5303 !BP_NOMCP(bp)) {
5304 int mb_idx = BP_FW_MB_IDX(bp);
5305 u32 drv_pulse;
5306 u32 mcp_pulse;
5307
5308 ++bp->fw_drv_pulse_wr_seq;
5309 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5310 /* TBD - add SYSTEM_TIME */
5311 drv_pulse = bp->fw_drv_pulse_wr_seq;
5312 bnx2x_drv_pulse(bp);
5313
5314 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5315 MCP_PULSE_SEQ_MASK);
5316 /* The delta between driver pulse and mcp response
5317 * should be 1 (before mcp response) or 0 (after mcp response)
5318 */
5319 if ((drv_pulse != mcp_pulse) &&
5320 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
5321 /* someone lost a heartbeat... */
5322 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5323 drv_pulse, mcp_pulse);
5324 }
5325 }
5326
5327 if (bp->state == BNX2X_STATE_OPEN)
5328 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5329
5330 /* sample pf vf bulletin board for new posts from pf */
5331 if (IS_VF(bp))
5332 bnx2x_sample_bulletin(bp);
5333
5334 mod_timer(&bp->timer, jiffies + bp->current_interval);
5335 }
5336
5337 /* end of Statistics */
5338
5339 /* nic init */
5340
5341 /*
5342 * nic init service functions
5343 */
5344
5345 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5346 {
5347 u32 i;
5348 if (!(len%4) && !(addr%4))
5349 for (i = 0; i < len; i += 4)
5350 REG_WR(bp, addr + i, fill);
5351 else
5352 for (i = 0; i < len; i++)
5353 REG_WR8(bp, addr + i, fill);
5354
5355 }
5356
5357 /* helper: writes FP SP data to FW - data_size in dwords */
5358 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5359 int fw_sb_id,
5360 u32 *sb_data_p,
5361 u32 data_size)
5362 {
5363 int index;
5364 for (index = 0; index < data_size; index++)
5365 REG_WR(bp, BAR_CSTRORM_INTMEM +
5366 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5367 sizeof(u32)*index,
5368 *(sb_data_p + index));
5369 }
5370
5371 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5372 {
5373 u32 *sb_data_p;
5374 u32 data_size = 0;
5375 struct hc_status_block_data_e2 sb_data_e2;
5376 struct hc_status_block_data_e1x sb_data_e1x;
5377
5378 /* disable the function first */
5379 if (!CHIP_IS_E1x(bp)) {
5380 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5381 sb_data_e2.common.state = SB_DISABLED;
5382 sb_data_e2.common.p_func.vf_valid = false;
5383 sb_data_p = (u32 *)&sb_data_e2;
5384 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5385 } else {
5386 memset(&sb_data_e1x, 0,
5387 sizeof(struct hc_status_block_data_e1x));
5388 sb_data_e1x.common.state = SB_DISABLED;
5389 sb_data_e1x.common.p_func.vf_valid = false;
5390 sb_data_p = (u32 *)&sb_data_e1x;
5391 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5392 }
5393 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5394
5395 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5396 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5397 CSTORM_STATUS_BLOCK_SIZE);
5398 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5399 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5400 CSTORM_SYNC_BLOCK_SIZE);
5401 }
5402
5403 /* helper: writes SP SB data to FW */
5404 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5405 struct hc_sp_status_block_data *sp_sb_data)
5406 {
5407 int func = BP_FUNC(bp);
5408 int i;
5409 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5410 REG_WR(bp, BAR_CSTRORM_INTMEM +
5411 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5412 i*sizeof(u32),
5413 *((u32 *)sp_sb_data + i));
5414 }
5415
5416 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5417 {
5418 int func = BP_FUNC(bp);
5419 struct hc_sp_status_block_data sp_sb_data;
5420 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5421
5422 sp_sb_data.state = SB_DISABLED;
5423 sp_sb_data.p_func.vf_valid = false;
5424
5425 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5426
5427 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5428 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5429 CSTORM_SP_STATUS_BLOCK_SIZE);
5430 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5431 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5432 CSTORM_SP_SYNC_BLOCK_SIZE);
5433
5434 }
5435
5436
5437 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5438 int igu_sb_id, int igu_seg_id)
5439 {
5440 hc_sm->igu_sb_id = igu_sb_id;
5441 hc_sm->igu_seg_id = igu_seg_id;
5442 hc_sm->timer_value = 0xFF;
5443 hc_sm->time_to_expire = 0xFFFFFFFF;
5444 }
5445
5446
5447 /* allocates state machine ids. */
5448 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5449 {
5450 /* zero out state machine indices */
5451 /* rx indices */
5452 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5453
5454 /* tx indices */
5455 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5456 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5457 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5458 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5459
5460 /* map indices */
5461 /* rx indices */
5462 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5463 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5464
5465 /* tx indices */
5466 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5467 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5468 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5469 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5470 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5471 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5472 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5473 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5474 }
5475
5476 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5477 u8 vf_valid, int fw_sb_id, int igu_sb_id)
5478 {
5479 int igu_seg_id;
5480
5481 struct hc_status_block_data_e2 sb_data_e2;
5482 struct hc_status_block_data_e1x sb_data_e1x;
5483 struct hc_status_block_sm *hc_sm_p;
5484 int data_size;
5485 u32 *sb_data_p;
5486
5487 if (CHIP_INT_MODE_IS_BC(bp))
5488 igu_seg_id = HC_SEG_ACCESS_NORM;
5489 else
5490 igu_seg_id = IGU_SEG_ACCESS_NORM;
5491
5492 bnx2x_zero_fp_sb(bp, fw_sb_id);
5493
5494 if (!CHIP_IS_E1x(bp)) {
5495 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5496 sb_data_e2.common.state = SB_ENABLED;
5497 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5498 sb_data_e2.common.p_func.vf_id = vfid;
5499 sb_data_e2.common.p_func.vf_valid = vf_valid;
5500 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5501 sb_data_e2.common.same_igu_sb_1b = true;
5502 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5503 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5504 hc_sm_p = sb_data_e2.common.state_machine;
5505 sb_data_p = (u32 *)&sb_data_e2;
5506 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5507 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5508 } else {
5509 memset(&sb_data_e1x, 0,
5510 sizeof(struct hc_status_block_data_e1x));
5511 sb_data_e1x.common.state = SB_ENABLED;
5512 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5513 sb_data_e1x.common.p_func.vf_id = 0xff;
5514 sb_data_e1x.common.p_func.vf_valid = false;
5515 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5516 sb_data_e1x.common.same_igu_sb_1b = true;
5517 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5518 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5519 hc_sm_p = sb_data_e1x.common.state_machine;
5520 sb_data_p = (u32 *)&sb_data_e1x;
5521 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5522 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5523 }
5524
5525 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5526 igu_sb_id, igu_seg_id);
5527 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5528 igu_sb_id, igu_seg_id);
5529
5530 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5531
5532 /* write indecies to HW */
5533 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5534 }
5535
5536 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5537 u16 tx_usec, u16 rx_usec)
5538 {
5539 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5540 false, rx_usec);
5541 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5542 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5543 tx_usec);
5544 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5545 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5546 tx_usec);
5547 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5548 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5549 tx_usec);
5550 }
5551
5552 static void bnx2x_init_def_sb(struct bnx2x *bp)
5553 {
5554 struct host_sp_status_block *def_sb = bp->def_status_blk;
5555 dma_addr_t mapping = bp->def_status_blk_mapping;
5556 int igu_sp_sb_index;
5557 int igu_seg_id;
5558 int port = BP_PORT(bp);
5559 int func = BP_FUNC(bp);
5560 int reg_offset, reg_offset_en5;
5561 u64 section;
5562 int index;
5563 struct hc_sp_status_block_data sp_sb_data;
5564 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5565
5566 if (CHIP_INT_MODE_IS_BC(bp)) {
5567 igu_sp_sb_index = DEF_SB_IGU_ID;
5568 igu_seg_id = HC_SEG_ACCESS_DEF;
5569 } else {
5570 igu_sp_sb_index = bp->igu_dsb_id;
5571 igu_seg_id = IGU_SEG_ACCESS_DEF;
5572 }
5573
5574 /* ATTN */
5575 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5576 atten_status_block);
5577 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5578
5579 bp->attn_state = 0;
5580
5581 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5582 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5583 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5584 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5585 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5586 int sindex;
5587 /* take care of sig[0]..sig[4] */
5588 for (sindex = 0; sindex < 4; sindex++)
5589 bp->attn_group[index].sig[sindex] =
5590 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5591
5592 if (!CHIP_IS_E1x(bp))
5593 /*
5594 * enable5 is separate from the rest of the registers,
5595 * and therefore the address skip is 4
5596 * and not 16 between the different groups
5597 */
5598 bp->attn_group[index].sig[4] = REG_RD(bp,
5599 reg_offset_en5 + 0x4*index);
5600 else
5601 bp->attn_group[index].sig[4] = 0;
5602 }
5603
5604 if (bp->common.int_block == INT_BLOCK_HC) {
5605 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5606 HC_REG_ATTN_MSG0_ADDR_L);
5607
5608 REG_WR(bp, reg_offset, U64_LO(section));
5609 REG_WR(bp, reg_offset + 4, U64_HI(section));
5610 } else if (!CHIP_IS_E1x(bp)) {
5611 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5612 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5613 }
5614
5615 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5616 sp_sb);
5617
5618 bnx2x_zero_sp_sb(bp);
5619
5620 sp_sb_data.state = SB_ENABLED;
5621 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5622 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5623 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5624 sp_sb_data.igu_seg_id = igu_seg_id;
5625 sp_sb_data.p_func.pf_id = func;
5626 sp_sb_data.p_func.vnic_id = BP_VN(bp);
5627 sp_sb_data.p_func.vf_id = 0xff;
5628
5629 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5630
5631 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5632 }
5633
5634 void bnx2x_update_coalesce(struct bnx2x *bp)
5635 {
5636 int i;
5637
5638 for_each_eth_queue(bp, i)
5639 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5640 bp->tx_ticks, bp->rx_ticks);
5641 }
5642
5643 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5644 {
5645 spin_lock_init(&bp->spq_lock);
5646 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5647
5648 bp->spq_prod_idx = 0;
5649 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5650 bp->spq_prod_bd = bp->spq;
5651 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5652 }
5653
5654 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5655 {
5656 int i;
5657 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5658 union event_ring_elem *elem =
5659 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5660
5661 elem->next_page.addr.hi =
5662 cpu_to_le32(U64_HI(bp->eq_mapping +
5663 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5664 elem->next_page.addr.lo =
5665 cpu_to_le32(U64_LO(bp->eq_mapping +
5666 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5667 }
5668 bp->eq_cons = 0;
5669 bp->eq_prod = NUM_EQ_DESC;
5670 bp->eq_cons_sb = BNX2X_EQ_INDEX;
5671 /* we want a warning message before it gets rought... */
5672 atomic_set(&bp->eq_spq_left,
5673 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5674 }
5675
5676
5677 /* called with netif_addr_lock_bh() */
5678 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5679 unsigned long rx_mode_flags,
5680 unsigned long rx_accept_flags,
5681 unsigned long tx_accept_flags,
5682 unsigned long ramrod_flags)
5683 {
5684 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5685 int rc;
5686
5687 memset(&ramrod_param, 0, sizeof(ramrod_param));
5688
5689 /* Prepare ramrod parameters */
5690 ramrod_param.cid = 0;
5691 ramrod_param.cl_id = cl_id;
5692 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5693 ramrod_param.func_id = BP_FUNC(bp);
5694
5695 ramrod_param.pstate = &bp->sp_state;
5696 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5697
5698 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5699 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5700
5701 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5702
5703 ramrod_param.ramrod_flags = ramrod_flags;
5704 ramrod_param.rx_mode_flags = rx_mode_flags;
5705
5706 ramrod_param.rx_accept_flags = rx_accept_flags;
5707 ramrod_param.tx_accept_flags = tx_accept_flags;
5708
5709 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5710 if (rc < 0) {
5711 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5712 return;
5713 }
5714 }
5715
5716 /* called with netif_addr_lock_bh() */
5717 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5718 {
5719 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5720 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5721
5722 if (!NO_FCOE(bp))
5723
5724 /* Configure rx_mode of FCoE Queue */
5725 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5726
5727 switch (bp->rx_mode) {
5728 case BNX2X_RX_MODE_NONE:
5729 /*
5730 * 'drop all' supersedes any accept flags that may have been
5731 * passed to the function.
5732 */
5733 break;
5734 case BNX2X_RX_MODE_NORMAL:
5735 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5736 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5737 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5738
5739 /* internal switching mode */
5740 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5741 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5742 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5743
5744 break;
5745 case BNX2X_RX_MODE_ALLMULTI:
5746 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5747 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5748 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5749
5750 /* internal switching mode */
5751 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5752 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5753 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5754
5755 break;
5756 case BNX2X_RX_MODE_PROMISC:
5757 /* According to deffinition of SI mode, iface in promisc mode
5758 * should receive matched and unmatched (in resolution of port)
5759 * unicast packets.
5760 */
5761 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5762 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5763 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5764 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5765
5766 /* internal switching mode */
5767 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5768 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5769
5770 if (IS_MF_SI(bp))
5771 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5772 else
5773 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5774
5775 break;
5776 default:
5777 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5778 return;
5779 }
5780
5781 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5782 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5783 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
5784 }
5785
5786 __set_bit(RAMROD_RX, &ramrod_flags);
5787 __set_bit(RAMROD_TX, &ramrod_flags);
5788
5789 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5790 tx_accept_flags, ramrod_flags);
5791 }
5792
5793 static void bnx2x_init_internal_common(struct bnx2x *bp)
5794 {
5795 int i;
5796
5797 if (IS_MF_SI(bp))
5798 /*
5799 * In switch independent mode, the TSTORM needs to accept
5800 * packets that failed classification, since approximate match
5801 * mac addresses aren't written to NIG LLH
5802 */
5803 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5804 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5805 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5806 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5807 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5808
5809 /* Zero this manually as its initialization is
5810 currently missing in the initTool */
5811 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5812 REG_WR(bp, BAR_USTRORM_INTMEM +
5813 USTORM_AGG_DATA_OFFSET + i * 4, 0);
5814 if (!CHIP_IS_E1x(bp)) {
5815 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5816 CHIP_INT_MODE_IS_BC(bp) ?
5817 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5818 }
5819 }
5820
5821 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5822 {
5823 switch (load_code) {
5824 case FW_MSG_CODE_DRV_LOAD_COMMON:
5825 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5826 bnx2x_init_internal_common(bp);
5827 /* no break */
5828
5829 case FW_MSG_CODE_DRV_LOAD_PORT:
5830 /* nothing to do */
5831 /* no break */
5832
5833 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5834 /* internal memory per function is
5835 initialized inside bnx2x_pf_init */
5836 break;
5837
5838 default:
5839 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5840 break;
5841 }
5842 }
5843
5844 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5845 {
5846 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
5847 }
5848
5849 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5850 {
5851 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
5852 }
5853
5854 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5855 {
5856 if (CHIP_IS_E1x(fp->bp))
5857 return BP_L_ID(fp->bp) + fp->index;
5858 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5859 return bnx2x_fp_igu_sb_id(fp);
5860 }
5861
5862 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5863 {
5864 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5865 u8 cos;
5866 unsigned long q_type = 0;
5867 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
5868 fp->rx_queue = fp_idx;
5869 fp->cid = fp_idx;
5870 fp->cl_id = bnx2x_fp_cl_id(fp);
5871 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5872 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5873 /* qZone id equals to FW (per path) client id */
5874 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5875
5876 /* init shortcut */
5877 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5878
5879 /* Setup SB indicies */
5880 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5881
5882 /* Configure Queue State object */
5883 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5884 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5885
5886 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5887
5888 /* init tx data */
5889 for_each_cos_in_tx_queue(fp, cos) {
5890 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
5891 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
5892 FP_COS_TO_TXQ(fp, cos, bp),
5893 BNX2X_TX_SB_INDEX_BASE + cos, fp);
5894 cids[cos] = fp->txdata_ptr[cos]->cid;
5895 }
5896
5897 /* nothing more for vf to do here */
5898 if (IS_VF(bp))
5899 return;
5900
5901 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5902 fp->fw_sb_id, fp->igu_sb_id);
5903 bnx2x_update_fpsb_idx(fp);
5904 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
5905 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5906 bnx2x_sp_mapping(bp, q_rdata), q_type);
5907
5908 /**
5909 * Configure classification DBs: Always enable Tx switching
5910 */
5911 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5912
5913 DP(NETIF_MSG_IFUP,
5914 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
5915 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5916 fp->igu_sb_id);
5917 }
5918
5919 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
5920 {
5921 int i;
5922
5923 for (i = 1; i <= NUM_TX_RINGS; i++) {
5924 struct eth_tx_next_bd *tx_next_bd =
5925 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
5926
5927 tx_next_bd->addr_hi =
5928 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
5929 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5930 tx_next_bd->addr_lo =
5931 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
5932 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5933 }
5934
5935 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
5936 txdata->tx_db.data.zero_fill1 = 0;
5937 txdata->tx_db.data.prod = 0;
5938
5939 txdata->tx_pkt_prod = 0;
5940 txdata->tx_pkt_cons = 0;
5941 txdata->tx_bd_prod = 0;
5942 txdata->tx_bd_cons = 0;
5943 txdata->tx_pkt = 0;
5944 }
5945
5946 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
5947 {
5948 int i;
5949
5950 for_each_tx_queue_cnic(bp, i)
5951 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
5952 }
5953 static void bnx2x_init_tx_rings(struct bnx2x *bp)
5954 {
5955 int i;
5956 u8 cos;
5957
5958 for_each_eth_queue(bp, i)
5959 for_each_cos_in_tx_queue(&bp->fp[i], cos)
5960 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
5961 }
5962
5963 void bnx2x_nic_init_cnic(struct bnx2x *bp)
5964 {
5965 if (!NO_FCOE(bp))
5966 bnx2x_init_fcoe_fp(bp);
5967
5968 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5969 BNX2X_VF_ID_INVALID, false,
5970 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
5971
5972 /* ensure status block indices were read */
5973 rmb();
5974 bnx2x_init_rx_rings_cnic(bp);
5975 bnx2x_init_tx_rings_cnic(bp);
5976
5977 /* flush all */
5978 mb();
5979 mmiowb();
5980 }
5981
5982 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5983 {
5984 int i;
5985
5986 for_each_eth_queue(bp, i)
5987 bnx2x_init_eth_fp(bp, i);
5988
5989 /* ensure status block indices were read */
5990 rmb();
5991 bnx2x_init_rx_rings(bp);
5992 bnx2x_init_tx_rings(bp);
5993
5994 if (IS_VF(bp))
5995 return;
5996
5997 /* Initialize MOD_ABS interrupts */
5998 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5999 bp->common.shmem_base, bp->common.shmem2_base,
6000 BP_PORT(bp));
6001
6002 bnx2x_init_def_sb(bp);
6003 bnx2x_update_dsb_idx(bp);
6004 bnx2x_init_sp_ring(bp);
6005 bnx2x_init_eq_ring(bp);
6006 bnx2x_init_internal(bp, load_code);
6007 bnx2x_pf_init(bp);
6008 bnx2x_stats_init(bp);
6009
6010 /* flush all before enabling interrupts */
6011 mb();
6012 mmiowb();
6013
6014 bnx2x_int_enable(bp);
6015
6016 /* Check for SPIO5 */
6017 bnx2x_attn_int_deasserted0(bp,
6018 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6019 AEU_INPUTS_ATTN_BITS_SPIO5);
6020 }
6021
6022 /* end of nic init */
6023
6024 /*
6025 * gzip service functions
6026 */
6027
6028 static int bnx2x_gunzip_init(struct bnx2x *bp)
6029 {
6030 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6031 &bp->gunzip_mapping, GFP_KERNEL);
6032 if (bp->gunzip_buf == NULL)
6033 goto gunzip_nomem1;
6034
6035 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6036 if (bp->strm == NULL)
6037 goto gunzip_nomem2;
6038
6039 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6040 if (bp->strm->workspace == NULL)
6041 goto gunzip_nomem3;
6042
6043 return 0;
6044
6045 gunzip_nomem3:
6046 kfree(bp->strm);
6047 bp->strm = NULL;
6048
6049 gunzip_nomem2:
6050 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6051 bp->gunzip_mapping);
6052 bp->gunzip_buf = NULL;
6053
6054 gunzip_nomem1:
6055 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6056 return -ENOMEM;
6057 }
6058
6059 static void bnx2x_gunzip_end(struct bnx2x *bp)
6060 {
6061 if (bp->strm) {
6062 vfree(bp->strm->workspace);
6063 kfree(bp->strm);
6064 bp->strm = NULL;
6065 }
6066
6067 if (bp->gunzip_buf) {
6068 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6069 bp->gunzip_mapping);
6070 bp->gunzip_buf = NULL;
6071 }
6072 }
6073
6074 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6075 {
6076 int n, rc;
6077
6078 /* check gzip header */
6079 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6080 BNX2X_ERR("Bad gzip header\n");
6081 return -EINVAL;
6082 }
6083
6084 n = 10;
6085
6086 #define FNAME 0x8
6087
6088 if (zbuf[3] & FNAME)
6089 while ((zbuf[n++] != 0) && (n < len));
6090
6091 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6092 bp->strm->avail_in = len - n;
6093 bp->strm->next_out = bp->gunzip_buf;
6094 bp->strm->avail_out = FW_BUF_SIZE;
6095
6096 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6097 if (rc != Z_OK)
6098 return rc;
6099
6100 rc = zlib_inflate(bp->strm, Z_FINISH);
6101 if ((rc != Z_OK) && (rc != Z_STREAM_END))
6102 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6103 bp->strm->msg);
6104
6105 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6106 if (bp->gunzip_outlen & 0x3)
6107 netdev_err(bp->dev,
6108 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6109 bp->gunzip_outlen);
6110 bp->gunzip_outlen >>= 2;
6111
6112 zlib_inflateEnd(bp->strm);
6113
6114 if (rc == Z_STREAM_END)
6115 return 0;
6116
6117 return rc;
6118 }
6119
6120 /* nic load/unload */
6121
6122 /*
6123 * General service functions
6124 */
6125
6126 /* send a NIG loopback debug packet */
6127 static void bnx2x_lb_pckt(struct bnx2x *bp)
6128 {
6129 u32 wb_write[3];
6130
6131 /* Ethernet source and destination addresses */
6132 wb_write[0] = 0x55555555;
6133 wb_write[1] = 0x55555555;
6134 wb_write[2] = 0x20; /* SOP */
6135 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6136
6137 /* NON-IP protocol */
6138 wb_write[0] = 0x09000000;
6139 wb_write[1] = 0x55555555;
6140 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
6141 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6142 }
6143
6144 /* some of the internal memories
6145 * are not directly readable from the driver
6146 * to test them we send debug packets
6147 */
6148 static int bnx2x_int_mem_test(struct bnx2x *bp)
6149 {
6150 int factor;
6151 int count, i;
6152 u32 val = 0;
6153
6154 if (CHIP_REV_IS_FPGA(bp))
6155 factor = 120;
6156 else if (CHIP_REV_IS_EMUL(bp))
6157 factor = 200;
6158 else
6159 factor = 1;
6160
6161 /* Disable inputs of parser neighbor blocks */
6162 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6163 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6164 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6165 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6166
6167 /* Write 0 to parser credits for CFC search request */
6168 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6169
6170 /* send Ethernet packet */
6171 bnx2x_lb_pckt(bp);
6172
6173 /* TODO do i reset NIG statistic? */
6174 /* Wait until NIG register shows 1 packet of size 0x10 */
6175 count = 1000 * factor;
6176 while (count) {
6177
6178 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6179 val = *bnx2x_sp(bp, wb_data[0]);
6180 if (val == 0x10)
6181 break;
6182
6183 msleep(10);
6184 count--;
6185 }
6186 if (val != 0x10) {
6187 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6188 return -1;
6189 }
6190
6191 /* Wait until PRS register shows 1 packet */
6192 count = 1000 * factor;
6193 while (count) {
6194 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6195 if (val == 1)
6196 break;
6197
6198 msleep(10);
6199 count--;
6200 }
6201 if (val != 0x1) {
6202 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6203 return -2;
6204 }
6205
6206 /* Reset and init BRB, PRS */
6207 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6208 msleep(50);
6209 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6210 msleep(50);
6211 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6212 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6213
6214 DP(NETIF_MSG_HW, "part2\n");
6215
6216 /* Disable inputs of parser neighbor blocks */
6217 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6218 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6219 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6220 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6221
6222 /* Write 0 to parser credits for CFC search request */
6223 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6224
6225 /* send 10 Ethernet packets */
6226 for (i = 0; i < 10; i++)
6227 bnx2x_lb_pckt(bp);
6228
6229 /* Wait until NIG register shows 10 + 1
6230 packets of size 11*0x10 = 0xb0 */
6231 count = 1000 * factor;
6232 while (count) {
6233
6234 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6235 val = *bnx2x_sp(bp, wb_data[0]);
6236 if (val == 0xb0)
6237 break;
6238
6239 msleep(10);
6240 count--;
6241 }
6242 if (val != 0xb0) {
6243 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6244 return -3;
6245 }
6246
6247 /* Wait until PRS register shows 2 packets */
6248 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6249 if (val != 2)
6250 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6251
6252 /* Write 1 to parser credits for CFC search request */
6253 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6254
6255 /* Wait until PRS register shows 3 packets */
6256 msleep(10 * factor);
6257 /* Wait until NIG register shows 1 packet of size 0x10 */
6258 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6259 if (val != 3)
6260 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6261
6262 /* clear NIG EOP FIFO */
6263 for (i = 0; i < 11; i++)
6264 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6265 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6266 if (val != 1) {
6267 BNX2X_ERR("clear of NIG failed\n");
6268 return -4;
6269 }
6270
6271 /* Reset and init BRB, PRS, NIG */
6272 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6273 msleep(50);
6274 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6275 msleep(50);
6276 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6277 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6278 if (!CNIC_SUPPORT(bp))
6279 /* set NIC mode */
6280 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6281
6282 /* Enable inputs of parser neighbor blocks */
6283 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6284 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6285 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6286 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6287
6288 DP(NETIF_MSG_HW, "done\n");
6289
6290 return 0; /* OK */
6291 }
6292
6293 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6294 {
6295 u32 val;
6296
6297 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6298 if (!CHIP_IS_E1x(bp))
6299 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6300 else
6301 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6302 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6303 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6304 /*
6305 * mask read length error interrupts in brb for parser
6306 * (parsing unit and 'checksum and crc' unit)
6307 * these errors are legal (PU reads fixed length and CAC can cause
6308 * read length error on truncated packets)
6309 */
6310 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6311 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6312 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6313 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6314 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6315 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6316 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6317 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6318 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6319 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6320 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6321 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6322 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6323 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6324 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6325 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6326 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6327 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6328 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6329
6330 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
6331 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6332 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6333 if (!CHIP_IS_E1x(bp))
6334 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6335 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6336 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6337
6338 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6339 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6340 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6341 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6342
6343 if (!CHIP_IS_E1x(bp))
6344 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6345 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6346
6347 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6348 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6349 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6350 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
6351 }
6352
6353 static void bnx2x_reset_common(struct bnx2x *bp)
6354 {
6355 u32 val = 0x1400;
6356
6357 /* reset_common */
6358 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6359 0xd3ffff7f);
6360
6361 if (CHIP_IS_E3(bp)) {
6362 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6363 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6364 }
6365
6366 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6367 }
6368
6369 static void bnx2x_setup_dmae(struct bnx2x *bp)
6370 {
6371 bp->dmae_ready = 0;
6372 spin_lock_init(&bp->dmae_lock);
6373 }
6374
6375 static void bnx2x_init_pxp(struct bnx2x *bp)
6376 {
6377 u16 devctl;
6378 int r_order, w_order;
6379
6380 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6381 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6382 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6383 if (bp->mrrs == -1)
6384 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6385 else {
6386 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6387 r_order = bp->mrrs;
6388 }
6389
6390 bnx2x_init_pxp_arb(bp, r_order, w_order);
6391 }
6392
6393 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6394 {
6395 int is_required;
6396 u32 val;
6397 int port;
6398
6399 if (BP_NOMCP(bp))
6400 return;
6401
6402 is_required = 0;
6403 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6404 SHARED_HW_CFG_FAN_FAILURE_MASK;
6405
6406 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6407 is_required = 1;
6408
6409 /*
6410 * The fan failure mechanism is usually related to the PHY type since
6411 * the power consumption of the board is affected by the PHY. Currently,
6412 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6413 */
6414 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6415 for (port = PORT_0; port < PORT_MAX; port++) {
6416 is_required |=
6417 bnx2x_fan_failure_det_req(
6418 bp,
6419 bp->common.shmem_base,
6420 bp->common.shmem2_base,
6421 port);
6422 }
6423
6424 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6425
6426 if (is_required == 0)
6427 return;
6428
6429 /* Fan failure is indicated by SPIO 5 */
6430 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6431
6432 /* set to active low mode */
6433 val = REG_RD(bp, MISC_REG_SPIO_INT);
6434 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6435 REG_WR(bp, MISC_REG_SPIO_INT, val);
6436
6437 /* enable interrupt to signal the IGU */
6438 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6439 val |= MISC_SPIO_SPIO5;
6440 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6441 }
6442
6443 void bnx2x_pf_disable(struct bnx2x *bp)
6444 {
6445 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6446 val &= ~IGU_PF_CONF_FUNC_EN;
6447
6448 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6449 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6450 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6451 }
6452
6453 static void bnx2x__common_init_phy(struct bnx2x *bp)
6454 {
6455 u32 shmem_base[2], shmem2_base[2];
6456 /* Avoid common init in case MFW supports LFA */
6457 if (SHMEM2_RD(bp, size) >
6458 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6459 return;
6460 shmem_base[0] = bp->common.shmem_base;
6461 shmem2_base[0] = bp->common.shmem2_base;
6462 if (!CHIP_IS_E1x(bp)) {
6463 shmem_base[1] =
6464 SHMEM2_RD(bp, other_shmem_base_addr);
6465 shmem2_base[1] =
6466 SHMEM2_RD(bp, other_shmem2_base_addr);
6467 }
6468 bnx2x_acquire_phy_lock(bp);
6469 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6470 bp->common.chip_id);
6471 bnx2x_release_phy_lock(bp);
6472 }
6473
6474 /**
6475 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6476 *
6477 * @bp: driver handle
6478 */
6479 static int bnx2x_init_hw_common(struct bnx2x *bp)
6480 {
6481 u32 val;
6482
6483 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
6484
6485 /*
6486 * take the RESET lock to protect undi_unload flow from accessing
6487 * registers while we're resetting the chip
6488 */
6489 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6490
6491 bnx2x_reset_common(bp);
6492 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6493
6494 val = 0xfffc;
6495 if (CHIP_IS_E3(bp)) {
6496 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6497 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6498 }
6499 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6500
6501 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6502
6503 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6504
6505 if (!CHIP_IS_E1x(bp)) {
6506 u8 abs_func_id;
6507
6508 /**
6509 * 4-port mode or 2-port mode we need to turn of master-enable
6510 * for everyone, after that, turn it back on for self.
6511 * so, we disregard multi-function or not, and always disable
6512 * for all functions on the given path, this means 0,2,4,6 for
6513 * path 0 and 1,3,5,7 for path 1
6514 */
6515 for (abs_func_id = BP_PATH(bp);
6516 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6517 if (abs_func_id == BP_ABS_FUNC(bp)) {
6518 REG_WR(bp,
6519 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6520 1);
6521 continue;
6522 }
6523
6524 bnx2x_pretend_func(bp, abs_func_id);
6525 /* clear pf enable */
6526 bnx2x_pf_disable(bp);
6527 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6528 }
6529 }
6530
6531 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6532 if (CHIP_IS_E1(bp)) {
6533 /* enable HW interrupt from PXP on USDM overflow
6534 bit 16 on INT_MASK_0 */
6535 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6536 }
6537
6538 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6539 bnx2x_init_pxp(bp);
6540
6541 #ifdef __BIG_ENDIAN
6542 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6543 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6544 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6545 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6546 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6547 /* make sure this value is 0 */
6548 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6549
6550 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6551 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6552 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6553 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6554 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6555 #endif
6556
6557 bnx2x_ilt_init_page_size(bp, INITOP_SET);
6558
6559 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6560 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6561
6562 /* let the HW do it's magic ... */
6563 msleep(100);
6564 /* finish PXP init */
6565 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6566 if (val != 1) {
6567 BNX2X_ERR("PXP2 CFG failed\n");
6568 return -EBUSY;
6569 }
6570 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6571 if (val != 1) {
6572 BNX2X_ERR("PXP2 RD_INIT failed\n");
6573 return -EBUSY;
6574 }
6575
6576 /* Timers bug workaround E2 only. We need to set the entire ILT to
6577 * have entries with value "0" and valid bit on.
6578 * This needs to be done by the first PF that is loaded in a path
6579 * (i.e. common phase)
6580 */
6581 if (!CHIP_IS_E1x(bp)) {
6582 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6583 * (i.e. vnic3) to start even if it is marked as "scan-off".
6584 * This occurs when a different function (func2,3) is being marked
6585 * as "scan-off". Real-life scenario for example: if a driver is being
6586 * load-unloaded while func6,7 are down. This will cause the timer to access
6587 * the ilt, translate to a logical address and send a request to read/write.
6588 * Since the ilt for the function that is down is not valid, this will cause
6589 * a translation error which is unrecoverable.
6590 * The Workaround is intended to make sure that when this happens nothing fatal
6591 * will occur. The workaround:
6592 * 1. First PF driver which loads on a path will:
6593 * a. After taking the chip out of reset, by using pretend,
6594 * it will write "0" to the following registers of
6595 * the other vnics.
6596 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6597 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6598 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6599 * And for itself it will write '1' to
6600 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6601 * dmae-operations (writing to pram for example.)
6602 * note: can be done for only function 6,7 but cleaner this
6603 * way.
6604 * b. Write zero+valid to the entire ILT.
6605 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6606 * VNIC3 (of that port). The range allocated will be the
6607 * entire ILT. This is needed to prevent ILT range error.
6608 * 2. Any PF driver load flow:
6609 * a. ILT update with the physical addresses of the allocated
6610 * logical pages.
6611 * b. Wait 20msec. - note that this timeout is needed to make
6612 * sure there are no requests in one of the PXP internal
6613 * queues with "old" ILT addresses.
6614 * c. PF enable in the PGLC.
6615 * d. Clear the was_error of the PF in the PGLC. (could have
6616 * occurred while driver was down)
6617 * e. PF enable in the CFC (WEAK + STRONG)
6618 * f. Timers scan enable
6619 * 3. PF driver unload flow:
6620 * a. Clear the Timers scan_en.
6621 * b. Polling for scan_on=0 for that PF.
6622 * c. Clear the PF enable bit in the PXP.
6623 * d. Clear the PF enable in the CFC (WEAK + STRONG)
6624 * e. Write zero+valid to all ILT entries (The valid bit must
6625 * stay set)
6626 * f. If this is VNIC 3 of a port then also init
6627 * first_timers_ilt_entry to zero and last_timers_ilt_entry
6628 * to the last enrty in the ILT.
6629 *
6630 * Notes:
6631 * Currently the PF error in the PGLC is non recoverable.
6632 * In the future the there will be a recovery routine for this error.
6633 * Currently attention is masked.
6634 * Having an MCP lock on the load/unload process does not guarantee that
6635 * there is no Timer disable during Func6/7 enable. This is because the
6636 * Timers scan is currently being cleared by the MCP on FLR.
6637 * Step 2.d can be done only for PF6/7 and the driver can also check if
6638 * there is error before clearing it. But the flow above is simpler and
6639 * more general.
6640 * All ILT entries are written by zero+valid and not just PF6/7
6641 * ILT entries since in the future the ILT entries allocation for
6642 * PF-s might be dynamic.
6643 */
6644 struct ilt_client_info ilt_cli;
6645 struct bnx2x_ilt ilt;
6646 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6647 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6648
6649 /* initialize dummy TM client */
6650 ilt_cli.start = 0;
6651 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6652 ilt_cli.client_num = ILT_CLIENT_TM;
6653
6654 /* Step 1: set zeroes to all ilt page entries with valid bit on
6655 * Step 2: set the timers first/last ilt entry to point
6656 * to the entire range to prevent ILT range error for 3rd/4th
6657 * vnic (this code assumes existence of the vnic)
6658 *
6659 * both steps performed by call to bnx2x_ilt_client_init_op()
6660 * with dummy TM client
6661 *
6662 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6663 * and his brother are split registers
6664 */
6665 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6666 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6667 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6668
6669 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6670 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6671 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6672 }
6673
6674 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6675 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6676
6677 if (!CHIP_IS_E1x(bp)) {
6678 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6679 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6680 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6681
6682 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6683
6684 /* let the HW do it's magic ... */
6685 do {
6686 msleep(200);
6687 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6688 } while (factor-- && (val != 1));
6689
6690 if (val != 1) {
6691 BNX2X_ERR("ATC_INIT failed\n");
6692 return -EBUSY;
6693 }
6694 }
6695
6696 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6697
6698 bnx2x_iov_init_dmae(bp);
6699
6700 /* clean the DMAE memory */
6701 bp->dmae_ready = 1;
6702 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6703
6704 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6705
6706 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6707
6708 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6709
6710 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6711
6712 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6713 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6714 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6715 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6716
6717 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6718
6719
6720 /* QM queues pointers table */
6721 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6722
6723 /* soft reset pulse */
6724 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6725 REG_WR(bp, QM_REG_SOFT_RESET, 0);
6726
6727 if (CNIC_SUPPORT(bp))
6728 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6729
6730 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6731 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
6732 if (!CHIP_REV_IS_SLOW(bp))
6733 /* enable hw interrupt from doorbell Q */
6734 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6735
6736 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6737
6738 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6739 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6740
6741 if (!CHIP_IS_E1(bp))
6742 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6743
6744 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6745 if (IS_MF_AFEX(bp)) {
6746 /* configure that VNTag and VLAN headers must be
6747 * received in afex mode
6748 */
6749 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6750 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6751 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6752 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6753 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6754 } else {
6755 /* Bit-map indicating which L2 hdrs may appear
6756 * after the basic Ethernet header
6757 */
6758 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6759 bp->path_has_ovlan ? 7 : 6);
6760 }
6761 }
6762
6763 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6764 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6765 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6766 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6767
6768 if (!CHIP_IS_E1x(bp)) {
6769 /* reset VFC memories */
6770 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6771 VFC_MEMORIES_RST_REG_CAM_RST |
6772 VFC_MEMORIES_RST_REG_RAM_RST);
6773 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6774 VFC_MEMORIES_RST_REG_CAM_RST |
6775 VFC_MEMORIES_RST_REG_RAM_RST);
6776
6777 msleep(20);
6778 }
6779
6780 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6781 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6782 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6783 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6784
6785 /* sync semi rtc */
6786 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6787 0x80000000);
6788 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6789 0x80000000);
6790
6791 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6792 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6793 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6794
6795 if (!CHIP_IS_E1x(bp)) {
6796 if (IS_MF_AFEX(bp)) {
6797 /* configure that VNTag and VLAN headers must be
6798 * sent in afex mode
6799 */
6800 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
6801 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
6802 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
6803 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
6804 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
6805 } else {
6806 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6807 bp->path_has_ovlan ? 7 : 6);
6808 }
6809 }
6810
6811 REG_WR(bp, SRC_REG_SOFT_RST, 1);
6812
6813 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6814
6815 if (CNIC_SUPPORT(bp)) {
6816 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6817 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6818 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6819 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6820 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6821 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6822 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6823 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6824 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6825 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6826 }
6827 REG_WR(bp, SRC_REG_SOFT_RST, 0);
6828
6829 if (sizeof(union cdu_context) != 1024)
6830 /* we currently assume that a context is 1024 bytes */
6831 dev_alert(&bp->pdev->dev,
6832 "please adjust the size of cdu_context(%ld)\n",
6833 (long)sizeof(union cdu_context));
6834
6835 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6836 val = (4 << 24) + (0 << 12) + 1024;
6837 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6838
6839 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6840 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6841 /* enable context validation interrupt from CFC */
6842 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6843
6844 /* set the thresholds to prevent CFC/CDU race */
6845 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6846
6847 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6848
6849 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6850 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6851
6852 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6853 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
6854
6855 /* Reset PCIE errors for debug */
6856 REG_WR(bp, 0x2814, 0xffffffff);
6857 REG_WR(bp, 0x3820, 0xffffffff);
6858
6859 if (!CHIP_IS_E1x(bp)) {
6860 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6861 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6862 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6863 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6864 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6865 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6866 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6867 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6868 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6869 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6870 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6871 }
6872
6873 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
6874 if (!CHIP_IS_E1(bp)) {
6875 /* in E3 this done in per-port section */
6876 if (!CHIP_IS_E3(bp))
6877 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
6878 }
6879 if (CHIP_IS_E1H(bp))
6880 /* not applicable for E2 (and above ...) */
6881 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
6882
6883 if (CHIP_REV_IS_SLOW(bp))
6884 msleep(200);
6885
6886 /* finish CFC init */
6887 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6888 if (val != 1) {
6889 BNX2X_ERR("CFC LL_INIT failed\n");
6890 return -EBUSY;
6891 }
6892 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6893 if (val != 1) {
6894 BNX2X_ERR("CFC AC_INIT failed\n");
6895 return -EBUSY;
6896 }
6897 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6898 if (val != 1) {
6899 BNX2X_ERR("CFC CAM_INIT failed\n");
6900 return -EBUSY;
6901 }
6902 REG_WR(bp, CFC_REG_DEBUG0, 0);
6903
6904 if (CHIP_IS_E1(bp)) {
6905 /* read NIG statistic
6906 to see if this is our first up since powerup */
6907 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6908 val = *bnx2x_sp(bp, wb_data[0]);
6909
6910 /* do internal memory self test */
6911 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6912 BNX2X_ERR("internal mem self test failed\n");
6913 return -EBUSY;
6914 }
6915 }
6916
6917 bnx2x_setup_fan_failure_detection(bp);
6918
6919 /* clear PXP2 attentions */
6920 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6921
6922 bnx2x_enable_blocks_attention(bp);
6923 bnx2x_enable_blocks_parity(bp);
6924
6925 if (!BP_NOMCP(bp)) {
6926 if (CHIP_IS_E1x(bp))
6927 bnx2x__common_init_phy(bp);
6928 } else
6929 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6930
6931 return 0;
6932 }
6933
6934 /**
6935 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6936 *
6937 * @bp: driver handle
6938 */
6939 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6940 {
6941 int rc = bnx2x_init_hw_common(bp);
6942
6943 if (rc)
6944 return rc;
6945
6946 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6947 if (!BP_NOMCP(bp))
6948 bnx2x__common_init_phy(bp);
6949
6950 return 0;
6951 }
6952
6953 static int bnx2x_init_hw_port(struct bnx2x *bp)
6954 {
6955 int port = BP_PORT(bp);
6956 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
6957 u32 low, high;
6958 u32 val;
6959
6960
6961 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
6962
6963 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6964
6965 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6966 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6967 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6968
6969 /* Timers bug workaround: disables the pf_master bit in pglue at
6970 * common phase, we need to enable it here before any dmae access are
6971 * attempted. Therefore we manually added the enable-master to the
6972 * port phase (it also happens in the function phase)
6973 */
6974 if (!CHIP_IS_E1x(bp))
6975 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6976
6977 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6978 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6979 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6980 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6981
6982 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6983 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6984 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6985 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6986
6987 /* QM cid (connection) count */
6988 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
6989
6990 if (CNIC_SUPPORT(bp)) {
6991 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6992 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6993 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
6994 }
6995
6996 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6997
6998 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6999
7000 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7001
7002 if (IS_MF(bp))
7003 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7004 else if (bp->dev->mtu > 4096) {
7005 if (bp->flags & ONE_PORT_FLAG)
7006 low = 160;
7007 else {
7008 val = bp->dev->mtu;
7009 /* (24*1024 + val*4)/256 */
7010 low = 96 + (val/64) +
7011 ((val % 64) ? 1 : 0);
7012 }
7013 } else
7014 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7015 high = low + 56; /* 14*1024/256 */
7016 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7017 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7018 }
7019
7020 if (CHIP_MODE_IS_4_PORT(bp))
7021 REG_WR(bp, (BP_PORT(bp) ?
7022 BRB1_REG_MAC_GUARANTIED_1 :
7023 BRB1_REG_MAC_GUARANTIED_0), 40);
7024
7025
7026 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7027 if (CHIP_IS_E3B0(bp)) {
7028 if (IS_MF_AFEX(bp)) {
7029 /* configure headers for AFEX mode */
7030 REG_WR(bp, BP_PORT(bp) ?
7031 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7032 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7033 REG_WR(bp, BP_PORT(bp) ?
7034 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7035 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7036 REG_WR(bp, BP_PORT(bp) ?
7037 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7038 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7039 } else {
7040 /* Ovlan exists only if we are in multi-function +
7041 * switch-dependent mode, in switch-independent there
7042 * is no ovlan headers
7043 */
7044 REG_WR(bp, BP_PORT(bp) ?
7045 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7046 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7047 (bp->path_has_ovlan ? 7 : 6));
7048 }
7049 }
7050
7051 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7052 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7053 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7054 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7055
7056 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7057 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7058 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7059 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7060
7061 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7062 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7063
7064 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7065
7066 if (CHIP_IS_E1x(bp)) {
7067 /* configure PBF to work without PAUSE mtu 9000 */
7068 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7069
7070 /* update threshold */
7071 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7072 /* update init credit */
7073 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7074
7075 /* probe changes */
7076 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7077 udelay(50);
7078 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7079 }
7080
7081 if (CNIC_SUPPORT(bp))
7082 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7083
7084 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7085 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7086
7087 if (CHIP_IS_E1(bp)) {
7088 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7089 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7090 }
7091 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7092
7093 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7094
7095 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7096 /* init aeu_mask_attn_func_0/1:
7097 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
7098 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
7099 * bits 4-7 are used for "per vn group attention" */
7100 val = IS_MF(bp) ? 0xF7 : 0x7;
7101 /* Enable DCBX attention for all but E1 */
7102 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7103 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7104
7105 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7106
7107 if (!CHIP_IS_E1x(bp)) {
7108 /* Bit-map indicating which L2 hdrs may appear after the
7109 * basic Ethernet header
7110 */
7111 if (IS_MF_AFEX(bp))
7112 REG_WR(bp, BP_PORT(bp) ?
7113 NIG_REG_P1_HDRS_AFTER_BASIC :
7114 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7115 else
7116 REG_WR(bp, BP_PORT(bp) ?
7117 NIG_REG_P1_HDRS_AFTER_BASIC :
7118 NIG_REG_P0_HDRS_AFTER_BASIC,
7119 IS_MF_SD(bp) ? 7 : 6);
7120
7121 if (CHIP_IS_E3(bp))
7122 REG_WR(bp, BP_PORT(bp) ?
7123 NIG_REG_LLH1_MF_MODE :
7124 NIG_REG_LLH_MF_MODE, IS_MF(bp));
7125 }
7126 if (!CHIP_IS_E3(bp))
7127 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7128
7129 if (!CHIP_IS_E1(bp)) {
7130 /* 0x2 disable mf_ov, 0x1 enable */
7131 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7132 (IS_MF_SD(bp) ? 0x1 : 0x2));
7133
7134 if (!CHIP_IS_E1x(bp)) {
7135 val = 0;
7136 switch (bp->mf_mode) {
7137 case MULTI_FUNCTION_SD:
7138 val = 1;
7139 break;
7140 case MULTI_FUNCTION_SI:
7141 case MULTI_FUNCTION_AFEX:
7142 val = 2;
7143 break;
7144 }
7145
7146 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7147 NIG_REG_LLH0_CLS_TYPE), val);
7148 }
7149 {
7150 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7151 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7152 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7153 }
7154 }
7155
7156 /* If SPIO5 is set to generate interrupts, enable it for this port */
7157 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7158 if (val & MISC_SPIO_SPIO5) {
7159 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7160 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7161 val = REG_RD(bp, reg_addr);
7162 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7163 REG_WR(bp, reg_addr, val);
7164 }
7165
7166 return 0;
7167 }
7168
7169 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7170 {
7171 int reg;
7172 u32 wb_write[2];
7173
7174 if (CHIP_IS_E1(bp))
7175 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7176 else
7177 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7178
7179 wb_write[0] = ONCHIP_ADDR1(addr);
7180 wb_write[1] = ONCHIP_ADDR2(addr);
7181 REG_WR_DMAE(bp, reg, wb_write, 2);
7182 }
7183
7184 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7185 {
7186 u32 data, ctl, cnt = 100;
7187 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7188 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7189 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7190 u32 sb_bit = 1 << (idu_sb_id%32);
7191 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7192 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7193
7194 /* Not supported in BC mode */
7195 if (CHIP_INT_MODE_IS_BC(bp))
7196 return;
7197
7198 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7199 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7200 IGU_REGULAR_CLEANUP_SET |
7201 IGU_REGULAR_BCLEANUP;
7202
7203 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7204 func_encode << IGU_CTRL_REG_FID_SHIFT |
7205 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7206
7207 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7208 data, igu_addr_data);
7209 REG_WR(bp, igu_addr_data, data);
7210 mmiowb();
7211 barrier();
7212 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7213 ctl, igu_addr_ctl);
7214 REG_WR(bp, igu_addr_ctl, ctl);
7215 mmiowb();
7216 barrier();
7217
7218 /* wait for clean up to finish */
7219 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7220 msleep(20);
7221
7222
7223 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7224 DP(NETIF_MSG_HW,
7225 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7226 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7227 }
7228 }
7229
7230 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7231 {
7232 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7233 }
7234
7235 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7236 {
7237 u32 i, base = FUNC_ILT_BASE(func);
7238 for (i = base; i < base + ILT_PER_FUNC; i++)
7239 bnx2x_ilt_wr(bp, i, 0);
7240 }
7241
7242
7243 static void bnx2x_init_searcher(struct bnx2x *bp)
7244 {
7245 int port = BP_PORT(bp);
7246 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7247 /* T1 hash bits value determines the T1 number of entries */
7248 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7249 }
7250
7251 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7252 {
7253 int rc;
7254 struct bnx2x_func_state_params func_params = {NULL};
7255 struct bnx2x_func_switch_update_params *switch_update_params =
7256 &func_params.params.switch_update;
7257
7258 /* Prepare parameters for function state transitions */
7259 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7260 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7261
7262 func_params.f_obj = &bp->func_obj;
7263 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7264
7265 /* Function parameters */
7266 switch_update_params->suspend = suspend;
7267
7268 rc = bnx2x_func_state_change(bp, &func_params);
7269
7270 return rc;
7271 }
7272
7273 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7274 {
7275 int rc, i, port = BP_PORT(bp);
7276 int vlan_en = 0, mac_en[NUM_MACS];
7277
7278
7279 /* Close input from network */
7280 if (bp->mf_mode == SINGLE_FUNCTION) {
7281 bnx2x_set_rx_filter(&bp->link_params, 0);
7282 } else {
7283 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7284 NIG_REG_LLH0_FUNC_EN);
7285 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7286 NIG_REG_LLH0_FUNC_EN, 0);
7287 for (i = 0; i < NUM_MACS; i++) {
7288 mac_en[i] = REG_RD(bp, port ?
7289 (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7290 4 * i) :
7291 (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7292 4 * i));
7293 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7294 4 * i) :
7295 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7296 }
7297 }
7298
7299 /* Close BMC to host */
7300 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7301 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7302
7303 /* Suspend Tx switching to the PF. Completion of this ramrod
7304 * further guarantees that all the packets of that PF / child
7305 * VFs in BRB were processed by the Parser, so it is safe to
7306 * change the NIC_MODE register.
7307 */
7308 rc = bnx2x_func_switch_update(bp, 1);
7309 if (rc) {
7310 BNX2X_ERR("Can't suspend tx-switching!\n");
7311 return rc;
7312 }
7313
7314 /* Change NIC_MODE register */
7315 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7316
7317 /* Open input from network */
7318 if (bp->mf_mode == SINGLE_FUNCTION) {
7319 bnx2x_set_rx_filter(&bp->link_params, 1);
7320 } else {
7321 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7322 NIG_REG_LLH0_FUNC_EN, vlan_en);
7323 for (i = 0; i < NUM_MACS; i++) {
7324 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7325 4 * i) :
7326 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7327 mac_en[i]);
7328 }
7329 }
7330
7331 /* Enable BMC to host */
7332 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7333 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7334
7335 /* Resume Tx switching to the PF */
7336 rc = bnx2x_func_switch_update(bp, 0);
7337 if (rc) {
7338 BNX2X_ERR("Can't resume tx-switching!\n");
7339 return rc;
7340 }
7341
7342 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7343 return 0;
7344 }
7345
7346 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7347 {
7348 int rc;
7349
7350 bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7351
7352 if (CONFIGURE_NIC_MODE(bp)) {
7353 /* Configrue searcher as part of function hw init */
7354 bnx2x_init_searcher(bp);
7355
7356 /* Reset NIC mode */
7357 rc = bnx2x_reset_nic_mode(bp);
7358 if (rc)
7359 BNX2X_ERR("Can't change NIC mode!\n");
7360 return rc;
7361 }
7362
7363 return 0;
7364 }
7365
7366 static int bnx2x_init_hw_func(struct bnx2x *bp)
7367 {
7368 int port = BP_PORT(bp);
7369 int func = BP_FUNC(bp);
7370 int init_phase = PHASE_PF0 + func;
7371 struct bnx2x_ilt *ilt = BP_ILT(bp);
7372 u16 cdu_ilt_start;
7373 u32 addr, val;
7374 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7375 int i, main_mem_width, rc;
7376
7377 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
7378
7379 /* FLR cleanup - hmmm */
7380 if (!CHIP_IS_E1x(bp)) {
7381 rc = bnx2x_pf_flr_clnup(bp);
7382 if (rc)
7383 return rc;
7384 }
7385
7386 /* set MSI reconfigure capability */
7387 if (bp->common.int_block == INT_BLOCK_HC) {
7388 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7389 val = REG_RD(bp, addr);
7390 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7391 REG_WR(bp, addr, val);
7392 }
7393
7394 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7395 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7396
7397 ilt = BP_ILT(bp);
7398 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7399
7400 if (IS_SRIOV(bp))
7401 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7402 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7403
7404 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7405 * those of the VFs, so start line should be reset
7406 */
7407 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7408 for (i = 0; i < L2_ILT_LINES(bp); i++) {
7409 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7410 ilt->lines[cdu_ilt_start + i].page_mapping =
7411 bp->context[i].cxt_mapping;
7412 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7413 }
7414
7415 bnx2x_ilt_init_op(bp, INITOP_SET);
7416
7417 if (!CONFIGURE_NIC_MODE(bp)) {
7418 bnx2x_init_searcher(bp);
7419 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7420 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7421 } else {
7422 /* Set NIC mode */
7423 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7424 DP(NETIF_MSG_IFUP, "NIC MODE configrued\n");
7425
7426 }
7427
7428 if (!CHIP_IS_E1x(bp)) {
7429 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7430
7431 /* Turn on a single ISR mode in IGU if driver is going to use
7432 * INT#x or MSI
7433 */
7434 if (!(bp->flags & USING_MSIX_FLAG))
7435 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7436 /*
7437 * Timers workaround bug: function init part.
7438 * Need to wait 20msec after initializing ILT,
7439 * needed to make sure there are no requests in
7440 * one of the PXP internal queues with "old" ILT addresses
7441 */
7442 msleep(20);
7443 /*
7444 * Master enable - Due to WB DMAE writes performed before this
7445 * register is re-initialized as part of the regular function
7446 * init
7447 */
7448 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7449 /* Enable the function in IGU */
7450 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7451 }
7452
7453 bp->dmae_ready = 1;
7454
7455 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7456
7457 if (!CHIP_IS_E1x(bp))
7458 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7459
7460 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7461 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7462 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7463 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7464 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7465 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7466 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7467 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7468 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7469 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7470 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7471 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7472 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7473
7474 if (!CHIP_IS_E1x(bp))
7475 REG_WR(bp, QM_REG_PF_EN, 1);
7476
7477 if (!CHIP_IS_E1x(bp)) {
7478 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7479 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7480 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7481 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7482 }
7483 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7484
7485 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7486 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7487
7488 bnx2x_iov_init_dq(bp);
7489
7490 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7491 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7492 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7493 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7494 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7495 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7496 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7497 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7498 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7499 if (!CHIP_IS_E1x(bp))
7500 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7501
7502 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7503
7504 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7505
7506 if (!CHIP_IS_E1x(bp))
7507 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7508
7509 if (IS_MF(bp)) {
7510 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7511 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7512 }
7513
7514 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7515
7516 /* HC init per function */
7517 if (bp->common.int_block == INT_BLOCK_HC) {
7518 if (CHIP_IS_E1H(bp)) {
7519 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7520
7521 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7522 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7523 }
7524 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7525
7526 } else {
7527 int num_segs, sb_idx, prod_offset;
7528
7529 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7530
7531 if (!CHIP_IS_E1x(bp)) {
7532 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7533 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7534 }
7535
7536 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7537
7538 if (!CHIP_IS_E1x(bp)) {
7539 int dsb_idx = 0;
7540 /**
7541 * Producer memory:
7542 * E2 mode: address 0-135 match to the mapping memory;
7543 * 136 - PF0 default prod; 137 - PF1 default prod;
7544 * 138 - PF2 default prod; 139 - PF3 default prod;
7545 * 140 - PF0 attn prod; 141 - PF1 attn prod;
7546 * 142 - PF2 attn prod; 143 - PF3 attn prod;
7547 * 144-147 reserved.
7548 *
7549 * E1.5 mode - In backward compatible mode;
7550 * for non default SB; each even line in the memory
7551 * holds the U producer and each odd line hold
7552 * the C producer. The first 128 producers are for
7553 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7554 * producers are for the DSB for each PF.
7555 * Each PF has five segments: (the order inside each
7556 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7557 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7558 * 144-147 attn prods;
7559 */
7560 /* non-default-status-blocks */
7561 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7562 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7563 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7564 prod_offset = (bp->igu_base_sb + sb_idx) *
7565 num_segs;
7566
7567 for (i = 0; i < num_segs; i++) {
7568 addr = IGU_REG_PROD_CONS_MEMORY +
7569 (prod_offset + i) * 4;
7570 REG_WR(bp, addr, 0);
7571 }
7572 /* send consumer update with value 0 */
7573 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7574 USTORM_ID, 0, IGU_INT_NOP, 1);
7575 bnx2x_igu_clear_sb(bp,
7576 bp->igu_base_sb + sb_idx);
7577 }
7578
7579 /* default-status-blocks */
7580 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7581 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7582
7583 if (CHIP_MODE_IS_4_PORT(bp))
7584 dsb_idx = BP_FUNC(bp);
7585 else
7586 dsb_idx = BP_VN(bp);
7587
7588 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7589 IGU_BC_BASE_DSB_PROD + dsb_idx :
7590 IGU_NORM_BASE_DSB_PROD + dsb_idx);
7591
7592 /*
7593 * igu prods come in chunks of E1HVN_MAX (4) -
7594 * does not matters what is the current chip mode
7595 */
7596 for (i = 0; i < (num_segs * E1HVN_MAX);
7597 i += E1HVN_MAX) {
7598 addr = IGU_REG_PROD_CONS_MEMORY +
7599 (prod_offset + i)*4;
7600 REG_WR(bp, addr, 0);
7601 }
7602 /* send consumer update with 0 */
7603 if (CHIP_INT_MODE_IS_BC(bp)) {
7604 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7605 USTORM_ID, 0, IGU_INT_NOP, 1);
7606 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7607 CSTORM_ID, 0, IGU_INT_NOP, 1);
7608 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7609 XSTORM_ID, 0, IGU_INT_NOP, 1);
7610 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7611 TSTORM_ID, 0, IGU_INT_NOP, 1);
7612 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7613 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7614 } else {
7615 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7616 USTORM_ID, 0, IGU_INT_NOP, 1);
7617 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7618 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7619 }
7620 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7621
7622 /* !!! these should become driver const once
7623 rf-tool supports split-68 const */
7624 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7625 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7626 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7627 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7628 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7629 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7630 }
7631 }
7632
7633 /* Reset PCIE errors for debug */
7634 REG_WR(bp, 0x2114, 0xffffffff);
7635 REG_WR(bp, 0x2120, 0xffffffff);
7636
7637 if (CHIP_IS_E1x(bp)) {
7638 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7639 main_mem_base = HC_REG_MAIN_MEMORY +
7640 BP_PORT(bp) * (main_mem_size * 4);
7641 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7642 main_mem_width = 8;
7643
7644 val = REG_RD(bp, main_mem_prty_clr);
7645 if (val)
7646 DP(NETIF_MSG_HW,
7647 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7648 val);
7649
7650 /* Clear "false" parity errors in MSI-X table */
7651 for (i = main_mem_base;
7652 i < main_mem_base + main_mem_size * 4;
7653 i += main_mem_width) {
7654 bnx2x_read_dmae(bp, i, main_mem_width / 4);
7655 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7656 i, main_mem_width / 4);
7657 }
7658 /* Clear HC parity attention */
7659 REG_RD(bp, main_mem_prty_clr);
7660 }
7661
7662 #ifdef BNX2X_STOP_ON_ERROR
7663 /* Enable STORMs SP logging */
7664 REG_WR8(bp, BAR_USTRORM_INTMEM +
7665 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7666 REG_WR8(bp, BAR_TSTRORM_INTMEM +
7667 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7668 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7669 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7670 REG_WR8(bp, BAR_XSTRORM_INTMEM +
7671 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7672 #endif
7673
7674 bnx2x_phy_probe(&bp->link_params);
7675
7676 return 0;
7677 }
7678
7679
7680 void bnx2x_free_mem_cnic(struct bnx2x *bp)
7681 {
7682 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
7683
7684 if (!CHIP_IS_E1x(bp))
7685 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7686 sizeof(struct host_hc_status_block_e2));
7687 else
7688 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7689 sizeof(struct host_hc_status_block_e1x));
7690
7691 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7692 }
7693
7694 void bnx2x_free_mem(struct bnx2x *bp)
7695 {
7696 int i;
7697
7698 /* fastpath */
7699 bnx2x_free_fp_mem(bp);
7700 /* end of fastpath */
7701
7702 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
7703 sizeof(struct host_sp_status_block));
7704
7705 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7706 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7707
7708 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
7709 sizeof(struct bnx2x_slowpath));
7710
7711 for (i = 0; i < L2_ILT_LINES(bp); i++)
7712 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7713 bp->context[i].size);
7714 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7715
7716 BNX2X_FREE(bp->ilt->lines);
7717
7718 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
7719
7720 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7721 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7722 }
7723
7724
7725 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
7726 {
7727 if (!CHIP_IS_E1x(bp))
7728 /* size = the status block + ramrod buffers */
7729 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7730 sizeof(struct host_hc_status_block_e2));
7731 else
7732 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb,
7733 &bp->cnic_sb_mapping,
7734 sizeof(struct
7735 host_hc_status_block_e1x));
7736
7737 if (CONFIGURE_NIC_MODE(bp))
7738 /* allocate searcher T2 table, as it wan't allocated before */
7739 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7740
7741 /* write address to which L5 should insert its values */
7742 bp->cnic_eth_dev.addr_drv_info_to_mcp =
7743 &bp->slowpath->drv_info_to_mcp;
7744
7745 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
7746 goto alloc_mem_err;
7747
7748 return 0;
7749
7750 alloc_mem_err:
7751 bnx2x_free_mem_cnic(bp);
7752 BNX2X_ERR("Can't allocate memory\n");
7753 return -ENOMEM;
7754 }
7755
7756 int bnx2x_alloc_mem(struct bnx2x *bp)
7757 {
7758 int i, allocated, context_size;
7759
7760 if (!CONFIGURE_NIC_MODE(bp))
7761 /* allocate searcher T2 table */
7762 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7763
7764 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7765 sizeof(struct host_sp_status_block));
7766
7767 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7768 sizeof(struct bnx2x_slowpath));
7769
7770 /* Allocate memory for CDU context:
7771 * This memory is allocated separately and not in the generic ILT
7772 * functions because CDU differs in few aspects:
7773 * 1. There are multiple entities allocating memory for context -
7774 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7775 * its own ILT lines.
7776 * 2. Since CDU page-size is not a single 4KB page (which is the case
7777 * for the other ILT clients), to be efficient we want to support
7778 * allocation of sub-page-size in the last entry.
7779 * 3. Context pointers are used by the driver to pass to FW / update
7780 * the context (for the other ILT clients the pointers are used just to
7781 * free the memory during unload).
7782 */
7783 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7784
7785 for (i = 0, allocated = 0; allocated < context_size; i++) {
7786 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
7787 (context_size - allocated));
7788 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
7789 &bp->context[i].cxt_mapping,
7790 bp->context[i].size);
7791 allocated += bp->context[i].size;
7792 }
7793 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
7794
7795 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7796 goto alloc_mem_err;
7797
7798 if (bnx2x_iov_alloc_mem(bp))
7799 goto alloc_mem_err;
7800
7801 /* Slow path ring */
7802 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
7803
7804 /* EQ */
7805 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
7806 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7807
7808 return 0;
7809
7810 alloc_mem_err:
7811 bnx2x_free_mem(bp);
7812 BNX2X_ERR("Can't allocate memory\n");
7813 return -ENOMEM;
7814 }
7815
7816 /*
7817 * Init service functions
7818 */
7819
7820 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
7821 struct bnx2x_vlan_mac_obj *obj, bool set,
7822 int mac_type, unsigned long *ramrod_flags)
7823 {
7824 int rc;
7825 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
7826
7827 memset(&ramrod_param, 0, sizeof(ramrod_param));
7828
7829 /* Fill general parameters */
7830 ramrod_param.vlan_mac_obj = obj;
7831 ramrod_param.ramrod_flags = *ramrod_flags;
7832
7833 /* Fill a user request section if needed */
7834 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
7835 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
7836
7837 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
7838
7839 /* Set the command: ADD or DEL */
7840 if (set)
7841 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
7842 else
7843 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
7844 }
7845
7846 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7847
7848 if (rc == -EEXIST) {
7849 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
7850 /* do not treat adding same MAC as error */
7851 rc = 0;
7852 } else if (rc < 0)
7853 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7854
7855 return rc;
7856 }
7857
7858 int bnx2x_del_all_macs(struct bnx2x *bp,
7859 struct bnx2x_vlan_mac_obj *mac_obj,
7860 int mac_type, bool wait_for_comp)
7861 {
7862 int rc;
7863 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
7864
7865 /* Wait for completion of requested */
7866 if (wait_for_comp)
7867 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7868
7869 /* Set the mac type of addresses we want to clear */
7870 __set_bit(mac_type, &vlan_mac_flags);
7871
7872 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
7873 if (rc < 0)
7874 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
7875
7876 return rc;
7877 }
7878
7879 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
7880 {
7881 unsigned long ramrod_flags = 0;
7882
7883 if (is_zero_ether_addr(bp->dev->dev_addr) &&
7884 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
7885 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
7886 "Ignoring Zero MAC for STORAGE SD mode\n");
7887 return 0;
7888 }
7889
7890 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
7891
7892 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7893 /* Eth MAC is set on RSS leading client (fp[0]) */
7894 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->sp_objs->mac_obj,
7895 set, BNX2X_ETH_MAC, &ramrod_flags);
7896 }
7897
7898 int bnx2x_setup_leading(struct bnx2x *bp)
7899 {
7900 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
7901 }
7902
7903 /**
7904 * bnx2x_set_int_mode - configure interrupt mode
7905 *
7906 * @bp: driver handle
7907 *
7908 * In case of MSI-X it will also try to enable MSI-X.
7909 */
7910 int bnx2x_set_int_mode(struct bnx2x *bp)
7911 {
7912 int rc = 0;
7913
7914 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX)
7915 return -EINVAL;
7916
7917 switch (int_mode) {
7918 case BNX2X_INT_MODE_MSIX:
7919 /* attempt to enable msix */
7920 rc = bnx2x_enable_msix(bp);
7921
7922 /* msix attained */
7923 if (!rc)
7924 return 0;
7925
7926 /* vfs use only msix */
7927 if (rc && IS_VF(bp))
7928 return rc;
7929
7930 /* failed to enable multiple MSI-X */
7931 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
7932 bp->num_queues,
7933 1 + bp->num_cnic_queues);
7934
7935 /* falling through... */
7936 case BNX2X_INT_MODE_MSI:
7937 bnx2x_enable_msi(bp);
7938
7939 /* falling through... */
7940 case BNX2X_INT_MODE_INTX:
7941 bp->num_ethernet_queues = 1;
7942 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
7943 BNX2X_DEV_INFO("set number of queues to 1\n");
7944 break;
7945 default:
7946 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
7947 return -EINVAL;
7948 }
7949 return 0;
7950 }
7951
7952 /* must be called prior to any HW initializations */
7953 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7954 {
7955 if (IS_SRIOV(bp))
7956 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
7957 return L2_ILT_LINES(bp);
7958 }
7959
7960 void bnx2x_ilt_set_info(struct bnx2x *bp)
7961 {
7962 struct ilt_client_info *ilt_client;
7963 struct bnx2x_ilt *ilt = BP_ILT(bp);
7964 u16 line = 0;
7965
7966 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7967 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7968
7969 /* CDU */
7970 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7971 ilt_client->client_num = ILT_CLIENT_CDU;
7972 ilt_client->page_size = CDU_ILT_PAGE_SZ;
7973 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7974 ilt_client->start = line;
7975 line += bnx2x_cid_ilt_lines(bp);
7976
7977 if (CNIC_SUPPORT(bp))
7978 line += CNIC_ILT_LINES;
7979 ilt_client->end = line - 1;
7980
7981 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7982 ilt_client->start,
7983 ilt_client->end,
7984 ilt_client->page_size,
7985 ilt_client->flags,
7986 ilog2(ilt_client->page_size >> 12));
7987
7988 /* QM */
7989 if (QM_INIT(bp->qm_cid_count)) {
7990 ilt_client = &ilt->clients[ILT_CLIENT_QM];
7991 ilt_client->client_num = ILT_CLIENT_QM;
7992 ilt_client->page_size = QM_ILT_PAGE_SZ;
7993 ilt_client->flags = 0;
7994 ilt_client->start = line;
7995
7996 /* 4 bytes for each cid */
7997 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7998 QM_ILT_PAGE_SZ);
7999
8000 ilt_client->end = line - 1;
8001
8002 DP(NETIF_MSG_IFUP,
8003 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8004 ilt_client->start,
8005 ilt_client->end,
8006 ilt_client->page_size,
8007 ilt_client->flags,
8008 ilog2(ilt_client->page_size >> 12));
8009
8010 }
8011
8012 if (CNIC_SUPPORT(bp)) {
8013 /* SRC */
8014 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8015 ilt_client->client_num = ILT_CLIENT_SRC;
8016 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8017 ilt_client->flags = 0;
8018 ilt_client->start = line;
8019 line += SRC_ILT_LINES;
8020 ilt_client->end = line - 1;
8021
8022 DP(NETIF_MSG_IFUP,
8023 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8024 ilt_client->start,
8025 ilt_client->end,
8026 ilt_client->page_size,
8027 ilt_client->flags,
8028 ilog2(ilt_client->page_size >> 12));
8029
8030 /* TM */
8031 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8032 ilt_client->client_num = ILT_CLIENT_TM;
8033 ilt_client->page_size = TM_ILT_PAGE_SZ;
8034 ilt_client->flags = 0;
8035 ilt_client->start = line;
8036 line += TM_ILT_LINES;
8037 ilt_client->end = line - 1;
8038
8039 DP(NETIF_MSG_IFUP,
8040 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8041 ilt_client->start,
8042 ilt_client->end,
8043 ilt_client->page_size,
8044 ilt_client->flags,
8045 ilog2(ilt_client->page_size >> 12));
8046 }
8047
8048 BUG_ON(line > ILT_MAX_LINES);
8049 }
8050
8051 /**
8052 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8053 *
8054 * @bp: driver handle
8055 * @fp: pointer to fastpath
8056 * @init_params: pointer to parameters structure
8057 *
8058 * parameters configured:
8059 * - HC configuration
8060 * - Queue's CDU context
8061 */
8062 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8063 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8064 {
8065
8066 u8 cos;
8067 int cxt_index, cxt_offset;
8068
8069 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8070 if (!IS_FCOE_FP(fp)) {
8071 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8072 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8073
8074 /* If HC is supporterd, enable host coalescing in the transition
8075 * to INIT state.
8076 */
8077 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8078 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8079
8080 /* HC rate */
8081 init_params->rx.hc_rate = bp->rx_ticks ?
8082 (1000000 / bp->rx_ticks) : 0;
8083 init_params->tx.hc_rate = bp->tx_ticks ?
8084 (1000000 / bp->tx_ticks) : 0;
8085
8086 /* FW SB ID */
8087 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8088 fp->fw_sb_id;
8089
8090 /*
8091 * CQ index among the SB indices: FCoE clients uses the default
8092 * SB, therefore it's different.
8093 */
8094 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8095 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8096 }
8097
8098 /* set maximum number of COSs supported by this queue */
8099 init_params->max_cos = fp->max_cos;
8100
8101 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8102 fp->index, init_params->max_cos);
8103
8104 /* set the context pointers queue object */
8105 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8106 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8107 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8108 ILT_PAGE_CIDS);
8109 init_params->cxts[cos] =
8110 &bp->context[cxt_index].vcxt[cxt_offset].eth;
8111 }
8112 }
8113
8114 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8115 struct bnx2x_queue_state_params *q_params,
8116 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8117 int tx_index, bool leading)
8118 {
8119 memset(tx_only_params, 0, sizeof(*tx_only_params));
8120
8121 /* Set the command */
8122 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8123
8124 /* Set tx-only QUEUE flags: don't zero statistics */
8125 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8126
8127 /* choose the index of the cid to send the slow path on */
8128 tx_only_params->cid_index = tx_index;
8129
8130 /* Set general TX_ONLY_SETUP parameters */
8131 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8132
8133 /* Set Tx TX_ONLY_SETUP parameters */
8134 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8135
8136 DP(NETIF_MSG_IFUP,
8137 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8138 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8139 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8140 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8141
8142 /* send the ramrod */
8143 return bnx2x_queue_state_change(bp, q_params);
8144 }
8145
8146
8147 /**
8148 * bnx2x_setup_queue - setup queue
8149 *
8150 * @bp: driver handle
8151 * @fp: pointer to fastpath
8152 * @leading: is leading
8153 *
8154 * This function performs 2 steps in a Queue state machine
8155 * actually: 1) RESET->INIT 2) INIT->SETUP
8156 */
8157
8158 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8159 bool leading)
8160 {
8161 struct bnx2x_queue_state_params q_params = {NULL};
8162 struct bnx2x_queue_setup_params *setup_params =
8163 &q_params.params.setup;
8164 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8165 &q_params.params.tx_only;
8166 int rc;
8167 u8 tx_index;
8168
8169 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8170
8171 /* reset IGU state skip FCoE L2 queue */
8172 if (!IS_FCOE_FP(fp))
8173 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8174 IGU_INT_ENABLE, 0);
8175
8176 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8177 /* We want to wait for completion in this context */
8178 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8179
8180 /* Prepare the INIT parameters */
8181 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8182
8183 /* Set the command */
8184 q_params.cmd = BNX2X_Q_CMD_INIT;
8185
8186 /* Change the state to INIT */
8187 rc = bnx2x_queue_state_change(bp, &q_params);
8188 if (rc) {
8189 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8190 return rc;
8191 }
8192
8193 DP(NETIF_MSG_IFUP, "init complete\n");
8194
8195
8196 /* Now move the Queue to the SETUP state... */
8197 memset(setup_params, 0, sizeof(*setup_params));
8198
8199 /* Set QUEUE flags */
8200 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8201
8202 /* Set general SETUP parameters */
8203 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8204 FIRST_TX_COS_INDEX);
8205
8206 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8207 &setup_params->rxq_params);
8208
8209 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8210 FIRST_TX_COS_INDEX);
8211
8212 /* Set the command */
8213 q_params.cmd = BNX2X_Q_CMD_SETUP;
8214
8215 if (IS_FCOE_FP(fp))
8216 bp->fcoe_init = true;
8217
8218 /* Change the state to SETUP */
8219 rc = bnx2x_queue_state_change(bp, &q_params);
8220 if (rc) {
8221 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8222 return rc;
8223 }
8224
8225 /* loop through the relevant tx-only indices */
8226 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8227 tx_index < fp->max_cos;
8228 tx_index++) {
8229
8230 /* prepare and send tx-only ramrod*/
8231 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8232 tx_only_params, tx_index, leading);
8233 if (rc) {
8234 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8235 fp->index, tx_index);
8236 return rc;
8237 }
8238 }
8239
8240 return rc;
8241 }
8242
8243 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8244 {
8245 struct bnx2x_fastpath *fp = &bp->fp[index];
8246 struct bnx2x_fp_txdata *txdata;
8247 struct bnx2x_queue_state_params q_params = {NULL};
8248 int rc, tx_index;
8249
8250 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8251
8252 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8253 /* We want to wait for completion in this context */
8254 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8255
8256
8257 /* close tx-only connections */
8258 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8259 tx_index < fp->max_cos;
8260 tx_index++){
8261
8262 /* ascertain this is a normal queue*/
8263 txdata = fp->txdata_ptr[tx_index];
8264
8265 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8266 txdata->txq_index);
8267
8268 /* send halt terminate on tx-only connection */
8269 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8270 memset(&q_params.params.terminate, 0,
8271 sizeof(q_params.params.terminate));
8272 q_params.params.terminate.cid_index = tx_index;
8273
8274 rc = bnx2x_queue_state_change(bp, &q_params);
8275 if (rc)
8276 return rc;
8277
8278 /* send halt terminate on tx-only connection */
8279 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8280 memset(&q_params.params.cfc_del, 0,
8281 sizeof(q_params.params.cfc_del));
8282 q_params.params.cfc_del.cid_index = tx_index;
8283 rc = bnx2x_queue_state_change(bp, &q_params);
8284 if (rc)
8285 return rc;
8286 }
8287 /* Stop the primary connection: */
8288 /* ...halt the connection */
8289 q_params.cmd = BNX2X_Q_CMD_HALT;
8290 rc = bnx2x_queue_state_change(bp, &q_params);
8291 if (rc)
8292 return rc;
8293
8294 /* ...terminate the connection */
8295 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8296 memset(&q_params.params.terminate, 0,
8297 sizeof(q_params.params.terminate));
8298 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8299 rc = bnx2x_queue_state_change(bp, &q_params);
8300 if (rc)
8301 return rc;
8302 /* ...delete cfc entry */
8303 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8304 memset(&q_params.params.cfc_del, 0,
8305 sizeof(q_params.params.cfc_del));
8306 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8307 return bnx2x_queue_state_change(bp, &q_params);
8308 }
8309
8310
8311 static void bnx2x_reset_func(struct bnx2x *bp)
8312 {
8313 int port = BP_PORT(bp);
8314 int func = BP_FUNC(bp);
8315 int i;
8316
8317 /* Disable the function in the FW */
8318 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8319 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8320 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8321 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8322
8323 /* FP SBs */
8324 for_each_eth_queue(bp, i) {
8325 struct bnx2x_fastpath *fp = &bp->fp[i];
8326 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8327 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8328 SB_DISABLED);
8329 }
8330
8331 if (CNIC_LOADED(bp))
8332 /* CNIC SB */
8333 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8334 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8335 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8336
8337 /* SP SB */
8338 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8339 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8340 SB_DISABLED);
8341
8342 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8343 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8344 0);
8345
8346 /* Configure IGU */
8347 if (bp->common.int_block == INT_BLOCK_HC) {
8348 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8349 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8350 } else {
8351 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8352 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8353 }
8354
8355 if (CNIC_LOADED(bp)) {
8356 /* Disable Timer scan */
8357 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8358 /*
8359 * Wait for at least 10ms and up to 2 second for the timers
8360 * scan to complete
8361 */
8362 for (i = 0; i < 200; i++) {
8363 msleep(10);
8364 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8365 break;
8366 }
8367 }
8368 /* Clear ILT */
8369 bnx2x_clear_func_ilt(bp, func);
8370
8371 /* Timers workaround bug for E2: if this is vnic-3,
8372 * we need to set the entire ilt range for this timers.
8373 */
8374 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8375 struct ilt_client_info ilt_cli;
8376 /* use dummy TM client */
8377 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8378 ilt_cli.start = 0;
8379 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8380 ilt_cli.client_num = ILT_CLIENT_TM;
8381
8382 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8383 }
8384
8385 /* this assumes that reset_port() called before reset_func()*/
8386 if (!CHIP_IS_E1x(bp))
8387 bnx2x_pf_disable(bp);
8388
8389 bp->dmae_ready = 0;
8390 }
8391
8392 static void bnx2x_reset_port(struct bnx2x *bp)
8393 {
8394 int port = BP_PORT(bp);
8395 u32 val;
8396
8397 /* Reset physical Link */
8398 bnx2x__link_reset(bp);
8399
8400 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8401
8402 /* Do not rcv packets to BRB */
8403 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8404 /* Do not direct rcv packets that are not for MCP to the BRB */
8405 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8406 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8407
8408 /* Configure AEU */
8409 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8410
8411 msleep(100);
8412 /* Check for BRB port occupancy */
8413 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8414 if (val)
8415 DP(NETIF_MSG_IFDOWN,
8416 "BRB1 is not empty %d blocks are occupied\n", val);
8417
8418 /* TODO: Close Doorbell port? */
8419 }
8420
8421 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8422 {
8423 struct bnx2x_func_state_params func_params = {NULL};
8424
8425 /* Prepare parameters for function state transitions */
8426 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8427
8428 func_params.f_obj = &bp->func_obj;
8429 func_params.cmd = BNX2X_F_CMD_HW_RESET;
8430
8431 func_params.params.hw_init.load_phase = load_code;
8432
8433 return bnx2x_func_state_change(bp, &func_params);
8434 }
8435
8436 static int bnx2x_func_stop(struct bnx2x *bp)
8437 {
8438 struct bnx2x_func_state_params func_params = {NULL};
8439 int rc;
8440
8441 /* Prepare parameters for function state transitions */
8442 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8443 func_params.f_obj = &bp->func_obj;
8444 func_params.cmd = BNX2X_F_CMD_STOP;
8445
8446 /*
8447 * Try to stop the function the 'good way'. If fails (in case
8448 * of a parity error during bnx2x_chip_cleanup()) and we are
8449 * not in a debug mode, perform a state transaction in order to
8450 * enable further HW_RESET transaction.
8451 */
8452 rc = bnx2x_func_state_change(bp, &func_params);
8453 if (rc) {
8454 #ifdef BNX2X_STOP_ON_ERROR
8455 return rc;
8456 #else
8457 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8458 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8459 return bnx2x_func_state_change(bp, &func_params);
8460 #endif
8461 }
8462
8463 return 0;
8464 }
8465
8466 /**
8467 * bnx2x_send_unload_req - request unload mode from the MCP.
8468 *
8469 * @bp: driver handle
8470 * @unload_mode: requested function's unload mode
8471 *
8472 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8473 */
8474 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8475 {
8476 u32 reset_code = 0;
8477 int port = BP_PORT(bp);
8478
8479 /* Select the UNLOAD request mode */
8480 if (unload_mode == UNLOAD_NORMAL)
8481 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8482
8483 else if (bp->flags & NO_WOL_FLAG)
8484 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8485
8486 else if (bp->wol) {
8487 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8488 u8 *mac_addr = bp->dev->dev_addr;
8489 u32 val;
8490 u16 pmc;
8491
8492 /* The mac address is written to entries 1-4 to
8493 * preserve entry 0 which is used by the PMF
8494 */
8495 u8 entry = (BP_VN(bp) + 1)*8;
8496
8497 val = (mac_addr[0] << 8) | mac_addr[1];
8498 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8499
8500 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8501 (mac_addr[4] << 8) | mac_addr[5];
8502 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8503
8504 /* Enable the PME and clear the status */
8505 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
8506 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8507 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
8508
8509 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8510
8511 } else
8512 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8513
8514 /* Send the request to the MCP */
8515 if (!BP_NOMCP(bp))
8516 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8517 else {
8518 int path = BP_PATH(bp);
8519
8520 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
8521 path, load_count[path][0], load_count[path][1],
8522 load_count[path][2]);
8523 load_count[path][0]--;
8524 load_count[path][1 + port]--;
8525 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
8526 path, load_count[path][0], load_count[path][1],
8527 load_count[path][2]);
8528 if (load_count[path][0] == 0)
8529 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8530 else if (load_count[path][1 + port] == 0)
8531 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8532 else
8533 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8534 }
8535
8536 return reset_code;
8537 }
8538
8539 /**
8540 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8541 *
8542 * @bp: driver handle
8543 * @keep_link: true iff link should be kept up
8544 */
8545 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
8546 {
8547 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8548
8549 /* Report UNLOAD_DONE to MCP */
8550 if (!BP_NOMCP(bp))
8551 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
8552 }
8553
8554 static int bnx2x_func_wait_started(struct bnx2x *bp)
8555 {
8556 int tout = 50;
8557 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8558
8559 if (!bp->port.pmf)
8560 return 0;
8561
8562 /*
8563 * (assumption: No Attention from MCP at this stage)
8564 * PMF probably in the middle of TXdisable/enable transaction
8565 * 1. Sync IRS for default SB
8566 * 2. Sync SP queue - this guarantes us that attention handling started
8567 * 3. Wait, that TXdisable/enable transaction completes
8568 *
8569 * 1+2 guranty that if DCBx attention was scheduled it already changed
8570 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
8571 * received complettion for the transaction the state is TX_STOPPED.
8572 * State will return to STARTED after completion of TX_STOPPED-->STARTED
8573 * transaction.
8574 */
8575
8576 /* make sure default SB ISR is done */
8577 if (msix)
8578 synchronize_irq(bp->msix_table[0].vector);
8579 else
8580 synchronize_irq(bp->pdev->irq);
8581
8582 flush_workqueue(bnx2x_wq);
8583
8584 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8585 BNX2X_F_STATE_STARTED && tout--)
8586 msleep(20);
8587
8588 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8589 BNX2X_F_STATE_STARTED) {
8590 #ifdef BNX2X_STOP_ON_ERROR
8591 BNX2X_ERR("Wrong function state\n");
8592 return -EBUSY;
8593 #else
8594 /*
8595 * Failed to complete the transaction in a "good way"
8596 * Force both transactions with CLR bit
8597 */
8598 struct bnx2x_func_state_params func_params = {NULL};
8599
8600 DP(NETIF_MSG_IFDOWN,
8601 "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8602
8603 func_params.f_obj = &bp->func_obj;
8604 __set_bit(RAMROD_DRV_CLR_ONLY,
8605 &func_params.ramrod_flags);
8606
8607 /* STARTED-->TX_ST0PPED */
8608 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8609 bnx2x_func_state_change(bp, &func_params);
8610
8611 /* TX_ST0PPED-->STARTED */
8612 func_params.cmd = BNX2X_F_CMD_TX_START;
8613 return bnx2x_func_state_change(bp, &func_params);
8614 #endif
8615 }
8616
8617 return 0;
8618 }
8619
8620 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
8621 {
8622 int port = BP_PORT(bp);
8623 int i, rc = 0;
8624 u8 cos;
8625 struct bnx2x_mcast_ramrod_params rparam = {NULL};
8626 u32 reset_code;
8627
8628 /* Wait until tx fastpath tasks complete */
8629 for_each_tx_queue(bp, i) {
8630 struct bnx2x_fastpath *fp = &bp->fp[i];
8631
8632 for_each_cos_in_tx_queue(fp, cos)
8633 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
8634 #ifdef BNX2X_STOP_ON_ERROR
8635 if (rc)
8636 return;
8637 #endif
8638 }
8639
8640 /* Give HW time to discard old tx messages */
8641 usleep_range(1000, 1000);
8642
8643 /* Clean all ETH MACs */
8644 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8645 false);
8646 if (rc < 0)
8647 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8648
8649 /* Clean up UC list */
8650 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
8651 true);
8652 if (rc < 0)
8653 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8654 rc);
8655
8656 /* Disable LLH */
8657 if (!CHIP_IS_E1(bp))
8658 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8659
8660 /* Set "drop all" (stop Rx).
8661 * We need to take a netif_addr_lock() here in order to prevent
8662 * a race between the completion code and this code.
8663 */
8664 netif_addr_lock_bh(bp->dev);
8665 /* Schedule the rx_mode command */
8666 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8667 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8668 else
8669 bnx2x_set_storm_rx_mode(bp);
8670
8671 /* Cleanup multicast configuration */
8672 rparam.mcast_obj = &bp->mcast_obj;
8673 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8674 if (rc < 0)
8675 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8676
8677 netif_addr_unlock_bh(bp->dev);
8678
8679 bnx2x_iov_chip_cleanup(bp);
8680
8681
8682 /*
8683 * Send the UNLOAD_REQUEST to the MCP. This will return if
8684 * this function should perform FUNC, PORT or COMMON HW
8685 * reset.
8686 */
8687 reset_code = bnx2x_send_unload_req(bp, unload_mode);
8688
8689 /*
8690 * (assumption: No Attention from MCP at this stage)
8691 * PMF probably in the middle of TXdisable/enable transaction
8692 */
8693 rc = bnx2x_func_wait_started(bp);
8694 if (rc) {
8695 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8696 #ifdef BNX2X_STOP_ON_ERROR
8697 return;
8698 #endif
8699 }
8700
8701 /* Close multi and leading connections
8702 * Completions for ramrods are collected in a synchronous way
8703 */
8704 for_each_eth_queue(bp, i)
8705 if (bnx2x_stop_queue(bp, i))
8706 #ifdef BNX2X_STOP_ON_ERROR
8707 return;
8708 #else
8709 goto unload_error;
8710 #endif
8711
8712 if (CNIC_LOADED(bp)) {
8713 for_each_cnic_queue(bp, i)
8714 if (bnx2x_stop_queue(bp, i))
8715 #ifdef BNX2X_STOP_ON_ERROR
8716 return;
8717 #else
8718 goto unload_error;
8719 #endif
8720 }
8721
8722 /* If SP settings didn't get completed so far - something
8723 * very wrong has happen.
8724 */
8725 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8726 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8727
8728 #ifndef BNX2X_STOP_ON_ERROR
8729 unload_error:
8730 #endif
8731 rc = bnx2x_func_stop(bp);
8732 if (rc) {
8733 BNX2X_ERR("Function stop failed!\n");
8734 #ifdef BNX2X_STOP_ON_ERROR
8735 return;
8736 #endif
8737 }
8738
8739 /* Disable HW interrupts, NAPI */
8740 bnx2x_netif_stop(bp, 1);
8741 /* Delete all NAPI objects */
8742 bnx2x_del_all_napi(bp);
8743 if (CNIC_LOADED(bp))
8744 bnx2x_del_all_napi_cnic(bp);
8745
8746 /* Release IRQs */
8747 bnx2x_free_irq(bp);
8748
8749 /* Reset the chip */
8750 rc = bnx2x_reset_hw(bp, reset_code);
8751 if (rc)
8752 BNX2X_ERR("HW_RESET failed\n");
8753
8754
8755 /* Report UNLOAD_DONE to MCP */
8756 bnx2x_send_unload_done(bp, keep_link);
8757 }
8758
8759 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8760 {
8761 u32 val;
8762
8763 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8764
8765 if (CHIP_IS_E1(bp)) {
8766 int port = BP_PORT(bp);
8767 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8768 MISC_REG_AEU_MASK_ATTN_FUNC_0;
8769
8770 val = REG_RD(bp, addr);
8771 val &= ~(0x300);
8772 REG_WR(bp, addr, val);
8773 } else {
8774 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8775 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8776 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8777 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8778 }
8779 }
8780
8781 /* Close gates #2, #3 and #4: */
8782 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8783 {
8784 u32 val;
8785
8786 /* Gates #2 and #4a are closed/opened for "not E1" only */
8787 if (!CHIP_IS_E1(bp)) {
8788 /* #4 */
8789 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
8790 /* #2 */
8791 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
8792 }
8793
8794 /* #3 */
8795 if (CHIP_IS_E1x(bp)) {
8796 /* Prevent interrupts from HC on both ports */
8797 val = REG_RD(bp, HC_REG_CONFIG_1);
8798 REG_WR(bp, HC_REG_CONFIG_1,
8799 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
8800 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
8801
8802 val = REG_RD(bp, HC_REG_CONFIG_0);
8803 REG_WR(bp, HC_REG_CONFIG_0,
8804 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
8805 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
8806 } else {
8807 /* Prevent incomming interrupts in IGU */
8808 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8809
8810 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
8811 (!close) ?
8812 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
8813 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
8814 }
8815
8816 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
8817 close ? "closing" : "opening");
8818 mmiowb();
8819 }
8820
8821 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
8822
8823 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
8824 {
8825 /* Do some magic... */
8826 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8827 *magic_val = val & SHARED_MF_CLP_MAGIC;
8828 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
8829 }
8830
8831 /**
8832 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
8833 *
8834 * @bp: driver handle
8835 * @magic_val: old value of the `magic' bit.
8836 */
8837 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
8838 {
8839 /* Restore the `magic' bit value... */
8840 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8841 MF_CFG_WR(bp, shared_mf_config.clp_mb,
8842 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
8843 }
8844
8845 /**
8846 * bnx2x_reset_mcp_prep - prepare for MCP reset.
8847 *
8848 * @bp: driver handle
8849 * @magic_val: old value of 'magic' bit.
8850 *
8851 * Takes care of CLP configurations.
8852 */
8853 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
8854 {
8855 u32 shmem;
8856 u32 validity_offset;
8857
8858 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
8859
8860 /* Set `magic' bit in order to save MF config */
8861 if (!CHIP_IS_E1(bp))
8862 bnx2x_clp_reset_prep(bp, magic_val);
8863
8864 /* Get shmem offset */
8865 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8866 validity_offset =
8867 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
8868
8869 /* Clear validity map flags */
8870 if (shmem > 0)
8871 REG_WR(bp, shmem + validity_offset, 0);
8872 }
8873
8874 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
8875 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
8876
8877 /**
8878 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
8879 *
8880 * @bp: driver handle
8881 */
8882 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
8883 {
8884 /* special handling for emulation and FPGA,
8885 wait 10 times longer */
8886 if (CHIP_REV_IS_SLOW(bp))
8887 msleep(MCP_ONE_TIMEOUT*10);
8888 else
8889 msleep(MCP_ONE_TIMEOUT);
8890 }
8891
8892 /*
8893 * initializes bp->common.shmem_base and waits for validity signature to appear
8894 */
8895 static int bnx2x_init_shmem(struct bnx2x *bp)
8896 {
8897 int cnt = 0;
8898 u32 val = 0;
8899
8900 do {
8901 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8902 if (bp->common.shmem_base) {
8903 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8904 if (val & SHR_MEM_VALIDITY_MB)
8905 return 0;
8906 }
8907
8908 bnx2x_mcp_wait_one(bp);
8909
8910 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
8911
8912 BNX2X_ERR("BAD MCP validity signature\n");
8913
8914 return -ENODEV;
8915 }
8916
8917 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8918 {
8919 int rc = bnx2x_init_shmem(bp);
8920
8921 /* Restore the `magic' bit value */
8922 if (!CHIP_IS_E1(bp))
8923 bnx2x_clp_reset_done(bp, magic_val);
8924
8925 return rc;
8926 }
8927
8928 static void bnx2x_pxp_prep(struct bnx2x *bp)
8929 {
8930 if (!CHIP_IS_E1(bp)) {
8931 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8932 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
8933 mmiowb();
8934 }
8935 }
8936
8937 /*
8938 * Reset the whole chip except for:
8939 * - PCIE core
8940 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8941 * one reset bit)
8942 * - IGU
8943 * - MISC (including AEU)
8944 * - GRC
8945 * - RBCN, RBCP
8946 */
8947 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
8948 {
8949 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8950 u32 global_bits2, stay_reset2;
8951
8952 /*
8953 * Bits that have to be set in reset_mask2 if we want to reset 'global'
8954 * (per chip) blocks.
8955 */
8956 global_bits2 =
8957 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
8958 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
8959
8960 /* Don't reset the following blocks.
8961 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
8962 * reset, as in 4 port device they might still be owned
8963 * by the MCP (there is only one leader per path).
8964 */
8965 not_reset_mask1 =
8966 MISC_REGISTERS_RESET_REG_1_RST_HC |
8967 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
8968 MISC_REGISTERS_RESET_REG_1_RST_PXP;
8969
8970 not_reset_mask2 =
8971 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
8972 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8973 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8974 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8975 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8976 MISC_REGISTERS_RESET_REG_2_RST_GRC |
8977 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8978 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
8979 MISC_REGISTERS_RESET_REG_2_RST_ATC |
8980 MISC_REGISTERS_RESET_REG_2_PGLC |
8981 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
8982 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
8983 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
8984 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
8985 MISC_REGISTERS_RESET_REG_2_UMAC0 |
8986 MISC_REGISTERS_RESET_REG_2_UMAC1;
8987
8988 /*
8989 * Keep the following blocks in reset:
8990 * - all xxMACs are handled by the bnx2x_link code.
8991 */
8992 stay_reset2 =
8993 MISC_REGISTERS_RESET_REG_2_XMAC |
8994 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
8995
8996 /* Full reset masks according to the chip */
8997 reset_mask1 = 0xffffffff;
8998
8999 if (CHIP_IS_E1(bp))
9000 reset_mask2 = 0xffff;
9001 else if (CHIP_IS_E1H(bp))
9002 reset_mask2 = 0x1ffff;
9003 else if (CHIP_IS_E2(bp))
9004 reset_mask2 = 0xfffff;
9005 else /* CHIP_IS_E3 */
9006 reset_mask2 = 0x3ffffff;
9007
9008 /* Don't reset global blocks unless we need to */
9009 if (!global)
9010 reset_mask2 &= ~global_bits2;
9011
9012 /*
9013 * In case of attention in the QM, we need to reset PXP
9014 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9015 * because otherwise QM reset would release 'close the gates' shortly
9016 * before resetting the PXP, then the PSWRQ would send a write
9017 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9018 * read the payload data from PSWWR, but PSWWR would not
9019 * respond. The write queue in PGLUE would stuck, dmae commands
9020 * would not return. Therefore it's important to reset the second
9021 * reset register (containing the
9022 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9023 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9024 * bit).
9025 */
9026 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9027 reset_mask2 & (~not_reset_mask2));
9028
9029 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9030 reset_mask1 & (~not_reset_mask1));
9031
9032 barrier();
9033 mmiowb();
9034
9035 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9036 reset_mask2 & (~stay_reset2));
9037
9038 barrier();
9039 mmiowb();
9040
9041 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9042 mmiowb();
9043 }
9044
9045 /**
9046 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9047 * It should get cleared in no more than 1s.
9048 *
9049 * @bp: driver handle
9050 *
9051 * It should get cleared in no more than 1s. Returns 0 if
9052 * pending writes bit gets cleared.
9053 */
9054 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9055 {
9056 u32 cnt = 1000;
9057 u32 pend_bits = 0;
9058
9059 do {
9060 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9061
9062 if (pend_bits == 0)
9063 break;
9064
9065 usleep_range(1000, 1000);
9066 } while (cnt-- > 0);
9067
9068 if (cnt <= 0) {
9069 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9070 pend_bits);
9071 return -EBUSY;
9072 }
9073
9074 return 0;
9075 }
9076
9077 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9078 {
9079 int cnt = 1000;
9080 u32 val = 0;
9081 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9082 u32 tags_63_32 = 0;
9083
9084 /* Empty the Tetris buffer, wait for 1s */
9085 do {
9086 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9087 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9088 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9089 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9090 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9091 if (CHIP_IS_E3(bp))
9092 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9093
9094 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9095 ((port_is_idle_0 & 0x1) == 0x1) &&
9096 ((port_is_idle_1 & 0x1) == 0x1) &&
9097 (pgl_exp_rom2 == 0xffffffff) &&
9098 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9099 break;
9100 usleep_range(1000, 1000);
9101 } while (cnt-- > 0);
9102
9103 if (cnt <= 0) {
9104 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9105 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9106 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9107 pgl_exp_rom2);
9108 return -EAGAIN;
9109 }
9110
9111 barrier();
9112
9113 /* Close gates #2, #3 and #4 */
9114 bnx2x_set_234_gates(bp, true);
9115
9116 /* Poll for IGU VQs for 57712 and newer chips */
9117 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9118 return -EAGAIN;
9119
9120
9121 /* TBD: Indicate that "process kill" is in progress to MCP */
9122
9123 /* Clear "unprepared" bit */
9124 REG_WR(bp, MISC_REG_UNPREPARED, 0);
9125 barrier();
9126
9127 /* Make sure all is written to the chip before the reset */
9128 mmiowb();
9129
9130 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9131 * PSWHST, GRC and PSWRD Tetris buffer.
9132 */
9133 usleep_range(1000, 1000);
9134
9135 /* Prepare to chip reset: */
9136 /* MCP */
9137 if (global)
9138 bnx2x_reset_mcp_prep(bp, &val);
9139
9140 /* PXP */
9141 bnx2x_pxp_prep(bp);
9142 barrier();
9143
9144 /* reset the chip */
9145 bnx2x_process_kill_chip_reset(bp, global);
9146 barrier();
9147
9148 /* Recover after reset: */
9149 /* MCP */
9150 if (global && bnx2x_reset_mcp_comp(bp, val))
9151 return -EAGAIN;
9152
9153 /* TBD: Add resetting the NO_MCP mode DB here */
9154
9155 /* Open the gates #2, #3 and #4 */
9156 bnx2x_set_234_gates(bp, false);
9157
9158 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9159 * reset state, re-enable attentions. */
9160
9161 return 0;
9162 }
9163
9164 static int bnx2x_leader_reset(struct bnx2x *bp)
9165 {
9166 int rc = 0;
9167 bool global = bnx2x_reset_is_global(bp);
9168 u32 load_code;
9169
9170 /* if not going to reset MCP - load "fake" driver to reset HW while
9171 * driver is owner of the HW
9172 */
9173 if (!global && !BP_NOMCP(bp)) {
9174 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9175 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9176 if (!load_code) {
9177 BNX2X_ERR("MCP response failure, aborting\n");
9178 rc = -EAGAIN;
9179 goto exit_leader_reset;
9180 }
9181 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9182 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9183 BNX2X_ERR("MCP unexpected resp, aborting\n");
9184 rc = -EAGAIN;
9185 goto exit_leader_reset2;
9186 }
9187 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9188 if (!load_code) {
9189 BNX2X_ERR("MCP response failure, aborting\n");
9190 rc = -EAGAIN;
9191 goto exit_leader_reset2;
9192 }
9193 }
9194
9195 /* Try to recover after the failure */
9196 if (bnx2x_process_kill(bp, global)) {
9197 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9198 BP_PATH(bp));
9199 rc = -EAGAIN;
9200 goto exit_leader_reset2;
9201 }
9202
9203 /*
9204 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9205 * state.
9206 */
9207 bnx2x_set_reset_done(bp);
9208 if (global)
9209 bnx2x_clear_reset_global(bp);
9210
9211 exit_leader_reset2:
9212 /* unload "fake driver" if it was loaded */
9213 if (!global && !BP_NOMCP(bp)) {
9214 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9215 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9216 }
9217 exit_leader_reset:
9218 bp->is_leader = 0;
9219 bnx2x_release_leader_lock(bp);
9220 smp_mb();
9221 return rc;
9222 }
9223
9224 static void bnx2x_recovery_failed(struct bnx2x *bp)
9225 {
9226 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9227
9228 /* Disconnect this device */
9229 netif_device_detach(bp->dev);
9230
9231 /*
9232 * Block ifup for all function on this engine until "process kill"
9233 * or power cycle.
9234 */
9235 bnx2x_set_reset_in_progress(bp);
9236
9237 /* Shut down the power */
9238 bnx2x_set_power_state(bp, PCI_D3hot);
9239
9240 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9241
9242 smp_mb();
9243 }
9244
9245 /*
9246 * Assumption: runs under rtnl lock. This together with the fact
9247 * that it's called only from bnx2x_sp_rtnl() ensure that it
9248 * will never be called when netif_running(bp->dev) is false.
9249 */
9250 static void bnx2x_parity_recover(struct bnx2x *bp)
9251 {
9252 bool global = false;
9253 u32 error_recovered, error_unrecovered;
9254 bool is_parity;
9255
9256 DP(NETIF_MSG_HW, "Handling parity\n");
9257 while (1) {
9258 switch (bp->recovery_state) {
9259 case BNX2X_RECOVERY_INIT:
9260 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9261 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9262 WARN_ON(!is_parity);
9263
9264 /* Try to get a LEADER_LOCK HW lock */
9265 if (bnx2x_trylock_leader_lock(bp)) {
9266 bnx2x_set_reset_in_progress(bp);
9267 /*
9268 * Check if there is a global attention and if
9269 * there was a global attention, set the global
9270 * reset bit.
9271 */
9272
9273 if (global)
9274 bnx2x_set_reset_global(bp);
9275
9276 bp->is_leader = 1;
9277 }
9278
9279 /* Stop the driver */
9280 /* If interface has been removed - break */
9281 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9282 return;
9283
9284 bp->recovery_state = BNX2X_RECOVERY_WAIT;
9285
9286 /* Ensure "is_leader", MCP command sequence and
9287 * "recovery_state" update values are seen on other
9288 * CPUs.
9289 */
9290 smp_mb();
9291 break;
9292
9293 case BNX2X_RECOVERY_WAIT:
9294 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9295 if (bp->is_leader) {
9296 int other_engine = BP_PATH(bp) ? 0 : 1;
9297 bool other_load_status =
9298 bnx2x_get_load_status(bp, other_engine);
9299 bool load_status =
9300 bnx2x_get_load_status(bp, BP_PATH(bp));
9301 global = bnx2x_reset_is_global(bp);
9302
9303 /*
9304 * In case of a parity in a global block, let
9305 * the first leader that performs a
9306 * leader_reset() reset the global blocks in
9307 * order to clear global attentions. Otherwise
9308 * the the gates will remain closed for that
9309 * engine.
9310 */
9311 if (load_status ||
9312 (global && other_load_status)) {
9313 /* Wait until all other functions get
9314 * down.
9315 */
9316 schedule_delayed_work(&bp->sp_rtnl_task,
9317 HZ/10);
9318 return;
9319 } else {
9320 /* If all other functions got down -
9321 * try to bring the chip back to
9322 * normal. In any case it's an exit
9323 * point for a leader.
9324 */
9325 if (bnx2x_leader_reset(bp)) {
9326 bnx2x_recovery_failed(bp);
9327 return;
9328 }
9329
9330 /* If we are here, means that the
9331 * leader has succeeded and doesn't
9332 * want to be a leader any more. Try
9333 * to continue as a none-leader.
9334 */
9335 break;
9336 }
9337 } else { /* non-leader */
9338 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9339 /* Try to get a LEADER_LOCK HW lock as
9340 * long as a former leader may have
9341 * been unloaded by the user or
9342 * released a leadership by another
9343 * reason.
9344 */
9345 if (bnx2x_trylock_leader_lock(bp)) {
9346 /* I'm a leader now! Restart a
9347 * switch case.
9348 */
9349 bp->is_leader = 1;
9350 break;
9351 }
9352
9353 schedule_delayed_work(&bp->sp_rtnl_task,
9354 HZ/10);
9355 return;
9356
9357 } else {
9358 /*
9359 * If there was a global attention, wait
9360 * for it to be cleared.
9361 */
9362 if (bnx2x_reset_is_global(bp)) {
9363 schedule_delayed_work(
9364 &bp->sp_rtnl_task,
9365 HZ/10);
9366 return;
9367 }
9368
9369 error_recovered =
9370 bp->eth_stats.recoverable_error;
9371 error_unrecovered =
9372 bp->eth_stats.unrecoverable_error;
9373 bp->recovery_state =
9374 BNX2X_RECOVERY_NIC_LOADING;
9375 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9376 error_unrecovered++;
9377 netdev_err(bp->dev,
9378 "Recovery failed. Power cycle needed\n");
9379 /* Disconnect this device */
9380 netif_device_detach(bp->dev);
9381 /* Shut down the power */
9382 bnx2x_set_power_state(
9383 bp, PCI_D3hot);
9384 smp_mb();
9385 } else {
9386 bp->recovery_state =
9387 BNX2X_RECOVERY_DONE;
9388 error_recovered++;
9389 smp_mb();
9390 }
9391 bp->eth_stats.recoverable_error =
9392 error_recovered;
9393 bp->eth_stats.unrecoverable_error =
9394 error_unrecovered;
9395
9396 return;
9397 }
9398 }
9399 default:
9400 return;
9401 }
9402 }
9403 }
9404
9405 static int bnx2x_close(struct net_device *dev);
9406
9407 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9408 * scheduled on a general queue in order to prevent a dead lock.
9409 */
9410 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9411 {
9412 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9413
9414 rtnl_lock();
9415
9416 if (!netif_running(bp->dev)) {
9417 rtnl_unlock();
9418 return;
9419 }
9420
9421 /* if stop on error is defined no recovery flows should be executed */
9422 #ifdef BNX2X_STOP_ON_ERROR
9423 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9424 "you will need to reboot when done\n");
9425 goto sp_rtnl_not_reset;
9426 #endif
9427
9428 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9429 /*
9430 * Clear all pending SP commands as we are going to reset the
9431 * function anyway.
9432 */
9433 bp->sp_rtnl_state = 0;
9434 smp_mb();
9435
9436 bnx2x_parity_recover(bp);
9437
9438 rtnl_unlock();
9439 return;
9440 }
9441
9442 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9443 /*
9444 * Clear all pending SP commands as we are going to reset the
9445 * function anyway.
9446 */
9447 bp->sp_rtnl_state = 0;
9448 smp_mb();
9449
9450 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
9451 bnx2x_nic_load(bp, LOAD_NORMAL);
9452
9453 rtnl_unlock();
9454 return;
9455 }
9456 #ifdef BNX2X_STOP_ON_ERROR
9457 sp_rtnl_not_reset:
9458 #endif
9459 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9460 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9461 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9462 bnx2x_after_function_update(bp);
9463 /*
9464 * in case of fan failure we need to reset id if the "stop on error"
9465 * debug flag is set, since we trying to prevent permanent overheating
9466 * damage
9467 */
9468 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
9469 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9470 netif_device_detach(bp->dev);
9471 bnx2x_close(bp->dev);
9472 rtnl_unlock();
9473 return;
9474 }
9475
9476 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9477 DP(BNX2X_MSG_SP,
9478 "sending set mcast vf pf channel message from rtnl sp-task\n");
9479 bnx2x_vfpf_set_mcast(bp->dev);
9480 }
9481
9482 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
9483 &bp->sp_rtnl_state)) {
9484 DP(BNX2X_MSG_SP,
9485 "sending set storm rx mode vf pf channel message from rtnl sp-task\n");
9486 bnx2x_vfpf_storm_rx_mode(bp);
9487 }
9488
9489 /* work which needs rtnl lock not-taken (as it takes the lock itself and
9490 * can be called from other contexts as well)
9491 */
9492 rtnl_unlock();
9493
9494 /* enable SR-IOV if applicable */
9495 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
9496 &bp->sp_rtnl_state))
9497 bnx2x_enable_sriov(bp);
9498 }
9499
9500 static void bnx2x_period_task(struct work_struct *work)
9501 {
9502 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9503
9504 if (!netif_running(bp->dev))
9505 goto period_task_exit;
9506
9507 if (CHIP_REV_IS_SLOW(bp)) {
9508 BNX2X_ERR("period task called on emulation, ignoring\n");
9509 goto period_task_exit;
9510 }
9511
9512 bnx2x_acquire_phy_lock(bp);
9513 /*
9514 * The barrier is needed to ensure the ordering between the writing to
9515 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9516 * the reading here.
9517 */
9518 smp_mb();
9519 if (bp->port.pmf) {
9520 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9521
9522 /* Re-queue task in 1 sec */
9523 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9524 }
9525
9526 bnx2x_release_phy_lock(bp);
9527 period_task_exit:
9528 return;
9529 }
9530
9531 /*
9532 * Init service functions
9533 */
9534
9535 u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
9536 {
9537 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9538 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9539 return base + (BP_ABS_FUNC(bp)) * stride;
9540 }
9541
9542 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
9543 {
9544 u32 reg = bnx2x_get_pretend_reg(bp);
9545
9546 /* Flush all outstanding writes */
9547 mmiowb();
9548
9549 /* Pretend to be function 0 */
9550 REG_WR(bp, reg, 0);
9551 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
9552
9553 /* From now we are in the "like-E1" mode */
9554 bnx2x_int_disable(bp);
9555
9556 /* Flush all outstanding writes */
9557 mmiowb();
9558
9559 /* Restore the original function */
9560 REG_WR(bp, reg, BP_ABS_FUNC(bp));
9561 REG_RD(bp, reg);
9562 }
9563
9564 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
9565 {
9566 if (CHIP_IS_E1(bp))
9567 bnx2x_int_disable(bp);
9568 else
9569 bnx2x_undi_int_disable_e1h(bp);
9570 }
9571
9572 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
9573 struct bnx2x_mac_vals *vals)
9574 {
9575 u32 val, base_addr, offset, mask, reset_reg;
9576 bool mac_stopped = false;
9577 u8 port = BP_PORT(bp);
9578
9579 /* reset addresses as they also mark which values were changed */
9580 vals->bmac_addr = 0;
9581 vals->umac_addr = 0;
9582 vals->xmac_addr = 0;
9583 vals->emac_addr = 0;
9584
9585 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
9586
9587 if (!CHIP_IS_E3(bp)) {
9588 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9589 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9590 if ((mask & reset_reg) && val) {
9591 u32 wb_data[2];
9592 BNX2X_DEV_INFO("Disable bmac Rx\n");
9593 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9594 : NIG_REG_INGRESS_BMAC0_MEM;
9595 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9596 : BIGMAC_REGISTER_BMAC_CONTROL;
9597
9598 /*
9599 * use rd/wr since we cannot use dmae. This is safe
9600 * since MCP won't access the bus due to the request
9601 * to unload, and no function on the path can be
9602 * loaded at this time.
9603 */
9604 wb_data[0] = REG_RD(bp, base_addr + offset);
9605 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9606 vals->bmac_addr = base_addr + offset;
9607 vals->bmac_val[0] = wb_data[0];
9608 vals->bmac_val[1] = wb_data[1];
9609 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9610 REG_WR(bp, vals->bmac_addr, wb_data[0]);
9611 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
9612
9613 }
9614 BNX2X_DEV_INFO("Disable emac Rx\n");
9615 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
9616 vals->emac_val = REG_RD(bp, vals->emac_addr);
9617 REG_WR(bp, vals->emac_addr, 0);
9618 mac_stopped = true;
9619 } else {
9620 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9621 BNX2X_DEV_INFO("Disable xmac Rx\n");
9622 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9623 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9624 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9625 val & ~(1 << 1));
9626 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9627 val | (1 << 1));
9628 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9629 vals->xmac_val = REG_RD(bp, vals->xmac_addr);
9630 REG_WR(bp, vals->xmac_addr, 0);
9631 mac_stopped = true;
9632 }
9633 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9634 if (mask & reset_reg) {
9635 BNX2X_DEV_INFO("Disable umac Rx\n");
9636 base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9637 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9638 vals->umac_val = REG_RD(bp, vals->umac_addr);
9639 REG_WR(bp, vals->umac_addr, 0);
9640 mac_stopped = true;
9641 }
9642 }
9643
9644 if (mac_stopped)
9645 msleep(20);
9646
9647 }
9648
9649 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9650 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9651 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9652 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9653
9654 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
9655 {
9656 u16 rcq, bd;
9657 u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9658
9659 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9660 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9661
9662 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9663 REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9664
9665 BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9666 port, bd, rcq);
9667 }
9668
9669 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
9670 {
9671 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
9672 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9673 if (!rc) {
9674 BNX2X_ERR("MCP response failure, aborting\n");
9675 return -EBUSY;
9676 }
9677
9678 return 0;
9679 }
9680
9681 static struct bnx2x_prev_path_list *
9682 bnx2x_prev_path_get_entry(struct bnx2x *bp)
9683 {
9684 struct bnx2x_prev_path_list *tmp_list;
9685
9686 list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
9687 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9688 bp->pdev->bus->number == tmp_list->bus &&
9689 BP_PATH(bp) == tmp_list->path)
9690 return tmp_list;
9691
9692 return NULL;
9693 }
9694
9695 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
9696 {
9697 struct bnx2x_prev_path_list *tmp_list;
9698 int rc = false;
9699
9700 if (down_trylock(&bnx2x_prev_sem))
9701 return false;
9702
9703 list_for_each_entry(tmp_list, &bnx2x_prev_list, list) {
9704 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9705 bp->pdev->bus->number == tmp_list->bus &&
9706 BP_PATH(bp) == tmp_list->path) {
9707 rc = true;
9708 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9709 BP_PATH(bp));
9710 break;
9711 }
9712 }
9713
9714 up(&bnx2x_prev_sem);
9715
9716 return rc;
9717 }
9718
9719 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
9720 {
9721 struct bnx2x_prev_path_list *tmp_list;
9722 int rc;
9723
9724 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
9725 if (!tmp_list) {
9726 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9727 return -ENOMEM;
9728 }
9729
9730 tmp_list->bus = bp->pdev->bus->number;
9731 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
9732 tmp_list->path = BP_PATH(bp);
9733 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
9734
9735 rc = down_interruptible(&bnx2x_prev_sem);
9736 if (rc) {
9737 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9738 kfree(tmp_list);
9739 } else {
9740 BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n",
9741 BP_PATH(bp));
9742 list_add(&tmp_list->list, &bnx2x_prev_list);
9743 up(&bnx2x_prev_sem);
9744 }
9745
9746 return rc;
9747 }
9748
9749 static int bnx2x_do_flr(struct bnx2x *bp)
9750 {
9751 int i;
9752 u16 status;
9753 struct pci_dev *dev = bp->pdev;
9754
9755
9756 if (CHIP_IS_E1x(bp)) {
9757 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
9758 return -EINVAL;
9759 }
9760
9761 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9762 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9763 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
9764 bp->common.bc_ver);
9765 return -EINVAL;
9766 }
9767
9768 /* Wait for Transaction Pending bit clean */
9769 for (i = 0; i < 4; i++) {
9770 if (i)
9771 msleep((1 << (i - 1)) * 100);
9772
9773 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
9774 if (!(status & PCI_EXP_DEVSTA_TRPND))
9775 goto clear;
9776 }
9777
9778 dev_err(&dev->dev,
9779 "transaction is not cleared; proceeding with reset anyway\n");
9780
9781 clear:
9782
9783 BNX2X_DEV_INFO("Initiating FLR\n");
9784 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
9785
9786 return 0;
9787 }
9788
9789 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
9790 {
9791 int rc;
9792
9793 BNX2X_DEV_INFO("Uncommon unload Flow\n");
9794
9795 /* Test if previous unload process was already finished for this path */
9796 if (bnx2x_prev_is_path_marked(bp))
9797 return bnx2x_prev_mcp_done(bp);
9798
9799 /* If function has FLR capabilities, and existing FW version matches
9800 * the one required, then FLR will be sufficient to clean any residue
9801 * left by previous driver
9802 */
9803 rc = bnx2x_nic_load_analyze_req(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9804
9805 if (!rc) {
9806 /* fw version is good */
9807 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
9808 rc = bnx2x_do_flr(bp);
9809 }
9810
9811 if (!rc) {
9812 /* FLR was performed */
9813 BNX2X_DEV_INFO("FLR successful\n");
9814 return 0;
9815 }
9816
9817 BNX2X_DEV_INFO("Could not FLR\n");
9818
9819 /* Close the MCP request, return failure*/
9820 rc = bnx2x_prev_mcp_done(bp);
9821 if (!rc)
9822 rc = BNX2X_PREV_WAIT_NEEDED;
9823
9824 return rc;
9825 }
9826
9827 static int bnx2x_prev_unload_common(struct bnx2x *bp)
9828 {
9829 u32 reset_reg, tmp_reg = 0, rc;
9830 bool prev_undi = false;
9831 struct bnx2x_mac_vals mac_vals;
9832
9833 /* It is possible a previous function received 'common' answer,
9834 * but hasn't loaded yet, therefore creating a scenario of
9835 * multiple functions receiving 'common' on the same path.
9836 */
9837 BNX2X_DEV_INFO("Common unload Flow\n");
9838
9839 memset(&mac_vals, 0, sizeof(mac_vals));
9840
9841 if (bnx2x_prev_is_path_marked(bp))
9842 return bnx2x_prev_mcp_done(bp);
9843
9844 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9845
9846 /* Reset should be performed after BRB is emptied */
9847 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9848 u32 timer_count = 1000;
9849
9850 /* Close the MAC Rx to prevent BRB from filling up */
9851 bnx2x_prev_unload_close_mac(bp, &mac_vals);
9852
9853 /* close LLH filters towards the BRB */
9854 bnx2x_set_rx_filter(&bp->link_params, 0);
9855
9856 /* Check if the UNDI driver was previously loaded
9857 * UNDI driver initializes CID offset for normal bell to 0x7
9858 */
9859 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9860 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9861 tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
9862 if (tmp_reg == 0x7) {
9863 BNX2X_DEV_INFO("UNDI previously loaded\n");
9864 prev_undi = true;
9865 /* clear the UNDI indication */
9866 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
9867 /* clear possible idle check errors */
9868 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
9869 }
9870 }
9871 /* wait until BRB is empty */
9872 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9873 while (timer_count) {
9874 u32 prev_brb = tmp_reg;
9875
9876 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9877 if (!tmp_reg)
9878 break;
9879
9880 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
9881
9882 /* reset timer as long as BRB actually gets emptied */
9883 if (prev_brb > tmp_reg)
9884 timer_count = 1000;
9885 else
9886 timer_count--;
9887
9888 /* If UNDI resides in memory, manually increment it */
9889 if (prev_undi)
9890 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
9891
9892 udelay(10);
9893 }
9894
9895 if (!timer_count)
9896 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
9897
9898 }
9899
9900 /* No packets are in the pipeline, path is ready for reset */
9901 bnx2x_reset_common(bp);
9902
9903 if (mac_vals.xmac_addr)
9904 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
9905 if (mac_vals.umac_addr)
9906 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
9907 if (mac_vals.emac_addr)
9908 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
9909 if (mac_vals.bmac_addr) {
9910 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9911 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9912 }
9913
9914 rc = bnx2x_prev_mark_path(bp, prev_undi);
9915 if (rc) {
9916 bnx2x_prev_mcp_done(bp);
9917 return rc;
9918 }
9919
9920 return bnx2x_prev_mcp_done(bp);
9921 }
9922
9923 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
9924 * and boot began, or when kdump kernel was loaded. Either case would invalidate
9925 * the addresses of the transaction, resulting in was-error bit set in the pci
9926 * causing all hw-to-host pcie transactions to timeout. If this happened we want
9927 * to clear the interrupt which detected this from the pglueb and the was done
9928 * bit
9929 */
9930 static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
9931 {
9932 if (!CHIP_IS_E1x(bp)) {
9933 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
9934 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9935 BNX2X_ERR("was error bit was found to be set in pglueb upon startup. Clearing");
9936 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9937 1 << BP_FUNC(bp));
9938 }
9939 }
9940 }
9941
9942 static int bnx2x_prev_unload(struct bnx2x *bp)
9943 {
9944 int time_counter = 10;
9945 u32 rc, fw, hw_lock_reg, hw_lock_val;
9946 struct bnx2x_prev_path_list *prev_list;
9947 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
9948
9949 /* clear hw from errors which may have resulted from an interrupted
9950 * dmae transaction.
9951 */
9952 bnx2x_prev_interrupted_dmae(bp);
9953
9954 /* Release previously held locks */
9955 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
9956 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
9957 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
9958
9959 hw_lock_val = (REG_RD(bp, hw_lock_reg));
9960 if (hw_lock_val) {
9961 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9962 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
9963 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
9964 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
9965 }
9966
9967 BNX2X_DEV_INFO("Release Previously held hw lock\n");
9968 REG_WR(bp, hw_lock_reg, 0xffffffff);
9969 } else
9970 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
9971
9972 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
9973 BNX2X_DEV_INFO("Release previously held alr\n");
9974 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
9975 }
9976
9977 do {
9978 /* Lock MCP using an unload request */
9979 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9980 if (!fw) {
9981 BNX2X_ERR("MCP response failure, aborting\n");
9982 rc = -EBUSY;
9983 break;
9984 }
9985
9986 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9987 rc = bnx2x_prev_unload_common(bp);
9988 break;
9989 }
9990
9991 /* non-common reply from MCP night require looping */
9992 rc = bnx2x_prev_unload_uncommon(bp);
9993 if (rc != BNX2X_PREV_WAIT_NEEDED)
9994 break;
9995
9996 msleep(20);
9997 } while (--time_counter);
9998
9999 if (!time_counter || rc) {
10000 BNX2X_ERR("Failed unloading previous driver, aborting\n");
10001 rc = -EBUSY;
10002 }
10003
10004 /* Mark function if its port was used to boot from SAN */
10005 prev_list = bnx2x_prev_path_get_entry(bp);
10006 if (prev_list && (prev_list->undi & (1 << BP_PORT(bp))))
10007 bp->link_params.feature_config_flags |=
10008 FEATURE_CONFIG_BOOT_FROM_SAN;
10009
10010 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10011
10012 return rc;
10013 }
10014
10015 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10016 {
10017 u32 val, val2, val3, val4, id, boot_mode;
10018 u16 pmc;
10019
10020 /* Get the chip revision id and number. */
10021 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10022 val = REG_RD(bp, MISC_REG_CHIP_NUM);
10023 id = ((val & 0xffff) << 16);
10024 val = REG_RD(bp, MISC_REG_CHIP_REV);
10025 id |= ((val & 0xf) << 12);
10026 val = REG_RD(bp, MISC_REG_CHIP_METAL);
10027 id |= ((val & 0xff) << 4);
10028 val = REG_RD(bp, MISC_REG_BOND_ID);
10029 id |= (val & 0xf);
10030 bp->common.chip_id = id;
10031
10032 /* force 57811 according to MISC register */
10033 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10034 if (CHIP_IS_57810(bp))
10035 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10036 (bp->common.chip_id & 0x0000FFFF);
10037 else if (CHIP_IS_57810_MF(bp))
10038 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10039 (bp->common.chip_id & 0x0000FFFF);
10040 bp->common.chip_id |= 0x1;
10041 }
10042
10043 /* Set doorbell size */
10044 bp->db_size = (1 << BNX2X_DB_SHIFT);
10045
10046 if (!CHIP_IS_E1x(bp)) {
10047 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10048 if ((val & 1) == 0)
10049 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10050 else
10051 val = (val >> 1) & 1;
10052 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10053 "2_PORT_MODE");
10054 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10055 CHIP_2_PORT_MODE;
10056
10057 if (CHIP_MODE_IS_4_PORT(bp))
10058 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
10059 else
10060 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
10061 } else {
10062 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10063 bp->pfid = bp->pf_num; /* 0..7 */
10064 }
10065
10066 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10067
10068 bp->link_params.chip_id = bp->common.chip_id;
10069 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10070
10071 val = (REG_RD(bp, 0x2874) & 0x55);
10072 if ((bp->common.chip_id & 0x1) ||
10073 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10074 bp->flags |= ONE_PORT_FLAG;
10075 BNX2X_DEV_INFO("single port device\n");
10076 }
10077
10078 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10079 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10080 (val & MCPR_NVM_CFG4_FLASH_SIZE));
10081 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10082 bp->common.flash_size, bp->common.flash_size);
10083
10084 bnx2x_init_shmem(bp);
10085
10086
10087
10088 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10089 MISC_REG_GENERIC_CR_1 :
10090 MISC_REG_GENERIC_CR_0));
10091
10092 bp->link_params.shmem_base = bp->common.shmem_base;
10093 bp->link_params.shmem2_base = bp->common.shmem2_base;
10094 if (SHMEM2_RD(bp, size) >
10095 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10096 bp->link_params.lfa_base =
10097 REG_RD(bp, bp->common.shmem2_base +
10098 (u32)offsetof(struct shmem2_region,
10099 lfa_host_addr[BP_PORT(bp)]));
10100 else
10101 bp->link_params.lfa_base = 0;
10102 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
10103 bp->common.shmem_base, bp->common.shmem2_base);
10104
10105 if (!bp->common.shmem_base) {
10106 BNX2X_DEV_INFO("MCP not active\n");
10107 bp->flags |= NO_MCP_FLAG;
10108 return;
10109 }
10110
10111 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10112 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10113
10114 bp->link_params.hw_led_mode = ((bp->common.hw_config &
10115 SHARED_HW_CFG_LED_MODE_MASK) >>
10116 SHARED_HW_CFG_LED_MODE_SHIFT);
10117
10118 bp->link_params.feature_config_flags = 0;
10119 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10120 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10121 bp->link_params.feature_config_flags |=
10122 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10123 else
10124 bp->link_params.feature_config_flags &=
10125 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10126
10127 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10128 bp->common.bc_ver = val;
10129 BNX2X_DEV_INFO("bc_ver %X\n", val);
10130 if (val < BNX2X_BC_VER) {
10131 /* for now only warn
10132 * later we might need to enforce this */
10133 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10134 BNX2X_BC_VER, val);
10135 }
10136 bp->link_params.feature_config_flags |=
10137 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10138 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10139
10140 bp->link_params.feature_config_flags |=
10141 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10142 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10143 bp->link_params.feature_config_flags |=
10144 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10145 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10146 bp->link_params.feature_config_flags |=
10147 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10148 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10149
10150 bp->link_params.feature_config_flags |=
10151 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10152 FEATURE_CONFIG_MT_SUPPORT : 0;
10153
10154 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10155 BC_SUPPORTS_PFC_STATS : 0;
10156
10157 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10158 BC_SUPPORTS_FCOE_FEATURES : 0;
10159
10160 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10161 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10162 boot_mode = SHMEM_RD(bp,
10163 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10164 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10165 switch (boot_mode) {
10166 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10167 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10168 break;
10169 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10170 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10171 break;
10172 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10173 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10174 break;
10175 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10176 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10177 break;
10178 }
10179
10180 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
10181 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10182
10183 BNX2X_DEV_INFO("%sWoL capable\n",
10184 (bp->flags & NO_WOL_FLAG) ? "not " : "");
10185
10186 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10187 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10188 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10189 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10190
10191 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10192 val, val2, val3, val4);
10193 }
10194
10195 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10196 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10197
10198 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10199 {
10200 int pfid = BP_FUNC(bp);
10201 int igu_sb_id;
10202 u32 val;
10203 u8 fid, igu_sb_cnt = 0;
10204
10205 bp->igu_base_sb = 0xff;
10206 if (CHIP_INT_MODE_IS_BC(bp)) {
10207 int vn = BP_VN(bp);
10208 igu_sb_cnt = bp->igu_sb_cnt;
10209 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10210 FP_SB_MAX_E1x;
10211
10212 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
10213 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10214
10215 return 0;
10216 }
10217
10218 /* IGU in normal mode - read CAM */
10219 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10220 igu_sb_id++) {
10221 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10222 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10223 continue;
10224 fid = IGU_FID(val);
10225 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10226 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10227 continue;
10228 if (IGU_VEC(val) == 0)
10229 /* default status block */
10230 bp->igu_dsb_id = igu_sb_id;
10231 else {
10232 if (bp->igu_base_sb == 0xff)
10233 bp->igu_base_sb = igu_sb_id;
10234 igu_sb_cnt++;
10235 }
10236 }
10237 }
10238
10239 #ifdef CONFIG_PCI_MSI
10240 /* Due to new PF resource allocation by MFW T7.4 and above, it's
10241 * optional that number of CAM entries will not be equal to the value
10242 * advertised in PCI.
10243 * Driver should use the minimal value of both as the actual status
10244 * block count
10245 */
10246 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10247 #endif
10248
10249 if (igu_sb_cnt == 0) {
10250 BNX2X_ERR("CAM configuration error\n");
10251 return -EINVAL;
10252 }
10253
10254 return 0;
10255 }
10256
10257 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10258 {
10259 int cfg_size = 0, idx, port = BP_PORT(bp);
10260
10261 /* Aggregation of supported attributes of all external phys */
10262 bp->port.supported[0] = 0;
10263 bp->port.supported[1] = 0;
10264 switch (bp->link_params.num_phys) {
10265 case 1:
10266 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10267 cfg_size = 1;
10268 break;
10269 case 2:
10270 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10271 cfg_size = 1;
10272 break;
10273 case 3:
10274 if (bp->link_params.multi_phy_config &
10275 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10276 bp->port.supported[1] =
10277 bp->link_params.phy[EXT_PHY1].supported;
10278 bp->port.supported[0] =
10279 bp->link_params.phy[EXT_PHY2].supported;
10280 } else {
10281 bp->port.supported[0] =
10282 bp->link_params.phy[EXT_PHY1].supported;
10283 bp->port.supported[1] =
10284 bp->link_params.phy[EXT_PHY2].supported;
10285 }
10286 cfg_size = 2;
10287 break;
10288 }
10289
10290 if (!(bp->port.supported[0] || bp->port.supported[1])) {
10291 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10292 SHMEM_RD(bp,
10293 dev_info.port_hw_config[port].external_phy_config),
10294 SHMEM_RD(bp,
10295 dev_info.port_hw_config[port].external_phy_config2));
10296 return;
10297 }
10298
10299 if (CHIP_IS_E3(bp))
10300 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10301 else {
10302 switch (switch_cfg) {
10303 case SWITCH_CFG_1G:
10304 bp->port.phy_addr = REG_RD(
10305 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10306 break;
10307 case SWITCH_CFG_10G:
10308 bp->port.phy_addr = REG_RD(
10309 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10310 break;
10311 default:
10312 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10313 bp->port.link_config[0]);
10314 return;
10315 }
10316 }
10317 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10318 /* mask what we support according to speed_cap_mask per configuration */
10319 for (idx = 0; idx < cfg_size; idx++) {
10320 if (!(bp->link_params.speed_cap_mask[idx] &
10321 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10322 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10323
10324 if (!(bp->link_params.speed_cap_mask[idx] &
10325 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
10326 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
10327
10328 if (!(bp->link_params.speed_cap_mask[idx] &
10329 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
10330 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
10331
10332 if (!(bp->link_params.speed_cap_mask[idx] &
10333 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
10334 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
10335
10336 if (!(bp->link_params.speed_cap_mask[idx] &
10337 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
10338 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
10339 SUPPORTED_1000baseT_Full);
10340
10341 if (!(bp->link_params.speed_cap_mask[idx] &
10342 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
10343 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
10344
10345 if (!(bp->link_params.speed_cap_mask[idx] &
10346 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
10347 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
10348
10349 }
10350
10351 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10352 bp->port.supported[1]);
10353 }
10354
10355 static void bnx2x_link_settings_requested(struct bnx2x *bp)
10356 {
10357 u32 link_config, idx, cfg_size = 0;
10358 bp->port.advertising[0] = 0;
10359 bp->port.advertising[1] = 0;
10360 switch (bp->link_params.num_phys) {
10361 case 1:
10362 case 2:
10363 cfg_size = 1;
10364 break;
10365 case 3:
10366 cfg_size = 2;
10367 break;
10368 }
10369 for (idx = 0; idx < cfg_size; idx++) {
10370 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10371 link_config = bp->port.link_config[idx];
10372 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
10373 case PORT_FEATURE_LINK_SPEED_AUTO:
10374 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10375 bp->link_params.req_line_speed[idx] =
10376 SPEED_AUTO_NEG;
10377 bp->port.advertising[idx] |=
10378 bp->port.supported[idx];
10379 if (bp->link_params.phy[EXT_PHY1].type ==
10380 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10381 bp->port.advertising[idx] |=
10382 (SUPPORTED_100baseT_Half |
10383 SUPPORTED_100baseT_Full);
10384 } else {
10385 /* force 10G, no AN */
10386 bp->link_params.req_line_speed[idx] =
10387 SPEED_10000;
10388 bp->port.advertising[idx] |=
10389 (ADVERTISED_10000baseT_Full |
10390 ADVERTISED_FIBRE);
10391 continue;
10392 }
10393 break;
10394
10395 case PORT_FEATURE_LINK_SPEED_10M_FULL:
10396 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10397 bp->link_params.req_line_speed[idx] =
10398 SPEED_10;
10399 bp->port.advertising[idx] |=
10400 (ADVERTISED_10baseT_Full |
10401 ADVERTISED_TP);
10402 } else {
10403 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10404 link_config,
10405 bp->link_params.speed_cap_mask[idx]);
10406 return;
10407 }
10408 break;
10409
10410 case PORT_FEATURE_LINK_SPEED_10M_HALF:
10411 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10412 bp->link_params.req_line_speed[idx] =
10413 SPEED_10;
10414 bp->link_params.req_duplex[idx] =
10415 DUPLEX_HALF;
10416 bp->port.advertising[idx] |=
10417 (ADVERTISED_10baseT_Half |
10418 ADVERTISED_TP);
10419 } else {
10420 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10421 link_config,
10422 bp->link_params.speed_cap_mask[idx]);
10423 return;
10424 }
10425 break;
10426
10427 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10428 if (bp->port.supported[idx] &
10429 SUPPORTED_100baseT_Full) {
10430 bp->link_params.req_line_speed[idx] =
10431 SPEED_100;
10432 bp->port.advertising[idx] |=
10433 (ADVERTISED_100baseT_Full |
10434 ADVERTISED_TP);
10435 } else {
10436 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10437 link_config,
10438 bp->link_params.speed_cap_mask[idx]);
10439 return;
10440 }
10441 break;
10442
10443 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10444 if (bp->port.supported[idx] &
10445 SUPPORTED_100baseT_Half) {
10446 bp->link_params.req_line_speed[idx] =
10447 SPEED_100;
10448 bp->link_params.req_duplex[idx] =
10449 DUPLEX_HALF;
10450 bp->port.advertising[idx] |=
10451 (ADVERTISED_100baseT_Half |
10452 ADVERTISED_TP);
10453 } else {
10454 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10455 link_config,
10456 bp->link_params.speed_cap_mask[idx]);
10457 return;
10458 }
10459 break;
10460
10461 case PORT_FEATURE_LINK_SPEED_1G:
10462 if (bp->port.supported[idx] &
10463 SUPPORTED_1000baseT_Full) {
10464 bp->link_params.req_line_speed[idx] =
10465 SPEED_1000;
10466 bp->port.advertising[idx] |=
10467 (ADVERTISED_1000baseT_Full |
10468 ADVERTISED_TP);
10469 } else {
10470 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10471 link_config,
10472 bp->link_params.speed_cap_mask[idx]);
10473 return;
10474 }
10475 break;
10476
10477 case PORT_FEATURE_LINK_SPEED_2_5G:
10478 if (bp->port.supported[idx] &
10479 SUPPORTED_2500baseX_Full) {
10480 bp->link_params.req_line_speed[idx] =
10481 SPEED_2500;
10482 bp->port.advertising[idx] |=
10483 (ADVERTISED_2500baseX_Full |
10484 ADVERTISED_TP);
10485 } else {
10486 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10487 link_config,
10488 bp->link_params.speed_cap_mask[idx]);
10489 return;
10490 }
10491 break;
10492
10493 case PORT_FEATURE_LINK_SPEED_10G_CX4:
10494 if (bp->port.supported[idx] &
10495 SUPPORTED_10000baseT_Full) {
10496 bp->link_params.req_line_speed[idx] =
10497 SPEED_10000;
10498 bp->port.advertising[idx] |=
10499 (ADVERTISED_10000baseT_Full |
10500 ADVERTISED_FIBRE);
10501 } else {
10502 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10503 link_config,
10504 bp->link_params.speed_cap_mask[idx]);
10505 return;
10506 }
10507 break;
10508 case PORT_FEATURE_LINK_SPEED_20G:
10509 bp->link_params.req_line_speed[idx] = SPEED_20000;
10510
10511 break;
10512 default:
10513 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10514 link_config);
10515 bp->link_params.req_line_speed[idx] =
10516 SPEED_AUTO_NEG;
10517 bp->port.advertising[idx] =
10518 bp->port.supported[idx];
10519 break;
10520 }
10521
10522 bp->link_params.req_flow_ctrl[idx] = (link_config &
10523 PORT_FEATURE_FLOW_CONTROL_MASK);
10524 if (bp->link_params.req_flow_ctrl[idx] ==
10525 BNX2X_FLOW_CTRL_AUTO) {
10526 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
10527 bp->link_params.req_flow_ctrl[idx] =
10528 BNX2X_FLOW_CTRL_NONE;
10529 else
10530 bnx2x_set_requested_fc(bp);
10531 }
10532
10533 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10534 bp->link_params.req_line_speed[idx],
10535 bp->link_params.req_duplex[idx],
10536 bp->link_params.req_flow_ctrl[idx],
10537 bp->port.advertising[idx]);
10538 }
10539 }
10540
10541 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
10542 {
10543 mac_hi = cpu_to_be16(mac_hi);
10544 mac_lo = cpu_to_be32(mac_lo);
10545 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
10546 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
10547 }
10548
10549 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
10550 {
10551 int port = BP_PORT(bp);
10552 u32 config;
10553 u32 ext_phy_type, ext_phy_config, eee_mode;
10554
10555 bp->link_params.bp = bp;
10556 bp->link_params.port = port;
10557
10558 bp->link_params.lane_config =
10559 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
10560
10561 bp->link_params.speed_cap_mask[0] =
10562 SHMEM_RD(bp,
10563 dev_info.port_hw_config[port].speed_capability_mask);
10564 bp->link_params.speed_cap_mask[1] =
10565 SHMEM_RD(bp,
10566 dev_info.port_hw_config[port].speed_capability_mask2);
10567 bp->port.link_config[0] =
10568 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10569
10570 bp->port.link_config[1] =
10571 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
10572
10573 bp->link_params.multi_phy_config =
10574 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
10575 /* If the device is capable of WoL, set the default state according
10576 * to the HW
10577 */
10578 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
10579 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10580 (config & PORT_FEATURE_WOL_ENABLED));
10581
10582 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10583 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
10584 bp->flags |= NO_ISCSI_FLAG;
10585 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10586 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
10587 bp->flags |= NO_FCOE_FLAG;
10588
10589 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
10590 bp->link_params.lane_config,
10591 bp->link_params.speed_cap_mask[0],
10592 bp->port.link_config[0]);
10593
10594 bp->link_params.switch_cfg = (bp->port.link_config[0] &
10595 PORT_FEATURE_CONNECTED_SWITCH_MASK);
10596 bnx2x_phy_probe(&bp->link_params);
10597 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
10598
10599 bnx2x_link_settings_requested(bp);
10600
10601 /*
10602 * If connected directly, work with the internal PHY, otherwise, work
10603 * with the external PHY
10604 */
10605 ext_phy_config =
10606 SHMEM_RD(bp,
10607 dev_info.port_hw_config[port].external_phy_config);
10608 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10609 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
10610 bp->mdio.prtad = bp->port.phy_addr;
10611
10612 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10613 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10614 bp->mdio.prtad =
10615 XGXS_EXT_PHY_ADDR(ext_phy_config);
10616
10617 /* Configure link feature according to nvram value */
10618 eee_mode = (((SHMEM_RD(bp, dev_info.
10619 port_feature_config[port].eee_power_mode)) &
10620 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
10621 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
10622 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10623 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10624 EEE_MODE_ENABLE_LPI |
10625 EEE_MODE_OUTPUT_TIME;
10626 } else {
10627 bp->link_params.eee_mode = 0;
10628 }
10629 }
10630
10631 void bnx2x_get_iscsi_info(struct bnx2x *bp)
10632 {
10633 u32 no_flags = NO_ISCSI_FLAG;
10634 int port = BP_PORT(bp);
10635 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10636 drv_lic_key[port].max_iscsi_conn);
10637
10638 if (!CNIC_SUPPORT(bp)) {
10639 bp->flags |= no_flags;
10640 return;
10641 }
10642
10643 /* Get the number of maximum allowed iSCSI connections */
10644 bp->cnic_eth_dev.max_iscsi_conn =
10645 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10646 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
10647
10648 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10649 bp->cnic_eth_dev.max_iscsi_conn);
10650
10651 /*
10652 * If maximum allowed number of connections is zero -
10653 * disable the feature.
10654 */
10655 if (!bp->cnic_eth_dev.max_iscsi_conn)
10656 bp->flags |= no_flags;
10657
10658 }
10659
10660 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
10661 {
10662 /* Port info */
10663 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10664 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
10665 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10666 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
10667
10668 /* Node info */
10669 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10670 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
10671 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10672 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
10673 }
10674 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
10675 {
10676 int port = BP_PORT(bp);
10677 int func = BP_ABS_FUNC(bp);
10678 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10679 drv_lic_key[port].max_fcoe_conn);
10680
10681 if (!CNIC_SUPPORT(bp)) {
10682 bp->flags |= NO_FCOE_FLAG;
10683 return;
10684 }
10685
10686 /* Get the number of maximum allowed FCoE connections */
10687 bp->cnic_eth_dev.max_fcoe_conn =
10688 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
10689 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
10690
10691 /* Read the WWN: */
10692 if (!IS_MF(bp)) {
10693 /* Port info */
10694 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10695 SHMEM_RD(bp,
10696 dev_info.port_hw_config[port].
10697 fcoe_wwn_port_name_upper);
10698 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10699 SHMEM_RD(bp,
10700 dev_info.port_hw_config[port].
10701 fcoe_wwn_port_name_lower);
10702
10703 /* Node info */
10704 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10705 SHMEM_RD(bp,
10706 dev_info.port_hw_config[port].
10707 fcoe_wwn_node_name_upper);
10708 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10709 SHMEM_RD(bp,
10710 dev_info.port_hw_config[port].
10711 fcoe_wwn_node_name_lower);
10712 } else if (!IS_MF_SD(bp)) {
10713 /*
10714 * Read the WWN info only if the FCoE feature is enabled for
10715 * this function.
10716 */
10717 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
10718 bnx2x_get_ext_wwn_info(bp, func);
10719
10720 } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
10721 bnx2x_get_ext_wwn_info(bp, func);
10722 }
10723
10724 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
10725
10726 /*
10727 * If maximum allowed number of connections is zero -
10728 * disable the feature.
10729 */
10730 if (!bp->cnic_eth_dev.max_fcoe_conn)
10731 bp->flags |= NO_FCOE_FLAG;
10732 }
10733
10734 static void bnx2x_get_cnic_info(struct bnx2x *bp)
10735 {
10736 /*
10737 * iSCSI may be dynamically disabled but reading
10738 * info here we will decrease memory usage by driver
10739 * if the feature is disabled for good
10740 */
10741 bnx2x_get_iscsi_info(bp);
10742 bnx2x_get_fcoe_info(bp);
10743 }
10744
10745 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
10746 {
10747 u32 val, val2;
10748 int func = BP_ABS_FUNC(bp);
10749 int port = BP_PORT(bp);
10750 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
10751 u8 *fip_mac = bp->fip_mac;
10752
10753 if (IS_MF(bp)) {
10754 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
10755 * FCoE MAC then the appropriate feature should be disabled.
10756 * In non SD mode features configuration comes from struct
10757 * func_ext_config.
10758 */
10759 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
10760 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
10761 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
10762 val2 = MF_CFG_RD(bp, func_ext_config[func].
10763 iscsi_mac_addr_upper);
10764 val = MF_CFG_RD(bp, func_ext_config[func].
10765 iscsi_mac_addr_lower);
10766 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10767 BNX2X_DEV_INFO
10768 ("Read iSCSI MAC: %pM\n", iscsi_mac);
10769 } else {
10770 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
10771 }
10772
10773 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
10774 val2 = MF_CFG_RD(bp, func_ext_config[func].
10775 fcoe_mac_addr_upper);
10776 val = MF_CFG_RD(bp, func_ext_config[func].
10777 fcoe_mac_addr_lower);
10778 bnx2x_set_mac_buf(fip_mac, val, val2);
10779 BNX2X_DEV_INFO
10780 ("Read FCoE L2 MAC: %pM\n", fip_mac);
10781 } else {
10782 bp->flags |= NO_FCOE_FLAG;
10783 }
10784
10785 bp->mf_ext_config = cfg;
10786
10787 } else { /* SD MODE */
10788 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
10789 /* use primary mac as iscsi mac */
10790 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
10791
10792 BNX2X_DEV_INFO("SD ISCSI MODE\n");
10793 BNX2X_DEV_INFO
10794 ("Read iSCSI MAC: %pM\n", iscsi_mac);
10795 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
10796 /* use primary mac as fip mac */
10797 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
10798 BNX2X_DEV_INFO("SD FCoE MODE\n");
10799 BNX2X_DEV_INFO
10800 ("Read FIP MAC: %pM\n", fip_mac);
10801 }
10802 }
10803
10804 if (IS_MF_STORAGE_SD(bp))
10805 /* Zero primary MAC configuration */
10806 memset(bp->dev->dev_addr, 0, ETH_ALEN);
10807
10808 if (IS_MF_FCOE_AFEX(bp) || IS_MF_FCOE_SD(bp))
10809 /* use FIP MAC as primary MAC */
10810 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
10811
10812 } else {
10813 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10814 iscsi_mac_upper);
10815 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10816 iscsi_mac_lower);
10817 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10818
10819 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10820 fcoe_fip_mac_upper);
10821 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10822 fcoe_fip_mac_lower);
10823 bnx2x_set_mac_buf(fip_mac, val, val2);
10824 }
10825
10826 /* Disable iSCSI OOO if MAC configuration is invalid. */
10827 if (!is_valid_ether_addr(iscsi_mac)) {
10828 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
10829 memset(iscsi_mac, 0, ETH_ALEN);
10830 }
10831
10832 /* Disable FCoE if MAC configuration is invalid. */
10833 if (!is_valid_ether_addr(fip_mac)) {
10834 bp->flags |= NO_FCOE_FLAG;
10835 memset(bp->fip_mac, 0, ETH_ALEN);
10836 }
10837 }
10838
10839 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
10840 {
10841 u32 val, val2;
10842 int func = BP_ABS_FUNC(bp);
10843 int port = BP_PORT(bp);
10844
10845 /* Zero primary MAC configuration */
10846 memset(bp->dev->dev_addr, 0, ETH_ALEN);
10847
10848 if (BP_NOMCP(bp)) {
10849 BNX2X_ERROR("warning: random MAC workaround active\n");
10850 eth_hw_addr_random(bp->dev);
10851 } else if (IS_MF(bp)) {
10852 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
10853 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
10854 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
10855 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
10856 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10857
10858 if (CNIC_SUPPORT(bp))
10859 bnx2x_get_cnic_mac_hwinfo(bp);
10860 } else {
10861 /* in SF read MACs from port configuration */
10862 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
10863 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
10864 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10865
10866 if (CNIC_SUPPORT(bp))
10867 bnx2x_get_cnic_mac_hwinfo(bp);
10868 }
10869
10870 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
10871
10872 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
10873 dev_err(&bp->pdev->dev,
10874 "bad Ethernet MAC address configuration: %pM\n"
10875 "change it manually before bringing up the appropriate network interface\n",
10876 bp->dev->dev_addr);
10877 }
10878
10879 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
10880 {
10881 int tmp;
10882 u32 cfg;
10883
10884 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
10885 /* Take function: tmp = func */
10886 tmp = BP_ABS_FUNC(bp);
10887 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
10888 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
10889 } else {
10890 /* Take port: tmp = port */
10891 tmp = BP_PORT(bp);
10892 cfg = SHMEM_RD(bp,
10893 dev_info.port_hw_config[tmp].generic_features);
10894 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
10895 }
10896 return cfg;
10897 }
10898
10899 static int bnx2x_get_hwinfo(struct bnx2x *bp)
10900 {
10901 int /*abs*/func = BP_ABS_FUNC(bp);
10902 int vn;
10903 u32 val = 0;
10904 int rc = 0;
10905
10906 bnx2x_get_common_hwinfo(bp);
10907
10908 /*
10909 * initialize IGU parameters
10910 */
10911 if (CHIP_IS_E1x(bp)) {
10912 bp->common.int_block = INT_BLOCK_HC;
10913
10914 bp->igu_dsb_id = DEF_SB_IGU_ID;
10915 bp->igu_base_sb = 0;
10916 } else {
10917 bp->common.int_block = INT_BLOCK_IGU;
10918
10919 /* do not allow device reset during IGU info preocessing */
10920 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10921
10922 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
10923
10924 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10925 int tout = 5000;
10926
10927 BNX2X_DEV_INFO("FORCING Normal Mode\n");
10928
10929 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
10930 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
10931 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
10932
10933 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10934 tout--;
10935 usleep_range(1000, 1000);
10936 }
10937
10938 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10939 dev_err(&bp->pdev->dev,
10940 "FORCING Normal Mode failed!!!\n");
10941 bnx2x_release_hw_lock(bp,
10942 HW_LOCK_RESOURCE_RESET);
10943 return -EPERM;
10944 }
10945 }
10946
10947 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10948 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
10949 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
10950 } else
10951 BNX2X_DEV_INFO("IGU Normal Mode\n");
10952
10953 rc = bnx2x_get_igu_cam_info(bp);
10954 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10955 if (rc)
10956 return rc;
10957 }
10958
10959 /*
10960 * set base FW non-default (fast path) status block id, this value is
10961 * used to initialize the fw_sb_id saved on the fp/queue structure to
10962 * determine the id used by the FW.
10963 */
10964 if (CHIP_IS_E1x(bp))
10965 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
10966 else /*
10967 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
10968 * the same queue are indicated on the same IGU SB). So we prefer
10969 * FW and IGU SBs to be the same value.
10970 */
10971 bp->base_fw_ndsb = bp->igu_base_sb;
10972
10973 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
10974 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
10975 bp->igu_sb_cnt, bp->base_fw_ndsb);
10976
10977 /*
10978 * Initialize MF configuration
10979 */
10980
10981 bp->mf_ov = 0;
10982 bp->mf_mode = 0;
10983 vn = BP_VN(bp);
10984
10985 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
10986 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
10987 bp->common.shmem2_base, SHMEM2_RD(bp, size),
10988 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
10989
10990 if (SHMEM2_HAS(bp, mf_cfg_addr))
10991 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
10992 else
10993 bp->common.mf_cfg_base = bp->common.shmem_base +
10994 offsetof(struct shmem_region, func_mb) +
10995 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
10996 /*
10997 * get mf configuration:
10998 * 1. existence of MF configuration
10999 * 2. MAC address must be legal (check only upper bytes)
11000 * for Switch-Independent mode;
11001 * OVLAN must be legal for Switch-Dependent mode
11002 * 3. SF_MODE configures specific MF mode
11003 */
11004 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11005 /* get mf configuration */
11006 val = SHMEM_RD(bp,
11007 dev_info.shared_feature_config.config);
11008 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11009
11010 switch (val) {
11011 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11012 val = MF_CFG_RD(bp, func_mf_config[func].
11013 mac_upper);
11014 /* check for legal mac (upper bytes)*/
11015 if (val != 0xffff) {
11016 bp->mf_mode = MULTI_FUNCTION_SI;
11017 bp->mf_config[vn] = MF_CFG_RD(bp,
11018 func_mf_config[func].config);
11019 } else
11020 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11021 break;
11022 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11023 if ((!CHIP_IS_E1x(bp)) &&
11024 (MF_CFG_RD(bp, func_mf_config[func].
11025 mac_upper) != 0xffff) &&
11026 (SHMEM2_HAS(bp,
11027 afex_driver_support))) {
11028 bp->mf_mode = MULTI_FUNCTION_AFEX;
11029 bp->mf_config[vn] = MF_CFG_RD(bp,
11030 func_mf_config[func].config);
11031 } else {
11032 BNX2X_DEV_INFO("can not configure afex mode\n");
11033 }
11034 break;
11035 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11036 /* get OV configuration */
11037 val = MF_CFG_RD(bp,
11038 func_mf_config[FUNC_0].e1hov_tag);
11039 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11040
11041 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11042 bp->mf_mode = MULTI_FUNCTION_SD;
11043 bp->mf_config[vn] = MF_CFG_RD(bp,
11044 func_mf_config[func].config);
11045 } else
11046 BNX2X_DEV_INFO("illegal OV for SD\n");
11047 break;
11048 default:
11049 /* Unknown configuration: reset mf_config */
11050 bp->mf_config[vn] = 0;
11051 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11052 }
11053 }
11054
11055 BNX2X_DEV_INFO("%s function mode\n",
11056 IS_MF(bp) ? "multi" : "single");
11057
11058 switch (bp->mf_mode) {
11059 case MULTI_FUNCTION_SD:
11060 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11061 FUNC_MF_CFG_E1HOV_TAG_MASK;
11062 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11063 bp->mf_ov = val;
11064 bp->path_has_ovlan = true;
11065
11066 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11067 func, bp->mf_ov, bp->mf_ov);
11068 } else {
11069 dev_err(&bp->pdev->dev,
11070 "No valid MF OV for func %d, aborting\n",
11071 func);
11072 return -EPERM;
11073 }
11074 break;
11075 case MULTI_FUNCTION_AFEX:
11076 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11077 break;
11078 case MULTI_FUNCTION_SI:
11079 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11080 func);
11081 break;
11082 default:
11083 if (vn) {
11084 dev_err(&bp->pdev->dev,
11085 "VN %d is in a single function mode, aborting\n",
11086 vn);
11087 return -EPERM;
11088 }
11089 break;
11090 }
11091
11092 /* check if other port on the path needs ovlan:
11093 * Since MF configuration is shared between ports
11094 * Possible mixed modes are only
11095 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11096 */
11097 if (CHIP_MODE_IS_4_PORT(bp) &&
11098 !bp->path_has_ovlan &&
11099 !IS_MF(bp) &&
11100 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11101 u8 other_port = !BP_PORT(bp);
11102 u8 other_func = BP_PATH(bp) + 2*other_port;
11103 val = MF_CFG_RD(bp,
11104 func_mf_config[other_func].e1hov_tag);
11105 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11106 bp->path_has_ovlan = true;
11107 }
11108 }
11109
11110 /* adjust igu_sb_cnt to MF for E1x */
11111 if (CHIP_IS_E1x(bp) && IS_MF(bp))
11112 bp->igu_sb_cnt /= E1HVN_MAX;
11113
11114 /* port info */
11115 bnx2x_get_port_hwinfo(bp);
11116
11117 /* Get MAC addresses */
11118 bnx2x_get_mac_hwinfo(bp);
11119
11120 bnx2x_get_cnic_info(bp);
11121
11122 return rc;
11123 }
11124
11125 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11126 {
11127 int cnt, i, block_end, rodi;
11128 char vpd_start[BNX2X_VPD_LEN+1];
11129 char str_id_reg[VENDOR_ID_LEN+1];
11130 char str_id_cap[VENDOR_ID_LEN+1];
11131 char *vpd_data;
11132 char *vpd_extended_data = NULL;
11133 u8 len;
11134
11135 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11136 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11137
11138 if (cnt < BNX2X_VPD_LEN)
11139 goto out_not_found;
11140
11141 /* VPD RO tag should be first tag after identifier string, hence
11142 * we should be able to find it in first BNX2X_VPD_LEN chars
11143 */
11144 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11145 PCI_VPD_LRDT_RO_DATA);
11146 if (i < 0)
11147 goto out_not_found;
11148
11149 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11150 pci_vpd_lrdt_size(&vpd_start[i]);
11151
11152 i += PCI_VPD_LRDT_TAG_SIZE;
11153
11154 if (block_end > BNX2X_VPD_LEN) {
11155 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11156 if (vpd_extended_data == NULL)
11157 goto out_not_found;
11158
11159 /* read rest of vpd image into vpd_extended_data */
11160 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11161 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11162 block_end - BNX2X_VPD_LEN,
11163 vpd_extended_data + BNX2X_VPD_LEN);
11164 if (cnt < (block_end - BNX2X_VPD_LEN))
11165 goto out_not_found;
11166 vpd_data = vpd_extended_data;
11167 } else
11168 vpd_data = vpd_start;
11169
11170 /* now vpd_data holds full vpd content in both cases */
11171
11172 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11173 PCI_VPD_RO_KEYWORD_MFR_ID);
11174 if (rodi < 0)
11175 goto out_not_found;
11176
11177 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11178
11179 if (len != VENDOR_ID_LEN)
11180 goto out_not_found;
11181
11182 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11183
11184 /* vendor specific info */
11185 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11186 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11187 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11188 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11189
11190 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11191 PCI_VPD_RO_KEYWORD_VENDOR0);
11192 if (rodi >= 0) {
11193 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11194
11195 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11196
11197 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11198 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11199 bp->fw_ver[len] = ' ';
11200 }
11201 }
11202 kfree(vpd_extended_data);
11203 return;
11204 }
11205 out_not_found:
11206 kfree(vpd_extended_data);
11207 return;
11208 }
11209
11210 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
11211 {
11212 u32 flags = 0;
11213
11214 if (CHIP_REV_IS_FPGA(bp))
11215 SET_FLAGS(flags, MODE_FPGA);
11216 else if (CHIP_REV_IS_EMUL(bp))
11217 SET_FLAGS(flags, MODE_EMUL);
11218 else
11219 SET_FLAGS(flags, MODE_ASIC);
11220
11221 if (CHIP_MODE_IS_4_PORT(bp))
11222 SET_FLAGS(flags, MODE_PORT4);
11223 else
11224 SET_FLAGS(flags, MODE_PORT2);
11225
11226 if (CHIP_IS_E2(bp))
11227 SET_FLAGS(flags, MODE_E2);
11228 else if (CHIP_IS_E3(bp)) {
11229 SET_FLAGS(flags, MODE_E3);
11230 if (CHIP_REV(bp) == CHIP_REV_Ax)
11231 SET_FLAGS(flags, MODE_E3_A0);
11232 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11233 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
11234 }
11235
11236 if (IS_MF(bp)) {
11237 SET_FLAGS(flags, MODE_MF);
11238 switch (bp->mf_mode) {
11239 case MULTI_FUNCTION_SD:
11240 SET_FLAGS(flags, MODE_MF_SD);
11241 break;
11242 case MULTI_FUNCTION_SI:
11243 SET_FLAGS(flags, MODE_MF_SI);
11244 break;
11245 case MULTI_FUNCTION_AFEX:
11246 SET_FLAGS(flags, MODE_MF_AFEX);
11247 break;
11248 }
11249 } else
11250 SET_FLAGS(flags, MODE_SF);
11251
11252 #if defined(__LITTLE_ENDIAN)
11253 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11254 #else /*(__BIG_ENDIAN)*/
11255 SET_FLAGS(flags, MODE_BIG_ENDIAN);
11256 #endif
11257 INIT_MODE_FLAGS(bp) = flags;
11258 }
11259
11260 static int bnx2x_init_bp(struct bnx2x *bp)
11261 {
11262 int func;
11263 int rc;
11264
11265 mutex_init(&bp->port.phy_mutex);
11266 mutex_init(&bp->fw_mb_mutex);
11267 spin_lock_init(&bp->stats_lock);
11268
11269
11270 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
11271 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
11272 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
11273 if (IS_PF(bp)) {
11274 rc = bnx2x_get_hwinfo(bp);
11275 if (rc)
11276 return rc;
11277 } else {
11278 random_ether_addr(bp->dev->dev_addr);
11279 }
11280
11281 bnx2x_set_modes_bitmap(bp);
11282
11283 rc = bnx2x_alloc_mem_bp(bp);
11284 if (rc)
11285 return rc;
11286
11287 bnx2x_read_fwinfo(bp);
11288
11289 func = BP_FUNC(bp);
11290
11291 /* need to reset chip if undi was active */
11292 if (IS_PF(bp) && !BP_NOMCP(bp)) {
11293 /* init fw_seq */
11294 bp->fw_seq =
11295 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11296 DRV_MSG_SEQ_NUMBER_MASK;
11297 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11298
11299 bnx2x_prev_unload(bp);
11300 }
11301
11302
11303 if (CHIP_REV_IS_FPGA(bp))
11304 dev_err(&bp->pdev->dev, "FPGA detected\n");
11305
11306 if (BP_NOMCP(bp) && (func == 0))
11307 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
11308
11309 bp->disable_tpa = disable_tpa;
11310 bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
11311
11312 /* Set TPA flags */
11313 if (bp->disable_tpa) {
11314 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11315 bp->dev->features &= ~NETIF_F_LRO;
11316 } else {
11317 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11318 bp->dev->features |= NETIF_F_LRO;
11319 }
11320
11321 if (CHIP_IS_E1(bp))
11322 bp->dropless_fc = 0;
11323 else
11324 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
11325
11326 bp->mrrs = mrrs;
11327
11328 bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
11329 if (IS_VF(bp))
11330 bp->rx_ring_size = MAX_RX_AVAIL;
11331
11332 /* make sure that the numbers are in the right granularity */
11333 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11334 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
11335
11336 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
11337
11338 init_timer(&bp->timer);
11339 bp->timer.expires = jiffies + bp->current_interval;
11340 bp->timer.data = (unsigned long) bp;
11341 bp->timer.function = bnx2x_timer;
11342
11343 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
11344 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
11345 SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
11346 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
11347 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
11348 bnx2x_dcbx_init_params(bp);
11349 } else {
11350 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
11351 }
11352
11353 if (CHIP_IS_E1x(bp))
11354 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
11355 else
11356 bp->cnic_base_cl_id = FP_SB_MAX_E2;
11357
11358 /* multiple tx priority */
11359 if (IS_VF(bp))
11360 bp->max_cos = 1;
11361 else if (CHIP_IS_E1x(bp))
11362 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
11363 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
11364 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
11365 else if (CHIP_IS_E3B0(bp))
11366 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
11367 else
11368 BNX2X_ERR("unknown chip %x revision %x\n",
11369 CHIP_NUM(bp), CHIP_REV(bp));
11370 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
11371
11372 /* We need at least one default status block for slow-path events,
11373 * second status block for the L2 queue, and a third status block for
11374 * CNIC if supproted.
11375 */
11376 if (CNIC_SUPPORT(bp))
11377 bp->min_msix_vec_cnt = 3;
11378 else
11379 bp->min_msix_vec_cnt = 2;
11380 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
11381
11382 return rc;
11383 }
11384
11385
11386 /****************************************************************************
11387 * General service functions
11388 ****************************************************************************/
11389
11390 /*
11391 * net_device service functions
11392 */
11393
11394 static int bnx2x_open_epilog(struct bnx2x *bp)
11395 {
11396 /* Enable sriov via delayed work. This must be done via delayed work
11397 * because it causes the probe of the vf devices to be run, which invoke
11398 * register_netdevice which must have rtnl lock taken. As we are holding
11399 * the lock right now, that could only work if the probe would not take
11400 * the lock. However, as the probe of the vf may be called from other
11401 * contexts as well (such as passthrough to vm failes) it can't assume
11402 * the lock is being held for it. Using delayed work here allows the
11403 * probe code to simply take the lock (i.e. wait for it to be released
11404 * if it is being held).
11405 */
11406 smp_mb__before_clear_bit();
11407 set_bit(BNX2X_SP_RTNL_ENABLE_SRIOV, &bp->sp_rtnl_state);
11408 smp_mb__after_clear_bit();
11409 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11410
11411 return 0;
11412 }
11413
11414 /* called with rtnl_lock */
11415 static int bnx2x_open(struct net_device *dev)
11416 {
11417 struct bnx2x *bp = netdev_priv(dev);
11418 bool global = false;
11419 int other_engine = BP_PATH(bp) ? 0 : 1;
11420 bool other_load_status, load_status;
11421 int rc;
11422
11423 bp->stats_init = true;
11424
11425 netif_carrier_off(dev);
11426
11427 bnx2x_set_power_state(bp, PCI_D0);
11428
11429 /* If parity had happen during the unload, then attentions
11430 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
11431 * want the first function loaded on the current engine to
11432 * complete the recovery.
11433 * Parity recovery is only relevant for PF driver.
11434 */
11435 if (IS_PF(bp)) {
11436 other_load_status = bnx2x_get_load_status(bp, other_engine);
11437 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
11438 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
11439 bnx2x_chk_parity_attn(bp, &global, true)) {
11440 do {
11441 /* If there are attentions and they are in a
11442 * global blocks, set the GLOBAL_RESET bit
11443 * regardless whether it will be this function
11444 * that will complete the recovery or not.
11445 */
11446 if (global)
11447 bnx2x_set_reset_global(bp);
11448
11449 /* Only the first function on the current
11450 * engine should try to recover in open. In case
11451 * of attentions in global blocks only the first
11452 * in the chip should try to recover.
11453 */
11454 if ((!load_status &&
11455 (!global || !other_load_status)) &&
11456 bnx2x_trylock_leader_lock(bp) &&
11457 !bnx2x_leader_reset(bp)) {
11458 netdev_info(bp->dev,
11459 "Recovered in open\n");
11460 break;
11461 }
11462
11463 /* recovery has failed... */
11464 bnx2x_set_power_state(bp, PCI_D3hot);
11465 bp->recovery_state = BNX2X_RECOVERY_FAILED;
11466
11467 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11468 "If you still see this message after a few retries then power cycle is required.\n");
11469
11470 return -EAGAIN;
11471 } while (0);
11472 }
11473 }
11474
11475 bp->recovery_state = BNX2X_RECOVERY_DONE;
11476 rc = bnx2x_nic_load(bp, LOAD_OPEN);
11477 if (rc)
11478 return rc;
11479 return bnx2x_open_epilog(bp);
11480 }
11481
11482 /* called with rtnl_lock */
11483 static int bnx2x_close(struct net_device *dev)
11484 {
11485 struct bnx2x *bp = netdev_priv(dev);
11486
11487 /* Unload the driver, release IRQs */
11488 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
11489
11490 /* Power off */
11491 bnx2x_set_power_state(bp, PCI_D3hot);
11492
11493 return 0;
11494 }
11495
11496 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11497 struct bnx2x_mcast_ramrod_params *p)
11498 {
11499 int mc_count = netdev_mc_count(bp->dev);
11500 struct bnx2x_mcast_list_elem *mc_mac =
11501 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11502 struct netdev_hw_addr *ha;
11503
11504 if (!mc_mac)
11505 return -ENOMEM;
11506
11507 INIT_LIST_HEAD(&p->mcast_list);
11508
11509 netdev_for_each_mc_addr(ha, bp->dev) {
11510 mc_mac->mac = bnx2x_mc_addr(ha);
11511 list_add_tail(&mc_mac->link, &p->mcast_list);
11512 mc_mac++;
11513 }
11514
11515 p->mcast_list_len = mc_count;
11516
11517 return 0;
11518 }
11519
11520 static void bnx2x_free_mcast_macs_list(
11521 struct bnx2x_mcast_ramrod_params *p)
11522 {
11523 struct bnx2x_mcast_list_elem *mc_mac =
11524 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11525 link);
11526
11527 WARN_ON(!mc_mac);
11528 kfree(mc_mac);
11529 }
11530
11531 /**
11532 * bnx2x_set_uc_list - configure a new unicast MACs list.
11533 *
11534 * @bp: driver handle
11535 *
11536 * We will use zero (0) as a MAC type for these MACs.
11537 */
11538 static int bnx2x_set_uc_list(struct bnx2x *bp)
11539 {
11540 int rc;
11541 struct net_device *dev = bp->dev;
11542 struct netdev_hw_addr *ha;
11543 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
11544 unsigned long ramrod_flags = 0;
11545
11546 /* First schedule a cleanup up of old configuration */
11547 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11548 if (rc < 0) {
11549 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11550 return rc;
11551 }
11552
11553 netdev_for_each_uc_addr(ha, dev) {
11554 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11555 BNX2X_UC_LIST_MAC, &ramrod_flags);
11556 if (rc == -EEXIST) {
11557 DP(BNX2X_MSG_SP,
11558 "Failed to schedule ADD operations: %d\n", rc);
11559 /* do not treat adding same MAC as error */
11560 rc = 0;
11561
11562 } else if (rc < 0) {
11563
11564 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11565 rc);
11566 return rc;
11567 }
11568 }
11569
11570 /* Execute the pending commands */
11571 __set_bit(RAMROD_CONT, &ramrod_flags);
11572 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11573 BNX2X_UC_LIST_MAC, &ramrod_flags);
11574 }
11575
11576 static int bnx2x_set_mc_list(struct bnx2x *bp)
11577 {
11578 struct net_device *dev = bp->dev;
11579 struct bnx2x_mcast_ramrod_params rparam = {NULL};
11580 int rc = 0;
11581
11582 rparam.mcast_obj = &bp->mcast_obj;
11583
11584 /* first, clear all configured multicast MACs */
11585 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11586 if (rc < 0) {
11587 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
11588 return rc;
11589 }
11590
11591 /* then, configure a new MACs list */
11592 if (netdev_mc_count(dev)) {
11593 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11594 if (rc) {
11595 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11596 rc);
11597 return rc;
11598 }
11599
11600 /* Now add the new MACs */
11601 rc = bnx2x_config_mcast(bp, &rparam,
11602 BNX2X_MCAST_CMD_ADD);
11603 if (rc < 0)
11604 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11605 rc);
11606
11607 bnx2x_free_mcast_macs_list(&rparam);
11608 }
11609
11610 return rc;
11611 }
11612
11613 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
11614 void bnx2x_set_rx_mode(struct net_device *dev)
11615 {
11616 struct bnx2x *bp = netdev_priv(dev);
11617 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
11618
11619 if (bp->state != BNX2X_STATE_OPEN) {
11620 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
11621 return;
11622 }
11623
11624 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
11625
11626 if (dev->flags & IFF_PROMISC)
11627 rx_mode = BNX2X_RX_MODE_PROMISC;
11628 else if ((dev->flags & IFF_ALLMULTI) ||
11629 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
11630 CHIP_IS_E1(bp)))
11631 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11632 else {
11633 if (IS_PF(bp)) {
11634 /* some multicasts */
11635 if (bnx2x_set_mc_list(bp) < 0)
11636 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11637
11638 if (bnx2x_set_uc_list(bp) < 0)
11639 rx_mode = BNX2X_RX_MODE_PROMISC;
11640 } else {
11641 /* configuring mcast to a vf involves sleeping (when we
11642 * wait for the pf's response). Since this function is
11643 * called from non sleepable context we must schedule
11644 * a work item for this purpose
11645 */
11646 smp_mb__before_clear_bit();
11647 set_bit(BNX2X_SP_RTNL_VFPF_MCAST,
11648 &bp->sp_rtnl_state);
11649 smp_mb__after_clear_bit();
11650 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11651 }
11652 }
11653
11654 bp->rx_mode = rx_mode;
11655 /* handle ISCSI SD mode */
11656 if (IS_MF_ISCSI_SD(bp))
11657 bp->rx_mode = BNX2X_RX_MODE_NONE;
11658
11659 /* Schedule the rx_mode command */
11660 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
11661 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
11662 return;
11663 }
11664
11665 if (IS_PF(bp)) {
11666 bnx2x_set_storm_rx_mode(bp);
11667 } else {
11668 /* configuring rx mode to storms in a vf involves sleeping (when
11669 * we wait for the pf's response). Since this function is
11670 * called from non sleepable context we must schedule
11671 * a work item for this purpose
11672 */
11673 smp_mb__before_clear_bit();
11674 set_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
11675 &bp->sp_rtnl_state);
11676 smp_mb__after_clear_bit();
11677 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11678 }
11679 }
11680
11681 /* called with rtnl_lock */
11682 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
11683 int devad, u16 addr)
11684 {
11685 struct bnx2x *bp = netdev_priv(netdev);
11686 u16 value;
11687 int rc;
11688
11689 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
11690 prtad, devad, addr);
11691
11692 /* The HW expects different devad if CL22 is used */
11693 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11694
11695 bnx2x_acquire_phy_lock(bp);
11696 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
11697 bnx2x_release_phy_lock(bp);
11698 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
11699
11700 if (!rc)
11701 rc = value;
11702 return rc;
11703 }
11704
11705 /* called with rtnl_lock */
11706 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
11707 u16 addr, u16 value)
11708 {
11709 struct bnx2x *bp = netdev_priv(netdev);
11710 int rc;
11711
11712 DP(NETIF_MSG_LINK,
11713 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
11714 prtad, devad, addr, value);
11715
11716 /* The HW expects different devad if CL22 is used */
11717 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11718
11719 bnx2x_acquire_phy_lock(bp);
11720 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
11721 bnx2x_release_phy_lock(bp);
11722 return rc;
11723 }
11724
11725 /* called with rtnl_lock */
11726 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11727 {
11728 struct bnx2x *bp = netdev_priv(dev);
11729 struct mii_ioctl_data *mdio = if_mii(ifr);
11730
11731 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
11732 mdio->phy_id, mdio->reg_num, mdio->val_in);
11733
11734 if (!netif_running(dev))
11735 return -EAGAIN;
11736
11737 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
11738 }
11739
11740 #ifdef CONFIG_NET_POLL_CONTROLLER
11741 static void poll_bnx2x(struct net_device *dev)
11742 {
11743 struct bnx2x *bp = netdev_priv(dev);
11744 int i;
11745
11746 for_each_eth_queue(bp, i) {
11747 struct bnx2x_fastpath *fp = &bp->fp[i];
11748 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
11749 }
11750 }
11751 #endif
11752
11753 static int bnx2x_validate_addr(struct net_device *dev)
11754 {
11755 struct bnx2x *bp = netdev_priv(dev);
11756
11757 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
11758 BNX2X_ERR("Non-valid Ethernet address\n");
11759 return -EADDRNOTAVAIL;
11760 }
11761 return 0;
11762 }
11763
11764 static const struct net_device_ops bnx2x_netdev_ops = {
11765 .ndo_open = bnx2x_open,
11766 .ndo_stop = bnx2x_close,
11767 .ndo_start_xmit = bnx2x_start_xmit,
11768 .ndo_select_queue = bnx2x_select_queue,
11769 .ndo_set_rx_mode = bnx2x_set_rx_mode,
11770 .ndo_set_mac_address = bnx2x_change_mac_addr,
11771 .ndo_validate_addr = bnx2x_validate_addr,
11772 .ndo_do_ioctl = bnx2x_ioctl,
11773 .ndo_change_mtu = bnx2x_change_mtu,
11774 .ndo_fix_features = bnx2x_fix_features,
11775 .ndo_set_features = bnx2x_set_features,
11776 .ndo_tx_timeout = bnx2x_tx_timeout,
11777 #ifdef CONFIG_NET_POLL_CONTROLLER
11778 .ndo_poll_controller = poll_bnx2x,
11779 #endif
11780 .ndo_setup_tc = bnx2x_setup_tc,
11781 #ifdef CONFIG_BNX2X_SRIOV
11782 .ndo_set_vf_mac = bnx2x_set_vf_mac,
11783 #endif
11784 #ifdef NETDEV_FCOE_WWNN
11785 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
11786 #endif
11787 };
11788
11789 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
11790 {
11791 struct device *dev = &bp->pdev->dev;
11792
11793 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
11794 bp->flags |= USING_DAC_FLAG;
11795 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
11796 dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
11797 return -EIO;
11798 }
11799 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
11800 dev_err(dev, "System does not support DMA, aborting\n");
11801 return -EIO;
11802 }
11803
11804 return 0;
11805 }
11806
11807 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
11808 struct net_device *dev, unsigned long board_type)
11809 {
11810 int rc;
11811 u32 pci_cfg_dword;
11812 bool chip_is_e1x = (board_type == BCM57710 ||
11813 board_type == BCM57711 ||
11814 board_type == BCM57711E);
11815
11816 SET_NETDEV_DEV(dev, &pdev->dev);
11817
11818 bp->dev = dev;
11819 bp->pdev = pdev;
11820
11821 rc = pci_enable_device(pdev);
11822 if (rc) {
11823 dev_err(&bp->pdev->dev,
11824 "Cannot enable PCI device, aborting\n");
11825 goto err_out;
11826 }
11827
11828 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11829 dev_err(&bp->pdev->dev,
11830 "Cannot find PCI device base address, aborting\n");
11831 rc = -ENODEV;
11832 goto err_out_disable;
11833 }
11834
11835 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
11836 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
11837 rc = -ENODEV;
11838 goto err_out_disable;
11839 }
11840
11841 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
11842 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
11843 PCICFG_REVESION_ID_ERROR_VAL) {
11844 pr_err("PCI device error, probably due to fan failure, aborting\n");
11845 rc = -ENODEV;
11846 goto err_out_disable;
11847 }
11848
11849 if (atomic_read(&pdev->enable_cnt) == 1) {
11850 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
11851 if (rc) {
11852 dev_err(&bp->pdev->dev,
11853 "Cannot obtain PCI resources, aborting\n");
11854 goto err_out_disable;
11855 }
11856
11857 pci_set_master(pdev);
11858 pci_save_state(pdev);
11859 }
11860
11861 if (IS_PF(bp)) {
11862 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11863 if (bp->pm_cap == 0) {
11864 dev_err(&bp->pdev->dev,
11865 "Cannot find power management capability, aborting\n");
11866 rc = -EIO;
11867 goto err_out_release;
11868 }
11869 }
11870
11871 if (!pci_is_pcie(pdev)) {
11872 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
11873 rc = -EIO;
11874 goto err_out_release;
11875 }
11876
11877 rc = bnx2x_set_coherency_mask(bp);
11878 if (rc)
11879 goto err_out_release;
11880
11881 dev->mem_start = pci_resource_start(pdev, 0);
11882 dev->base_addr = dev->mem_start;
11883 dev->mem_end = pci_resource_end(pdev, 0);
11884
11885 dev->irq = pdev->irq;
11886
11887 bp->regview = pci_ioremap_bar(pdev, 0);
11888 if (!bp->regview) {
11889 dev_err(&bp->pdev->dev,
11890 "Cannot map register space, aborting\n");
11891 rc = -ENOMEM;
11892 goto err_out_release;
11893 }
11894
11895 /* In E1/E1H use pci device function given by kernel.
11896 * In E2/E3 read physical function from ME register since these chips
11897 * support Physical Device Assignment where kernel BDF maybe arbitrary
11898 * (depending on hypervisor).
11899 */
11900 if (chip_is_e1x) {
11901 bp->pf_num = PCI_FUNC(pdev->devfn);
11902 } else {
11903 /* chip is E2/3*/
11904 pci_read_config_dword(bp->pdev,
11905 PCICFG_ME_REGISTER, &pci_cfg_dword);
11906 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
11907 ME_REG_ABS_PF_NUM_SHIFT);
11908 }
11909 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
11910
11911 bnx2x_set_power_state(bp, PCI_D0);
11912
11913 /* clean indirect addresses */
11914 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
11915 PCICFG_VENDOR_ID_OFFSET);
11916 /*
11917 * Clean the following indirect addresses for all functions since it
11918 * is not used by the driver.
11919 */
11920 if (IS_PF(bp)) {
11921 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
11922 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
11923 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
11924 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
11925
11926 if (chip_is_e1x) {
11927 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
11928 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
11929 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
11930 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
11931 }
11932
11933 /* Enable internal target-read (in case we are probed after PF
11934 * FLR). Must be done prior to any BAR read access. Only for
11935 * 57712 and up
11936 */
11937 if (!chip_is_e1x)
11938 REG_WR(bp,
11939 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11940 }
11941
11942 dev->watchdog_timeo = TX_TIMEOUT;
11943
11944 dev->netdev_ops = &bnx2x_netdev_ops;
11945 bnx2x_set_ethtool_ops(dev);
11946
11947 dev->priv_flags |= IFF_UNICAST_FLT;
11948
11949 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11950 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
11951 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
11952 NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX;
11953
11954 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11955 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
11956
11957 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
11958 if (bp->flags & USING_DAC_FLAG)
11959 dev->features |= NETIF_F_HIGHDMA;
11960
11961 /* Add Loopback capability to the device */
11962 dev->hw_features |= NETIF_F_LOOPBACK;
11963
11964 #ifdef BCM_DCBNL
11965 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
11966 #endif
11967
11968 /* get_port_hwinfo() will set prtad and mmds properly */
11969 bp->mdio.prtad = MDIO_PRTAD_NONE;
11970 bp->mdio.mmds = 0;
11971 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
11972 bp->mdio.dev = dev;
11973 bp->mdio.mdio_read = bnx2x_mdio_read;
11974 bp->mdio.mdio_write = bnx2x_mdio_write;
11975
11976 return 0;
11977
11978 err_out_release:
11979 if (atomic_read(&pdev->enable_cnt) == 1)
11980 pci_release_regions(pdev);
11981
11982 err_out_disable:
11983 pci_disable_device(pdev);
11984 pci_set_drvdata(pdev, NULL);
11985
11986 err_out:
11987 return rc;
11988 }
11989
11990 static void bnx2x_get_pcie_width_speed(struct bnx2x *bp, int *width, int *speed)
11991 {
11992 u32 val = 0;
11993
11994 pci_read_config_dword(bp->pdev, PCICFG_LINK_CONTROL, &val);
11995 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
11996
11997 /* return value of 1=2.5GHz 2=5GHz */
11998 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
11999 }
12000
12001 static int bnx2x_check_firmware(struct bnx2x *bp)
12002 {
12003 const struct firmware *firmware = bp->firmware;
12004 struct bnx2x_fw_file_hdr *fw_hdr;
12005 struct bnx2x_fw_file_section *sections;
12006 u32 offset, len, num_ops;
12007 u16 *ops_offsets;
12008 int i;
12009 const u8 *fw_ver;
12010
12011 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12012 BNX2X_ERR("Wrong FW size\n");
12013 return -EINVAL;
12014 }
12015
12016 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12017 sections = (struct bnx2x_fw_file_section *)fw_hdr;
12018
12019 /* Make sure none of the offsets and sizes make us read beyond
12020 * the end of the firmware data */
12021 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12022 offset = be32_to_cpu(sections[i].offset);
12023 len = be32_to_cpu(sections[i].len);
12024 if (offset + len > firmware->size) {
12025 BNX2X_ERR("Section %d length is out of bounds\n", i);
12026 return -EINVAL;
12027 }
12028 }
12029
12030 /* Likewise for the init_ops offsets */
12031 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
12032 ops_offsets = (u16 *)(firmware->data + offset);
12033 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12034
12035 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12036 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
12037 BNX2X_ERR("Section offset %d is out of bounds\n", i);
12038 return -EINVAL;
12039 }
12040 }
12041
12042 /* Check FW version */
12043 offset = be32_to_cpu(fw_hdr->fw_version.offset);
12044 fw_ver = firmware->data + offset;
12045 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12046 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12047 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12048 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
12049 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12050 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12051 BCM_5710_FW_MAJOR_VERSION,
12052 BCM_5710_FW_MINOR_VERSION,
12053 BCM_5710_FW_REVISION_VERSION,
12054 BCM_5710_FW_ENGINEERING_VERSION);
12055 return -EINVAL;
12056 }
12057
12058 return 0;
12059 }
12060
12061 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12062 {
12063 const __be32 *source = (const __be32 *)_source;
12064 u32 *target = (u32 *)_target;
12065 u32 i;
12066
12067 for (i = 0; i < n/4; i++)
12068 target[i] = be32_to_cpu(source[i]);
12069 }
12070
12071 /*
12072 Ops array is stored in the following format:
12073 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12074 */
12075 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12076 {
12077 const __be32 *source = (const __be32 *)_source;
12078 struct raw_op *target = (struct raw_op *)_target;
12079 u32 i, j, tmp;
12080
12081 for (i = 0, j = 0; i < n/8; i++, j += 2) {
12082 tmp = be32_to_cpu(source[j]);
12083 target[i].op = (tmp >> 24) & 0xff;
12084 target[i].offset = tmp & 0xffffff;
12085 target[i].raw_data = be32_to_cpu(source[j + 1]);
12086 }
12087 }
12088
12089 /* IRO array is stored in the following format:
12090 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12091 */
12092 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12093 {
12094 const __be32 *source = (const __be32 *)_source;
12095 struct iro *target = (struct iro *)_target;
12096 u32 i, j, tmp;
12097
12098 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12099 target[i].base = be32_to_cpu(source[j]);
12100 j++;
12101 tmp = be32_to_cpu(source[j]);
12102 target[i].m1 = (tmp >> 16) & 0xffff;
12103 target[i].m2 = tmp & 0xffff;
12104 j++;
12105 tmp = be32_to_cpu(source[j]);
12106 target[i].m3 = (tmp >> 16) & 0xffff;
12107 target[i].size = tmp & 0xffff;
12108 j++;
12109 }
12110 }
12111
12112 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12113 {
12114 const __be16 *source = (const __be16 *)_source;
12115 u16 *target = (u16 *)_target;
12116 u32 i;
12117
12118 for (i = 0; i < n/2; i++)
12119 target[i] = be16_to_cpu(source[i]);
12120 }
12121
12122 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
12123 do { \
12124 u32 len = be32_to_cpu(fw_hdr->arr.len); \
12125 bp->arr = kmalloc(len, GFP_KERNEL); \
12126 if (!bp->arr) \
12127 goto lbl; \
12128 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
12129 (u8 *)bp->arr, len); \
12130 } while (0)
12131
12132 static int bnx2x_init_firmware(struct bnx2x *bp)
12133 {
12134 const char *fw_file_name;
12135 struct bnx2x_fw_file_hdr *fw_hdr;
12136 int rc;
12137
12138 if (bp->firmware)
12139 return 0;
12140
12141 if (CHIP_IS_E1(bp))
12142 fw_file_name = FW_FILE_NAME_E1;
12143 else if (CHIP_IS_E1H(bp))
12144 fw_file_name = FW_FILE_NAME_E1H;
12145 else if (!CHIP_IS_E1x(bp))
12146 fw_file_name = FW_FILE_NAME_E2;
12147 else {
12148 BNX2X_ERR("Unsupported chip revision\n");
12149 return -EINVAL;
12150 }
12151 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
12152
12153 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12154 if (rc) {
12155 BNX2X_ERR("Can't load firmware file %s\n",
12156 fw_file_name);
12157 goto request_firmware_exit;
12158 }
12159
12160 rc = bnx2x_check_firmware(bp);
12161 if (rc) {
12162 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12163 goto request_firmware_exit;
12164 }
12165
12166 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12167
12168 /* Initialize the pointers to the init arrays */
12169 /* Blob */
12170 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12171
12172 /* Opcodes */
12173 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12174
12175 /* Offsets */
12176 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12177 be16_to_cpu_n);
12178
12179 /* STORMs firmware */
12180 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12181 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12182 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
12183 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12184 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12185 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12186 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
12187 be32_to_cpu(fw_hdr->usem_pram_data.offset);
12188 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12189 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12190 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
12191 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12192 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12193 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12194 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
12195 be32_to_cpu(fw_hdr->csem_pram_data.offset);
12196 /* IRO */
12197 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
12198
12199 return 0;
12200
12201 iro_alloc_err:
12202 kfree(bp->init_ops_offsets);
12203 init_offsets_alloc_err:
12204 kfree(bp->init_ops);
12205 init_ops_alloc_err:
12206 kfree(bp->init_data);
12207 request_firmware_exit:
12208 release_firmware(bp->firmware);
12209 bp->firmware = NULL;
12210
12211 return rc;
12212 }
12213
12214 static void bnx2x_release_firmware(struct bnx2x *bp)
12215 {
12216 kfree(bp->init_ops_offsets);
12217 kfree(bp->init_ops);
12218 kfree(bp->init_data);
12219 release_firmware(bp->firmware);
12220 bp->firmware = NULL;
12221 }
12222
12223
12224 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12225 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12226 .init_hw_cmn = bnx2x_init_hw_common,
12227 .init_hw_port = bnx2x_init_hw_port,
12228 .init_hw_func = bnx2x_init_hw_func,
12229
12230 .reset_hw_cmn = bnx2x_reset_common,
12231 .reset_hw_port = bnx2x_reset_port,
12232 .reset_hw_func = bnx2x_reset_func,
12233
12234 .gunzip_init = bnx2x_gunzip_init,
12235 .gunzip_end = bnx2x_gunzip_end,
12236
12237 .init_fw = bnx2x_init_firmware,
12238 .release_fw = bnx2x_release_firmware,
12239 };
12240
12241 void bnx2x__init_func_obj(struct bnx2x *bp)
12242 {
12243 /* Prepare DMAE related driver resources */
12244 bnx2x_setup_dmae(bp);
12245
12246 bnx2x_init_func_obj(bp, &bp->func_obj,
12247 bnx2x_sp(bp, func_rdata),
12248 bnx2x_sp_mapping(bp, func_rdata),
12249 bnx2x_sp(bp, func_afex_rdata),
12250 bnx2x_sp_mapping(bp, func_afex_rdata),
12251 &bnx2x_func_sp_drv);
12252 }
12253
12254 /* must be called after sriov-enable */
12255 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
12256 {
12257 int cid_count = BNX2X_L2_MAX_CID(bp);
12258
12259 if (IS_SRIOV(bp))
12260 cid_count += BNX2X_VF_CIDS;
12261
12262 if (CNIC_SUPPORT(bp))
12263 cid_count += CNIC_CID_MAX;
12264
12265 return roundup(cid_count, QM_CID_ROUND);
12266 }
12267
12268 /**
12269 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
12270 *
12271 * @dev: pci device
12272 *
12273 */
12274 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev,
12275 int cnic_cnt, bool is_vf)
12276 {
12277 int pos, index;
12278 u16 control = 0;
12279
12280 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
12281
12282 /*
12283 * If MSI-X is not supported - return number of SBs needed to support
12284 * one fast path queue: one FP queue + SB for CNIC
12285 */
12286 if (!pos) {
12287 dev_info(&pdev->dev, "no msix capability found\n");
12288 return 1 + cnic_cnt;
12289 }
12290 dev_info(&pdev->dev, "msix capability found\n");
12291
12292 /*
12293 * The value in the PCI configuration space is the index of the last
12294 * entry, namely one less than the actual size of the table, which is
12295 * exactly what we want to return from this function: number of all SBs
12296 * without the default SB.
12297 * For VFs there is no default SB, then we return (index+1).
12298 */
12299 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
12300
12301 index = control & PCI_MSIX_FLAGS_QSIZE;
12302
12303 return is_vf ? index + 1 : index;
12304 }
12305
12306 static int set_max_cos_est(int chip_id)
12307 {
12308 switch (chip_id) {
12309 case BCM57710:
12310 case BCM57711:
12311 case BCM57711E:
12312 return BNX2X_MULTI_TX_COS_E1X;
12313 case BCM57712:
12314 case BCM57712_MF:
12315 case BCM57712_VF:
12316 return BNX2X_MULTI_TX_COS_E2_E3A0;
12317 case BCM57800:
12318 case BCM57800_MF:
12319 case BCM57800_VF:
12320 case BCM57810:
12321 case BCM57810_MF:
12322 case BCM57840_4_10:
12323 case BCM57840_2_20:
12324 case BCM57840_O:
12325 case BCM57840_MFO:
12326 case BCM57810_VF:
12327 case BCM57840_MF:
12328 case BCM57840_VF:
12329 case BCM57811:
12330 case BCM57811_MF:
12331 case BCM57811_VF:
12332 return BNX2X_MULTI_TX_COS_E3B0;
12333 return 1;
12334 default:
12335 pr_err("Unknown board_type (%d), aborting\n", chip_id);
12336 return -ENODEV;
12337 }
12338 }
12339
12340 static int set_is_vf(int chip_id)
12341 {
12342 switch (chip_id) {
12343 case BCM57712_VF:
12344 case BCM57800_VF:
12345 case BCM57810_VF:
12346 case BCM57840_VF:
12347 case BCM57811_VF:
12348 return true;
12349 default:
12350 return false;
12351 }
12352 }
12353
12354 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
12355
12356 static int bnx2x_init_one(struct pci_dev *pdev,
12357 const struct pci_device_id *ent)
12358 {
12359 struct net_device *dev = NULL;
12360 struct bnx2x *bp;
12361 int pcie_width, pcie_speed;
12362 int rc, max_non_def_sbs;
12363 int rx_count, tx_count, rss_count, doorbell_size;
12364 int max_cos_est;
12365 bool is_vf;
12366 int cnic_cnt;
12367
12368 /* An estimated maximum supported CoS number according to the chip
12369 * version.
12370 * We will try to roughly estimate the maximum number of CoSes this chip
12371 * may support in order to minimize the memory allocated for Tx
12372 * netdev_queue's. This number will be accurately calculated during the
12373 * initialization of bp->max_cos based on the chip versions AND chip
12374 * revision in the bnx2x_init_bp().
12375 */
12376 max_cos_est = set_max_cos_est(ent->driver_data);
12377 if (max_cos_est < 0)
12378 return max_cos_est;
12379 is_vf = set_is_vf(ent->driver_data);
12380 cnic_cnt = is_vf ? 0 : 1;
12381
12382 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt, is_vf);
12383
12384 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
12385 rss_count = is_vf ? 1 : max_non_def_sbs - cnic_cnt;
12386
12387 if (rss_count < 1)
12388 return -EINVAL;
12389
12390 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
12391 rx_count = rss_count + cnic_cnt;
12392
12393 /* Maximum number of netdev Tx queues:
12394 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
12395 */
12396 tx_count = rss_count * max_cos_est + cnic_cnt;
12397
12398 /* dev zeroed in init_etherdev */
12399 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
12400 if (!dev)
12401 return -ENOMEM;
12402
12403 bp = netdev_priv(dev);
12404
12405 bp->flags = 0;
12406 if (is_vf)
12407 bp->flags |= IS_VF_FLAG;
12408
12409 bp->igu_sb_cnt = max_non_def_sbs;
12410 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
12411 bp->msg_enable = debug;
12412 bp->cnic_support = cnic_cnt;
12413 bp->cnic_probe = bnx2x_cnic_probe;
12414
12415 pci_set_drvdata(pdev, dev);
12416
12417 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
12418 if (rc < 0) {
12419 free_netdev(dev);
12420 return rc;
12421 }
12422
12423 BNX2X_DEV_INFO("This is a %s function\n",
12424 IS_PF(bp) ? "physical" : "virtual");
12425 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
12426 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
12427 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
12428 tx_count, rx_count);
12429
12430 rc = bnx2x_init_bp(bp);
12431 if (rc)
12432 goto init_one_exit;
12433
12434 /* Map doorbells here as we need the real value of bp->max_cos which
12435 * is initialized in bnx2x_init_bp() to determine the number of
12436 * l2 connections.
12437 */
12438 if (IS_VF(bp)) {
12439 bnx2x_vf_map_doorbells(bp);
12440 rc = bnx2x_vf_pci_alloc(bp);
12441 if (rc)
12442 goto init_one_exit;
12443 } else {
12444 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
12445 if (doorbell_size > pci_resource_len(pdev, 2)) {
12446 dev_err(&bp->pdev->dev,
12447 "Cannot map doorbells, bar size too small, aborting\n");
12448 rc = -ENOMEM;
12449 goto init_one_exit;
12450 }
12451 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
12452 doorbell_size);
12453 }
12454 if (!bp->doorbells) {
12455 dev_err(&bp->pdev->dev,
12456 "Cannot map doorbell space, aborting\n");
12457 rc = -ENOMEM;
12458 goto init_one_exit;
12459 }
12460
12461 if (IS_VF(bp)) {
12462 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
12463 if (rc)
12464 goto init_one_exit;
12465 }
12466
12467 /* Enable SRIOV if capability found in configuration space.
12468 * Once the generic SR-IOV framework makes it in from the
12469 * pci tree this will be revised, to allow dynamic control
12470 * over the number of VFs. Right now, change the num of vfs
12471 * param below to enable SR-IOV.
12472 */
12473 rc = bnx2x_iov_init_one(bp, int_mode, 0/*num vfs*/);
12474 if (rc)
12475 goto init_one_exit;
12476
12477 /* calc qm_cid_count */
12478 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
12479 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
12480
12481 /* disable FCOE L2 queue for E1x*/
12482 if (CHIP_IS_E1x(bp))
12483 bp->flags |= NO_FCOE_FLAG;
12484
12485 /* disable FCOE for 57840 device, until FW supports it */
12486 switch (ent->driver_data) {
12487 case BCM57840_O:
12488 case BCM57840_4_10:
12489 case BCM57840_2_20:
12490 case BCM57840_MFO:
12491 case BCM57840_MF:
12492 bp->flags |= NO_FCOE_FLAG;
12493 }
12494
12495 /* Set bp->num_queues for MSI-X mode*/
12496 bnx2x_set_num_queues(bp);
12497
12498 /* Configure interrupt mode: try to enable MSI-X/MSI if
12499 * needed.
12500 */
12501 rc = bnx2x_set_int_mode(bp);
12502 if (rc) {
12503 dev_err(&pdev->dev, "Cannot set interrupts\n");
12504 goto init_one_exit;
12505 }
12506
12507 /* register the net device */
12508 rc = register_netdev(dev);
12509 if (rc) {
12510 dev_err(&pdev->dev, "Cannot register net device\n");
12511 goto init_one_exit;
12512 }
12513 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
12514
12515
12516 if (!NO_FCOE(bp)) {
12517 /* Add storage MAC address */
12518 rtnl_lock();
12519 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12520 rtnl_unlock();
12521 }
12522
12523 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
12524 BNX2X_DEV_INFO("got pcie width %d and speed %d\n",
12525 pcie_width, pcie_speed);
12526
12527 BNX2X_DEV_INFO(
12528 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
12529 board_info[ent->driver_data].name,
12530 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
12531 pcie_width,
12532 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
12533 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
12534 "5GHz (Gen2)" : "2.5GHz",
12535 dev->base_addr, bp->pdev->irq, dev->dev_addr);
12536
12537 return 0;
12538
12539 init_one_exit:
12540 if (bp->regview)
12541 iounmap(bp->regview);
12542
12543 if (IS_PF(bp) && bp->doorbells)
12544 iounmap(bp->doorbells);
12545
12546 free_netdev(dev);
12547
12548 if (atomic_read(&pdev->enable_cnt) == 1)
12549 pci_release_regions(pdev);
12550
12551 pci_disable_device(pdev);
12552 pci_set_drvdata(pdev, NULL);
12553
12554 return rc;
12555 }
12556
12557 static void bnx2x_remove_one(struct pci_dev *pdev)
12558 {
12559 struct net_device *dev = pci_get_drvdata(pdev);
12560 struct bnx2x *bp;
12561
12562 if (!dev) {
12563 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
12564 return;
12565 }
12566 bp = netdev_priv(dev);
12567
12568 /* Delete storage MAC address */
12569 if (!NO_FCOE(bp)) {
12570 rtnl_lock();
12571 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12572 rtnl_unlock();
12573 }
12574
12575 #ifdef BCM_DCBNL
12576 /* Delete app tlvs from dcbnl */
12577 bnx2x_dcbnl_update_applist(bp, true);
12578 #endif
12579
12580 unregister_netdev(dev);
12581
12582 /* Power on: we can't let PCI layer write to us while we are in D3 */
12583 if (IS_PF(bp))
12584 bnx2x_set_power_state(bp, PCI_D0);
12585
12586 /* Disable MSI/MSI-X */
12587 bnx2x_disable_msi(bp);
12588
12589 /* Power off */
12590 if (IS_PF(bp))
12591 bnx2x_set_power_state(bp, PCI_D3hot);
12592
12593 /* Make sure RESET task is not scheduled before continuing */
12594 cancel_delayed_work_sync(&bp->sp_rtnl_task);
12595
12596 bnx2x_iov_remove_one(bp);
12597
12598 /* send message via vfpf channel to release the resources of this vf */
12599 if (IS_VF(bp))
12600 bnx2x_vfpf_release(bp);
12601
12602 if (bp->regview)
12603 iounmap(bp->regview);
12604
12605 /* for vf doorbells are part of the regview and were unmapped along with
12606 * it. FW is only loaded by PF.
12607 */
12608 if (IS_PF(bp)) {
12609 if (bp->doorbells)
12610 iounmap(bp->doorbells);
12611
12612 bnx2x_release_firmware(bp);
12613 }
12614 bnx2x_free_mem_bp(bp);
12615
12616 free_netdev(dev);
12617
12618 if (atomic_read(&pdev->enable_cnt) == 1)
12619 pci_release_regions(pdev);
12620
12621 pci_disable_device(pdev);
12622 pci_set_drvdata(pdev, NULL);
12623 }
12624
12625 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
12626 {
12627 int i;
12628
12629 bp->state = BNX2X_STATE_ERROR;
12630
12631 bp->rx_mode = BNX2X_RX_MODE_NONE;
12632
12633 if (CNIC_LOADED(bp))
12634 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
12635
12636 /* Stop Tx */
12637 bnx2x_tx_disable(bp);
12638
12639 bnx2x_netif_stop(bp, 0);
12640 /* Delete all NAPI objects */
12641 bnx2x_del_all_napi(bp);
12642 if (CNIC_LOADED(bp))
12643 bnx2x_del_all_napi_cnic(bp);
12644
12645 del_timer_sync(&bp->timer);
12646
12647 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
12648
12649 /* Release IRQs */
12650 bnx2x_free_irq(bp);
12651
12652 /* Free SKBs, SGEs, TPA pool and driver internals */
12653 bnx2x_free_skbs(bp);
12654
12655 for_each_rx_queue(bp, i)
12656 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
12657
12658 bnx2x_free_mem(bp);
12659
12660 bp->state = BNX2X_STATE_CLOSED;
12661
12662 netif_carrier_off(bp->dev);
12663
12664 return 0;
12665 }
12666
12667 static void bnx2x_eeh_recover(struct bnx2x *bp)
12668 {
12669 u32 val;
12670
12671 mutex_init(&bp->port.phy_mutex);
12672
12673
12674 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
12675 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12676 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12677 BNX2X_ERR("BAD MCP validity signature\n");
12678 }
12679
12680 /**
12681 * bnx2x_io_error_detected - called when PCI error is detected
12682 * @pdev: Pointer to PCI device
12683 * @state: The current pci connection state
12684 *
12685 * This function is called after a PCI bus error affecting
12686 * this device has been detected.
12687 */
12688 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
12689 pci_channel_state_t state)
12690 {
12691 struct net_device *dev = pci_get_drvdata(pdev);
12692 struct bnx2x *bp = netdev_priv(dev);
12693
12694 rtnl_lock();
12695
12696 netif_device_detach(dev);
12697
12698 if (state == pci_channel_io_perm_failure) {
12699 rtnl_unlock();
12700 return PCI_ERS_RESULT_DISCONNECT;
12701 }
12702
12703 if (netif_running(dev))
12704 bnx2x_eeh_nic_unload(bp);
12705
12706 pci_disable_device(pdev);
12707
12708 rtnl_unlock();
12709
12710 /* Request a slot reset */
12711 return PCI_ERS_RESULT_NEED_RESET;
12712 }
12713
12714 /**
12715 * bnx2x_io_slot_reset - called after the PCI bus has been reset
12716 * @pdev: Pointer to PCI device
12717 *
12718 * Restart the card from scratch, as if from a cold-boot.
12719 */
12720 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
12721 {
12722 struct net_device *dev = pci_get_drvdata(pdev);
12723 struct bnx2x *bp = netdev_priv(dev);
12724
12725 rtnl_lock();
12726
12727 if (pci_enable_device(pdev)) {
12728 dev_err(&pdev->dev,
12729 "Cannot re-enable PCI device after reset\n");
12730 rtnl_unlock();
12731 return PCI_ERS_RESULT_DISCONNECT;
12732 }
12733
12734 pci_set_master(pdev);
12735 pci_restore_state(pdev);
12736
12737 if (netif_running(dev))
12738 bnx2x_set_power_state(bp, PCI_D0);
12739
12740 rtnl_unlock();
12741
12742 return PCI_ERS_RESULT_RECOVERED;
12743 }
12744
12745 /**
12746 * bnx2x_io_resume - called when traffic can start flowing again
12747 * @pdev: Pointer to PCI device
12748 *
12749 * This callback is called when the error recovery driver tells us that
12750 * its OK to resume normal operation.
12751 */
12752 static void bnx2x_io_resume(struct pci_dev *pdev)
12753 {
12754 struct net_device *dev = pci_get_drvdata(pdev);
12755 struct bnx2x *bp = netdev_priv(dev);
12756
12757 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
12758 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
12759 return;
12760 }
12761
12762 rtnl_lock();
12763
12764 bnx2x_eeh_recover(bp);
12765
12766 if (netif_running(dev))
12767 bnx2x_nic_load(bp, LOAD_NORMAL);
12768
12769 netif_device_attach(dev);
12770
12771 rtnl_unlock();
12772 }
12773
12774 static const struct pci_error_handlers bnx2x_err_handler = {
12775 .error_detected = bnx2x_io_error_detected,
12776 .slot_reset = bnx2x_io_slot_reset,
12777 .resume = bnx2x_io_resume,
12778 };
12779
12780 static struct pci_driver bnx2x_pci_driver = {
12781 .name = DRV_MODULE_NAME,
12782 .id_table = bnx2x_pci_tbl,
12783 .probe = bnx2x_init_one,
12784 .remove = bnx2x_remove_one,
12785 .suspend = bnx2x_suspend,
12786 .resume = bnx2x_resume,
12787 .err_handler = &bnx2x_err_handler,
12788 };
12789
12790 static int __init bnx2x_init(void)
12791 {
12792 int ret;
12793
12794 pr_info("%s", version);
12795
12796 bnx2x_wq = create_singlethread_workqueue("bnx2x");
12797 if (bnx2x_wq == NULL) {
12798 pr_err("Cannot create workqueue\n");
12799 return -ENOMEM;
12800 }
12801
12802 ret = pci_register_driver(&bnx2x_pci_driver);
12803 if (ret) {
12804 pr_err("Cannot register driver\n");
12805 destroy_workqueue(bnx2x_wq);
12806 }
12807 return ret;
12808 }
12809
12810 static void __exit bnx2x_cleanup(void)
12811 {
12812 struct list_head *pos, *q;
12813 pci_unregister_driver(&bnx2x_pci_driver);
12814
12815 destroy_workqueue(bnx2x_wq);
12816
12817 /* Free globablly allocated resources */
12818 list_for_each_safe(pos, q, &bnx2x_prev_list) {
12819 struct bnx2x_prev_path_list *tmp =
12820 list_entry(pos, struct bnx2x_prev_path_list, list);
12821 list_del(pos);
12822 kfree(tmp);
12823 }
12824 }
12825
12826 void bnx2x_notify_link_changed(struct bnx2x *bp)
12827 {
12828 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
12829 }
12830
12831 module_init(bnx2x_init);
12832 module_exit(bnx2x_cleanup);
12833
12834 /**
12835 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
12836 *
12837 * @bp: driver handle
12838 * @set: set or clear the CAM entry
12839 *
12840 * This function will wait until the ramdord completion returns.
12841 * Return 0 if success, -ENODEV if ramrod doesn't return.
12842 */
12843 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
12844 {
12845 unsigned long ramrod_flags = 0;
12846
12847 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12848 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
12849 &bp->iscsi_l2_mac_obj, true,
12850 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
12851 }
12852
12853 /* count denotes the number of new completions we have seen */
12854 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
12855 {
12856 struct eth_spe *spe;
12857 int cxt_index, cxt_offset;
12858
12859 #ifdef BNX2X_STOP_ON_ERROR
12860 if (unlikely(bp->panic))
12861 return;
12862 #endif
12863
12864 spin_lock_bh(&bp->spq_lock);
12865 BUG_ON(bp->cnic_spq_pending < count);
12866 bp->cnic_spq_pending -= count;
12867
12868
12869 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
12870 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
12871 & SPE_HDR_CONN_TYPE) >>
12872 SPE_HDR_CONN_TYPE_SHIFT;
12873 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
12874 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
12875
12876 /* Set validation for iSCSI L2 client before sending SETUP
12877 * ramrod
12878 */
12879 if (type == ETH_CONNECTION_TYPE) {
12880 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
12881 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
12882 ILT_PAGE_CIDS;
12883 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
12884 (cxt_index * ILT_PAGE_CIDS);
12885 bnx2x_set_ctx_validation(bp,
12886 &bp->context[cxt_index].
12887 vcxt[cxt_offset].eth,
12888 BNX2X_ISCSI_ETH_CID(bp));
12889 }
12890 }
12891
12892 /*
12893 * There may be not more than 8 L2, not more than 8 L5 SPEs
12894 * and in the air. We also check that number of outstanding
12895 * COMMON ramrods is not more than the EQ and SPQ can
12896 * accommodate.
12897 */
12898 if (type == ETH_CONNECTION_TYPE) {
12899 if (!atomic_read(&bp->cq_spq_left))
12900 break;
12901 else
12902 atomic_dec(&bp->cq_spq_left);
12903 } else if (type == NONE_CONNECTION_TYPE) {
12904 if (!atomic_read(&bp->eq_spq_left))
12905 break;
12906 else
12907 atomic_dec(&bp->eq_spq_left);
12908 } else if ((type == ISCSI_CONNECTION_TYPE) ||
12909 (type == FCOE_CONNECTION_TYPE)) {
12910 if (bp->cnic_spq_pending >=
12911 bp->cnic_eth_dev.max_kwqe_pending)
12912 break;
12913 else
12914 bp->cnic_spq_pending++;
12915 } else {
12916 BNX2X_ERR("Unknown SPE type: %d\n", type);
12917 bnx2x_panic();
12918 break;
12919 }
12920
12921 spe = bnx2x_sp_get_next(bp);
12922 *spe = *bp->cnic_kwq_cons;
12923
12924 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
12925 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
12926
12927 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
12928 bp->cnic_kwq_cons = bp->cnic_kwq;
12929 else
12930 bp->cnic_kwq_cons++;
12931 }
12932 bnx2x_sp_prod_update(bp);
12933 spin_unlock_bh(&bp->spq_lock);
12934 }
12935
12936 static int bnx2x_cnic_sp_queue(struct net_device *dev,
12937 struct kwqe_16 *kwqes[], u32 count)
12938 {
12939 struct bnx2x *bp = netdev_priv(dev);
12940 int i;
12941
12942 #ifdef BNX2X_STOP_ON_ERROR
12943 if (unlikely(bp->panic)) {
12944 BNX2X_ERR("Can't post to SP queue while panic\n");
12945 return -EIO;
12946 }
12947 #endif
12948
12949 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
12950 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
12951 BNX2X_ERR("Handling parity error recovery. Try again later\n");
12952 return -EAGAIN;
12953 }
12954
12955 spin_lock_bh(&bp->spq_lock);
12956
12957 for (i = 0; i < count; i++) {
12958 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
12959
12960 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
12961 break;
12962
12963 *bp->cnic_kwq_prod = *spe;
12964
12965 bp->cnic_kwq_pending++;
12966
12967 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
12968 spe->hdr.conn_and_cmd_data, spe->hdr.type,
12969 spe->data.update_data_addr.hi,
12970 spe->data.update_data_addr.lo,
12971 bp->cnic_kwq_pending);
12972
12973 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
12974 bp->cnic_kwq_prod = bp->cnic_kwq;
12975 else
12976 bp->cnic_kwq_prod++;
12977 }
12978
12979 spin_unlock_bh(&bp->spq_lock);
12980
12981 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
12982 bnx2x_cnic_sp_post(bp, 0);
12983
12984 return i;
12985 }
12986
12987 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
12988 {
12989 struct cnic_ops *c_ops;
12990 int rc = 0;
12991
12992 mutex_lock(&bp->cnic_mutex);
12993 c_ops = rcu_dereference_protected(bp->cnic_ops,
12994 lockdep_is_held(&bp->cnic_mutex));
12995 if (c_ops)
12996 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
12997 mutex_unlock(&bp->cnic_mutex);
12998
12999 return rc;
13000 }
13001
13002 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13003 {
13004 struct cnic_ops *c_ops;
13005 int rc = 0;
13006
13007 rcu_read_lock();
13008 c_ops = rcu_dereference(bp->cnic_ops);
13009 if (c_ops)
13010 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13011 rcu_read_unlock();
13012
13013 return rc;
13014 }
13015
13016 /*
13017 * for commands that have no data
13018 */
13019 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
13020 {
13021 struct cnic_ctl_info ctl = {0};
13022
13023 ctl.cmd = cmd;
13024
13025 return bnx2x_cnic_ctl_send(bp, &ctl);
13026 }
13027
13028 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
13029 {
13030 struct cnic_ctl_info ctl = {0};
13031
13032 /* first we tell CNIC and only then we count this as a completion */
13033 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
13034 ctl.data.comp.cid = cid;
13035 ctl.data.comp.error = err;
13036
13037 bnx2x_cnic_ctl_send_bh(bp, &ctl);
13038 bnx2x_cnic_sp_post(bp, 0);
13039 }
13040
13041
13042 /* Called with netif_addr_lock_bh() taken.
13043 * Sets an rx_mode config for an iSCSI ETH client.
13044 * Doesn't block.
13045 * Completion should be checked outside.
13046 */
13047 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
13048 {
13049 unsigned long accept_flags = 0, ramrod_flags = 0;
13050 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13051 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
13052
13053 if (start) {
13054 /* Start accepting on iSCSI L2 ring. Accept all multicasts
13055 * because it's the only way for UIO Queue to accept
13056 * multicasts (in non-promiscuous mode only one Queue per
13057 * function will receive multicast packets (leading in our
13058 * case).
13059 */
13060 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
13061 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
13062 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
13063 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
13064
13065 /* Clear STOP_PENDING bit if START is requested */
13066 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
13067
13068 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
13069 } else
13070 /* Clear START_PENDING bit if STOP is requested */
13071 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
13072
13073 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
13074 set_bit(sched_state, &bp->sp_state);
13075 else {
13076 __set_bit(RAMROD_RX, &ramrod_flags);
13077 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
13078 ramrod_flags);
13079 }
13080 }
13081
13082
13083 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
13084 {
13085 struct bnx2x *bp = netdev_priv(dev);
13086 int rc = 0;
13087
13088 switch (ctl->cmd) {
13089 case DRV_CTL_CTXTBL_WR_CMD: {
13090 u32 index = ctl->data.io.offset;
13091 dma_addr_t addr = ctl->data.io.dma_addr;
13092
13093 bnx2x_ilt_wr(bp, index, addr);
13094 break;
13095 }
13096
13097 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
13098 int count = ctl->data.credit.credit_count;
13099
13100 bnx2x_cnic_sp_post(bp, count);
13101 break;
13102 }
13103
13104 /* rtnl_lock is held. */
13105 case DRV_CTL_START_L2_CMD: {
13106 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13107 unsigned long sp_bits = 0;
13108
13109 /* Configure the iSCSI classification object */
13110 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
13111 cp->iscsi_l2_client_id,
13112 cp->iscsi_l2_cid, BP_FUNC(bp),
13113 bnx2x_sp(bp, mac_rdata),
13114 bnx2x_sp_mapping(bp, mac_rdata),
13115 BNX2X_FILTER_MAC_PENDING,
13116 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
13117 &bp->macs_pool);
13118
13119 /* Set iSCSI MAC address */
13120 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
13121 if (rc)
13122 break;
13123
13124 mmiowb();
13125 barrier();
13126
13127 /* Start accepting on iSCSI L2 ring */
13128
13129 netif_addr_lock_bh(dev);
13130 bnx2x_set_iscsi_eth_rx_mode(bp, true);
13131 netif_addr_unlock_bh(dev);
13132
13133 /* bits to wait on */
13134 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13135 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
13136
13137 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13138 BNX2X_ERR("rx_mode completion timed out!\n");
13139
13140 break;
13141 }
13142
13143 /* rtnl_lock is held. */
13144 case DRV_CTL_STOP_L2_CMD: {
13145 unsigned long sp_bits = 0;
13146
13147 /* Stop accepting on iSCSI L2 ring */
13148 netif_addr_lock_bh(dev);
13149 bnx2x_set_iscsi_eth_rx_mode(bp, false);
13150 netif_addr_unlock_bh(dev);
13151
13152 /* bits to wait on */
13153 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13154 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
13155
13156 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13157 BNX2X_ERR("rx_mode completion timed out!\n");
13158
13159 mmiowb();
13160 barrier();
13161
13162 /* Unset iSCSI L2 MAC */
13163 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
13164 BNX2X_ISCSI_ETH_MAC, true);
13165 break;
13166 }
13167 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
13168 int count = ctl->data.credit.credit_count;
13169
13170 smp_mb__before_atomic_inc();
13171 atomic_add(count, &bp->cq_spq_left);
13172 smp_mb__after_atomic_inc();
13173 break;
13174 }
13175 case DRV_CTL_ULP_REGISTER_CMD: {
13176 int ulp_type = ctl->data.register_data.ulp_type;
13177
13178 if (CHIP_IS_E3(bp)) {
13179 int idx = BP_FW_MB_IDX(bp);
13180 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13181 int path = BP_PATH(bp);
13182 int port = BP_PORT(bp);
13183 int i;
13184 u32 scratch_offset;
13185 u32 *host_addr;
13186
13187 /* first write capability to shmem2 */
13188 if (ulp_type == CNIC_ULP_ISCSI)
13189 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13190 else if (ulp_type == CNIC_ULP_FCOE)
13191 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13192 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13193
13194 if ((ulp_type != CNIC_ULP_FCOE) ||
13195 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
13196 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
13197 break;
13198
13199 /* if reached here - should write fcoe capabilities */
13200 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
13201 if (!scratch_offset)
13202 break;
13203 scratch_offset += offsetof(struct glob_ncsi_oem_data,
13204 fcoe_features[path][port]);
13205 host_addr = (u32 *) &(ctl->data.register_data.
13206 fcoe_features);
13207 for (i = 0; i < sizeof(struct fcoe_capabilities);
13208 i += 4)
13209 REG_WR(bp, scratch_offset + i,
13210 *(host_addr + i/4));
13211 }
13212 break;
13213 }
13214
13215 case DRV_CTL_ULP_UNREGISTER_CMD: {
13216 int ulp_type = ctl->data.ulp_type;
13217
13218 if (CHIP_IS_E3(bp)) {
13219 int idx = BP_FW_MB_IDX(bp);
13220 u32 cap;
13221
13222 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13223 if (ulp_type == CNIC_ULP_ISCSI)
13224 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13225 else if (ulp_type == CNIC_ULP_FCOE)
13226 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13227 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13228 }
13229 break;
13230 }
13231
13232 default:
13233 BNX2X_ERR("unknown command %x\n", ctl->cmd);
13234 rc = -EINVAL;
13235 }
13236
13237 return rc;
13238 }
13239
13240 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
13241 {
13242 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13243
13244 if (bp->flags & USING_MSIX_FLAG) {
13245 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
13246 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
13247 cp->irq_arr[0].vector = bp->msix_table[1].vector;
13248 } else {
13249 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
13250 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
13251 }
13252 if (!CHIP_IS_E1x(bp))
13253 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
13254 else
13255 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
13256
13257 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
13258 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
13259 cp->irq_arr[1].status_blk = bp->def_status_blk;
13260 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
13261 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
13262
13263 cp->num_irq = 2;
13264 }
13265
13266 void bnx2x_setup_cnic_info(struct bnx2x *bp)
13267 {
13268 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13269
13270
13271 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13272 bnx2x_cid_ilt_lines(bp);
13273 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13274 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13275 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13276
13277 if (NO_ISCSI_OOO(bp))
13278 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13279 }
13280
13281 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
13282 void *data)
13283 {
13284 struct bnx2x *bp = netdev_priv(dev);
13285 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13286 int rc;
13287
13288 DP(NETIF_MSG_IFUP, "Register_cnic called\n");
13289
13290 if (ops == NULL) {
13291 BNX2X_ERR("NULL ops received\n");
13292 return -EINVAL;
13293 }
13294
13295 if (!CNIC_SUPPORT(bp)) {
13296 BNX2X_ERR("Can't register CNIC when not supported\n");
13297 return -EOPNOTSUPP;
13298 }
13299
13300 if (!CNIC_LOADED(bp)) {
13301 rc = bnx2x_load_cnic(bp);
13302 if (rc) {
13303 BNX2X_ERR("CNIC-related load failed\n");
13304 return rc;
13305 }
13306
13307 }
13308
13309 bp->cnic_enabled = true;
13310
13311 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
13312 if (!bp->cnic_kwq)
13313 return -ENOMEM;
13314
13315 bp->cnic_kwq_cons = bp->cnic_kwq;
13316 bp->cnic_kwq_prod = bp->cnic_kwq;
13317 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
13318
13319 bp->cnic_spq_pending = 0;
13320 bp->cnic_kwq_pending = 0;
13321
13322 bp->cnic_data = data;
13323
13324 cp->num_irq = 0;
13325 cp->drv_state |= CNIC_DRV_STATE_REGD;
13326 cp->iro_arr = bp->iro_arr;
13327
13328 bnx2x_setup_cnic_irq_info(bp);
13329
13330 rcu_assign_pointer(bp->cnic_ops, ops);
13331
13332 return 0;
13333 }
13334
13335 static int bnx2x_unregister_cnic(struct net_device *dev)
13336 {
13337 struct bnx2x *bp = netdev_priv(dev);
13338 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13339
13340 mutex_lock(&bp->cnic_mutex);
13341 cp->drv_state = 0;
13342 RCU_INIT_POINTER(bp->cnic_ops, NULL);
13343 mutex_unlock(&bp->cnic_mutex);
13344 synchronize_rcu();
13345 kfree(bp->cnic_kwq);
13346 bp->cnic_kwq = NULL;
13347
13348 return 0;
13349 }
13350
13351 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
13352 {
13353 struct bnx2x *bp = netdev_priv(dev);
13354 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13355
13356 /* If both iSCSI and FCoE are disabled - return NULL in
13357 * order to indicate CNIC that it should not try to work
13358 * with this device.
13359 */
13360 if (NO_ISCSI(bp) && NO_FCOE(bp))
13361 return NULL;
13362
13363 cp->drv_owner = THIS_MODULE;
13364 cp->chip_id = CHIP_ID(bp);
13365 cp->pdev = bp->pdev;
13366 cp->io_base = bp->regview;
13367 cp->io_base2 = bp->doorbells;
13368 cp->max_kwqe_pending = 8;
13369 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
13370 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13371 bnx2x_cid_ilt_lines(bp);
13372 cp->ctx_tbl_len = CNIC_ILT_LINES;
13373 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13374 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
13375 cp->drv_ctl = bnx2x_drv_ctl;
13376 cp->drv_register_cnic = bnx2x_register_cnic;
13377 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
13378 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13379 cp->iscsi_l2_client_id =
13380 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13381 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13382
13383 if (NO_ISCSI_OOO(bp))
13384 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13385
13386 if (NO_ISCSI(bp))
13387 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
13388
13389 if (NO_FCOE(bp))
13390 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
13391
13392 BNX2X_DEV_INFO(
13393 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
13394 cp->ctx_blk_size,
13395 cp->ctx_tbl_offset,
13396 cp->ctx_tbl_len,
13397 cp->starting_cid);
13398 return cp;
13399 }
13400
13401 u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
13402 {
13403 struct bnx2x *bp = fp->bp;
13404 u32 offset = BAR_USTRORM_INTMEM;
13405
13406 if (IS_VF(bp))
13407 return bnx2x_vf_ustorm_prods_offset(bp, fp);
13408 else if (!CHIP_IS_E1x(bp))
13409 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
13410 else
13411 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
13412
13413 return offset;
13414 }
13415
13416 /* called only on E1H or E2.
13417 * When pretending to be PF, the pretend value is the function number 0...7
13418 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
13419 * combination
13420 */
13421 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
13422 {
13423 u32 pretend_reg;
13424
13425 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
13426 return -1;
13427
13428 /* get my own pretend register */
13429 pretend_reg = bnx2x_get_pretend_reg(bp);
13430 REG_WR(bp, pretend_reg, pretend_func_val);
13431 REG_RD(bp, pretend_reg);
13432 return 0;
13433 }
Linus' kernel tree