arch/x86/oprofile/nmi_int.c

   1 /**
   2  * @file nmi_int.c
   3  *
   4  * @remark Copyright 2002 OProfile authors
   5  * @remark Read the file COPYING
   6  *
   7  * @author John Levon <levon@movementarian.org>
   8  */
   9
  10 #include <linux/init.h>
  11 #include <linux/notifier.h>
  12 #include <linux/smp.h>
  13 #include <linux/oprofile.h>
  14 #include <linux/sysdev.h>
  15 #include <linux/slab.h>
  16 #include <linux/moduleparam.h>
  17 #include <linux/kdebug.h>
  18 #include <asm/nmi.h>
  19 #include <asm/msr.h>
  20 #include <asm/apic.h>
  21
  22 #include "op_counter.h"
  23 #include "op_x86_model.h"
  24
  25 static struct op_x86_model_spec const *model;
  26 static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
  27 static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
  28
  29 static int nmi_start(void);
  30 static void nmi_stop(void);
  31
  32 /* 0 == registered but off, 1 == registered and on */
  33 static int nmi_enabled = 0;
  34
  35 #ifdef CONFIG_PM
  36
  37 static int nmi_suspend(struct sys_device *dev, pm_message_t state)
  38 {
  39         if (nmi_enabled == 1)
  40                 nmi_stop();
  41         return 0;
  42 }
  43
  44 static int nmi_resume(struct sys_device *dev)
  45 {
  46         if (nmi_enabled == 1)
  47                 nmi_start();
  48         return 0;
  49 }
  50
  51 static struct sysdev_class oprofile_sysclass = {
  52         .name           = "oprofile",
  53         .resume         = nmi_resume,
  54         .suspend        = nmi_suspend,
  55 };
  56
  57 static struct sys_device device_oprofile = {
  58         .id     = 0,
  59         .cls    = &oprofile_sysclass,
  60 };
  61
  62 static int __init init_sysfs(void)
  63 {
  64         int error;
  65
  66         error = sysdev_class_register(&oprofile_sysclass);
  67         if (!error)
  68                 error = sysdev_register(&device_oprofile);
  69         return error;
  70 }
  71
  72 static void exit_sysfs(void)
  73 {
  74         sysdev_unregister(&device_oprofile);
  75         sysdev_class_unregister(&oprofile_sysclass);
  76 }
  77
  78 #else
  79 #define init_sysfs() do { } while (0)
  80 #define exit_sysfs() do { } while (0)
  81 #endif /* CONFIG_PM */
  82
  83 static int profile_exceptions_notify(struct notifier_block *self,
  84                                      unsigned long val, void *data)
  85 {
  86         struct die_args *args = (struct die_args *)data;
  87         int ret = NOTIFY_DONE;
  88         int cpu = smp_processor_id();
  89
  90         switch (val) {
  91         case DIE_NMI:
  92                 if (model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu)))
  93                         ret = NOTIFY_STOP;
  94                 break;
  95         default:
  96                 break;
  97         }
  98         return ret;
  99 }
 100
 101 static void nmi_cpu_save_registers(struct op_msrs *msrs)
 102 {
 103         unsigned int const nr_ctrs = model->num_counters;
 104         unsigned int const nr_ctrls = model->num_controls;
 105         struct op_msr *counters = msrs->counters;
 106         struct op_msr *controls = msrs->controls;
 107         unsigned int i;
 108
 109         for (i = 0; i < nr_ctrs; ++i) {
 110                 if (counters[i].addr) {
 111                         rdmsr(counters[i].addr,
 112                                 counters[i].saved.low,
 113                                 counters[i].saved.high);
 114                 }
 115         }
 116
 117         for (i = 0; i < nr_ctrls; ++i) {
 118                 if (controls[i].addr) {
 119                         rdmsr(controls[i].addr,
 120                                 controls[i].saved.low,
 121                                 controls[i].saved.high);
 122                 }
 123         }
 124 }
 125
 126 static void nmi_save_registers(void *dummy)
 127 {
 128         int cpu = smp_processor_id();
 129         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 130         nmi_cpu_save_registers(msrs);
 131 }
 132
 133 static void free_msrs(void)
 134 {
 135         int i;
 136         for_each_possible_cpu(i) {
 137                 kfree(per_cpu(cpu_msrs, i).counters);
 138                 per_cpu(cpu_msrs, i).counters = NULL;
 139                 kfree(per_cpu(cpu_msrs, i).controls);
 140                 per_cpu(cpu_msrs, i).controls = NULL;
 141         }
 142 }
 143
 144 static int allocate_msrs(void)
 145 {
 146         int success = 1;
 147         size_t controls_size = sizeof(struct op_msr) * model->num_controls;
 148         size_t counters_size = sizeof(struct op_msr) * model->num_counters;
 149
 150         int i;
 151         for_each_possible_cpu(i) {
 152                 per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
 153                                                                 GFP_KERNEL);
 154                 if (!per_cpu(cpu_msrs, i).counters) {
 155                         success = 0;
 156                         break;
 157                 }
 158                 per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
 159                                                                 GFP_KERNEL);
 160                 if (!per_cpu(cpu_msrs, i).controls) {
 161                         success = 0;
 162                         break;
 163                 }
 164         }
 165
 166         if (!success)
 167                 free_msrs();
 168
 169         return success;
 170 }
 171
 172 static void nmi_cpu_setup(void *dummy)
 173 {
 174         int cpu = smp_processor_id();
 175         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 176         spin_lock(&oprofilefs_lock);
 177         model->setup_ctrs(msrs);
 178         spin_unlock(&oprofilefs_lock);
 179         per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
 180         apic_write(APIC_LVTPC, APIC_DM_NMI);
 181 }
 182
 183 static struct notifier_block profile_exceptions_nb = {
 184         .notifier_call = profile_exceptions_notify,
 185         .next = NULL,
 186         .priority = 0
 187 };
 188
 189 static int nmi_setup(void)
 190 {
 191         int err = 0;
 192         int cpu;
 193
 194         if (!allocate_msrs())
 195                 return -ENOMEM;
 196
 197         err = register_die_notifier(&profile_exceptions_nb);
 198         if (err) {
 199                 free_msrs();
 200                 return err;
 201         }
 202
 203         /* We need to serialize save and setup for HT because the subset
 204          * of msrs are distinct for save and setup operations
 205          */
 206
 207         /* Assume saved/restored counters are the same on all CPUs */
 208         model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
 209         for_each_possible_cpu(cpu) {
 210                 if (cpu != 0) {
 211                         memcpy(per_cpu(cpu_msrs, cpu).counters,
 212                                 per_cpu(cpu_msrs, 0).counters,
 213                                 sizeof(struct op_msr) * model->num_counters);
 214
 215                         memcpy(per_cpu(cpu_msrs, cpu).controls,
 216                                 per_cpu(cpu_msrs, 0).controls,
 217                                 sizeof(struct op_msr) * model->num_controls);
 218                 }
 219
 220         }
 221         on_each_cpu(nmi_save_registers, NULL, 0, 1);
 222         on_each_cpu(nmi_cpu_setup, NULL, 0, 1);
 223         nmi_enabled = 1;
 224         return 0;
 225 }
 226
 227 static void nmi_restore_registers(struct op_msrs *msrs)
 228 {
 229         unsigned int const nr_ctrs = model->num_counters;
 230         unsigned int const nr_ctrls = model->num_controls;
 231         struct op_msr *counters = msrs->counters;
 232         struct op_msr *controls = msrs->controls;
 233         unsigned int i;
 234
 235         for (i = 0; i < nr_ctrls; ++i) {
 236                 if (controls[i].addr) {
 237                         wrmsr(controls[i].addr,
 238                                 controls[i].saved.low,
 239                                 controls[i].saved.high);
 240                 }
 241         }
 242
 243         for (i = 0; i < nr_ctrs; ++i) {
 244                 if (counters[i].addr) {
 245                         wrmsr(counters[i].addr,
 246                                 counters[i].saved.low,
 247                                 counters[i].saved.high);
 248                 }
 249         }
 250 }
 251
 252 static void nmi_cpu_shutdown(void *dummy)
 253 {
 254         unsigned int v;
 255         int cpu = smp_processor_id();
 256         struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);
 257
 258         /* restoring APIC_LVTPC can trigger an apic error because the delivery
 259          * mode and vector nr combination can be illegal. That's by design: on
 260          * power on apic lvt contain a zero vector nr which are legal only for
 261          * NMI delivery mode. So inhibit apic err before restoring lvtpc
 262          */
 263         v = apic_read(APIC_LVTERR);
 264         apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
 265         apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
 266         apic_write(APIC_LVTERR, v);
 267         nmi_restore_registers(msrs);
 268 }
 269
 270 static void nmi_shutdown(void)
 271 {
 272         struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);
 273         nmi_enabled = 0;
 274         on_each_cpu(nmi_cpu_shutdown, NULL, 0, 1);
 275         unregister_die_notifier(&profile_exceptions_nb);
 276         model->shutdown(msrs);
 277         free_msrs();
 278 }
 279
 280 static void nmi_cpu_start(void *dummy)
 281 {
 282         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
 283         model->start(msrs);
 284 }
 285
 286 static int nmi_start(void)
 287 {
 288         on_each_cpu(nmi_cpu_start, NULL, 0, 1);
 289         return 0;
 290 }
 291
 292 static void nmi_cpu_stop(void *dummy)
 293 {
 294         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
 295         model->stop(msrs);
 296 }
 297
 298 static void nmi_stop(void)
 299 {
 300         on_each_cpu(nmi_cpu_stop, NULL, 0, 1);
 301 }
 302
 303 struct op_counter_config counter_config[OP_MAX_COUNTER];
 304
 305 static int nmi_create_files(struct super_block *sb, struct dentry *root)
 306 {
 307         unsigned int i;
 308
 309         for (i = 0; i < model->num_counters; ++i) {
 310                 struct dentry *dir;
 311                 char buf[4];
 312
 313                 /* quick little hack to _not_ expose a counter if it is not
 314                  * available for use.  This should protect userspace app.
 315                  * NOTE:  assumes 1:1 mapping here (that counters are organized
 316                  *        sequentially in their struct assignment).
 317                  */
 318                 if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
 319                         continue;
 320
 321                 snprintf(buf,  sizeof(buf), "%d", i);
 322                 dir = oprofilefs_mkdir(sb, root, buf);
 323                 oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
 324                 oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
 325                 oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
 326                 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
 327                 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
 328                 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
 329         }
 330
 331         return 0;
 332 }
 333
 334 static int p4force;
 335 module_param(p4force, int, 0);
 336
 337 static int __init p4_init(char **cpu_type)
 338 {
 339         __u8 cpu_model = boot_cpu_data.x86_model;
 340
 341         if (!p4force && (cpu_model > 6 || cpu_model == 5))
 342                 return 0;
 343
 344 #ifndef CONFIG_SMP
 345         *cpu_type = "i386/p4";
 346         model = &op_p4_spec;
 347         return 1;
 348 #else
 349         switch (smp_num_siblings) {
 350         case 1:
 351                 *cpu_type = "i386/p4";
 352                 model = &op_p4_spec;
 353                 return 1;
 354
 355         case 2:
 356                 *cpu_type = "i386/p4-ht";
 357                 model = &op_p4_ht2_spec;
 358                 return 1;
 359         }
 360 #endif
 361
 362         printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
 363         printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
 364         return 0;
 365 }
 366
 367 static int __init ppro_init(char **cpu_type)
 368 {
 369         __u8 cpu_model = boot_cpu_data.x86_model;
 370
 371         if (cpu_model == 14)
 372                 *cpu_type = "i386/core";
 373         else if (cpu_model == 15 || cpu_model == 23)
 374                 *cpu_type = "i386/core_2";
 375         else if (cpu_model > 0xd)
 376                 return 0;
 377         else if (cpu_model == 9) {
 378                 *cpu_type = "i386/p6_mobile";
 379         } else if (cpu_model > 5) {
 380                 *cpu_type = "i386/piii";
 381         } else if (cpu_model > 2) {
 382                 *cpu_type = "i386/pii";
 383         } else {
 384                 *cpu_type = "i386/ppro";
 385         }
 386
 387         model = &op_ppro_spec;
 388         return 1;
 389 }
 390
 391 /* in order to get sysfs right */
 392 static int using_nmi;
 393
 394 int __init op_nmi_init(struct oprofile_operations *ops)
 395 {
 396         __u8 vendor = boot_cpu_data.x86_vendor;
 397         __u8 family = boot_cpu_data.x86;
 398         char *cpu_type;
 399
 400         if (!cpu_has_apic)
 401                 return -ENODEV;
 402
 403         switch (vendor) {
 404         case X86_VENDOR_AMD:
 405                 /* Needs to be at least an Athlon (or hammer in 32bit mode) */
 406
 407                 switch (family) {
 408                 default:
 409                         return -ENODEV;
 410                 case 6:
 411                         model = &op_athlon_spec;
 412                         cpu_type = "i386/athlon";
 413                         break;
 414                 case 0xf:
 415                         model = &op_athlon_spec;
 416                         /* Actually it could be i386/hammer too, but give
 417                          user space an consistent name. */
 418                         cpu_type = "x86-64/hammer";
 419                         break;
 420                 case 0x10:
 421                         model = &op_athlon_spec;
 422                         cpu_type = "x86-64/family10";
 423                         break;
 424                 }
 425                 break;
 426
 427         case X86_VENDOR_INTEL:
 428                 switch (family) {
 429                         /* Pentium IV */
 430                 case 0xf:
 431                         if (!p4_init(&cpu_type))
 432                                 return -ENODEV;
 433                         break;
 434
 435                         /* A P6-class processor */
 436                 case 6:
 437                         if (!ppro_init(&cpu_type))
 438                                 return -ENODEV;
 439                         break;
 440
 441                 default:
 442                         return -ENODEV;
 443                 }
 444                 break;
 445
 446         default:
 447                 return -ENODEV;
 448         }
 449
 450         init_sysfs();
 451         using_nmi = 1;
 452         ops->create_files = nmi_create_files;
 453         ops->setup = nmi_setup;
 454         ops->shutdown = nmi_shutdown;
 455         ops->start = nmi_start;
 456         ops->stop = nmi_stop;
 457         ops->cpu_type = cpu_type;
 458         printk(KERN_INFO "oprofile: using NMI interrupt.\n");
 459         return 0;
 460 }
 461
 462 void op_nmi_exit(void)
 463 {
 464         if (using_nmi)
 465                 exit_sysfs();
 466 }