x86: move X86_FEATURE_CONSTANT_TSC into early cpu feature detection
[linux-2.6.git] / arch / x86 / kernel / smpboot_64.c
blob5bd42ce144da541e071809edba87280a282124e9
1 /*
2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2
17 * Fixes
18 * Felix Koop : NR_CPUS used properly
19 * Jose Renau : Handle single CPU case.
20 * Alan Cox : By repeated request 8) - Total BogoMIP report.
21 * Greg Wright : Fix for kernel stacks panic.
22 * Erich Boleyn : MP v1.4 and additional changes.
23 * Matthias Sattler : Changes for 2.1 kernel map.
24 * Michel Lespinasse : Changes for 2.1 kernel map.
25 * Michael Chastain : Change trampoline.S to gnu as.
26 * Alan Cox : Dumb bug: 'B' step PPro's are fine
27 * Ingo Molnar : Added APIC timers, based on code
28 * from Jose Renau
29 * Ingo Molnar : various cleanups and rewrites
30 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
31 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
32 * Andi Kleen : Changed for SMP boot into long mode.
33 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
34 * Andi Kleen : Converted to new state machine.
35 * Various cleanups.
36 * Probably mostly hotplug CPU ready now.
37 * Ashok Raj : CPU hotplug support
41 #include <linux/init.h>
43 #include <linux/mm.h>
44 #include <linux/kernel_stat.h>
45 #include <linux/bootmem.h>
46 #include <linux/thread_info.h>
47 #include <linux/module.h>
48 #include <linux/delay.h>
49 #include <linux/mc146818rtc.h>
50 #include <linux/smp.h>
51 #include <linux/kdebug.h>
53 #include <asm/mtrr.h>
54 #include <asm/pgalloc.h>
55 #include <asm/desc.h>
56 #include <asm/tlbflush.h>
57 #include <asm/proto.h>
58 #include <asm/nmi.h>
59 #include <asm/irq.h>
60 #include <asm/hw_irq.h>
61 #include <asm/numa.h>
63 /* Number of siblings per CPU package */
64 int smp_num_siblings = 1;
65 EXPORT_SYMBOL(smp_num_siblings);
67 /* Last level cache ID of each logical CPU */
68 DEFINE_PER_CPU(u8, cpu_llc_id) = BAD_APICID;
70 /* Bitmask of currently online CPUs */
71 cpumask_t cpu_online_map __read_mostly;
73 EXPORT_SYMBOL(cpu_online_map);
76 * Private maps to synchronize booting between AP and BP.
77 * Probably not needed anymore, but it makes for easier debugging. -AK
79 cpumask_t cpu_callin_map;
80 cpumask_t cpu_callout_map;
81 cpumask_t cpu_possible_map;
82 EXPORT_SYMBOL(cpu_possible_map);
84 /* Per CPU bogomips and other parameters */
85 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
86 EXPORT_PER_CPU_SYMBOL(cpu_info);
88 /* Set when the idlers are all forked */
89 int smp_threads_ready;
91 /* representing HT siblings of each logical CPU */
92 DEFINE_PER_CPU(cpumask_t, cpu_sibling_map);
93 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
95 /* representing HT and core siblings of each logical CPU */
96 DEFINE_PER_CPU(cpumask_t, cpu_core_map);
97 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
100 * Trampoline 80x86 program as an array.
103 extern const unsigned char trampoline_data[];
104 extern const unsigned char trampoline_end[];
106 /* State of each CPU */
107 DEFINE_PER_CPU(int, cpu_state) = { 0 };
110 * Store all idle threads, this can be reused instead of creating
111 * a new thread. Also avoids complicated thread destroy functionality
112 * for idle threads.
114 struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
116 #define get_idle_for_cpu(x) (idle_thread_array[(x)])
117 #define set_idle_for_cpu(x,p) (idle_thread_array[(x)] = (p))
120 * Currently trivial. Write the real->protected mode
121 * bootstrap into the page concerned. The caller
122 * has made sure it's suitably aligned.
125 static unsigned long __cpuinit setup_trampoline(void)
127 void *tramp = __va(SMP_TRAMPOLINE_BASE);
128 memcpy(tramp, trampoline_data, trampoline_end - trampoline_data);
129 return virt_to_phys(tramp);
133 * The bootstrap kernel entry code has set these up. Save them for
134 * a given CPU
137 static void __cpuinit smp_store_cpu_info(int id)
139 struct cpuinfo_x86 *c = &cpu_data(id);
141 *c = boot_cpu_data;
142 c->cpu_index = id;
143 identify_cpu(c);
144 print_cpu_info(c);
147 static atomic_t init_deasserted __cpuinitdata;
150 * Report back to the Boot Processor.
151 * Running on AP.
153 void __cpuinit smp_callin(void)
155 int cpuid, phys_id;
156 unsigned long timeout;
159 * If waken up by an INIT in an 82489DX configuration
160 * we may get here before an INIT-deassert IPI reaches
161 * our local APIC. We have to wait for the IPI or we'll
162 * lock up on an APIC access.
164 while (!atomic_read(&init_deasserted))
165 cpu_relax();
168 * (This works even if the APIC is not enabled.)
170 phys_id = GET_APIC_ID(apic_read(APIC_ID));
171 cpuid = smp_processor_id();
172 if (cpu_isset(cpuid, cpu_callin_map)) {
173 panic("smp_callin: phys CPU#%d, CPU#%d already present??\n",
174 phys_id, cpuid);
176 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
179 * STARTUP IPIs are fragile beasts as they might sometimes
180 * trigger some glue motherboard logic. Complete APIC bus
181 * silence for 1 second, this overestimates the time the
182 * boot CPU is spending to send the up to 2 STARTUP IPIs
183 * by a factor of two. This should be enough.
187 * Waiting 2s total for startup (udelay is not yet working)
189 timeout = jiffies + 2*HZ;
190 while (time_before(jiffies, timeout)) {
192 * Has the boot CPU finished it's STARTUP sequence?
194 if (cpu_isset(cpuid, cpu_callout_map))
195 break;
196 cpu_relax();
199 if (!time_before(jiffies, timeout)) {
200 panic("smp_callin: CPU%d started up but did not get a callout!\n",
201 cpuid);
205 * the boot CPU has finished the init stage and is spinning
206 * on callin_map until we finish. We are free to set up this
207 * CPU, first the APIC. (this is probably redundant on most
208 * boards)
211 Dprintk("CALLIN, before setup_local_APIC().\n");
212 setup_local_APIC();
213 end_local_APIC_setup();
216 * Get our bogomips.
218 * Need to enable IRQs because it can take longer and then
219 * the NMI watchdog might kill us.
221 local_irq_enable();
222 calibrate_delay();
223 local_irq_disable();
224 Dprintk("Stack at about %p\n",&cpuid);
227 * Save our processor parameters
229 smp_store_cpu_info(cpuid);
232 * Allow the master to continue.
234 cpu_set(cpuid, cpu_callin_map);
237 /* maps the cpu to the sched domain representing multi-core */
238 cpumask_t cpu_coregroup_map(int cpu)
240 struct cpuinfo_x86 *c = &cpu_data(cpu);
242 * For perf, we return last level cache shared map.
243 * And for power savings, we return cpu_core_map
245 if (sched_mc_power_savings || sched_smt_power_savings)
246 return per_cpu(cpu_core_map, cpu);
247 else
248 return c->llc_shared_map;
251 /* representing cpus for which sibling maps can be computed */
252 static cpumask_t cpu_sibling_setup_map;
254 static inline void set_cpu_sibling_map(int cpu)
256 int i;
257 struct cpuinfo_x86 *c = &cpu_data(cpu);
259 cpu_set(cpu, cpu_sibling_setup_map);
261 if (smp_num_siblings > 1) {
262 for_each_cpu_mask(i, cpu_sibling_setup_map) {
263 if (c->phys_proc_id == cpu_data(i).phys_proc_id &&
264 c->cpu_core_id == cpu_data(i).cpu_core_id) {
265 cpu_set(i, per_cpu(cpu_sibling_map, cpu));
266 cpu_set(cpu, per_cpu(cpu_sibling_map, i));
267 cpu_set(i, per_cpu(cpu_core_map, cpu));
268 cpu_set(cpu, per_cpu(cpu_core_map, i));
269 cpu_set(i, c->llc_shared_map);
270 cpu_set(cpu, cpu_data(i).llc_shared_map);
273 } else {
274 cpu_set(cpu, per_cpu(cpu_sibling_map, cpu));
277 cpu_set(cpu, c->llc_shared_map);
279 if (current_cpu_data.x86_max_cores == 1) {
280 per_cpu(cpu_core_map, cpu) = per_cpu(cpu_sibling_map, cpu);
281 c->booted_cores = 1;
282 return;
285 for_each_cpu_mask(i, cpu_sibling_setup_map) {
286 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID &&
287 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) {
288 cpu_set(i, c->llc_shared_map);
289 cpu_set(cpu, cpu_data(i).llc_shared_map);
291 if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
292 cpu_set(i, per_cpu(cpu_core_map, cpu));
293 cpu_set(cpu, per_cpu(cpu_core_map, i));
295 * Does this new cpu bringup a new core?
297 if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) {
299 * for each core in package, increment
300 * the booted_cores for this new cpu
302 if (first_cpu(per_cpu(cpu_sibling_map, i)) == i)
303 c->booted_cores++;
305 * increment the core count for all
306 * the other cpus in this package
308 if (i != cpu)
309 cpu_data(i).booted_cores++;
310 } else if (i != cpu && !c->booted_cores)
311 c->booted_cores = cpu_data(i).booted_cores;
317 * Setup code on secondary processor (after comming out of the trampoline)
319 void __cpuinit start_secondary(void)
322 * Dont put anything before smp_callin(), SMP
323 * booting is too fragile that we want to limit the
324 * things done here to the most necessary things.
326 cpu_init();
327 preempt_disable();
328 smp_callin();
330 /* otherwise gcc will move up the smp_processor_id before the cpu_init */
331 barrier();
334 * Check TSC sync first:
336 check_tsc_sync_target();
338 if (nmi_watchdog == NMI_IO_APIC) {
339 disable_8259A_irq(0);
340 enable_NMI_through_LVT0();
341 enable_8259A_irq(0);
345 * The sibling maps must be set before turing the online map on for
346 * this cpu
348 set_cpu_sibling_map(smp_processor_id());
351 * We need to hold call_lock, so there is no inconsistency
352 * between the time smp_call_function() determines number of
353 * IPI recipients, and the time when the determination is made
354 * for which cpus receive the IPI in genapic_flat.c. Holding this
355 * lock helps us to not include this cpu in a currently in progress
356 * smp_call_function().
358 lock_ipi_call_lock();
359 spin_lock(&vector_lock);
361 /* Setup the per cpu irq handling data structures */
362 __setup_vector_irq(smp_processor_id());
364 * Allow the master to continue.
366 cpu_set(smp_processor_id(), cpu_online_map);
367 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
368 spin_unlock(&vector_lock);
370 unlock_ipi_call_lock();
372 setup_secondary_clock();
374 cpu_idle();
377 extern volatile unsigned long init_rsp;
378 extern void (*initial_code)(void);
380 #ifdef APIC_DEBUG
381 static void inquire_remote_apic(int apicid)
383 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
384 char *names[] = { "ID", "VERSION", "SPIV" };
385 int timeout;
386 u32 status;
388 printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid);
390 for (i = 0; i < ARRAY_SIZE(regs); i++) {
391 printk(KERN_INFO "... APIC #%d %s: ", apicid, names[i]);
394 * Wait for idle.
396 status = safe_apic_wait_icr_idle();
397 if (status)
398 printk(KERN_CONT
399 "a previous APIC delivery may have failed\n");
401 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
402 apic_write(APIC_ICR, APIC_DM_REMRD | regs[i]);
404 timeout = 0;
405 do {
406 udelay(100);
407 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
408 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
410 switch (status) {
411 case APIC_ICR_RR_VALID:
412 status = apic_read(APIC_RRR);
413 printk(KERN_CONT "%08x\n", status);
414 break;
415 default:
416 printk(KERN_CONT "failed\n");
420 #endif
423 * Kick the secondary to wake up.
425 static int __cpuinit wakeup_secondary_via_INIT(int phys_apicid, unsigned int start_rip)
427 unsigned long send_status, accept_status = 0;
428 int maxlvt, num_starts, j;
430 Dprintk("Asserting INIT.\n");
433 * Turn INIT on target chip
435 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
438 * Send IPI
440 apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
441 | APIC_DM_INIT);
443 Dprintk("Waiting for send to finish...\n");
444 send_status = safe_apic_wait_icr_idle();
446 mdelay(10);
448 Dprintk("Deasserting INIT.\n");
450 /* Target chip */
451 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
453 /* Send IPI */
454 apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
456 Dprintk("Waiting for send to finish...\n");
457 send_status = safe_apic_wait_icr_idle();
459 mb();
460 atomic_set(&init_deasserted, 1);
462 num_starts = 2;
465 * Run STARTUP IPI loop.
467 Dprintk("#startup loops: %d.\n", num_starts);
469 maxlvt = lapic_get_maxlvt();
471 for (j = 1; j <= num_starts; j++) {
472 Dprintk("Sending STARTUP #%d.\n",j);
473 apic_write(APIC_ESR, 0);
474 apic_read(APIC_ESR);
475 Dprintk("After apic_write.\n");
478 * STARTUP IPI
481 /* Target chip */
482 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
484 /* Boot on the stack */
485 /* Kick the second */
486 apic_write(APIC_ICR, APIC_DM_STARTUP | (start_rip >> 12));
489 * Give the other CPU some time to accept the IPI.
491 udelay(300);
493 Dprintk("Startup point 1.\n");
495 Dprintk("Waiting for send to finish...\n");
496 send_status = safe_apic_wait_icr_idle();
499 * Give the other CPU some time to accept the IPI.
501 udelay(200);
503 * Due to the Pentium erratum 3AP.
505 if (maxlvt > 3) {
506 apic_write(APIC_ESR, 0);
508 accept_status = (apic_read(APIC_ESR) & 0xEF);
509 if (send_status || accept_status)
510 break;
512 Dprintk("After Startup.\n");
514 if (send_status)
515 printk(KERN_ERR "APIC never delivered???\n");
516 if (accept_status)
517 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
519 return (send_status | accept_status);
522 struct create_idle {
523 struct work_struct work;
524 struct task_struct *idle;
525 struct completion done;
526 int cpu;
529 static void __cpuinit do_fork_idle(struct work_struct *work)
531 struct create_idle *c_idle =
532 container_of(work, struct create_idle, work);
534 c_idle->idle = fork_idle(c_idle->cpu);
535 complete(&c_idle->done);
539 * Boot one CPU.
541 static int __cpuinit do_boot_cpu(int cpu, int apicid)
543 unsigned long boot_error;
544 int timeout;
545 unsigned long start_rip;
546 struct create_idle c_idle = {
547 .work = __WORK_INITIALIZER(c_idle.work, do_fork_idle),
548 .cpu = cpu,
549 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
552 /* allocate memory for gdts of secondary cpus. Hotplug is considered */
553 if (!cpu_gdt_descr[cpu].address &&
554 !(cpu_gdt_descr[cpu].address = get_zeroed_page(GFP_KERNEL))) {
555 printk(KERN_ERR "Failed to allocate GDT for CPU %d\n", cpu);
556 return -1;
559 /* Allocate node local memory for AP pdas */
560 if (cpu_pda(cpu) == &boot_cpu_pda[cpu]) {
561 struct x8664_pda *newpda, *pda;
562 int node = cpu_to_node(cpu);
563 pda = cpu_pda(cpu);
564 newpda = kmalloc_node(sizeof (struct x8664_pda), GFP_ATOMIC,
565 node);
566 if (newpda) {
567 memcpy(newpda, pda, sizeof (struct x8664_pda));
568 cpu_pda(cpu) = newpda;
569 } else
570 printk(KERN_ERR
571 "Could not allocate node local PDA for CPU %d on node %d\n",
572 cpu, node);
575 alternatives_smp_switch(1);
577 c_idle.idle = get_idle_for_cpu(cpu);
579 if (c_idle.idle) {
580 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *)
581 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1);
582 init_idle(c_idle.idle, cpu);
583 goto do_rest;
587 * During cold boot process, keventd thread is not spun up yet.
588 * When we do cpu hot-add, we create idle threads on the fly, we should
589 * not acquire any attributes from the calling context. Hence the clean
590 * way to create kernel_threads() is to do that from keventd().
591 * We do the current_is_keventd() due to the fact that ACPI notifier
592 * was also queuing to keventd() and when the caller is already running
593 * in context of keventd(), we would end up with locking up the keventd
594 * thread.
596 if (!keventd_up() || current_is_keventd())
597 c_idle.work.func(&c_idle.work);
598 else {
599 schedule_work(&c_idle.work);
600 wait_for_completion(&c_idle.done);
603 if (IS_ERR(c_idle.idle)) {
604 printk("failed fork for CPU %d\n", cpu);
605 return PTR_ERR(c_idle.idle);
608 set_idle_for_cpu(cpu, c_idle.idle);
610 do_rest:
612 cpu_pda(cpu)->pcurrent = c_idle.idle;
614 start_rip = setup_trampoline();
616 init_rsp = c_idle.idle->thread.sp;
617 load_sp0(&per_cpu(init_tss, cpu), &c_idle.idle->thread);
618 initial_code = start_secondary;
619 clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
621 printk(KERN_INFO "Booting processor %d/%d APIC 0x%x\n", cpu,
622 cpus_weight(cpu_present_map),
623 apicid);
626 * This grunge runs the startup process for
627 * the targeted processor.
630 atomic_set(&init_deasserted, 0);
632 Dprintk("Setting warm reset code and vector.\n");
634 CMOS_WRITE(0xa, 0xf);
635 local_flush_tlb();
636 Dprintk("1.\n");
637 *((volatile unsigned short *) phys_to_virt(0x469)) = start_rip >> 4;
638 Dprintk("2.\n");
639 *((volatile unsigned short *) phys_to_virt(0x467)) = start_rip & 0xf;
640 Dprintk("3.\n");
643 * Be paranoid about clearing APIC errors.
645 apic_write(APIC_ESR, 0);
646 apic_read(APIC_ESR);
649 * Status is now clean
651 boot_error = 0;
654 * Starting actual IPI sequence...
656 boot_error = wakeup_secondary_via_INIT(apicid, start_rip);
658 if (!boot_error) {
660 * allow APs to start initializing.
662 Dprintk("Before Callout %d.\n", cpu);
663 cpu_set(cpu, cpu_callout_map);
664 Dprintk("After Callout %d.\n", cpu);
667 * Wait 5s total for a response
669 for (timeout = 0; timeout < 50000; timeout++) {
670 if (cpu_isset(cpu, cpu_callin_map))
671 break; /* It has booted */
672 udelay(100);
675 if (cpu_isset(cpu, cpu_callin_map)) {
676 /* number CPUs logically, starting from 1 (BSP is 0) */
677 Dprintk("CPU has booted.\n");
678 } else {
679 boot_error = 1;
680 if (*((volatile unsigned char *)phys_to_virt(SMP_TRAMPOLINE_BASE))
681 == 0xA5)
682 /* trampoline started but...? */
683 printk("Stuck ??\n");
684 else
685 /* trampoline code not run */
686 printk("Not responding.\n");
687 #ifdef APIC_DEBUG
688 inquire_remote_apic(apicid);
689 #endif
692 if (boot_error) {
693 cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
694 clear_bit(cpu, (unsigned long *)&cpu_initialized); /* was set by cpu_init() */
695 clear_node_cpumask(cpu); /* was set by numa_add_cpu */
696 cpu_clear(cpu, cpu_present_map);
697 cpu_clear(cpu, cpu_possible_map);
698 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
699 return -EIO;
702 return 0;
705 cycles_t cacheflush_time;
706 unsigned long cache_decay_ticks;
709 * Cleanup possible dangling ends...
711 static __cpuinit void smp_cleanup_boot(void)
714 * Paranoid: Set warm reset code and vector here back
715 * to default values.
717 CMOS_WRITE(0, 0xf);
720 * Reset trampoline flag
722 *((volatile int *) phys_to_virt(0x467)) = 0;
726 * Fall back to non SMP mode after errors.
728 * RED-PEN audit/test this more. I bet there is more state messed up here.
730 static __init void disable_smp(void)
732 cpu_present_map = cpumask_of_cpu(0);
733 cpu_possible_map = cpumask_of_cpu(0);
734 if (smp_found_config)
735 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id);
736 else
737 phys_cpu_present_map = physid_mask_of_physid(0);
738 cpu_set(0, per_cpu(cpu_sibling_map, 0));
739 cpu_set(0, per_cpu(cpu_core_map, 0));
742 #ifdef CONFIG_HOTPLUG_CPU
744 int additional_cpus __initdata = -1;
747 * cpu_possible_map should be static, it cannot change as cpu's
748 * are onlined, or offlined. The reason is per-cpu data-structures
749 * are allocated by some modules at init time, and dont expect to
750 * do this dynamically on cpu arrival/departure.
751 * cpu_present_map on the other hand can change dynamically.
752 * In case when cpu_hotplug is not compiled, then we resort to current
753 * behaviour, which is cpu_possible == cpu_present.
754 * - Ashok Raj
756 * Three ways to find out the number of additional hotplug CPUs:
757 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
758 * - The user can overwrite it with additional_cpus=NUM
759 * - Otherwise don't reserve additional CPUs.
760 * We do this because additional CPUs waste a lot of memory.
761 * -AK
763 __init void prefill_possible_map(void)
765 int i;
766 int possible;
768 if (additional_cpus == -1) {
769 if (disabled_cpus > 0)
770 additional_cpus = disabled_cpus;
771 else
772 additional_cpus = 0;
774 possible = num_processors + additional_cpus;
775 if (possible > NR_CPUS)
776 possible = NR_CPUS;
778 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
779 possible,
780 max_t(int, possible - num_processors, 0));
782 for (i = 0; i < possible; i++)
783 cpu_set(i, cpu_possible_map);
785 #endif
788 * Various sanity checks.
790 static int __init smp_sanity_check(unsigned max_cpus)
792 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
793 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
794 hard_smp_processor_id());
795 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
799 * If we couldn't find an SMP configuration at boot time,
800 * get out of here now!
802 if (!smp_found_config) {
803 printk(KERN_NOTICE "SMP motherboard not detected.\n");
804 disable_smp();
805 if (APIC_init_uniprocessor())
806 printk(KERN_NOTICE "Local APIC not detected."
807 " Using dummy APIC emulation.\n");
808 return -1;
812 * Should not be necessary because the MP table should list the boot
813 * CPU too, but we do it for the sake of robustness anyway.
815 if (!physid_isset(boot_cpu_id, phys_cpu_present_map)) {
816 printk(KERN_NOTICE "weird, boot CPU (#%d) not listed by the BIOS.\n",
817 boot_cpu_id);
818 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
822 * If we couldn't find a local APIC, then get out of here now!
824 if (!cpu_has_apic) {
825 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
826 boot_cpu_id);
827 printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
828 nr_ioapics = 0;
829 return -1;
833 * If SMP should be disabled, then really disable it!
835 if (!max_cpus) {
836 printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n");
837 nr_ioapics = 0;
838 return -1;
841 return 0;
845 * Copy apicid's found by MP_processor_info from initial array to the per cpu
846 * data area. The x86_cpu_to_apicid_init array is then expendable and the
847 * x86_cpu_to_apicid_ptr is zeroed indicating that the static array is no
848 * longer available.
850 void __init smp_set_apicids(void)
852 int cpu;
854 for_each_cpu_mask(cpu, cpu_possible_map) {
855 if (per_cpu_offset(cpu))
856 per_cpu(x86_cpu_to_apicid, cpu) =
857 x86_cpu_to_apicid_init[cpu];
860 /* indicate the static array will be going away soon */
861 x86_cpu_to_apicid_ptr = NULL;
864 static void __init smp_cpu_index_default(void)
866 int i;
867 struct cpuinfo_x86 *c;
869 for_each_cpu_mask(i, cpu_possible_map) {
870 c = &cpu_data(i);
871 /* mark all to hotplug */
872 c->cpu_index = NR_CPUS;
877 * Prepare for SMP bootup. The MP table or ACPI has been read
878 * earlier. Just do some sanity checking here and enable APIC mode.
880 void __init smp_prepare_cpus(unsigned int max_cpus)
882 nmi_watchdog_default();
883 smp_cpu_index_default();
884 current_cpu_data = boot_cpu_data;
885 current_thread_info()->cpu = 0; /* needed? */
886 smp_set_apicids();
887 set_cpu_sibling_map(0);
889 if (smp_sanity_check(max_cpus) < 0) {
890 printk(KERN_INFO "SMP disabled\n");
891 disable_smp();
892 return;
897 * Switch from PIC to APIC mode.
899 setup_local_APIC();
902 * Enable IO APIC before setting up error vector
904 if (!skip_ioapic_setup && nr_ioapics)
905 enable_IO_APIC();
906 end_local_APIC_setup();
908 if (GET_APIC_ID(apic_read(APIC_ID)) != boot_cpu_id) {
909 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
910 GET_APIC_ID(apic_read(APIC_ID)), boot_cpu_id);
911 /* Or can we switch back to PIC here? */
915 * Now start the IO-APICs
917 if (!skip_ioapic_setup && nr_ioapics)
918 setup_IO_APIC();
919 else
920 nr_ioapics = 0;
923 * Set up local APIC timer on boot CPU.
926 setup_boot_clock();
930 * Early setup to make printk work.
932 void __init smp_prepare_boot_cpu(void)
934 int me = smp_processor_id();
935 cpu_set(me, cpu_online_map);
936 cpu_set(me, cpu_callout_map);
937 per_cpu(cpu_state, me) = CPU_ONLINE;
941 * Entry point to boot a CPU.
943 int __cpuinit __cpu_up(unsigned int cpu)
945 int apicid = cpu_present_to_apicid(cpu);
946 unsigned long flags;
947 int err;
949 WARN_ON(irqs_disabled());
951 Dprintk("++++++++++++++++++++=_---CPU UP %u\n", cpu);
953 if (apicid == BAD_APICID || apicid == boot_cpu_id ||
954 !physid_isset(apicid, phys_cpu_present_map)) {
955 printk("__cpu_up: bad cpu %d\n", cpu);
956 return -EINVAL;
960 * Already booted CPU?
962 if (cpu_isset(cpu, cpu_callin_map)) {
963 Dprintk("do_boot_cpu %d Already started\n", cpu);
964 return -ENOSYS;
968 * Save current MTRR state in case it was changed since early boot
969 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
971 mtrr_save_state();
973 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
974 /* Boot it! */
975 err = do_boot_cpu(cpu, apicid);
976 if (err < 0) {
977 Dprintk("do_boot_cpu failed %d\n", err);
978 return err;
981 /* Unleash the CPU! */
982 Dprintk("waiting for cpu %d\n", cpu);
985 * Make sure and check TSC sync:
987 local_irq_save(flags);
988 check_tsc_sync_source(cpu);
989 local_irq_restore(flags);
991 while (!cpu_isset(cpu, cpu_online_map))
992 cpu_relax();
993 err = 0;
995 return err;
999 * Finish the SMP boot.
1001 void __init smp_cpus_done(unsigned int max_cpus)
1003 smp_cleanup_boot();
1004 setup_ioapic_dest();
1005 check_nmi_watchdog();
1008 #ifdef CONFIG_HOTPLUG_CPU
1010 static void remove_siblinginfo(int cpu)
1012 int sibling;
1013 struct cpuinfo_x86 *c = &cpu_data(cpu);
1015 for_each_cpu_mask(sibling, per_cpu(cpu_core_map, cpu)) {
1016 cpu_clear(cpu, per_cpu(cpu_core_map, sibling));
1018 * last thread sibling in this cpu core going down
1020 if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1)
1021 cpu_data(sibling).booted_cores--;
1024 for_each_cpu_mask(sibling, per_cpu(cpu_sibling_map, cpu))
1025 cpu_clear(cpu, per_cpu(cpu_sibling_map, sibling));
1026 cpus_clear(per_cpu(cpu_sibling_map, cpu));
1027 cpus_clear(per_cpu(cpu_core_map, cpu));
1028 c->phys_proc_id = 0;
1029 c->cpu_core_id = 0;
1030 cpu_clear(cpu, cpu_sibling_setup_map);
1033 void remove_cpu_from_maps(void)
1035 int cpu = smp_processor_id();
1037 cpu_clear(cpu, cpu_callout_map);
1038 cpu_clear(cpu, cpu_callin_map);
1039 clear_bit(cpu, (unsigned long *)&cpu_initialized); /* was set by cpu_init() */
1040 clear_node_cpumask(cpu);
1043 int __cpu_disable(void)
1045 int cpu = smp_processor_id();
1048 * Perhaps use cpufreq to drop frequency, but that could go
1049 * into generic code.
1051 * We won't take down the boot processor on i386 due to some
1052 * interrupts only being able to be serviced by the BSP.
1053 * Especially so if we're not using an IOAPIC -zwane
1055 if (cpu == 0)
1056 return -EBUSY;
1058 if (nmi_watchdog == NMI_LOCAL_APIC)
1059 stop_apic_nmi_watchdog(NULL);
1060 clear_local_APIC();
1063 * HACK:
1064 * Allow any queued timer interrupts to get serviced
1065 * This is only a temporary solution until we cleanup
1066 * fixup_irqs as we do for IA64.
1068 local_irq_enable();
1069 mdelay(1);
1071 local_irq_disable();
1072 remove_siblinginfo(cpu);
1074 spin_lock(&vector_lock);
1075 /* It's now safe to remove this processor from the online map */
1076 cpu_clear(cpu, cpu_online_map);
1077 spin_unlock(&vector_lock);
1078 remove_cpu_from_maps();
1079 fixup_irqs(cpu_online_map);
1080 return 0;
1083 void __cpu_die(unsigned int cpu)
1085 /* We don't do anything here: idle task is faking death itself. */
1086 unsigned int i;
1088 for (i = 0; i < 10; i++) {
1089 /* They ack this in play_dead by setting CPU_DEAD */
1090 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1091 printk ("CPU %d is now offline\n", cpu);
1092 if (1 == num_online_cpus())
1093 alternatives_smp_switch(0);
1094 return;
1096 msleep(100);
1098 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1101 static __init int setup_additional_cpus(char *s)
1103 return s && get_option(&s, &additional_cpus) ? 0 : -EINVAL;
1105 early_param("additional_cpus", setup_additional_cpus);
1107 #else /* ... !CONFIG_HOTPLUG_CPU */
1109 int __cpu_disable(void)
1111 return -ENOSYS;
1114 void __cpu_die(unsigned int cpu)
1116 /* We said "no" in __cpu_disable */
1117 BUG();
1119 #endif /* CONFIG_HOTPLUG_CPU */