2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/cpu.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmi.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/arch_hooks.h>
39 #include <asm/i8253.h>
42 #include <mach_apic.h>
43 #include <mach_apicdef.h>
49 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
50 # error SPURIOUS_APIC_VECTOR definition error
54 * Knob to control our willingness to enable the local APIC.
56 * -1=force-disable, +1=force-enable
58 static int enable_local_apic __initdata
;
60 /* Local APIC timer verification ok */
61 static int local_apic_timer_verify_ok
;
62 /* Disable local APIC timer from the kernel commandline or via dmi quirk
63 or using CPU MSR check */
64 int local_apic_timer_disabled
;
65 /* Local APIC timer works in C2 */
66 int local_apic_timer_c2_ok
;
67 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
70 * Debug level, exported for io_apic.c
74 static unsigned int calibration_result
;
76 static int lapic_next_event(unsigned long delta
,
77 struct clock_event_device
*evt
);
78 static void lapic_timer_setup(enum clock_event_mode mode
,
79 struct clock_event_device
*evt
);
80 static void lapic_timer_broadcast(cpumask_t mask
);
81 static void apic_pm_activate(void);
84 * The local apic timer can be used for any function which is CPU local.
86 static struct clock_event_device lapic_clockevent
= {
88 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
89 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
91 .set_mode
= lapic_timer_setup
,
92 .set_next_event
= lapic_next_event
,
93 .broadcast
= lapic_timer_broadcast
,
97 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
99 /* Local APIC was disabled by the BIOS and enabled by the kernel */
100 static int enabled_via_apicbase
;
103 * Get the LAPIC version
105 static inline int lapic_get_version(void)
107 return GET_APIC_VERSION(apic_read(APIC_LVR
));
111 * Check, if the APIC is integrated or a separate chip
113 static inline int lapic_is_integrated(void)
115 return APIC_INTEGRATED(lapic_get_version());
119 * Check, whether this is a modern or a first generation APIC
121 static int modern_apic(void)
123 /* AMD systems use old APIC versions, so check the CPU */
124 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
125 boot_cpu_data
.x86
>= 0xf)
127 return lapic_get_version() >= 0x14;
130 void apic_wait_icr_idle(void)
132 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
136 u32
safe_apic_wait_icr_idle(void)
143 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
147 } while (timeout
++ < 1000);
153 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
155 void __cpuinit
enable_NMI_through_LVT0(void)
157 unsigned int v
= APIC_DM_NMI
;
159 /* Level triggered for 82489DX */
160 if (!lapic_is_integrated())
161 v
|= APIC_LVT_LEVEL_TRIGGER
;
162 apic_write_around(APIC_LVT0
, v
);
166 * get_physical_broadcast - Get number of physical broadcast IDs
168 int get_physical_broadcast(void)
170 return modern_apic() ? 0xff : 0xf;
174 * lapic_get_maxlvt - get the maximum number of local vector table entries
176 int lapic_get_maxlvt(void)
178 unsigned int v
= apic_read(APIC_LVR
);
180 /* 82489DXs do not report # of LVT entries. */
181 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
188 /* Clock divisor is set to 16 */
189 #define APIC_DIVISOR 16
192 * This function sets up the local APIC timer, with a timeout of
193 * 'clocks' APIC bus clock. During calibration we actually call
194 * this function twice on the boot CPU, once with a bogus timeout
195 * value, second time for real. The other (noncalibrating) CPUs
196 * call this function only once, with the real, calibrated value.
198 * We do reads before writes even if unnecessary, to get around the
199 * P5 APIC double write bug.
201 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
203 unsigned int lvtt_value
, tmp_value
;
205 lvtt_value
= LOCAL_TIMER_VECTOR
;
207 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
208 if (!lapic_is_integrated())
209 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
212 lvtt_value
|= APIC_LVT_MASKED
;
214 apic_write_around(APIC_LVTT
, lvtt_value
);
219 tmp_value
= apic_read(APIC_TDCR
);
220 apic_write_around(APIC_TDCR
, (tmp_value
221 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
225 apic_write_around(APIC_TMICT
, clocks
/APIC_DIVISOR
);
229 * Program the next event, relative to now
231 static int lapic_next_event(unsigned long delta
,
232 struct clock_event_device
*evt
)
234 apic_write_around(APIC_TMICT
, delta
);
239 * Setup the lapic timer in periodic or oneshot mode
241 static void lapic_timer_setup(enum clock_event_mode mode
,
242 struct clock_event_device
*evt
)
247 /* Lapic used for broadcast ? */
248 if (!local_apic_timer_verify_ok
)
251 local_irq_save(flags
);
254 case CLOCK_EVT_MODE_PERIODIC
:
255 case CLOCK_EVT_MODE_ONESHOT
:
256 __setup_APIC_LVTT(calibration_result
,
257 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
259 case CLOCK_EVT_MODE_UNUSED
:
260 case CLOCK_EVT_MODE_SHUTDOWN
:
261 v
= apic_read(APIC_LVTT
);
262 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
263 apic_write_around(APIC_LVTT
, v
);
265 case CLOCK_EVT_MODE_RESUME
:
266 /* Nothing to do here */
270 local_irq_restore(flags
);
274 * Local APIC timer broadcast function
276 static void lapic_timer_broadcast(cpumask_t mask
)
279 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
284 * Setup the local APIC timer for this CPU. Copy the initilized values
285 * of the boot CPU and register the clock event in the framework.
287 static void __devinit
setup_APIC_timer(void)
289 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
291 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
292 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
294 clockevents_register_device(levt
);
298 * In this functions we calibrate APIC bus clocks to the external timer.
300 * We want to do the calibration only once since we want to have local timer
301 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
304 * This was previously done by reading the PIT/HPET and waiting for a wrap
305 * around to find out, that a tick has elapsed. I have a box, where the PIT
306 * readout is broken, so it never gets out of the wait loop again. This was
307 * also reported by others.
309 * Monitoring the jiffies value is inaccurate and the clockevents
310 * infrastructure allows us to do a simple substitution of the interrupt
313 * The calibration routine also uses the pm_timer when possible, as the PIT
314 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
315 * back to normal later in the boot process).
318 #define LAPIC_CAL_LOOPS (HZ/10)
320 static __initdata
int lapic_cal_loops
= -1;
321 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
322 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
323 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
324 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
327 * Temporary interrupt handler.
329 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
331 unsigned long long tsc
= 0;
332 long tapic
= apic_read(APIC_TMCCT
);
333 unsigned long pm
= acpi_pm_read_early();
338 switch (lapic_cal_loops
++) {
340 lapic_cal_t1
= tapic
;
341 lapic_cal_tsc1
= tsc
;
343 lapic_cal_j1
= jiffies
;
346 case LAPIC_CAL_LOOPS
:
347 lapic_cal_t2
= tapic
;
348 lapic_cal_tsc2
= tsc
;
349 if (pm
< lapic_cal_pm1
)
350 pm
+= ACPI_PM_OVRRUN
;
352 lapic_cal_j2
= jiffies
;
358 * Setup the boot APIC
360 * Calibrate and verify the result.
362 void __init
setup_boot_APIC_clock(void)
364 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
365 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/10;
366 const long pm_thresh
= pm_100ms
/100;
367 void (*real_handler
)(struct clock_event_device
*dev
);
368 unsigned long deltaj
;
370 int pm_referenced
= 0;
373 * The local apic timer can be disabled via the kernel
374 * commandline or from the CPU detection code. Register the lapic
375 * timer as a dummy clock event source on SMP systems, so the
376 * broadcast mechanism is used. On UP systems simply ignore it.
378 if (local_apic_timer_disabled
) {
379 /* No broadcast on UP ! */
380 if (num_possible_cpus() > 1)
385 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
386 "calibrating APIC timer ...\n");
390 /* Replace the global interrupt handler */
391 real_handler
= global_clock_event
->event_handler
;
392 global_clock_event
->event_handler
= lapic_cal_handler
;
395 * Setup the APIC counter to 1e9. There is no way the lapic
396 * can underflow in the 100ms detection time frame
398 __setup_APIC_LVTT(1000000000, 0, 0);
400 /* Let the interrupts run */
403 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
408 /* Restore the real event handler */
409 global_clock_event
->event_handler
= real_handler
;
411 /* Build delta t1-t2 as apic timer counts down */
412 delta
= lapic_cal_t1
- lapic_cal_t2
;
413 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
415 /* Check, if the PM timer is available */
416 deltapm
= lapic_cal_pm2
- lapic_cal_pm1
;
417 apic_printk(APIC_VERBOSE
, "... PM timer delta = %ld\n", deltapm
);
423 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
425 if (deltapm
> (pm_100ms
- pm_thresh
) &&
426 deltapm
< (pm_100ms
+ pm_thresh
)) {
427 apic_printk(APIC_VERBOSE
, "... PM timer result ok\n");
429 res
= (((u64
) deltapm
) * mult
) >> 22;
430 do_div(res
, 1000000);
431 printk(KERN_WARNING
"APIC calibration not consistent "
432 "with PM Timer: %ldms instead of 100ms\n",
434 /* Correct the lapic counter value */
435 res
= (((u64
) delta
) * pm_100ms
);
436 do_div(res
, deltapm
);
437 printk(KERN_INFO
"APIC delta adjusted to PM-Timer: "
438 "%lu (%ld)\n", (unsigned long) res
, delta
);
444 /* Calculate the scaled math multiplication factor */
445 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
, 32);
446 lapic_clockevent
.max_delta_ns
=
447 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
448 lapic_clockevent
.min_delta_ns
=
449 clockevent_delta2ns(0xF, &lapic_clockevent
);
451 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
453 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
454 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
455 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
459 delta
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
460 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
462 (delta
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
463 (delta
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
466 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
468 calibration_result
/ (1000000 / HZ
),
469 calibration_result
% (1000000 / HZ
));
471 local_apic_timer_verify_ok
= 1;
473 /* We trust the pm timer based calibration */
474 if (!pm_referenced
) {
475 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
478 * Setup the apic timer manually
480 levt
->event_handler
= lapic_cal_handler
;
481 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
482 lapic_cal_loops
= -1;
484 /* Let the interrupts run */
487 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
492 /* Stop the lapic timer */
493 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
498 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
499 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
501 /* Check, if the jiffies result is consistent */
502 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
503 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
505 local_apic_timer_verify_ok
= 0;
509 if (!local_apic_timer_verify_ok
) {
511 "APIC timer disabled due to verification failure.\n");
512 /* No broadcast on UP ! */
513 if (num_possible_cpus() == 1)
517 * If nmi_watchdog is set to IO_APIC, we need the
518 * PIT/HPET going. Otherwise register lapic as a dummy
521 if (nmi_watchdog
!= NMI_IO_APIC
)
522 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
524 printk(KERN_WARNING
"APIC timer registered as dummy,"
525 " due to nmi_watchdog=1!\n");
528 /* Setup the lapic or request the broadcast */
532 void __devinit
setup_secondary_APIC_clock(void)
538 * The guts of the apic timer interrupt
540 static void local_apic_timer_interrupt(void)
542 int cpu
= smp_processor_id();
543 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
546 * Normally we should not be here till LAPIC has been initialized but
547 * in some cases like kdump, its possible that there is a pending LAPIC
548 * timer interrupt from previous kernel's context and is delivered in
549 * new kernel the moment interrupts are enabled.
551 * Interrupts are enabled early and LAPIC is setup much later, hence
552 * its possible that when we get here evt->event_handler is NULL.
553 * Check for event_handler being NULL and discard the interrupt as
556 if (!evt
->event_handler
) {
558 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
560 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
565 * the NMI deadlock-detector uses this.
567 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
569 evt
->event_handler(evt
);
573 * Local APIC timer interrupt. This is the most natural way for doing
574 * local interrupts, but local timer interrupts can be emulated by
575 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
577 * [ if a single-CPU system runs an SMP kernel then we call the local
578 * interrupt as well. Thus we cannot inline the local irq ... ]
580 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
582 struct pt_regs
*old_regs
= set_irq_regs(regs
);
585 * NOTE! We'd better ACK the irq immediately,
586 * because timer handling can be slow.
590 * update_process_times() expects us to have done irq_enter().
591 * Besides, if we don't timer interrupts ignore the global
592 * interrupt lock, which is the WrongThing (tm) to do.
595 local_apic_timer_interrupt();
598 set_irq_regs(old_regs
);
601 int setup_profiling_timer(unsigned int multiplier
)
607 * Local APIC start and shutdown
611 * clear_local_APIC - shutdown the local APIC
613 * This is called, when a CPU is disabled and before rebooting, so the state of
614 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
615 * leftovers during boot.
617 void clear_local_APIC(void)
619 int maxlvt
= lapic_get_maxlvt();
623 * Masking an LVT entry can trigger a local APIC error
624 * if the vector is zero. Mask LVTERR first to prevent this.
627 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
628 apic_write_around(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
631 * Careful: we have to set masks only first to deassert
632 * any level-triggered sources.
634 v
= apic_read(APIC_LVTT
);
635 apic_write_around(APIC_LVTT
, v
| APIC_LVT_MASKED
);
636 v
= apic_read(APIC_LVT0
);
637 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
638 v
= apic_read(APIC_LVT1
);
639 apic_write_around(APIC_LVT1
, v
| APIC_LVT_MASKED
);
641 v
= apic_read(APIC_LVTPC
);
642 apic_write_around(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
645 /* lets not touch this if we didn't frob it */
646 #ifdef CONFIG_X86_MCE_P4THERMAL
648 v
= apic_read(APIC_LVTTHMR
);
649 apic_write_around(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
653 * Clean APIC state for other OSs:
655 apic_write_around(APIC_LVTT
, APIC_LVT_MASKED
);
656 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
);
657 apic_write_around(APIC_LVT1
, APIC_LVT_MASKED
);
659 apic_write_around(APIC_LVTERR
, APIC_LVT_MASKED
);
661 apic_write_around(APIC_LVTPC
, APIC_LVT_MASKED
);
663 #ifdef CONFIG_X86_MCE_P4THERMAL
665 apic_write_around(APIC_LVTTHMR
, APIC_LVT_MASKED
);
667 /* Integrated APIC (!82489DX) ? */
668 if (lapic_is_integrated()) {
670 /* Clear ESR due to Pentium errata 3AP and 11AP */
671 apic_write(APIC_ESR
, 0);
677 * disable_local_APIC - clear and disable the local APIC
679 void disable_local_APIC(void)
686 * Disable APIC (implies clearing of registers
689 value
= apic_read(APIC_SPIV
);
690 value
&= ~APIC_SPIV_APIC_ENABLED
;
691 apic_write_around(APIC_SPIV
, value
);
694 * When LAPIC was disabled by the BIOS and enabled by the kernel,
695 * restore the disabled state.
697 if (enabled_via_apicbase
) {
700 rdmsr(MSR_IA32_APICBASE
, l
, h
);
701 l
&= ~MSR_IA32_APICBASE_ENABLE
;
702 wrmsr(MSR_IA32_APICBASE
, l
, h
);
707 * If Linux enabled the LAPIC against the BIOS default disable it down before
708 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
709 * not power-off. Additionally clear all LVT entries before disable_local_APIC
710 * for the case where Linux didn't enable the LAPIC.
712 void lapic_shutdown(void)
719 local_irq_save(flags
);
722 if (enabled_via_apicbase
)
723 disable_local_APIC();
725 local_irq_restore(flags
);
729 * This is to verify that we're looking at a real local APIC.
730 * Check these against your board if the CPUs aren't getting
731 * started for no apparent reason.
733 int __init
verify_local_APIC(void)
735 unsigned int reg0
, reg1
;
738 * The version register is read-only in a real APIC.
740 reg0
= apic_read(APIC_LVR
);
741 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
742 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
743 reg1
= apic_read(APIC_LVR
);
744 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
747 * The two version reads above should print the same
748 * numbers. If the second one is different, then we
749 * poke at a non-APIC.
755 * Check if the version looks reasonably.
757 reg1
= GET_APIC_VERSION(reg0
);
758 if (reg1
== 0x00 || reg1
== 0xff)
760 reg1
= lapic_get_maxlvt();
761 if (reg1
< 0x02 || reg1
== 0xff)
765 * The ID register is read/write in a real APIC.
767 reg0
= apic_read(APIC_ID
);
768 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
771 * The next two are just to see if we have sane values.
772 * They're only really relevant if we're in Virtual Wire
773 * compatibility mode, but most boxes are anymore.
775 reg0
= apic_read(APIC_LVT0
);
776 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
777 reg1
= apic_read(APIC_LVT1
);
778 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
784 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
786 void __init
sync_Arb_IDs(void)
789 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
792 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
797 apic_wait_icr_idle();
799 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
800 apic_write_around(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
805 * An initial setup of the virtual wire mode.
807 void __init
init_bsp_APIC(void)
812 * Don't do the setup now if we have a SMP BIOS as the
813 * through-I/O-APIC virtual wire mode might be active.
815 if (smp_found_config
|| !cpu_has_apic
)
819 * Do not trust the local APIC being empty at bootup.
826 value
= apic_read(APIC_SPIV
);
827 value
&= ~APIC_VECTOR_MASK
;
828 value
|= APIC_SPIV_APIC_ENABLED
;
830 /* This bit is reserved on P4/Xeon and should be cleared */
831 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
832 (boot_cpu_data
.x86
== 15))
833 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
835 value
|= APIC_SPIV_FOCUS_DISABLED
;
836 value
|= SPURIOUS_APIC_VECTOR
;
837 apic_write_around(APIC_SPIV
, value
);
840 * Set up the virtual wire mode.
842 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
844 if (!lapic_is_integrated()) /* 82489DX */
845 value
|= APIC_LVT_LEVEL_TRIGGER
;
846 apic_write_around(APIC_LVT1
, value
);
850 * setup_local_APIC - setup the local APIC
852 void __cpuinit
setup_local_APIC(void)
854 unsigned long oldvalue
, value
, maxlvt
, integrated
;
857 /* Pound the ESR really hard over the head with a big hammer - mbligh */
859 apic_write(APIC_ESR
, 0);
860 apic_write(APIC_ESR
, 0);
861 apic_write(APIC_ESR
, 0);
862 apic_write(APIC_ESR
, 0);
865 integrated
= lapic_is_integrated();
868 * Double-check whether this APIC is really registered.
870 if (!apic_id_registered())
874 * Intel recommends to set DFR, LDR and TPR before enabling
875 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
876 * document number 292116). So here it goes...
881 * Set Task Priority to 'accept all'. We never change this
884 value
= apic_read(APIC_TASKPRI
);
885 value
&= ~APIC_TPRI_MASK
;
886 apic_write_around(APIC_TASKPRI
, value
);
889 * After a crash, we no longer service the interrupts and a pending
890 * interrupt from previous kernel might still have ISR bit set.
892 * Most probably by now CPU has serviced that pending interrupt and
893 * it might not have done the ack_APIC_irq() because it thought,
894 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
895 * does not clear the ISR bit and cpu thinks it has already serivced
896 * the interrupt. Hence a vector might get locked. It was noticed
897 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
899 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
900 value
= apic_read(APIC_ISR
+ i
*0x10);
901 for (j
= 31; j
>= 0; j
--) {
908 * Now that we are all set up, enable the APIC
910 value
= apic_read(APIC_SPIV
);
911 value
&= ~APIC_VECTOR_MASK
;
915 value
|= APIC_SPIV_APIC_ENABLED
;
918 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
919 * certain networking cards. If high frequency interrupts are
920 * happening on a particular IOAPIC pin, plus the IOAPIC routing
921 * entry is masked/unmasked at a high rate as well then sooner or
922 * later IOAPIC line gets 'stuck', no more interrupts are received
923 * from the device. If focus CPU is disabled then the hang goes
926 * [ This bug can be reproduced easily with a level-triggered
927 * PCI Ne2000 networking cards and PII/PIII processors, dual
931 * Actually disabling the focus CPU check just makes the hang less
932 * frequent as it makes the interrupt distributon model be more
933 * like LRU than MRU (the short-term load is more even across CPUs).
934 * See also the comment in end_level_ioapic_irq(). --macro
937 /* Enable focus processor (bit==0) */
938 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
941 * Set spurious IRQ vector
943 value
|= SPURIOUS_APIC_VECTOR
;
944 apic_write_around(APIC_SPIV
, value
);
949 * set up through-local-APIC on the BP's LINT0. This is not
950 * strictly necessary in pure symmetric-IO mode, but sometimes
951 * we delegate interrupts to the 8259A.
954 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
956 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
957 if (!smp_processor_id() && (pic_mode
|| !value
)) {
958 value
= APIC_DM_EXTINT
;
959 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
962 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
963 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
966 apic_write_around(APIC_LVT0
, value
);
969 * only the BP should see the LINT1 NMI signal, obviously.
971 if (!smp_processor_id())
974 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
975 if (!integrated
) /* 82489DX */
976 value
|= APIC_LVT_LEVEL_TRIGGER
;
977 apic_write_around(APIC_LVT1
, value
);
979 if (integrated
&& !esr_disable
) {
981 maxlvt
= lapic_get_maxlvt();
982 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
983 apic_write(APIC_ESR
, 0);
984 oldvalue
= apic_read(APIC_ESR
);
986 /* enables sending errors */
987 value
= ERROR_APIC_VECTOR
;
988 apic_write_around(APIC_LVTERR
, value
);
990 * spec says clear errors after enabling vector.
993 apic_write(APIC_ESR
, 0);
994 value
= apic_read(APIC_ESR
);
995 if (value
!= oldvalue
)
996 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
997 "vector: 0x%08lx after: 0x%08lx\n",
1002 * Something untraceable is creating bad interrupts on
1003 * secondary quads ... for the moment, just leave the
1004 * ESR disabled - we can't do anything useful with the
1005 * errors anyway - mbligh
1007 printk(KERN_INFO
"Leaving ESR disabled.\n");
1009 printk(KERN_INFO
"No ESR for 82489DX.\n");
1012 /* Disable the local apic timer */
1013 value
= apic_read(APIC_LVTT
);
1014 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1015 apic_write_around(APIC_LVTT
, value
);
1017 setup_apic_nmi_watchdog(NULL
);
1022 * Detect and initialize APIC
1024 static int __init
detect_init_APIC(void)
1028 /* Disabled by kernel option? */
1029 if (enable_local_apic
< 0)
1032 switch (boot_cpu_data
.x86_vendor
) {
1033 case X86_VENDOR_AMD
:
1034 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1035 (boot_cpu_data
.x86
== 15))
1038 case X86_VENDOR_INTEL
:
1039 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1040 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1047 if (!cpu_has_apic
) {
1049 * Over-ride BIOS and try to enable the local APIC only if
1050 * "lapic" specified.
1052 if (enable_local_apic
<= 0) {
1053 printk(KERN_INFO
"Local APIC disabled by BIOS -- "
1054 "you can enable it with \"lapic\"\n");
1058 * Some BIOSes disable the local APIC in the APIC_BASE
1059 * MSR. This can only be done in software for Intel P6 or later
1060 * and AMD K7 (Model > 1) or later.
1062 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1063 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1065 "Local APIC disabled by BIOS -- reenabling.\n");
1066 l
&= ~MSR_IA32_APICBASE_BASE
;
1067 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1068 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1069 enabled_via_apicbase
= 1;
1073 * The APIC feature bit should now be enabled
1076 features
= cpuid_edx(1);
1077 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1078 printk(KERN_WARNING
"Could not enable APIC!\n");
1081 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1082 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1084 /* The BIOS may have set up the APIC at some other address */
1085 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1086 if (l
& MSR_IA32_APICBASE_ENABLE
)
1087 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1089 if (nmi_watchdog
!= NMI_NONE
&& nmi_watchdog
!= NMI_DISABLED
)
1090 nmi_watchdog
= NMI_LOCAL_APIC
;
1092 printk(KERN_INFO
"Found and enabled local APIC!\n");
1099 printk(KERN_INFO
"No local APIC present or hardware disabled\n");
1104 * init_apic_mappings - initialize APIC mappings
1106 void __init
init_apic_mappings(void)
1108 unsigned long apic_phys
;
1111 * If no local APIC can be found then set up a fake all
1112 * zeroes page to simulate the local APIC and another
1113 * one for the IO-APIC.
1115 if (!smp_found_config
&& detect_init_APIC()) {
1116 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1117 apic_phys
= __pa(apic_phys
);
1119 apic_phys
= mp_lapic_addr
;
1121 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1122 printk(KERN_DEBUG
"mapped APIC to %08lx (%08lx)\n", APIC_BASE
,
1126 * Fetch the APIC ID of the BSP in case we have a
1127 * default configuration (or the MP table is broken).
1129 if (boot_cpu_physical_apicid
== -1U)
1130 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
1132 #ifdef CONFIG_X86_IO_APIC
1134 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
1137 for (i
= 0; i
< nr_ioapics
; i
++) {
1138 if (smp_found_config
) {
1139 ioapic_phys
= mp_ioapics
[i
].mpc_apicaddr
;
1142 "WARNING: bogus zero IO-APIC "
1143 "address found in MPTABLE, "
1144 "disabling IO/APIC support!\n");
1145 smp_found_config
= 0;
1146 skip_ioapic_setup
= 1;
1147 goto fake_ioapic_page
;
1151 ioapic_phys
= (unsigned long)
1152 alloc_bootmem_pages(PAGE_SIZE
);
1153 ioapic_phys
= __pa(ioapic_phys
);
1155 set_fixmap_nocache(idx
, ioapic_phys
);
1156 printk(KERN_DEBUG
"mapped IOAPIC to %08lx (%08lx)\n",
1157 __fix_to_virt(idx
), ioapic_phys
);
1165 * This initializes the IO-APIC and APIC hardware if this is
1168 int __init
APIC_init_uniprocessor(void)
1170 if (enable_local_apic
< 0)
1171 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1173 if (!smp_found_config
&& !cpu_has_apic
)
1177 * Complain if the BIOS pretends there is one.
1179 if (!cpu_has_apic
&&
1180 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1181 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1182 boot_cpu_physical_apicid
);
1183 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1187 verify_local_APIC();
1192 * Hack: In case of kdump, after a crash, kernel might be booting
1193 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1194 * might be zero if read from MP tables. Get it from LAPIC.
1196 #ifdef CONFIG_CRASH_DUMP
1197 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
1199 phys_cpu_present_map
= physid_mask_of_physid(boot_cpu_physical_apicid
);
1203 #ifdef CONFIG_X86_IO_APIC
1204 if (smp_found_config
)
1205 if (!skip_ioapic_setup
&& nr_ioapics
)
1214 * Local APIC interrupts
1218 * This interrupt should _never_ happen with our APIC/SMP architecture
1220 void smp_spurious_interrupt(struct pt_regs
*regs
)
1226 * Check if this really is a spurious interrupt and ACK it
1227 * if it is a vectored one. Just in case...
1228 * Spurious interrupts should not be ACKed.
1230 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1231 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1234 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1235 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, "
1236 "should never happen.\n", smp_processor_id());
1237 __get_cpu_var(irq_stat
).irq_spurious_count
++;
1242 * This interrupt should never happen with our APIC/SMP architecture
1244 void smp_error_interrupt(struct pt_regs
*regs
)
1246 unsigned long v
, v1
;
1249 /* First tickle the hardware, only then report what went on. -- REW */
1250 v
= apic_read(APIC_ESR
);
1251 apic_write(APIC_ESR
, 0);
1252 v1
= apic_read(APIC_ESR
);
1254 atomic_inc(&irq_err_count
);
1256 /* Here is what the APIC error bits mean:
1259 2: Send accept error
1260 3: Receive accept error
1262 5: Send illegal vector
1263 6: Received illegal vector
1264 7: Illegal register address
1266 printk(KERN_DEBUG
"APIC error on CPU%d: %02lx(%02lx)\n",
1267 smp_processor_id(), v
, v1
);
1272 * Initialize APIC interrupts
1274 void __init
apic_intr_init(void)
1279 /* self generated IPI for local APIC timer */
1280 set_intr_gate(LOCAL_TIMER_VECTOR
, apic_timer_interrupt
);
1282 /* IPI vectors for APIC spurious and error interrupts */
1283 set_intr_gate(SPURIOUS_APIC_VECTOR
, spurious_interrupt
);
1284 set_intr_gate(ERROR_APIC_VECTOR
, error_interrupt
);
1286 /* thermal monitor LVT interrupt */
1287 #ifdef CONFIG_X86_MCE_P4THERMAL
1288 set_intr_gate(THERMAL_APIC_VECTOR
, thermal_interrupt
);
1293 * connect_bsp_APIC - attach the APIC to the interrupt system
1295 void __init
connect_bsp_APIC(void)
1299 * Do not trust the local APIC being empty at bootup.
1303 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1304 * local APIC to INT and NMI lines.
1306 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1307 "enabling APIC mode.\n");
1315 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1316 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1318 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1321 void disconnect_bsp_APIC(int virt_wire_setup
)
1325 * Put the board back into PIC mode (has an effect only on
1326 * certain older boards). Note that APIC interrupts, including
1327 * IPIs, won't work beyond this point! The only exception are
1330 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1331 "entering PIC mode.\n");
1335 /* Go back to Virtual Wire compatibility mode */
1336 unsigned long value
;
1338 /* For the spurious interrupt use vector F, and enable it */
1339 value
= apic_read(APIC_SPIV
);
1340 value
&= ~APIC_VECTOR_MASK
;
1341 value
|= APIC_SPIV_APIC_ENABLED
;
1343 apic_write_around(APIC_SPIV
, value
);
1345 if (!virt_wire_setup
) {
1347 * For LVT0 make it edge triggered, active high,
1348 * external and enabled
1350 value
= apic_read(APIC_LVT0
);
1351 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1352 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1353 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1354 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1355 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1356 apic_write_around(APIC_LVT0
, value
);
1359 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
);
1363 * For LVT1 make it edge triggered, active high, nmi and
1366 value
= apic_read(APIC_LVT1
);
1368 APIC_MODE_MASK
| APIC_SEND_PENDING
|
1369 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1370 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1371 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1372 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1373 apic_write_around(APIC_LVT1
, value
);
1384 /* r/w apic fields */
1385 unsigned int apic_id
;
1386 unsigned int apic_taskpri
;
1387 unsigned int apic_ldr
;
1388 unsigned int apic_dfr
;
1389 unsigned int apic_spiv
;
1390 unsigned int apic_lvtt
;
1391 unsigned int apic_lvtpc
;
1392 unsigned int apic_lvt0
;
1393 unsigned int apic_lvt1
;
1394 unsigned int apic_lvterr
;
1395 unsigned int apic_tmict
;
1396 unsigned int apic_tdcr
;
1397 unsigned int apic_thmr
;
1400 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1402 unsigned long flags
;
1405 if (!apic_pm_state
.active
)
1408 maxlvt
= lapic_get_maxlvt();
1410 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1411 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1412 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1413 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1414 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1415 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1417 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1418 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1419 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1420 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1421 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1422 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1423 #ifdef CONFIG_X86_MCE_P4THERMAL
1425 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1428 local_irq_save(flags
);
1429 disable_local_APIC();
1430 local_irq_restore(flags
);
1434 static int lapic_resume(struct sys_device
*dev
)
1437 unsigned long flags
;
1440 if (!apic_pm_state
.active
)
1443 maxlvt
= lapic_get_maxlvt();
1445 local_irq_save(flags
);
1448 * Make sure the APICBASE points to the right address
1450 * FIXME! This will be wrong if we ever support suspend on
1451 * SMP! We'll need to do this as part of the CPU restore!
1453 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1454 l
&= ~MSR_IA32_APICBASE_BASE
;
1455 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1456 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1458 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1459 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1460 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1461 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1462 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1463 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1464 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1465 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1466 #ifdef CONFIG_X86_MCE_P4THERMAL
1468 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1471 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1472 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1473 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1474 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1475 apic_write(APIC_ESR
, 0);
1476 apic_read(APIC_ESR
);
1477 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1478 apic_write(APIC_ESR
, 0);
1479 apic_read(APIC_ESR
);
1480 local_irq_restore(flags
);
1485 * This device has no shutdown method - fully functioning local APICs
1486 * are needed on every CPU up until machine_halt/restart/poweroff.
1489 static struct sysdev_class lapic_sysclass
= {
1491 .resume
= lapic_resume
,
1492 .suspend
= lapic_suspend
,
1495 static struct sys_device device_lapic
= {
1497 .cls
= &lapic_sysclass
,
1500 static void __devinit
apic_pm_activate(void)
1502 apic_pm_state
.active
= 1;
1505 static int __init
init_lapic_sysfs(void)
1511 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1513 error
= sysdev_class_register(&lapic_sysclass
);
1515 error
= sysdev_register(&device_lapic
);
1518 device_initcall(init_lapic_sysfs
);
1520 #else /* CONFIG_PM */
1522 static void apic_pm_activate(void) { }
1524 #endif /* CONFIG_PM */
1527 * APIC command line parameters
1529 static int __init
parse_lapic(char *arg
)
1531 enable_local_apic
= 1;
1534 early_param("lapic", parse_lapic
);
1536 static int __init
parse_nolapic(char *arg
)
1538 enable_local_apic
= -1;
1539 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1542 early_param("nolapic", parse_nolapic
);
1544 static int __init
parse_disable_lapic_timer(char *arg
)
1546 local_apic_timer_disabled
= 1;
1549 early_param("nolapic_timer", parse_disable_lapic_timer
);
1551 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1553 local_apic_timer_c2_ok
= 1;
1556 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1558 static int __init
apic_set_verbosity(char *str
)
1560 if (strcmp("debug", str
) == 0)
1561 apic_verbosity
= APIC_DEBUG
;
1562 else if (strcmp("verbose", str
) == 0)
1563 apic_verbosity
= APIC_VERBOSE
;
1566 __setup("apic=", apic_set_verbosity
);