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gianfar: Call gfar_halt_nodisable() from gfar_halt().
[linux-2.6.git] / drivers / net / gianfar.c
blob999d69168277f7190bb2d4e0367ea56a5ba473d8
1 /*
2 * drivers/net/gianfar.c
3 *
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
8 *
9 * Author: Andy Fleming
10 * Maintainer: Kumar Gala
11 *
12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * Copyright (c) 2007 MontaVista Software, Inc.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * Gianfar: AKA Lambda Draconis, "Dragon"
21 * RA 11 31 24.2
22 * Dec +69 19 52
23 * V 3.84
24 * B-V +1.62
25 *
26 * Theory of operation
27 *
28 * The driver is initialized through platform_device. Structures which
29 * define the configuration needed by the board are defined in a
30 * board structure in arch/ppc/platforms (though I do not
31 * discount the possibility that other architectures could one
32 * day be supported.
33 *
34 * The Gianfar Ethernet Controller uses a ring of buffer
35 * descriptors. The beginning is indicated by a register
36 * pointing to the physical address of the start of the ring.
37 * The end is determined by a "wrap" bit being set in the
38 * last descriptor of the ring.
39 *
40 * When a packet is received, the RXF bit in the
41 * IEVENT register is set, triggering an interrupt when the
42 * corresponding bit in the IMASK register is also set (if
43 * interrupt coalescing is active, then the interrupt may not
44 * happen immediately, but will wait until either a set number
45 * of frames or amount of time have passed). In NAPI, the
46 * interrupt handler will signal there is work to be done, and
47 * exit. This method will start at the last known empty
48 * descriptor, and process every subsequent descriptor until there
49 * are none left with data (NAPI will stop after a set number of
50 * packets to give time to other tasks, but will eventually
51 * process all the packets). The data arrives inside a
52 * pre-allocated skb, and so after the skb is passed up to the
53 * stack, a new skb must be allocated, and the address field in
54 * the buffer descriptor must be updated to indicate this new
55 * skb.
56 *
57 * When the kernel requests that a packet be transmitted, the
58 * driver starts where it left off last time, and points the
59 * descriptor at the buffer which was passed in. The driver
60 * then informs the DMA engine that there are packets ready to
61 * be transmitted. Once the controller is finished transmitting
62 * the packet, an interrupt may be triggered (under the same
63 * conditions as for reception, but depending on the TXF bit).
64 * The driver then cleans up the buffer.
65 */
66
67 #include <linux/kernel.h>
68 #include <linux/string.h>
69 #include <linux/errno.h>
70 #include <linux/unistd.h>
71 #include <linux/slab.h>
72 #include <linux/interrupt.h>
73 #include <linux/init.h>
74 #include <linux/delay.h>
75 #include <linux/netdevice.h>
76 #include <linux/etherdevice.h>
77 #include <linux/skbuff.h>
78 #include <linux/if_vlan.h>
79 #include <linux/spinlock.h>
80 #include <linux/mm.h>
81 #include <linux/platform_device.h>
82 #include <linux/ip.h>
83 #include <linux/tcp.h>
84 #include <linux/udp.h>
85 #include <linux/in.h>
86
87 #include <asm/io.h>
88 #include <asm/irq.h>
89 #include <asm/uaccess.h>
90 #include <linux/module.h>
91 #include <linux/dma-mapping.h>
92 #include <linux/crc32.h>
93 #include <linux/mii.h>
94 #include <linux/phy.h>
95
96 #include "gianfar.h"
97 #include "gianfar_mii.h"
98
99 #define TX_TIMEOUT (1*HZ)
100 #undef BRIEF_GFAR_ERRORS
101 #undef VERBOSE_GFAR_ERRORS
102
103 const char gfar_driver_name[] = "Gianfar Ethernet";
104 const char gfar_driver_version[] = "1.3";
105
106 static int gfar_enet_open(struct net_device *dev);
107 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
108 static void gfar_timeout(struct net_device *dev);
109 static int gfar_close(struct net_device *dev);
110 struct sk_buff *gfar_new_skb(struct net_device *dev);
111 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
112 struct sk_buff *skb);
113 static int gfar_set_mac_address(struct net_device *dev);
114 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
115 static irqreturn_t gfar_error(int irq, void *dev_id);
116 static irqreturn_t gfar_transmit(int irq, void *dev_id);
117 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
118 static void adjust_link(struct net_device *dev);
119 static void init_registers(struct net_device *dev);
120 static int init_phy(struct net_device *dev);
121 static int gfar_probe(struct platform_device *pdev);
122 static int gfar_remove(struct platform_device *pdev);
123 static void free_skb_resources(struct gfar_private *priv);
124 static void gfar_set_multi(struct net_device *dev);
125 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
126 static void gfar_configure_serdes(struct net_device *dev);
127 static int gfar_poll(struct napi_struct *napi, int budget);
128 #ifdef CONFIG_NET_POLL_CONTROLLER
129 static void gfar_netpoll(struct net_device *dev);
130 #endif
131 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
132 static int gfar_clean_tx_ring(struct net_device *dev);
133 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
134 static void gfar_vlan_rx_register(struct net_device *netdev,
135 struct vlan_group *grp);
136 void gfar_halt(struct net_device *dev);
137 static void gfar_halt_nodisable(struct net_device *dev);
138 void gfar_start(struct net_device *dev);
139 static void gfar_clear_exact_match(struct net_device *dev);
140 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
141
142 extern const struct ethtool_ops gfar_ethtool_ops;
143
144 MODULE_AUTHOR("Freescale Semiconductor, Inc");
145 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
146 MODULE_LICENSE("GPL");
147
148 /* Returns 1 if incoming frames use an FCB */
149 static inline int gfar_uses_fcb(struct gfar_private *priv)
150 {
151 return (priv->vlan_enable || priv->rx_csum_enable);
152 }
153
154 /* Set up the ethernet device structure, private data,
155 * and anything else we need before we start */
156 static int gfar_probe(struct platform_device *pdev)
157 {
158 u32 tempval;
159 struct net_device *dev = NULL;
160 struct gfar_private *priv = NULL;
161 struct gianfar_platform_data *einfo;
162 struct resource *r;
163 int err = 0;
164 DECLARE_MAC_BUF(mac);
165
166 einfo = (struct gianfar_platform_data *) pdev->dev.platform_data;
167
168 if (NULL == einfo) {
169 printk(KERN_ERR "gfar %d: Missing additional data!\n",
170 pdev->id);
171
172 return -ENODEV;
173 }
174
175 /* Create an ethernet device instance */
176 dev = alloc_etherdev(sizeof (*priv));
177
178 if (NULL == dev)
179 return -ENOMEM;
180
181 priv = netdev_priv(dev);
182 priv->dev = dev;
183
184 /* Set the info in the priv to the current info */
185 priv->einfo = einfo;
186
187 /* fill out IRQ fields */
188 if (einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
189 priv->interruptTransmit = platform_get_irq_byname(pdev, "tx");
190 priv->interruptReceive = platform_get_irq_byname(pdev, "rx");
191 priv->interruptError = platform_get_irq_byname(pdev, "error");
192 if (priv->interruptTransmit < 0 || priv->interruptReceive < 0 || priv->interruptError < 0)
193 goto regs_fail;
194 } else {
195 priv->interruptTransmit = platform_get_irq(pdev, 0);
196 if (priv->interruptTransmit < 0)
197 goto regs_fail;
198 }
199
200 /* get a pointer to the register memory */
201 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
202 priv->regs = ioremap(r->start, sizeof (struct gfar));
203
204 if (NULL == priv->regs) {
205 err = -ENOMEM;
206 goto regs_fail;
207 }
208
209 spin_lock_init(&priv->txlock);
210 spin_lock_init(&priv->rxlock);
211 spin_lock_init(&priv->bflock);
212
213 platform_set_drvdata(pdev, dev);
214
215 /* Stop the DMA engine now, in case it was running before */
216 /* (The firmware could have used it, and left it running). */
217 /* To do this, we write Graceful Receive Stop and Graceful */
218 /* Transmit Stop, and then wait until the corresponding bits */
219 /* in IEVENT indicate the stops have completed. */
220 tempval = gfar_read(&priv->regs->dmactrl);
221 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
222 gfar_write(&priv->regs->dmactrl, tempval);
223
224 tempval = gfar_read(&priv->regs->dmactrl);
225 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
226 gfar_write(&priv->regs->dmactrl, tempval);
227
228 while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC)))
229 cpu_relax();
230
231 /* Reset MAC layer */
232 gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
233
234 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
235 gfar_write(&priv->regs->maccfg1, tempval);
236
237 /* Initialize MACCFG2. */
238 gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
239
240 /* Initialize ECNTRL */
241 gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
242
243 /* Copy the station address into the dev structure, */
244 memcpy(dev->dev_addr, einfo->mac_addr, MAC_ADDR_LEN);
245
246 /* Set the dev->base_addr to the gfar reg region */
247 dev->base_addr = (unsigned long) (priv->regs);
248
249 SET_NETDEV_DEV(dev, &pdev->dev);
250
251 /* Fill in the dev structure */
252 dev->open = gfar_enet_open;
253 dev->hard_start_xmit = gfar_start_xmit;
254 dev->tx_timeout = gfar_timeout;
255 dev->watchdog_timeo = TX_TIMEOUT;
256 netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
257 #ifdef CONFIG_NET_POLL_CONTROLLER
258 dev->poll_controller = gfar_netpoll;
259 #endif
260 dev->stop = gfar_close;
261 dev->change_mtu = gfar_change_mtu;
262 dev->mtu = 1500;
263 dev->set_multicast_list = gfar_set_multi;
264
265 dev->ethtool_ops = &gfar_ethtool_ops;
266
267 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
268 priv->rx_csum_enable = 1;
269 dev->features |= NETIF_F_IP_CSUM;
270 } else
271 priv->rx_csum_enable = 0;
272
273 priv->vlgrp = NULL;
274
275 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
276 dev->vlan_rx_register = gfar_vlan_rx_register;
277
278 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
279
280 priv->vlan_enable = 1;
281 }
282
283 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
284 priv->extended_hash = 1;
285 priv->hash_width = 9;
286
287 priv->hash_regs[0] = &priv->regs->igaddr0;
288 priv->hash_regs[1] = &priv->regs->igaddr1;
289 priv->hash_regs[2] = &priv->regs->igaddr2;
290 priv->hash_regs[3] = &priv->regs->igaddr3;
291 priv->hash_regs[4] = &priv->regs->igaddr4;
292 priv->hash_regs[5] = &priv->regs->igaddr5;
293 priv->hash_regs[6] = &priv->regs->igaddr6;
294 priv->hash_regs[7] = &priv->regs->igaddr7;
295 priv->hash_regs[8] = &priv->regs->gaddr0;
296 priv->hash_regs[9] = &priv->regs->gaddr1;
297 priv->hash_regs[10] = &priv->regs->gaddr2;
298 priv->hash_regs[11] = &priv->regs->gaddr3;
299 priv->hash_regs[12] = &priv->regs->gaddr4;
300 priv->hash_regs[13] = &priv->regs->gaddr5;
301 priv->hash_regs[14] = &priv->regs->gaddr6;
302 priv->hash_regs[15] = &priv->regs->gaddr7;
303
304 } else {
305 priv->extended_hash = 0;
306 priv->hash_width = 8;
307
308 priv->hash_regs[0] = &priv->regs->gaddr0;
309 priv->hash_regs[1] = &priv->regs->gaddr1;
310 priv->hash_regs[2] = &priv->regs->gaddr2;
311 priv->hash_regs[3] = &priv->regs->gaddr3;
312 priv->hash_regs[4] = &priv->regs->gaddr4;
313 priv->hash_regs[5] = &priv->regs->gaddr5;
314 priv->hash_regs[6] = &priv->regs->gaddr6;
315 priv->hash_regs[7] = &priv->regs->gaddr7;
316 }
317
318 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
319 priv->padding = DEFAULT_PADDING;
320 else
321 priv->padding = 0;
322
323 if (dev->features & NETIF_F_IP_CSUM)
324 dev->hard_header_len += GMAC_FCB_LEN;
325
326 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
327 priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
328 priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
329
330 priv->txcoalescing = DEFAULT_TX_COALESCE;
331 priv->txcount = DEFAULT_TXCOUNT;
332 priv->txtime = DEFAULT_TXTIME;
333 priv->rxcoalescing = DEFAULT_RX_COALESCE;
334 priv->rxcount = DEFAULT_RXCOUNT;
335 priv->rxtime = DEFAULT_RXTIME;
336
337 /* Enable most messages by default */
338 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
339
340 err = register_netdev(dev);
341
342 if (err) {
343 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
344 dev->name);
345 goto register_fail;
346 }
347
348 /* Create all the sysfs files */
349 gfar_init_sysfs(dev);
350
351 /* Print out the device info */
352 printk(KERN_INFO DEVICE_NAME "%s\n",
353 dev->name, print_mac(mac, dev->dev_addr));
354
355 /* Even more device info helps when determining which kernel */
356 /* provided which set of benchmarks. */
357 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
358 printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
359 dev->name, priv->rx_ring_size, priv->tx_ring_size);
360
361 return 0;
362
363 register_fail:
364 iounmap(priv->regs);
365 regs_fail:
366 free_netdev(dev);
367 return err;
368 }
369
370 static int gfar_remove(struct platform_device *pdev)
371 {
372 struct net_device *dev = platform_get_drvdata(pdev);
373 struct gfar_private *priv = netdev_priv(dev);
374
375 platform_set_drvdata(pdev, NULL);
376
377 iounmap(priv->regs);
378 free_netdev(dev);
379
380 return 0;
381 }
382
383 #ifdef CONFIG_PM
384 static int gfar_suspend(struct platform_device *pdev, pm_message_t state)
385 {
386 struct net_device *dev = platform_get_drvdata(pdev);
387 struct gfar_private *priv = netdev_priv(dev);
388 unsigned long flags;
389 u32 tempval;
390
391 int magic_packet = priv->wol_en &&
392 (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
393
394 netif_device_detach(dev);
395
396 if (netif_running(dev)) {
397 spin_lock_irqsave(&priv->txlock, flags);
398 spin_lock(&priv->rxlock);
399
400 gfar_halt_nodisable(dev);
401
402 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
403 tempval = gfar_read(&priv->regs->maccfg1);
404
405 tempval &= ~MACCFG1_TX_EN;
406
407 if (!magic_packet)
408 tempval &= ~MACCFG1_RX_EN;
409
410 gfar_write(&priv->regs->maccfg1, tempval);
411
412 spin_unlock(&priv->rxlock);
413 spin_unlock_irqrestore(&priv->txlock, flags);
414
415 napi_disable(&priv->napi);
416
417 if (magic_packet) {
418 /* Enable interrupt on Magic Packet */
419 gfar_write(&priv->regs->imask, IMASK_MAG);
420
421 /* Enable Magic Packet mode */
422 tempval = gfar_read(&priv->regs->maccfg2);
423 tempval |= MACCFG2_MPEN;
424 gfar_write(&priv->regs->maccfg2, tempval);
425 } else {
426 phy_stop(priv->phydev);
427 }
428 }
429
430 return 0;
431 }
432
433 static int gfar_resume(struct platform_device *pdev)
434 {
435 struct net_device *dev = platform_get_drvdata(pdev);
436 struct gfar_private *priv = netdev_priv(dev);
437 unsigned long flags;
438 u32 tempval;
439 int magic_packet = priv->wol_en &&
440 (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
441
442 if (!netif_running(dev)) {
443 netif_device_attach(dev);
444 return 0;
445 }
446
447 if (!magic_packet && priv->phydev)
448 phy_start(priv->phydev);
449
450 /* Disable Magic Packet mode, in case something
451 * else woke us up.
452 */
453
454 spin_lock_irqsave(&priv->txlock, flags);
455 spin_lock(&priv->rxlock);
456
457 tempval = gfar_read(&priv->regs->maccfg2);
458 tempval &= ~MACCFG2_MPEN;
459 gfar_write(&priv->regs->maccfg2, tempval);
460
461 gfar_start(dev);
462
463 spin_unlock(&priv->rxlock);
464 spin_unlock_irqrestore(&priv->txlock, flags);
465
466 netif_device_attach(dev);
467
468 napi_enable(&priv->napi);
469
470 return 0;
471 }
472 #else
473 #define gfar_suspend NULL
474 #define gfar_resume NULL
475 #endif
476
477 /* Reads the controller's registers to determine what interface
478 * connects it to the PHY.
479 */
480 static phy_interface_t gfar_get_interface(struct net_device *dev)
481 {
482 struct gfar_private *priv = netdev_priv(dev);
483 u32 ecntrl = gfar_read(&priv->regs->ecntrl);
484
485 if (ecntrl & ECNTRL_SGMII_MODE)
486 return PHY_INTERFACE_MODE_SGMII;
487
488 if (ecntrl & ECNTRL_TBI_MODE) {
489 if (ecntrl & ECNTRL_REDUCED_MODE)
490 return PHY_INTERFACE_MODE_RTBI;
491 else
492 return PHY_INTERFACE_MODE_TBI;
493 }
494
495 if (ecntrl & ECNTRL_REDUCED_MODE) {
496 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
497 return PHY_INTERFACE_MODE_RMII;
498 else {
499 phy_interface_t interface = priv->einfo->interface;
500
501 /*
502 * This isn't autodetected right now, so it must
503 * be set by the device tree or platform code.
504 */
505 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
506 return PHY_INTERFACE_MODE_RGMII_ID;
507
508 return PHY_INTERFACE_MODE_RGMII;
509 }
510 }
511
512 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
513 return PHY_INTERFACE_MODE_GMII;
514
515 return PHY_INTERFACE_MODE_MII;
516 }
517
518
519 /* Initializes driver's PHY state, and attaches to the PHY.
520 * Returns 0 on success.
521 */
522 static int init_phy(struct net_device *dev)
523 {
524 struct gfar_private *priv = netdev_priv(dev);
525 uint gigabit_support =
526 priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
527 SUPPORTED_1000baseT_Full : 0;
528 struct phy_device *phydev;
529 char phy_id[BUS_ID_SIZE];
530 phy_interface_t interface;
531
532 priv->oldlink = 0;
533 priv->oldspeed = 0;
534 priv->oldduplex = -1;
535
536 snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->einfo->bus_id, priv->einfo->phy_id);
537
538 interface = gfar_get_interface(dev);
539
540 phydev = phy_connect(dev, phy_id, &adjust_link, 0, interface);
541
542 if (interface == PHY_INTERFACE_MODE_SGMII)
543 gfar_configure_serdes(dev);
544
545 if (IS_ERR(phydev)) {
546 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
547 return PTR_ERR(phydev);
548 }
549
550 /* Remove any features not supported by the controller */
551 phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
552 phydev->advertising = phydev->supported;
553
554 priv->phydev = phydev;
555
556 return 0;
557 }
558
559 /*
560 * Initialize TBI PHY interface for communicating with the
561 * SERDES lynx PHY on the chip. We communicate with this PHY
562 * through the MDIO bus on each controller, treating it as a
563 * "normal" PHY at the address found in the TBIPA register. We assume
564 * that the TBIPA register is valid. Either the MDIO bus code will set
565 * it to a value that doesn't conflict with other PHYs on the bus, or the
566 * value doesn't matter, as there are no other PHYs on the bus.
567 */
568 static void gfar_configure_serdes(struct net_device *dev)
569 {
570 struct gfar_private *priv = netdev_priv(dev);
571 struct gfar_mii __iomem *regs =
572 (void __iomem *)&priv->regs->gfar_mii_regs;
573 int tbipa = gfar_read(&priv->regs->tbipa);
574
575 /* Single clk mode, mii mode off(for serdes communication) */
576 gfar_local_mdio_write(regs, tbipa, MII_TBICON, TBICON_CLK_SELECT);
577
578 gfar_local_mdio_write(regs, tbipa, MII_ADVERTISE,
579 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
580 ADVERTISE_1000XPSE_ASYM);
581
582 gfar_local_mdio_write(regs, tbipa, MII_BMCR, BMCR_ANENABLE |
583 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
584 }
585
586 static void init_registers(struct net_device *dev)
587 {
588 struct gfar_private *priv = netdev_priv(dev);
589
590 /* Clear IEVENT */
591 gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
592
593 /* Initialize IMASK */
594 gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
595
596 /* Init hash registers to zero */
597 gfar_write(&priv->regs->igaddr0, 0);
598 gfar_write(&priv->regs->igaddr1, 0);
599 gfar_write(&priv->regs->igaddr2, 0);
600 gfar_write(&priv->regs->igaddr3, 0);
601 gfar_write(&priv->regs->igaddr4, 0);
602 gfar_write(&priv->regs->igaddr5, 0);
603 gfar_write(&priv->regs->igaddr6, 0);
604 gfar_write(&priv->regs->igaddr7, 0);
605
606 gfar_write(&priv->regs->gaddr0, 0);
607 gfar_write(&priv->regs->gaddr1, 0);
608 gfar_write(&priv->regs->gaddr2, 0);
609 gfar_write(&priv->regs->gaddr3, 0);
610 gfar_write(&priv->regs->gaddr4, 0);
611 gfar_write(&priv->regs->gaddr5, 0);
612 gfar_write(&priv->regs->gaddr6, 0);
613 gfar_write(&priv->regs->gaddr7, 0);
614
615 /* Zero out the rmon mib registers if it has them */
616 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
617 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
618
619 /* Mask off the CAM interrupts */
620 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
621 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
622 }
623
624 /* Initialize the max receive buffer length */
625 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
626
627 /* Initialize the Minimum Frame Length Register */
628 gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
629 }
630
631
632 /* Halt the receive and transmit queues */
633 static void gfar_halt_nodisable(struct net_device *dev)
634 {
635 struct gfar_private *priv = netdev_priv(dev);
636 struct gfar __iomem *regs = priv->regs;
637 u32 tempval;
638
639 /* Mask all interrupts */
640 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
641
642 /* Clear all interrupts */
643 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
644
645 /* Stop the DMA, and wait for it to stop */
646 tempval = gfar_read(&priv->regs->dmactrl);
647 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
648 != (DMACTRL_GRS | DMACTRL_GTS)) {
649 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
650 gfar_write(&priv->regs->dmactrl, tempval);
651
652 while (!(gfar_read(&priv->regs->ievent) &
653 (IEVENT_GRSC | IEVENT_GTSC)))
654 cpu_relax();
655 }
656 }
657
658 /* Halt the receive and transmit queues */
659 void gfar_halt(struct net_device *dev)
660 {
661 struct gfar_private *priv = netdev_priv(dev);
662 struct gfar __iomem *regs = priv->regs;
663 u32 tempval;
664
665 gfar_halt_nodisable(dev);
666
667 /* Disable Rx and Tx */
668 tempval = gfar_read(&regs->maccfg1);
669 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
670 gfar_write(&regs->maccfg1, tempval);
671 }
672
673 void stop_gfar(struct net_device *dev)
674 {
675 struct gfar_private *priv = netdev_priv(dev);
676 struct gfar __iomem *regs = priv->regs;
677 unsigned long flags;
678
679 phy_stop(priv->phydev);
680
681 /* Lock it down */
682 spin_lock_irqsave(&priv->txlock, flags);
683 spin_lock(&priv->rxlock);
684
685 gfar_halt(dev);
686
687 spin_unlock(&priv->rxlock);
688 spin_unlock_irqrestore(&priv->txlock, flags);
689
690 /* Free the IRQs */
691 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
692 free_irq(priv->interruptError, dev);
693 free_irq(priv->interruptTransmit, dev);
694 free_irq(priv->interruptReceive, dev);
695 } else {
696 free_irq(priv->interruptTransmit, dev);
697 }
698
699 free_skb_resources(priv);
700
701 dma_free_coherent(&dev->dev,
702 sizeof(struct txbd8)*priv->tx_ring_size
703 + sizeof(struct rxbd8)*priv->rx_ring_size,
704 priv->tx_bd_base,
705 gfar_read(&regs->tbase0));
706 }
707
708 /* If there are any tx skbs or rx skbs still around, free them.
709 * Then free tx_skbuff and rx_skbuff */
710 static void free_skb_resources(struct gfar_private *priv)
711 {
712 struct rxbd8 *rxbdp;
713 struct txbd8 *txbdp;
714 int i;
715
716 /* Go through all the buffer descriptors and free their data buffers */
717 txbdp = priv->tx_bd_base;
718
719 for (i = 0; i < priv->tx_ring_size; i++) {
720
721 if (priv->tx_skbuff[i]) {
722 dma_unmap_single(&priv->dev->dev, txbdp->bufPtr,
723 txbdp->length,
724 DMA_TO_DEVICE);
725 dev_kfree_skb_any(priv->tx_skbuff[i]);
726 priv->tx_skbuff[i] = NULL;
727 }
728
729 txbdp++;
730 }
731
732 kfree(priv->tx_skbuff);
733
734 rxbdp = priv->rx_bd_base;
735
736 /* rx_skbuff is not guaranteed to be allocated, so only
737 * free it and its contents if it is allocated */
738 if(priv->rx_skbuff != NULL) {
739 for (i = 0; i < priv->rx_ring_size; i++) {
740 if (priv->rx_skbuff[i]) {
741 dma_unmap_single(&priv->dev->dev, rxbdp->bufPtr,
742 priv->rx_buffer_size,
743 DMA_FROM_DEVICE);
744
745 dev_kfree_skb_any(priv->rx_skbuff[i]);
746 priv->rx_skbuff[i] = NULL;
747 }
748
749 rxbdp->status = 0;
750 rxbdp->length = 0;
751 rxbdp->bufPtr = 0;
752
753 rxbdp++;
754 }
755
756 kfree(priv->rx_skbuff);
757 }
758 }
759
760 void gfar_start(struct net_device *dev)
761 {
762 struct gfar_private *priv = netdev_priv(dev);
763 struct gfar __iomem *regs = priv->regs;
764 u32 tempval;
765
766 /* Enable Rx and Tx in MACCFG1 */
767 tempval = gfar_read(&regs->maccfg1);
768 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
769 gfar_write(&regs->maccfg1, tempval);
770
771 /* Initialize DMACTRL to have WWR and WOP */
772 tempval = gfar_read(&priv->regs->dmactrl);
773 tempval |= DMACTRL_INIT_SETTINGS;
774 gfar_write(&priv->regs->dmactrl, tempval);
775
776 /* Make sure we aren't stopped */
777 tempval = gfar_read(&priv->regs->dmactrl);
778 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
779 gfar_write(&priv->regs->dmactrl, tempval);
780
781 /* Clear THLT/RHLT, so that the DMA starts polling now */
782 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
783 gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
784
785 /* Unmask the interrupts we look for */
786 gfar_write(&regs->imask, IMASK_DEFAULT);
787 }
788
789 /* Bring the controller up and running */
790 int startup_gfar(struct net_device *dev)
791 {
792 struct txbd8 *txbdp;
793 struct rxbd8 *rxbdp;
794 dma_addr_t addr = 0;
795 unsigned long vaddr;
796 int i;
797 struct gfar_private *priv = netdev_priv(dev);
798 struct gfar __iomem *regs = priv->regs;
799 int err = 0;
800 u32 rctrl = 0;
801 u32 attrs = 0;
802
803 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
804
805 /* Allocate memory for the buffer descriptors */
806 vaddr = (unsigned long) dma_alloc_coherent(&dev->dev,
807 sizeof (struct txbd8) * priv->tx_ring_size +
808 sizeof (struct rxbd8) * priv->rx_ring_size,
809 &addr, GFP_KERNEL);
810
811 if (vaddr == 0) {
812 if (netif_msg_ifup(priv))
813 printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
814 dev->name);
815 return -ENOMEM;
816 }
817
818 priv->tx_bd_base = (struct txbd8 *) vaddr;
819
820 /* enet DMA only understands physical addresses */
821 gfar_write(&regs->tbase0, addr);
822
823 /* Start the rx descriptor ring where the tx ring leaves off */
824 addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
825 vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
826 priv->rx_bd_base = (struct rxbd8 *) vaddr;
827 gfar_write(&regs->rbase0, addr);
828
829 /* Setup the skbuff rings */
830 priv->tx_skbuff =
831 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
832 priv->tx_ring_size, GFP_KERNEL);
833
834 if (NULL == priv->tx_skbuff) {
835 if (netif_msg_ifup(priv))
836 printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
837 dev->name);
838 err = -ENOMEM;
839 goto tx_skb_fail;
840 }
841
842 for (i = 0; i < priv->tx_ring_size; i++)
843 priv->tx_skbuff[i] = NULL;
844
845 priv->rx_skbuff =
846 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
847 priv->rx_ring_size, GFP_KERNEL);
848
849 if (NULL == priv->rx_skbuff) {
850 if (netif_msg_ifup(priv))
851 printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
852 dev->name);
853 err = -ENOMEM;
854 goto rx_skb_fail;
855 }
856
857 for (i = 0; i < priv->rx_ring_size; i++)
858 priv->rx_skbuff[i] = NULL;
859
860 /* Initialize some variables in our dev structure */
861 priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
862 priv->cur_rx = priv->rx_bd_base;
863 priv->skb_curtx = priv->skb_dirtytx = 0;
864 priv->skb_currx = 0;
865
866 /* Initialize Transmit Descriptor Ring */
867 txbdp = priv->tx_bd_base;
868 for (i = 0; i < priv->tx_ring_size; i++) {
869 txbdp->status = 0;
870 txbdp->length = 0;
871 txbdp->bufPtr = 0;
872 txbdp++;
873 }
874
875 /* Set the last descriptor in the ring to indicate wrap */
876 txbdp--;
877 txbdp->status |= TXBD_WRAP;
878
879 rxbdp = priv->rx_bd_base;
880 for (i = 0; i < priv->rx_ring_size; i++) {
881 struct sk_buff *skb;
882
883 skb = gfar_new_skb(dev);
884
885 if (!skb) {
886 printk(KERN_ERR "%s: Can't allocate RX buffers\n",
887 dev->name);
888
889 goto err_rxalloc_fail;
890 }
891
892 priv->rx_skbuff[i] = skb;
893
894 gfar_new_rxbdp(dev, rxbdp, skb);
895
896 rxbdp++;
897 }
898
899 /* Set the last descriptor in the ring to wrap */
900 rxbdp--;
901 rxbdp->status |= RXBD_WRAP;
902
903 /* If the device has multiple interrupts, register for
904 * them. Otherwise, only register for the one */
905 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
906 /* Install our interrupt handlers for Error,
907 * Transmit, and Receive */
908 if (request_irq(priv->interruptError, gfar_error,
909 0, "enet_error", dev) < 0) {
910 if (netif_msg_intr(priv))
911 printk(KERN_ERR "%s: Can't get IRQ %d\n",
912 dev->name, priv->interruptError);
913
914 err = -1;
915 goto err_irq_fail;
916 }
917
918 if (request_irq(priv->interruptTransmit, gfar_transmit,
919 0, "enet_tx", dev) < 0) {
920 if (netif_msg_intr(priv))
921 printk(KERN_ERR "%s: Can't get IRQ %d\n",
922 dev->name, priv->interruptTransmit);
923
924 err = -1;
925
926 goto tx_irq_fail;
927 }
928
929 if (request_irq(priv->interruptReceive, gfar_receive,
930 0, "enet_rx", dev) < 0) {
931 if (netif_msg_intr(priv))
932 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
933 dev->name, priv->interruptReceive);
934
935 err = -1;
936 goto rx_irq_fail;
937 }
938 } else {
939 if (request_irq(priv->interruptTransmit, gfar_interrupt,
940 0, "gfar_interrupt", dev) < 0) {
941 if (netif_msg_intr(priv))
942 printk(KERN_ERR "%s: Can't get IRQ %d\n",
943 dev->name, priv->interruptError);
944
945 err = -1;
946 goto err_irq_fail;
947 }
948 }
949
950 phy_start(priv->phydev);
951
952 /* Configure the coalescing support */
953 if (priv->txcoalescing)
954 gfar_write(&regs->txic,
955 mk_ic_value(priv->txcount, priv->txtime));
956 else
957 gfar_write(&regs->txic, 0);
958
959 if (priv->rxcoalescing)
960 gfar_write(&regs->rxic,
961 mk_ic_value(priv->rxcount, priv->rxtime));
962 else
963 gfar_write(&regs->rxic, 0);
964
965 if (priv->rx_csum_enable)
966 rctrl |= RCTRL_CHECKSUMMING;
967
968 if (priv->extended_hash) {
969 rctrl |= RCTRL_EXTHASH;
970
971 gfar_clear_exact_match(dev);
972 rctrl |= RCTRL_EMEN;
973 }
974
975 if (priv->vlan_enable)
976 rctrl |= RCTRL_VLAN;
977
978 if (priv->padding) {
979 rctrl &= ~RCTRL_PAL_MASK;
980 rctrl |= RCTRL_PADDING(priv->padding);
981 }
982
983 /* Init rctrl based on our settings */
984 gfar_write(&priv->regs->rctrl, rctrl);
985
986 if (dev->features & NETIF_F_IP_CSUM)
987 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
988
989 /* Set the extraction length and index */
990 attrs = ATTRELI_EL(priv->rx_stash_size) |
991 ATTRELI_EI(priv->rx_stash_index);
992
993 gfar_write(&priv->regs->attreli, attrs);
994
995 /* Start with defaults, and add stashing or locking
996 * depending on the approprate variables */
997 attrs = ATTR_INIT_SETTINGS;
998
999 if (priv->bd_stash_en)
1000 attrs |= ATTR_BDSTASH;
1001
1002 if (priv->rx_stash_size != 0)
1003 attrs |= ATTR_BUFSTASH;
1004
1005 gfar_write(&priv->regs->attr, attrs);
1006
1007 gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
1008 gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
1009 gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1010
1011 /* Start the controller */
1012 gfar_start(dev);
1013
1014 return 0;
1015
1016 rx_irq_fail:
1017 free_irq(priv->interruptTransmit, dev);
1018 tx_irq_fail:
1019 free_irq(priv->interruptError, dev);
1020 err_irq_fail:
1021 err_rxalloc_fail:
1022 rx_skb_fail:
1023 free_skb_resources(priv);
1024 tx_skb_fail:
1025 dma_free_coherent(&dev->dev,
1026 sizeof(struct txbd8)*priv->tx_ring_size
1027 + sizeof(struct rxbd8)*priv->rx_ring_size,
1028 priv->tx_bd_base,
1029 gfar_read(&regs->tbase0));
1030
1031 return err;
1032 }
1033
1034 /* Called when something needs to use the ethernet device */
1035 /* Returns 0 for success. */
1036 static int gfar_enet_open(struct net_device *dev)
1037 {
1038 struct gfar_private *priv = netdev_priv(dev);
1039 int err;
1040
1041 napi_enable(&priv->napi);
1042
1043 /* Initialize a bunch of registers */
1044 init_registers(dev);
1045
1046 gfar_set_mac_address(dev);
1047
1048 err = init_phy(dev);
1049
1050 if(err) {
1051 napi_disable(&priv->napi);
1052 return err;
1053 }
1054
1055 err = startup_gfar(dev);
1056 if (err) {
1057 napi_disable(&priv->napi);
1058 return err;
1059 }
1060
1061 netif_start_queue(dev);
1062
1063 return err;
1064 }
1065
1066 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb, struct txbd8 *bdp)
1067 {
1068 struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
1069
1070 memset(fcb, 0, GMAC_FCB_LEN);
1071
1072 return fcb;
1073 }
1074
1075 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1076 {
1077 u8 flags = 0;
1078
1079 /* If we're here, it's a IP packet with a TCP or UDP
1080 * payload. We set it to checksum, using a pseudo-header
1081 * we provide
1082 */
1083 flags = TXFCB_DEFAULT;
1084
1085 /* Tell the controller what the protocol is */
1086 /* And provide the already calculated phcs */
1087 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1088 flags |= TXFCB_UDP;
1089 fcb->phcs = udp_hdr(skb)->check;
1090 } else
1091 fcb->phcs = tcp_hdr(skb)->check;
1092
1093 /* l3os is the distance between the start of the
1094 * frame (skb->data) and the start of the IP hdr.
1095 * l4os is the distance between the start of the
1096 * l3 hdr and the l4 hdr */
1097 fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1098 fcb->l4os = skb_network_header_len(skb);
1099
1100 fcb->flags = flags;
1101 }
1102
1103 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1104 {
1105 fcb->flags |= TXFCB_VLN;
1106 fcb->vlctl = vlan_tx_tag_get(skb);
1107 }
1108
1109 /* This is called by the kernel when a frame is ready for transmission. */
1110 /* It is pointed to by the dev->hard_start_xmit function pointer */
1111 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1112 {
1113 struct gfar_private *priv = netdev_priv(dev);
1114 struct txfcb *fcb = NULL;
1115 struct txbd8 *txbdp;
1116 u16 status;
1117 unsigned long flags;
1118
1119 /* Update transmit stats */
1120 dev->stats.tx_bytes += skb->len;
1121
1122 /* Lock priv now */
1123 spin_lock_irqsave(&priv->txlock, flags);
1124
1125 /* Point at the first free tx descriptor */
1126 txbdp = priv->cur_tx;
1127
1128 /* Clear all but the WRAP status flags */
1129 status = txbdp->status & TXBD_WRAP;
1130
1131 /* Set up checksumming */
1132 if (likely((dev->features & NETIF_F_IP_CSUM)
1133 && (CHECKSUM_PARTIAL == skb->ip_summed))) {
1134 fcb = gfar_add_fcb(skb, txbdp);
1135 status |= TXBD_TOE;
1136 gfar_tx_checksum(skb, fcb);
1137 }
1138
1139 if (priv->vlan_enable &&
1140 unlikely(priv->vlgrp && vlan_tx_tag_present(skb))) {
1141 if (unlikely(NULL == fcb)) {
1142 fcb = gfar_add_fcb(skb, txbdp);
1143 status |= TXBD_TOE;
1144 }
1145
1146 gfar_tx_vlan(skb, fcb);
1147 }
1148
1149 /* Set buffer length and pointer */
1150 txbdp->length = skb->len;
1151 txbdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1152 skb->len, DMA_TO_DEVICE);
1153
1154 /* Save the skb pointer so we can free it later */
1155 priv->tx_skbuff[priv->skb_curtx] = skb;
1156
1157 /* Update the current skb pointer (wrapping if this was the last) */
1158 priv->skb_curtx =
1159 (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1160
1161 /* Flag the BD as interrupt-causing */
1162 status |= TXBD_INTERRUPT;
1163
1164 /* Flag the BD as ready to go, last in frame, and */
1165 /* in need of CRC */
1166 status |= (TXBD_READY | TXBD_LAST | TXBD_CRC);
1167
1168 dev->trans_start = jiffies;
1169
1170 /* The powerpc-specific eieio() is used, as wmb() has too strong
1171 * semantics (it requires synchronization between cacheable and
1172 * uncacheable mappings, which eieio doesn't provide and which we
1173 * don't need), thus requiring a more expensive sync instruction. At
1174 * some point, the set of architecture-independent barrier functions
1175 * should be expanded to include weaker barriers.
1176 */
1177
1178 eieio();
1179 txbdp->status = status;
1180
1181 /* If this was the last BD in the ring, the next one */
1182 /* is at the beginning of the ring */
1183 if (txbdp->status & TXBD_WRAP)
1184 txbdp = priv->tx_bd_base;
1185 else
1186 txbdp++;
1187
1188 /* If the next BD still needs to be cleaned up, then the bds
1189 are full. We need to tell the kernel to stop sending us stuff. */
1190 if (txbdp == priv->dirty_tx) {
1191 netif_stop_queue(dev);
1192
1193 dev->stats.tx_fifo_errors++;
1194 }
1195
1196 /* Update the current txbd to the next one */
1197 priv->cur_tx = txbdp;
1198
1199 /* Tell the DMA to go go go */
1200 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1201
1202 /* Unlock priv */
1203 spin_unlock_irqrestore(&priv->txlock, flags);
1204
1205 return 0;
1206 }
1207
1208 /* Stops the kernel queue, and halts the controller */
1209 static int gfar_close(struct net_device *dev)
1210 {
1211 struct gfar_private *priv = netdev_priv(dev);
1212
1213 napi_disable(&priv->napi);
1214
1215 stop_gfar(dev);
1216
1217 /* Disconnect from the PHY */
1218 phy_disconnect(priv->phydev);
1219 priv->phydev = NULL;
1220
1221 netif_stop_queue(dev);
1222
1223 return 0;
1224 }
1225
1226 /* Changes the mac address if the controller is not running. */
1227 static int gfar_set_mac_address(struct net_device *dev)
1228 {
1229 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1230
1231 return 0;
1232 }
1233
1234
1235 /* Enables and disables VLAN insertion/extraction */
1236 static void gfar_vlan_rx_register(struct net_device *dev,
1237 struct vlan_group *grp)
1238 {
1239 struct gfar_private *priv = netdev_priv(dev);
1240 unsigned long flags;
1241 u32 tempval;
1242
1243 spin_lock_irqsave(&priv->rxlock, flags);
1244
1245 priv->vlgrp = grp;
1246
1247 if (grp) {
1248 /* Enable VLAN tag insertion */
1249 tempval = gfar_read(&priv->regs->tctrl);
1250 tempval |= TCTRL_VLINS;
1251
1252 gfar_write(&priv->regs->tctrl, tempval);
1253
1254 /* Enable VLAN tag extraction */
1255 tempval = gfar_read(&priv->regs->rctrl);
1256 tempval |= RCTRL_VLEX;
1257 gfar_write(&priv->regs->rctrl, tempval);
1258 } else {
1259 /* Disable VLAN tag insertion */
1260 tempval = gfar_read(&priv->regs->tctrl);
1261 tempval &= ~TCTRL_VLINS;
1262 gfar_write(&priv->regs->tctrl, tempval);
1263
1264 /* Disable VLAN tag extraction */
1265 tempval = gfar_read(&priv->regs->rctrl);
1266 tempval &= ~RCTRL_VLEX;
1267 gfar_write(&priv->regs->rctrl, tempval);
1268 }
1269
1270 spin_unlock_irqrestore(&priv->rxlock, flags);
1271 }
1272
1273 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1274 {
1275 int tempsize, tempval;
1276 struct gfar_private *priv = netdev_priv(dev);
1277 int oldsize = priv->rx_buffer_size;
1278 int frame_size = new_mtu + ETH_HLEN;
1279
1280 if (priv->vlan_enable)
1281 frame_size += VLAN_HLEN;
1282
1283 if (gfar_uses_fcb(priv))
1284 frame_size += GMAC_FCB_LEN;
1285
1286 frame_size += priv->padding;
1287
1288 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1289 if (netif_msg_drv(priv))
1290 printk(KERN_ERR "%s: Invalid MTU setting\n",
1291 dev->name);
1292 return -EINVAL;
1293 }
1294
1295 tempsize =
1296 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1297 INCREMENTAL_BUFFER_SIZE;
1298
1299 /* Only stop and start the controller if it isn't already
1300 * stopped, and we changed something */
1301 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1302 stop_gfar(dev);
1303
1304 priv->rx_buffer_size = tempsize;
1305
1306 dev->mtu = new_mtu;
1307
1308 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1309 gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1310
1311 /* If the mtu is larger than the max size for standard
1312 * ethernet frames (ie, a jumbo frame), then set maccfg2
1313 * to allow huge frames, and to check the length */
1314 tempval = gfar_read(&priv->regs->maccfg2);
1315
1316 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1317 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1318 else
1319 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1320
1321 gfar_write(&priv->regs->maccfg2, tempval);
1322
1323 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1324 startup_gfar(dev);
1325
1326 return 0;
1327 }
1328
1329 /* gfar_timeout gets called when a packet has not been
1330 * transmitted after a set amount of time.
1331 * For now, assume that clearing out all the structures, and
1332 * starting over will fix the problem. */
1333 static void gfar_timeout(struct net_device *dev)
1334 {
1335 dev->stats.tx_errors++;
1336
1337 if (dev->flags & IFF_UP) {
1338 stop_gfar(dev);
1339 startup_gfar(dev);
1340 }
1341
1342 netif_tx_schedule_all(dev);
1343 }
1344
1345 /* Interrupt Handler for Transmit complete */
1346 static int gfar_clean_tx_ring(struct net_device *dev)
1347 {
1348 struct txbd8 *bdp;
1349 struct gfar_private *priv = netdev_priv(dev);
1350 int howmany = 0;
1351
1352 bdp = priv->dirty_tx;
1353 while ((bdp->status & TXBD_READY) == 0) {
1354 /* If dirty_tx and cur_tx are the same, then either the */
1355 /* ring is empty or full now (it could only be full in the beginning, */
1356 /* obviously). If it is empty, we are done. */
1357 if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
1358 break;
1359
1360 howmany++;
1361
1362 /* Deferred means some collisions occurred during transmit, */
1363 /* but we eventually sent the packet. */
1364 if (bdp->status & TXBD_DEF)
1365 dev->stats.collisions++;
1366
1367 /* Free the sk buffer associated with this TxBD */
1368 dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
1369
1370 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
1371 priv->skb_dirtytx =
1372 (priv->skb_dirtytx +
1373 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1374
1375 /* Clean BD length for empty detection */
1376 bdp->length = 0;
1377
1378 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1379 if (bdp->status & TXBD_WRAP)
1380 bdp = priv->tx_bd_base;
1381 else
1382 bdp++;
1383
1384 /* Move dirty_tx to be the next bd */
1385 priv->dirty_tx = bdp;
1386
1387 /* We freed a buffer, so now we can restart transmission */
1388 if (netif_queue_stopped(dev))
1389 netif_wake_queue(dev);
1390 } /* while ((bdp->status & TXBD_READY) == 0) */
1391
1392 dev->stats.tx_packets += howmany;
1393
1394 return howmany;
1395 }
1396
1397 /* Interrupt Handler for Transmit complete */
1398 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1399 {
1400 struct net_device *dev = (struct net_device *) dev_id;
1401 struct gfar_private *priv = netdev_priv(dev);
1402
1403 /* Clear IEVENT */
1404 gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
1405
1406 /* Lock priv */
1407 spin_lock(&priv->txlock);
1408
1409 gfar_clean_tx_ring(dev);
1410
1411 /* If we are coalescing the interrupts, reset the timer */
1412 /* Otherwise, clear it */
1413 if (likely(priv->txcoalescing)) {
1414 gfar_write(&priv->regs->txic, 0);
1415 gfar_write(&priv->regs->txic,
1416 mk_ic_value(priv->txcount, priv->txtime));
1417 }
1418
1419 spin_unlock(&priv->txlock);
1420
1421 return IRQ_HANDLED;
1422 }
1423
1424 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1425 struct sk_buff *skb)
1426 {
1427 struct gfar_private *priv = netdev_priv(dev);
1428 u32 * status_len = (u32 *)bdp;
1429 u16 flags;
1430
1431 bdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1432 priv->rx_buffer_size, DMA_FROM_DEVICE);
1433
1434 flags = RXBD_EMPTY | RXBD_INTERRUPT;
1435
1436 if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1437 flags |= RXBD_WRAP;
1438
1439 eieio();
1440
1441 *status_len = (u32)flags << 16;
1442 }
1443
1444
1445 struct sk_buff * gfar_new_skb(struct net_device *dev)
1446 {
1447 unsigned int alignamount;
1448 struct gfar_private *priv = netdev_priv(dev);
1449 struct sk_buff *skb = NULL;
1450
1451 /* We have to allocate the skb, so keep trying till we succeed */
1452 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
1453
1454 if (!skb)
1455 return NULL;
1456
1457 alignamount = RXBUF_ALIGNMENT -
1458 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1459
1460 /* We need the data buffer to be aligned properly. We will reserve
1461 * as many bytes as needed to align the data properly
1462 */
1463 skb_reserve(skb, alignamount);
1464
1465 return skb;
1466 }
1467
1468 static inline void count_errors(unsigned short status, struct net_device *dev)
1469 {
1470 struct gfar_private *priv = netdev_priv(dev);
1471 struct net_device_stats *stats = &dev->stats;
1472 struct gfar_extra_stats *estats = &priv->extra_stats;
1473
1474 /* If the packet was truncated, none of the other errors
1475 * matter */
1476 if (status & RXBD_TRUNCATED) {
1477 stats->rx_length_errors++;
1478
1479 estats->rx_trunc++;
1480
1481 return;
1482 }
1483 /* Count the errors, if there were any */
1484 if (status & (RXBD_LARGE | RXBD_SHORT)) {
1485 stats->rx_length_errors++;
1486
1487 if (status & RXBD_LARGE)
1488 estats->rx_large++;
1489 else
1490 estats->rx_short++;
1491 }
1492 if (status & RXBD_NONOCTET) {
1493 stats->rx_frame_errors++;
1494 estats->rx_nonoctet++;
1495 }
1496 if (status & RXBD_CRCERR) {
1497 estats->rx_crcerr++;
1498 stats->rx_crc_errors++;
1499 }
1500 if (status & RXBD_OVERRUN) {
1501 estats->rx_overrun++;
1502 stats->rx_crc_errors++;
1503 }
1504 }
1505
1506 irqreturn_t gfar_receive(int irq, void *dev_id)
1507 {
1508 struct net_device *dev = (struct net_device *) dev_id;
1509 struct gfar_private *priv = netdev_priv(dev);
1510 u32 tempval;
1511
1512 /* support NAPI */
1513 /* Clear IEVENT, so interrupts aren't called again
1514 * because of the packets that have already arrived */
1515 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1516
1517 if (netif_rx_schedule_prep(dev, &priv->napi)) {
1518 tempval = gfar_read(&priv->regs->imask);
1519 tempval &= IMASK_RTX_DISABLED;
1520 gfar_write(&priv->regs->imask, tempval);
1521
1522 __netif_rx_schedule(dev, &priv->napi);
1523 } else {
1524 if (netif_msg_rx_err(priv))
1525 printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1526 dev->name, gfar_read(&priv->regs->ievent),
1527 gfar_read(&priv->regs->imask));
1528 }
1529
1530 return IRQ_HANDLED;
1531 }
1532
1533 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1534 {
1535 /* If valid headers were found, and valid sums
1536 * were verified, then we tell the kernel that no
1537 * checksumming is necessary. Otherwise, it is */
1538 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1539 skb->ip_summed = CHECKSUM_UNNECESSARY;
1540 else
1541 skb->ip_summed = CHECKSUM_NONE;
1542 }
1543
1544
1545 static inline struct rxfcb *gfar_get_fcb(struct sk_buff *skb)
1546 {
1547 struct rxfcb *fcb = (struct rxfcb *)skb->data;
1548
1549 /* Remove the FCB from the skb */
1550 skb_pull(skb, GMAC_FCB_LEN);
1551
1552 return fcb;
1553 }
1554
1555 /* gfar_process_frame() -- handle one incoming packet if skb
1556 * isn't NULL. */
1557 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1558 int length)
1559 {
1560 struct gfar_private *priv = netdev_priv(dev);
1561 struct rxfcb *fcb = NULL;
1562
1563 if (NULL == skb) {
1564 if (netif_msg_rx_err(priv))
1565 printk(KERN_WARNING "%s: Missing skb!!.\n", dev->name);
1566 dev->stats.rx_dropped++;
1567 priv->extra_stats.rx_skbmissing++;
1568 } else {
1569 int ret;
1570
1571 /* Prep the skb for the packet */
1572 skb_put(skb, length);
1573
1574 /* Grab the FCB if there is one */
1575 if (gfar_uses_fcb(priv))
1576 fcb = gfar_get_fcb(skb);
1577
1578 /* Remove the padded bytes, if there are any */
1579 if (priv->padding)
1580 skb_pull(skb, priv->padding);
1581
1582 if (priv->rx_csum_enable)
1583 gfar_rx_checksum(skb, fcb);
1584
1585 /* Tell the skb what kind of packet this is */
1586 skb->protocol = eth_type_trans(skb, dev);
1587
1588 /* Send the packet up the stack */
1589 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN))) {
1590 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp,
1591 fcb->vlctl);
1592 } else
1593 ret = netif_receive_skb(skb);
1594
1595 if (NET_RX_DROP == ret)
1596 priv->extra_stats.kernel_dropped++;
1597 }
1598
1599 return 0;
1600 }
1601
1602 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1603 * until the budget/quota has been reached. Returns the number
1604 * of frames handled
1605 */
1606 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1607 {
1608 struct rxbd8 *bdp;
1609 struct sk_buff *skb;
1610 u16 pkt_len;
1611 int howmany = 0;
1612 struct gfar_private *priv = netdev_priv(dev);
1613
1614 /* Get the first full descriptor */
1615 bdp = priv->cur_rx;
1616
1617 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1618 struct sk_buff *newskb;
1619 rmb();
1620
1621 /* Add another skb for the future */
1622 newskb = gfar_new_skb(dev);
1623
1624 skb = priv->rx_skbuff[priv->skb_currx];
1625
1626 /* We drop the frame if we failed to allocate a new buffer */
1627 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1628 bdp->status & RXBD_ERR)) {
1629 count_errors(bdp->status, dev);
1630
1631 if (unlikely(!newskb))
1632 newskb = skb;
1633
1634 if (skb) {
1635 dma_unmap_single(&priv->dev->dev,
1636 bdp->bufPtr,
1637 priv->rx_buffer_size,
1638 DMA_FROM_DEVICE);
1639
1640 dev_kfree_skb_any(skb);
1641 }
1642 } else {
1643 /* Increment the number of packets */
1644 dev->stats.rx_packets++;
1645 howmany++;
1646
1647 /* Remove the FCS from the packet length */
1648 pkt_len = bdp->length - 4;
1649
1650 gfar_process_frame(dev, skb, pkt_len);
1651
1652 dev->stats.rx_bytes += pkt_len;
1653 }
1654
1655 dev->last_rx = jiffies;
1656
1657 priv->rx_skbuff[priv->skb_currx] = newskb;
1658
1659 /* Setup the new bdp */
1660 gfar_new_rxbdp(dev, bdp, newskb);
1661
1662 /* Update to the next pointer */
1663 if (bdp->status & RXBD_WRAP)
1664 bdp = priv->rx_bd_base;
1665 else
1666 bdp++;
1667
1668 /* update to point at the next skb */
1669 priv->skb_currx =
1670 (priv->skb_currx + 1) &
1671 RX_RING_MOD_MASK(priv->rx_ring_size);
1672 }
1673
1674 /* Update the current rxbd pointer to be the next one */
1675 priv->cur_rx = bdp;
1676
1677 return howmany;
1678 }
1679
1680 static int gfar_poll(struct napi_struct *napi, int budget)
1681 {
1682 struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1683 struct net_device *dev = priv->dev;
1684 int howmany;
1685 unsigned long flags;
1686
1687 /* If we fail to get the lock, don't bother with the TX BDs */
1688 if (spin_trylock_irqsave(&priv->txlock, flags)) {
1689 gfar_clean_tx_ring(dev);
1690 spin_unlock_irqrestore(&priv->txlock, flags);
1691 }
1692
1693 howmany = gfar_clean_rx_ring(dev, budget);
1694
1695 if (howmany < budget) {
1696 netif_rx_complete(dev, napi);
1697
1698 /* Clear the halt bit in RSTAT */
1699 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1700
1701 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1702
1703 /* If we are coalescing interrupts, update the timer */
1704 /* Otherwise, clear it */
1705 if (likely(priv->rxcoalescing)) {
1706 gfar_write(&priv->regs->rxic, 0);
1707 gfar_write(&priv->regs->rxic,
1708 mk_ic_value(priv->rxcount, priv->rxtime));
1709 }
1710 }
1711
1712 return howmany;
1713 }
1714
1715 #ifdef CONFIG_NET_POLL_CONTROLLER
1716 /*
1717 * Polling 'interrupt' - used by things like netconsole to send skbs
1718 * without having to re-enable interrupts. It's not called while
1719 * the interrupt routine is executing.
1720 */
1721 static void gfar_netpoll(struct net_device *dev)
1722 {
1723 struct gfar_private *priv = netdev_priv(dev);
1724
1725 /* If the device has multiple interrupts, run tx/rx */
1726 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1727 disable_irq(priv->interruptTransmit);
1728 disable_irq(priv->interruptReceive);
1729 disable_irq(priv->interruptError);
1730 gfar_interrupt(priv->interruptTransmit, dev);
1731 enable_irq(priv->interruptError);
1732 enable_irq(priv->interruptReceive);
1733 enable_irq(priv->interruptTransmit);
1734 } else {
1735 disable_irq(priv->interruptTransmit);
1736 gfar_interrupt(priv->interruptTransmit, dev);
1737 enable_irq(priv->interruptTransmit);
1738 }
1739 }
1740 #endif
1741
1742 /* The interrupt handler for devices with one interrupt */
1743 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1744 {
1745 struct net_device *dev = dev_id;
1746 struct gfar_private *priv = netdev_priv(dev);
1747
1748 /* Save ievent for future reference */
1749 u32 events = gfar_read(&priv->regs->ievent);
1750
1751 /* Check for reception */
1752 if (events & IEVENT_RX_MASK)
1753 gfar_receive(irq, dev_id);
1754
1755 /* Check for transmit completion */
1756 if (events & IEVENT_TX_MASK)
1757 gfar_transmit(irq, dev_id);
1758
1759 /* Check for errors */
1760 if (events & IEVENT_ERR_MASK)
1761 gfar_error(irq, dev_id);
1762
1763 return IRQ_HANDLED;
1764 }
1765
1766 /* Called every time the controller might need to be made
1767 * aware of new link state. The PHY code conveys this
1768 * information through variables in the phydev structure, and this
1769 * function converts those variables into the appropriate
1770 * register values, and can bring down the device if needed.
1771 */
1772 static void adjust_link(struct net_device *dev)
1773 {
1774 struct gfar_private *priv = netdev_priv(dev);
1775 struct gfar __iomem *regs = priv->regs;
1776 unsigned long flags;
1777 struct phy_device *phydev = priv->phydev;
1778 int new_state = 0;
1779
1780 spin_lock_irqsave(&priv->txlock, flags);
1781 if (phydev->link) {
1782 u32 tempval = gfar_read(&regs->maccfg2);
1783 u32 ecntrl = gfar_read(&regs->ecntrl);
1784
1785 /* Now we make sure that we can be in full duplex mode.
1786 * If not, we operate in half-duplex mode. */
1787 if (phydev->duplex != priv->oldduplex) {
1788 new_state = 1;
1789 if (!(phydev->duplex))
1790 tempval &= ~(MACCFG2_FULL_DUPLEX);
1791 else
1792 tempval |= MACCFG2_FULL_DUPLEX;
1793
1794 priv->oldduplex = phydev->duplex;
1795 }
1796
1797 if (phydev->speed != priv->oldspeed) {
1798 new_state = 1;
1799 switch (phydev->speed) {
1800 case 1000:
1801 tempval =
1802 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1803 break;
1804 case 100:
1805 case 10:
1806 tempval =
1807 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1808
1809 /* Reduced mode distinguishes
1810 * between 10 and 100 */
1811 if (phydev->speed == SPEED_100)
1812 ecntrl |= ECNTRL_R100;
1813 else
1814 ecntrl &= ~(ECNTRL_R100);
1815 break;
1816 default:
1817 if (netif_msg_link(priv))
1818 printk(KERN_WARNING
1819 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
1820 dev->name, phydev->speed);
1821 break;
1822 }
1823
1824 priv->oldspeed = phydev->speed;
1825 }
1826
1827 gfar_write(&regs->maccfg2, tempval);
1828 gfar_write(&regs->ecntrl, ecntrl);
1829
1830 if (!priv->oldlink) {
1831 new_state = 1;
1832 priv->oldlink = 1;
1833 }
1834 } else if (priv->oldlink) {
1835 new_state = 1;
1836 priv->oldlink = 0;
1837 priv->oldspeed = 0;
1838 priv->oldduplex = -1;
1839 }
1840
1841 if (new_state && netif_msg_link(priv))
1842 phy_print_status(phydev);
1843
1844 spin_unlock_irqrestore(&priv->txlock, flags);
1845 }
1846
1847 /* Update the hash table based on the current list of multicast
1848 * addresses we subscribe to. Also, change the promiscuity of
1849 * the device based on the flags (this function is called
1850 * whenever dev->flags is changed */
1851 static void gfar_set_multi(struct net_device *dev)
1852 {
1853 struct dev_mc_list *mc_ptr;
1854 struct gfar_private *priv = netdev_priv(dev);
1855 struct gfar __iomem *regs = priv->regs;
1856 u32 tempval;
1857
1858 if(dev->flags & IFF_PROMISC) {
1859 /* Set RCTRL to PROM */
1860 tempval = gfar_read(&regs->rctrl);
1861 tempval |= RCTRL_PROM;
1862 gfar_write(&regs->rctrl, tempval);
1863 } else {
1864 /* Set RCTRL to not PROM */
1865 tempval = gfar_read(&regs->rctrl);
1866 tempval &= ~(RCTRL_PROM);
1867 gfar_write(&regs->rctrl, tempval);
1868 }
1869
1870 if(dev->flags & IFF_ALLMULTI) {
1871 /* Set the hash to rx all multicast frames */
1872 gfar_write(&regs->igaddr0, 0xffffffff);
1873 gfar_write(&regs->igaddr1, 0xffffffff);
1874 gfar_write(&regs->igaddr2, 0xffffffff);
1875 gfar_write(&regs->igaddr3, 0xffffffff);
1876 gfar_write(&regs->igaddr4, 0xffffffff);
1877 gfar_write(&regs->igaddr5, 0xffffffff);
1878 gfar_write(&regs->igaddr6, 0xffffffff);
1879 gfar_write(&regs->igaddr7, 0xffffffff);
1880 gfar_write(&regs->gaddr0, 0xffffffff);
1881 gfar_write(&regs->gaddr1, 0xffffffff);
1882 gfar_write(&regs->gaddr2, 0xffffffff);
1883 gfar_write(&regs->gaddr3, 0xffffffff);
1884 gfar_write(&regs->gaddr4, 0xffffffff);
1885 gfar_write(&regs->gaddr5, 0xffffffff);
1886 gfar_write(&regs->gaddr6, 0xffffffff);
1887 gfar_write(&regs->gaddr7, 0xffffffff);
1888 } else {
1889 int em_num;
1890 int idx;
1891
1892 /* zero out the hash */
1893 gfar_write(&regs->igaddr0, 0x0);
1894 gfar_write(&regs->igaddr1, 0x0);
1895 gfar_write(&regs->igaddr2, 0x0);
1896 gfar_write(&regs->igaddr3, 0x0);
1897 gfar_write(&regs->igaddr4, 0x0);
1898 gfar_write(&regs->igaddr5, 0x0);
1899 gfar_write(&regs->igaddr6, 0x0);
1900 gfar_write(&regs->igaddr7, 0x0);
1901 gfar_write(&regs->gaddr0, 0x0);
1902 gfar_write(&regs->gaddr1, 0x0);
1903 gfar_write(&regs->gaddr2, 0x0);
1904 gfar_write(&regs->gaddr3, 0x0);
1905 gfar_write(&regs->gaddr4, 0x0);
1906 gfar_write(&regs->gaddr5, 0x0);
1907 gfar_write(&regs->gaddr6, 0x0);
1908 gfar_write(&regs->gaddr7, 0x0);
1909
1910 /* If we have extended hash tables, we need to
1911 * clear the exact match registers to prepare for
1912 * setting them */
1913 if (priv->extended_hash) {
1914 em_num = GFAR_EM_NUM + 1;
1915 gfar_clear_exact_match(dev);
1916 idx = 1;
1917 } else {
1918 idx = 0;
1919 em_num = 0;
1920 }
1921
1922 if(dev->mc_count == 0)
1923 return;
1924
1925 /* Parse the list, and set the appropriate bits */
1926 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
1927 if (idx < em_num) {
1928 gfar_set_mac_for_addr(dev, idx,
1929 mc_ptr->dmi_addr);
1930 idx++;
1931 } else
1932 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
1933 }
1934 }
1935
1936 return;
1937 }
1938
1939
1940 /* Clears each of the exact match registers to zero, so they
1941 * don't interfere with normal reception */
1942 static void gfar_clear_exact_match(struct net_device *dev)
1943 {
1944 int idx;
1945 u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
1946
1947 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
1948 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
1949 }
1950
1951 /* Set the appropriate hash bit for the given addr */
1952 /* The algorithm works like so:
1953 * 1) Take the Destination Address (ie the multicast address), and
1954 * do a CRC on it (little endian), and reverse the bits of the
1955 * result.
1956 * 2) Use the 8 most significant bits as a hash into a 256-entry
1957 * table. The table is controlled through 8 32-bit registers:
1958 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
1959 * gaddr7. This means that the 3 most significant bits in the
1960 * hash index which gaddr register to use, and the 5 other bits
1961 * indicate which bit (assuming an IBM numbering scheme, which
1962 * for PowerPC (tm) is usually the case) in the register holds
1963 * the entry. */
1964 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
1965 {
1966 u32 tempval;
1967 struct gfar_private *priv = netdev_priv(dev);
1968 u32 result = ether_crc(MAC_ADDR_LEN, addr);
1969 int width = priv->hash_width;
1970 u8 whichbit = (result >> (32 - width)) & 0x1f;
1971 u8 whichreg = result >> (32 - width + 5);
1972 u32 value = (1 << (31-whichbit));
1973
1974 tempval = gfar_read(priv->hash_regs[whichreg]);
1975 tempval |= value;
1976 gfar_write(priv->hash_regs[whichreg], tempval);
1977
1978 return;
1979 }
1980
1981
1982 /* There are multiple MAC Address register pairs on some controllers
1983 * This function sets the numth pair to a given address
1984 */
1985 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
1986 {
1987 struct gfar_private *priv = netdev_priv(dev);
1988 int idx;
1989 char tmpbuf[MAC_ADDR_LEN];
1990 u32 tempval;
1991 u32 __iomem *macptr = &priv->regs->macstnaddr1;
1992
1993 macptr += num*2;
1994
1995 /* Now copy it into the mac registers backwards, cuz */
1996 /* little endian is silly */
1997 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
1998 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
1999
2000 gfar_write(macptr, *((u32 *) (tmpbuf)));
2001
2002 tempval = *((u32 *) (tmpbuf + 4));
2003
2004 gfar_write(macptr+1, tempval);
2005 }
2006
2007 /* GFAR error interrupt handler */
2008 static irqreturn_t gfar_error(int irq, void *dev_id)
2009 {
2010 struct net_device *dev = dev_id;
2011 struct gfar_private *priv = netdev_priv(dev);
2012
2013 /* Save ievent for future reference */
2014 u32 events = gfar_read(&priv->regs->ievent);
2015
2016 /* Clear IEVENT */
2017 gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2018
2019 /* Magic Packet is not an error. */
2020 if ((priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2021 (events & IEVENT_MAG))
2022 events &= ~IEVENT_MAG;
2023
2024 /* Hmm... */
2025 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2026 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2027 dev->name, events, gfar_read(&priv->regs->imask));
2028
2029 /* Update the error counters */
2030 if (events & IEVENT_TXE) {
2031 dev->stats.tx_errors++;
2032
2033 if (events & IEVENT_LC)
2034 dev->stats.tx_window_errors++;
2035 if (events & IEVENT_CRL)
2036 dev->stats.tx_aborted_errors++;
2037 if (events & IEVENT_XFUN) {
2038 if (netif_msg_tx_err(priv))
2039 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2040 "packet dropped.\n", dev->name);
2041 dev->stats.tx_dropped++;
2042 priv->extra_stats.tx_underrun++;
2043
2044 /* Reactivate the Tx Queues */
2045 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2046 }
2047 if (netif_msg_tx_err(priv))
2048 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2049 }
2050 if (events & IEVENT_BSY) {
2051 dev->stats.rx_errors++;
2052 priv->extra_stats.rx_bsy++;
2053
2054 gfar_receive(irq, dev_id);
2055
2056 if (netif_msg_rx_err(priv))
2057 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2058 dev->name, gfar_read(&priv->regs->rstat));
2059 }
2060 if (events & IEVENT_BABR) {
2061 dev->stats.rx_errors++;
2062 priv->extra_stats.rx_babr++;
2063
2064 if (netif_msg_rx_err(priv))
2065 printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2066 }
2067 if (events & IEVENT_EBERR) {
2068 priv->extra_stats.eberr++;
2069 if (netif_msg_rx_err(priv))
2070 printk(KERN_DEBUG "%s: bus error\n", dev->name);
2071 }
2072 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2073 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2074
2075 if (events & IEVENT_BABT) {
2076 priv->extra_stats.tx_babt++;
2077 if (netif_msg_tx_err(priv))
2078 printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2079 }
2080 return IRQ_HANDLED;
2081 }
2082
2083 /* work with hotplug and coldplug */
2084 MODULE_ALIAS("platform:fsl-gianfar");
2085
2086 /* Structure for a device driver */
2087 static struct platform_driver gfar_driver = {
2088 .probe = gfar_probe,
2089 .remove = gfar_remove,
2090 .suspend = gfar_suspend,
2091 .resume = gfar_resume,
2092 .driver = {
2093 .name = "fsl-gianfar",
2094 .owner = THIS_MODULE,
2095 },
2096 };
2097
2098 static int __init gfar_init(void)
2099 {
2100 int err = gfar_mdio_init();
2101
2102 if (err)
2103 return err;
2104
2105 err = platform_driver_register(&gfar_driver);
2106
2107 if (err)
2108 gfar_mdio_exit();
2109
2110 return err;
2111 }
2112
2113 static void __exit gfar_exit(void)
2114 {
2115 platform_driver_unregister(&gfar_driver);
2116 gfar_mdio_exit();
2117 }
2118
2119 module_init(gfar_init);
2120 module_exit(gfar_exit);
2121
Linus' kernel tree