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ARM: orion: Consolidate the creation of the uart platform data.
[linux-2.6.git] / arch / arm / mach-kirkwood / common.c
blob8cdf9f9f74b597a6e3e0d1c03c9cefdf8d2e1394
1 /*
2 * arch/arm/mach-kirkwood/common.c
3 *
4 * Core functions for Marvell Kirkwood SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/serial_8250.h>
15 #include <linux/mbus.h>
16 #include <linux/mv643xx_eth.h>
17 #include <linux/mv643xx_i2c.h>
18 #include <linux/ata_platform.h>
19 #include <linux/mtd/nand.h>
20 #include <linux/spi/orion_spi.h>
21 #include <net/dsa.h>
22 #include <asm/page.h>
23 #include <asm/timex.h>
24 #include <asm/kexec.h>
25 #include <asm/mach/map.h>
26 #include <asm/mach/time.h>
27 #include <mach/kirkwood.h>
28 #include <mach/bridge-regs.h>
29 #include <plat/audio.h>
30 #include <plat/cache-feroceon-l2.h>
31 #include <plat/ehci-orion.h>
32 #include <plat/mvsdio.h>
33 #include <plat/mv_xor.h>
34 #include <plat/orion_nand.h>
35 #include <plat/orion_wdt.h>
36 #include <plat/common.h>
37 #include <plat/time.h>
38 #include "common.h"
39
40 /*****************************************************************************
41 * I/O Address Mapping
42 ****************************************************************************/
43 static struct map_desc kirkwood_io_desc[] __initdata = {
44 {
45 .virtual = KIRKWOOD_PCIE_IO_VIRT_BASE,
46 .pfn = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
47 .length = KIRKWOOD_PCIE_IO_SIZE,
48 .type = MT_DEVICE,
49 }, {
50 .virtual = KIRKWOOD_PCIE1_IO_VIRT_BASE,
51 .pfn = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
52 .length = KIRKWOOD_PCIE1_IO_SIZE,
53 .type = MT_DEVICE,
54 }, {
55 .virtual = KIRKWOOD_REGS_VIRT_BASE,
56 .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
57 .length = KIRKWOOD_REGS_SIZE,
58 .type = MT_DEVICE,
59 },
60 };
61
62 void __init kirkwood_map_io(void)
63 {
64 iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
65 }
66
67 /*
68 * Default clock control bits. Any bit _not_ set in this variable
69 * will be cleared from the hardware after platform devices have been
70 * registered. Some reserved bits must be set to 1.
71 */
72 unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
73
74
75 /*****************************************************************************
76 * EHCI
77 ****************************************************************************/
78 static struct orion_ehci_data kirkwood_ehci_data = {
79 .dram = &kirkwood_mbus_dram_info,
80 .phy_version = EHCI_PHY_NA,
81 };
82
83 static u64 ehci_dmamask = DMA_BIT_MASK(32);
84
85
86 /*****************************************************************************
87 * EHCI0
88 ****************************************************************************/
89 static struct resource kirkwood_ehci_resources[] = {
90 {
91 .start = USB_PHYS_BASE,
92 .end = USB_PHYS_BASE + SZ_4K - 1,
93 .flags = IORESOURCE_MEM,
94 }, {
95 .start = IRQ_KIRKWOOD_USB,
96 .end = IRQ_KIRKWOOD_USB,
97 .flags = IORESOURCE_IRQ,
98 },
99 };
100
101 static struct platform_device kirkwood_ehci = {
102 .name = "orion-ehci",
103 .id = 0,
104 .dev = {
105 .dma_mask = &ehci_dmamask,
106 .coherent_dma_mask = DMA_BIT_MASK(32),
107 .platform_data = &kirkwood_ehci_data,
108 },
109 .resource = kirkwood_ehci_resources,
110 .num_resources = ARRAY_SIZE(kirkwood_ehci_resources),
111 };
112
113 void __init kirkwood_ehci_init(void)
114 {
115 kirkwood_clk_ctrl |= CGC_USB0;
116 platform_device_register(&kirkwood_ehci);
117 }
118
119
120 /*****************************************************************************
121 * GE00
122 ****************************************************************************/
123 struct mv643xx_eth_shared_platform_data kirkwood_ge00_shared_data = {
124 .dram = &kirkwood_mbus_dram_info,
125 };
126
127 static struct resource kirkwood_ge00_shared_resources[] = {
128 {
129 .name = "ge00 base",
130 .start = GE00_PHYS_BASE + 0x2000,
131 .end = GE00_PHYS_BASE + SZ_16K - 1,
132 .flags = IORESOURCE_MEM,
133 }, {
134 .name = "ge00 err irq",
135 .start = IRQ_KIRKWOOD_GE00_ERR,
136 .end = IRQ_KIRKWOOD_GE00_ERR,
137 .flags = IORESOURCE_IRQ,
138 },
139 };
140
141 static struct platform_device kirkwood_ge00_shared = {
142 .name = MV643XX_ETH_SHARED_NAME,
143 .id = 0,
144 .dev = {
145 .platform_data = &kirkwood_ge00_shared_data,
146 },
147 .num_resources = ARRAY_SIZE(kirkwood_ge00_shared_resources),
148 .resource = kirkwood_ge00_shared_resources,
149 };
150
151 static struct resource kirkwood_ge00_resources[] = {
152 {
153 .name = "ge00 irq",
154 .start = IRQ_KIRKWOOD_GE00_SUM,
155 .end = IRQ_KIRKWOOD_GE00_SUM,
156 .flags = IORESOURCE_IRQ,
157 },
158 };
159
160 static struct platform_device kirkwood_ge00 = {
161 .name = MV643XX_ETH_NAME,
162 .id = 0,
163 .num_resources = 1,
164 .resource = kirkwood_ge00_resources,
165 .dev = {
166 .coherent_dma_mask = DMA_BIT_MASK(32),
167 },
168 };
169
170 void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
171 {
172 kirkwood_clk_ctrl |= CGC_GE0;
173 eth_data->shared = &kirkwood_ge00_shared;
174 kirkwood_ge00.dev.platform_data = eth_data;
175
176 platform_device_register(&kirkwood_ge00_shared);
177 platform_device_register(&kirkwood_ge00);
178 }
179
180
181 /*****************************************************************************
182 * GE01
183 ****************************************************************************/
184 struct mv643xx_eth_shared_platform_data kirkwood_ge01_shared_data = {
185 .dram = &kirkwood_mbus_dram_info,
186 .shared_smi = &kirkwood_ge00_shared,
187 };
188
189 static struct resource kirkwood_ge01_shared_resources[] = {
190 {
191 .name = "ge01 base",
192 .start = GE01_PHYS_BASE + 0x2000,
193 .end = GE01_PHYS_BASE + SZ_16K - 1,
194 .flags = IORESOURCE_MEM,
195 }, {
196 .name = "ge01 err irq",
197 .start = IRQ_KIRKWOOD_GE01_ERR,
198 .end = IRQ_KIRKWOOD_GE01_ERR,
199 .flags = IORESOURCE_IRQ,
200 },
201 };
202
203 static struct platform_device kirkwood_ge01_shared = {
204 .name = MV643XX_ETH_SHARED_NAME,
205 .id = 1,
206 .dev = {
207 .platform_data = &kirkwood_ge01_shared_data,
208 },
209 .num_resources = ARRAY_SIZE(kirkwood_ge01_shared_resources),
210 .resource = kirkwood_ge01_shared_resources,
211 };
212
213 static struct resource kirkwood_ge01_resources[] = {
214 {
215 .name = "ge01 irq",
216 .start = IRQ_KIRKWOOD_GE01_SUM,
217 .end = IRQ_KIRKWOOD_GE01_SUM,
218 .flags = IORESOURCE_IRQ,
219 },
220 };
221
222 static struct platform_device kirkwood_ge01 = {
223 .name = MV643XX_ETH_NAME,
224 .id = 1,
225 .num_resources = 1,
226 .resource = kirkwood_ge01_resources,
227 .dev = {
228 .coherent_dma_mask = DMA_BIT_MASK(32),
229 },
230 };
231
232 void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
233 {
234 kirkwood_clk_ctrl |= CGC_GE1;
235 eth_data->shared = &kirkwood_ge01_shared;
236 kirkwood_ge01.dev.platform_data = eth_data;
237
238 platform_device_register(&kirkwood_ge01_shared);
239 platform_device_register(&kirkwood_ge01);
240 }
241
242
243 /*****************************************************************************
244 * Ethernet switch
245 ****************************************************************************/
246 static struct resource kirkwood_switch_resources[] = {
247 {
248 .start = 0,
249 .end = 0,
250 .flags = IORESOURCE_IRQ,
251 },
252 };
253
254 static struct platform_device kirkwood_switch_device = {
255 .name = "dsa",
256 .id = 0,
257 .num_resources = 0,
258 .resource = kirkwood_switch_resources,
259 };
260
261 void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq)
262 {
263 int i;
264
265 if (irq != NO_IRQ) {
266 kirkwood_switch_resources[0].start = irq;
267 kirkwood_switch_resources[0].end = irq;
268 kirkwood_switch_device.num_resources = 1;
269 }
270
271 d->netdev = &kirkwood_ge00.dev;
272 for (i = 0; i < d->nr_chips; i++)
273 d->chip[i].mii_bus = &kirkwood_ge00_shared.dev;
274 kirkwood_switch_device.dev.platform_data = d;
275
276 platform_device_register(&kirkwood_switch_device);
277 }
278
279
280 /*****************************************************************************
281 * NAND flash
282 ****************************************************************************/
283 static struct resource kirkwood_nand_resource = {
284 .flags = IORESOURCE_MEM,
285 .start = KIRKWOOD_NAND_MEM_PHYS_BASE,
286 .end = KIRKWOOD_NAND_MEM_PHYS_BASE +
287 KIRKWOOD_NAND_MEM_SIZE - 1,
288 };
289
290 static struct orion_nand_data kirkwood_nand_data = {
291 .cle = 0,
292 .ale = 1,
293 .width = 8,
294 };
295
296 static struct platform_device kirkwood_nand_flash = {
297 .name = "orion_nand",
298 .id = -1,
299 .dev = {
300 .platform_data = &kirkwood_nand_data,
301 },
302 .resource = &kirkwood_nand_resource,
303 .num_resources = 1,
304 };
305
306 void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts,
307 int chip_delay)
308 {
309 kirkwood_clk_ctrl |= CGC_RUNIT;
310 kirkwood_nand_data.parts = parts;
311 kirkwood_nand_data.nr_parts = nr_parts;
312 kirkwood_nand_data.chip_delay = chip_delay;
313 platform_device_register(&kirkwood_nand_flash);
314 }
315
316 void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
317 int (*dev_ready)(struct mtd_info *))
318 {
319 kirkwood_clk_ctrl |= CGC_RUNIT;
320 kirkwood_nand_data.parts = parts;
321 kirkwood_nand_data.nr_parts = nr_parts;
322 kirkwood_nand_data.dev_ready = dev_ready;
323 platform_device_register(&kirkwood_nand_flash);
324 }
325
326 /*****************************************************************************
327 * SoC RTC
328 ****************************************************************************/
329 static struct resource kirkwood_rtc_resource = {
330 .start = RTC_PHYS_BASE,
331 .end = RTC_PHYS_BASE + SZ_16 - 1,
332 .flags = IORESOURCE_MEM,
333 };
334
335 static void __init kirkwood_rtc_init(void)
336 {
337 platform_device_register_simple("rtc-mv", -1, &kirkwood_rtc_resource, 1);
338 }
339
340
341 /*****************************************************************************
342 * SATA
343 ****************************************************************************/
344 static struct resource kirkwood_sata_resources[] = {
345 {
346 .name = "sata base",
347 .start = SATA_PHYS_BASE,
348 .end = SATA_PHYS_BASE + 0x5000 - 1,
349 .flags = IORESOURCE_MEM,
350 }, {
351 .name = "sata irq",
352 .start = IRQ_KIRKWOOD_SATA,
353 .end = IRQ_KIRKWOOD_SATA,
354 .flags = IORESOURCE_IRQ,
355 },
356 };
357
358 static struct platform_device kirkwood_sata = {
359 .name = "sata_mv",
360 .id = 0,
361 .dev = {
362 .coherent_dma_mask = DMA_BIT_MASK(32),
363 },
364 .num_resources = ARRAY_SIZE(kirkwood_sata_resources),
365 .resource = kirkwood_sata_resources,
366 };
367
368 void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
369 {
370 kirkwood_clk_ctrl |= CGC_SATA0;
371 if (sata_data->n_ports > 1)
372 kirkwood_clk_ctrl |= CGC_SATA1;
373 sata_data->dram = &kirkwood_mbus_dram_info;
374 kirkwood_sata.dev.platform_data = sata_data;
375 platform_device_register(&kirkwood_sata);
376 }
377
378
379 /*****************************************************************************
380 * SD/SDIO/MMC
381 ****************************************************************************/
382 static struct resource mvsdio_resources[] = {
383 [0] = {
384 .start = SDIO_PHYS_BASE,
385 .end = SDIO_PHYS_BASE + SZ_1K - 1,
386 .flags = IORESOURCE_MEM,
387 },
388 [1] = {
389 .start = IRQ_KIRKWOOD_SDIO,
390 .end = IRQ_KIRKWOOD_SDIO,
391 .flags = IORESOURCE_IRQ,
392 },
393 };
394
395 static u64 mvsdio_dmamask = DMA_BIT_MASK(32);
396
397 static struct platform_device kirkwood_sdio = {
398 .name = "mvsdio",
399 .id = -1,
400 .dev = {
401 .dma_mask = &mvsdio_dmamask,
402 .coherent_dma_mask = DMA_BIT_MASK(32),
403 },
404 .num_resources = ARRAY_SIZE(mvsdio_resources),
405 .resource = mvsdio_resources,
406 };
407
408 void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
409 {
410 u32 dev, rev;
411
412 kirkwood_pcie_id(&dev, &rev);
413 if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */
414 mvsdio_data->clock = 100000000;
415 else
416 mvsdio_data->clock = 200000000;
417 mvsdio_data->dram = &kirkwood_mbus_dram_info;
418 kirkwood_clk_ctrl |= CGC_SDIO;
419 kirkwood_sdio.dev.platform_data = mvsdio_data;
420 platform_device_register(&kirkwood_sdio);
421 }
422
423
424 /*****************************************************************************
425 * SPI
426 ****************************************************************************/
427 static struct orion_spi_info kirkwood_spi_plat_data = {
428 };
429
430 static struct resource kirkwood_spi_resources[] = {
431 {
432 .start = SPI_PHYS_BASE,
433 .end = SPI_PHYS_BASE + SZ_512 - 1,
434 .flags = IORESOURCE_MEM,
435 },
436 };
437
438 static struct platform_device kirkwood_spi = {
439 .name = "orion_spi",
440 .id = 0,
441 .resource = kirkwood_spi_resources,
442 .dev = {
443 .platform_data = &kirkwood_spi_plat_data,
444 },
445 .num_resources = ARRAY_SIZE(kirkwood_spi_resources),
446 };
447
448 void __init kirkwood_spi_init()
449 {
450 kirkwood_clk_ctrl |= CGC_RUNIT;
451 platform_device_register(&kirkwood_spi);
452 }
453
454
455 /*****************************************************************************
456 * I2C
457 ****************************************************************************/
458 static struct mv64xxx_i2c_pdata kirkwood_i2c_pdata = {
459 .freq_m = 8, /* assumes 166 MHz TCLK */
460 .freq_n = 3,
461 .timeout = 1000, /* Default timeout of 1 second */
462 };
463
464 static struct resource kirkwood_i2c_resources[] = {
465 {
466 .start = I2C_PHYS_BASE,
467 .end = I2C_PHYS_BASE + 0x1f,
468 .flags = IORESOURCE_MEM,
469 }, {
470 .start = IRQ_KIRKWOOD_TWSI,
471 .end = IRQ_KIRKWOOD_TWSI,
472 .flags = IORESOURCE_IRQ,
473 },
474 };
475
476 static struct platform_device kirkwood_i2c = {
477 .name = MV64XXX_I2C_CTLR_NAME,
478 .id = 0,
479 .num_resources = ARRAY_SIZE(kirkwood_i2c_resources),
480 .resource = kirkwood_i2c_resources,
481 .dev = {
482 .platform_data = &kirkwood_i2c_pdata,
483 },
484 };
485
486 void __init kirkwood_i2c_init(void)
487 {
488 platform_device_register(&kirkwood_i2c);
489 }
490
491
492 /*****************************************************************************
493 * UART0
494 ****************************************************************************/
495
496 void __init kirkwood_uart0_init(void)
497 {
498 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
499 IRQ_KIRKWOOD_UART_0, kirkwood_tclk);
500 }
501
502
503 /*****************************************************************************
504 * UART1
505 ****************************************************************************/
506 void __init kirkwood_uart1_init(void)
507 {
508 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
509 IRQ_KIRKWOOD_UART_1, kirkwood_tclk);
510 }
511
512 /*****************************************************************************
513 * Cryptographic Engines and Security Accelerator (CESA)
514 ****************************************************************************/
515
516 static struct resource kirkwood_crypto_res[] = {
517 {
518 .name = "regs",
519 .start = CRYPTO_PHYS_BASE,
520 .end = CRYPTO_PHYS_BASE + 0xffff,
521 .flags = IORESOURCE_MEM,
522 }, {
523 .name = "sram",
524 .start = KIRKWOOD_SRAM_PHYS_BASE,
525 .end = KIRKWOOD_SRAM_PHYS_BASE + KIRKWOOD_SRAM_SIZE - 1,
526 .flags = IORESOURCE_MEM,
527 }, {
528 .name = "crypto interrupt",
529 .start = IRQ_KIRKWOOD_CRYPTO,
530 .end = IRQ_KIRKWOOD_CRYPTO,
531 .flags = IORESOURCE_IRQ,
532 },
533 };
534
535 static struct platform_device kirkwood_crypto_device = {
536 .name = "mv_crypto",
537 .id = -1,
538 .num_resources = ARRAY_SIZE(kirkwood_crypto_res),
539 .resource = kirkwood_crypto_res,
540 };
541
542 void __init kirkwood_crypto_init(void)
543 {
544 kirkwood_clk_ctrl |= CGC_CRYPTO;
545 platform_device_register(&kirkwood_crypto_device);
546 }
547
548
549 /*****************************************************************************
550 * XOR
551 ****************************************************************************/
552 static struct mv_xor_platform_shared_data kirkwood_xor_shared_data = {
553 .dram = &kirkwood_mbus_dram_info,
554 };
555
556
557 /*****************************************************************************
558 * XOR0
559 ****************************************************************************/
560 static struct resource kirkwood_xor0_shared_resources[] = {
561 {
562 .name = "xor 0 low",
563 .start = XOR0_PHYS_BASE,
564 .end = XOR0_PHYS_BASE + 0xff,
565 .flags = IORESOURCE_MEM,
566 }, {
567 .name = "xor 0 high",
568 .start = XOR0_HIGH_PHYS_BASE,
569 .end = XOR0_HIGH_PHYS_BASE + 0xff,
570 .flags = IORESOURCE_MEM,
571 },
572 };
573
574 static struct platform_device kirkwood_xor0_shared = {
575 .name = MV_XOR_SHARED_NAME,
576 .id = 0,
577 .dev = {
578 .platform_data = &kirkwood_xor_shared_data,
579 },
580 .num_resources = ARRAY_SIZE(kirkwood_xor0_shared_resources),
581 .resource = kirkwood_xor0_shared_resources,
582 };
583
584 static u64 kirkwood_xor_dmamask = DMA_BIT_MASK(32);
585
586 static struct resource kirkwood_xor00_resources[] = {
587 [0] = {
588 .start = IRQ_KIRKWOOD_XOR_00,
589 .end = IRQ_KIRKWOOD_XOR_00,
590 .flags = IORESOURCE_IRQ,
591 },
592 };
593
594 static struct mv_xor_platform_data kirkwood_xor00_data = {
595 .shared = &kirkwood_xor0_shared,
596 .hw_id = 0,
597 .pool_size = PAGE_SIZE,
598 };
599
600 static struct platform_device kirkwood_xor00_channel = {
601 .name = MV_XOR_NAME,
602 .id = 0,
603 .num_resources = ARRAY_SIZE(kirkwood_xor00_resources),
604 .resource = kirkwood_xor00_resources,
605 .dev = {
606 .dma_mask = &kirkwood_xor_dmamask,
607 .coherent_dma_mask = DMA_BIT_MASK(64),
608 .platform_data = &kirkwood_xor00_data,
609 },
610 };
611
612 static struct resource kirkwood_xor01_resources[] = {
613 [0] = {
614 .start = IRQ_KIRKWOOD_XOR_01,
615 .end = IRQ_KIRKWOOD_XOR_01,
616 .flags = IORESOURCE_IRQ,
617 },
618 };
619
620 static struct mv_xor_platform_data kirkwood_xor01_data = {
621 .shared = &kirkwood_xor0_shared,
622 .hw_id = 1,
623 .pool_size = PAGE_SIZE,
624 };
625
626 static struct platform_device kirkwood_xor01_channel = {
627 .name = MV_XOR_NAME,
628 .id = 1,
629 .num_resources = ARRAY_SIZE(kirkwood_xor01_resources),
630 .resource = kirkwood_xor01_resources,
631 .dev = {
632 .dma_mask = &kirkwood_xor_dmamask,
633 .coherent_dma_mask = DMA_BIT_MASK(64),
634 .platform_data = &kirkwood_xor01_data,
635 },
636 };
637
638 static void __init kirkwood_xor0_init(void)
639 {
640 kirkwood_clk_ctrl |= CGC_XOR0;
641 platform_device_register(&kirkwood_xor0_shared);
642
643 /*
644 * two engines can't do memset simultaneously, this limitation
645 * satisfied by removing memset support from one of the engines.
646 */
647 dma_cap_set(DMA_MEMCPY, kirkwood_xor00_data.cap_mask);
648 dma_cap_set(DMA_XOR, kirkwood_xor00_data.cap_mask);
649 platform_device_register(&kirkwood_xor00_channel);
650
651 dma_cap_set(DMA_MEMCPY, kirkwood_xor01_data.cap_mask);
652 dma_cap_set(DMA_MEMSET, kirkwood_xor01_data.cap_mask);
653 dma_cap_set(DMA_XOR, kirkwood_xor01_data.cap_mask);
654 platform_device_register(&kirkwood_xor01_channel);
655 }
656
657
658 /*****************************************************************************
659 * XOR1
660 ****************************************************************************/
661 static struct resource kirkwood_xor1_shared_resources[] = {
662 {
663 .name = "xor 1 low",
664 .start = XOR1_PHYS_BASE,
665 .end = XOR1_PHYS_BASE + 0xff,
666 .flags = IORESOURCE_MEM,
667 }, {
668 .name = "xor 1 high",
669 .start = XOR1_HIGH_PHYS_BASE,
670 .end = XOR1_HIGH_PHYS_BASE + 0xff,
671 .flags = IORESOURCE_MEM,
672 },
673 };
674
675 static struct platform_device kirkwood_xor1_shared = {
676 .name = MV_XOR_SHARED_NAME,
677 .id = 1,
678 .dev = {
679 .platform_data = &kirkwood_xor_shared_data,
680 },
681 .num_resources = ARRAY_SIZE(kirkwood_xor1_shared_resources),
682 .resource = kirkwood_xor1_shared_resources,
683 };
684
685 static struct resource kirkwood_xor10_resources[] = {
686 [0] = {
687 .start = IRQ_KIRKWOOD_XOR_10,
688 .end = IRQ_KIRKWOOD_XOR_10,
689 .flags = IORESOURCE_IRQ,
690 },
691 };
692
693 static struct mv_xor_platform_data kirkwood_xor10_data = {
694 .shared = &kirkwood_xor1_shared,
695 .hw_id = 0,
696 .pool_size = PAGE_SIZE,
697 };
698
699 static struct platform_device kirkwood_xor10_channel = {
700 .name = MV_XOR_NAME,
701 .id = 2,
702 .num_resources = ARRAY_SIZE(kirkwood_xor10_resources),
703 .resource = kirkwood_xor10_resources,
704 .dev = {
705 .dma_mask = &kirkwood_xor_dmamask,
706 .coherent_dma_mask = DMA_BIT_MASK(64),
707 .platform_data = &kirkwood_xor10_data,
708 },
709 };
710
711 static struct resource kirkwood_xor11_resources[] = {
712 [0] = {
713 .start = IRQ_KIRKWOOD_XOR_11,
714 .end = IRQ_KIRKWOOD_XOR_11,
715 .flags = IORESOURCE_IRQ,
716 },
717 };
718
719 static struct mv_xor_platform_data kirkwood_xor11_data = {
720 .shared = &kirkwood_xor1_shared,
721 .hw_id = 1,
722 .pool_size = PAGE_SIZE,
723 };
724
725 static struct platform_device kirkwood_xor11_channel = {
726 .name = MV_XOR_NAME,
727 .id = 3,
728 .num_resources = ARRAY_SIZE(kirkwood_xor11_resources),
729 .resource = kirkwood_xor11_resources,
730 .dev = {
731 .dma_mask = &kirkwood_xor_dmamask,
732 .coherent_dma_mask = DMA_BIT_MASK(64),
733 .platform_data = &kirkwood_xor11_data,
734 },
735 };
736
737 static void __init kirkwood_xor1_init(void)
738 {
739 kirkwood_clk_ctrl |= CGC_XOR1;
740 platform_device_register(&kirkwood_xor1_shared);
741
742 /*
743 * two engines can't do memset simultaneously, this limitation
744 * satisfied by removing memset support from one of the engines.
745 */
746 dma_cap_set(DMA_MEMCPY, kirkwood_xor10_data.cap_mask);
747 dma_cap_set(DMA_XOR, kirkwood_xor10_data.cap_mask);
748 platform_device_register(&kirkwood_xor10_channel);
749
750 dma_cap_set(DMA_MEMCPY, kirkwood_xor11_data.cap_mask);
751 dma_cap_set(DMA_MEMSET, kirkwood_xor11_data.cap_mask);
752 dma_cap_set(DMA_XOR, kirkwood_xor11_data.cap_mask);
753 platform_device_register(&kirkwood_xor11_channel);
754 }
755
756
757 /*****************************************************************************
758 * Watchdog
759 ****************************************************************************/
760 static struct orion_wdt_platform_data kirkwood_wdt_data = {
761 .tclk = 0,
762 };
763
764 static struct platform_device kirkwood_wdt_device = {
765 .name = "orion_wdt",
766 .id = -1,
767 .dev = {
768 .platform_data = &kirkwood_wdt_data,
769 },
770 .num_resources = 0,
771 };
772
773 static void __init kirkwood_wdt_init(void)
774 {
775 kirkwood_wdt_data.tclk = kirkwood_tclk;
776 platform_device_register(&kirkwood_wdt_device);
777 }
778
779
780 /*****************************************************************************
781 * Time handling
782 ****************************************************************************/
783 void __init kirkwood_init_early(void)
784 {
785 orion_time_set_base(TIMER_VIRT_BASE);
786 }
787
788 int kirkwood_tclk;
789
790 static int __init kirkwood_find_tclk(void)
791 {
792 u32 dev, rev;
793
794 kirkwood_pcie_id(&dev, &rev);
795
796 if (dev == MV88F6281_DEV_ID || dev == MV88F6282_DEV_ID)
797 if (((readl(SAMPLE_AT_RESET) >> 21) & 1) == 0)
798 return 200000000;
799
800 return 166666667;
801 }
802
803 static void __init kirkwood_timer_init(void)
804 {
805 kirkwood_tclk = kirkwood_find_tclk();
806
807 orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
808 IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
809 }
810
811 struct sys_timer kirkwood_timer = {
812 .init = kirkwood_timer_init,
813 };
814
815 /*****************************************************************************
816 * Audio
817 ****************************************************************************/
818 static struct resource kirkwood_i2s_resources[] = {
819 [0] = {
820 .start = AUDIO_PHYS_BASE,
821 .end = AUDIO_PHYS_BASE + SZ_16K - 1,
822 .flags = IORESOURCE_MEM,
823 },
824 [1] = {
825 .start = IRQ_KIRKWOOD_I2S,
826 .end = IRQ_KIRKWOOD_I2S,
827 .flags = IORESOURCE_IRQ,
828 },
829 };
830
831 static struct kirkwood_asoc_platform_data kirkwood_i2s_data = {
832 .dram = &kirkwood_mbus_dram_info,
833 .burst = 128,
834 };
835
836 static struct platform_device kirkwood_i2s_device = {
837 .name = "kirkwood-i2s",
838 .id = -1,
839 .num_resources = ARRAY_SIZE(kirkwood_i2s_resources),
840 .resource = kirkwood_i2s_resources,
841 .dev = {
842 .platform_data = &kirkwood_i2s_data,
843 },
844 };
845
846 static struct platform_device kirkwood_pcm_device = {
847 .name = "kirkwood-pcm-audio",
848 .id = -1,
849 };
850
851 void __init kirkwood_audio_init(void)
852 {
853 kirkwood_clk_ctrl |= CGC_AUDIO;
854 platform_device_register(&kirkwood_i2s_device);
855 platform_device_register(&kirkwood_pcm_device);
856 }
857
858 /*****************************************************************************
859 * General
860 ****************************************************************************/
861 /*
862 * Identify device ID and revision.
863 */
864 static char * __init kirkwood_id(void)
865 {
866 u32 dev, rev;
867
868 kirkwood_pcie_id(&dev, &rev);
869
870 if (dev == MV88F6281_DEV_ID) {
871 if (rev == MV88F6281_REV_Z0)
872 return "MV88F6281-Z0";
873 else if (rev == MV88F6281_REV_A0)
874 return "MV88F6281-A0";
875 else if (rev == MV88F6281_REV_A1)
876 return "MV88F6281-A1";
877 else
878 return "MV88F6281-Rev-Unsupported";
879 } else if (dev == MV88F6192_DEV_ID) {
880 if (rev == MV88F6192_REV_Z0)
881 return "MV88F6192-Z0";
882 else if (rev == MV88F6192_REV_A0)
883 return "MV88F6192-A0";
884 else if (rev == MV88F6192_REV_A1)
885 return "MV88F6192-A1";
886 else
887 return "MV88F6192-Rev-Unsupported";
888 } else if (dev == MV88F6180_DEV_ID) {
889 if (rev == MV88F6180_REV_A0)
890 return "MV88F6180-Rev-A0";
891 else if (rev == MV88F6180_REV_A1)
892 return "MV88F6180-Rev-A1";
893 else
894 return "MV88F6180-Rev-Unsupported";
895 } else if (dev == MV88F6282_DEV_ID) {
896 if (rev == MV88F6282_REV_A0)
897 return "MV88F6282-Rev-A0";
898 else
899 return "MV88F6282-Rev-Unsupported";
900 } else {
901 return "Device-Unknown";
902 }
903 }
904
905 static void __init kirkwood_l2_init(void)
906 {
907 #ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
908 writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG);
909 feroceon_l2_init(1);
910 #else
911 writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG);
912 feroceon_l2_init(0);
913 #endif
914 }
915
916 void __init kirkwood_init(void)
917 {
918 printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
919 kirkwood_id(), kirkwood_tclk);
920 kirkwood_ge00_shared_data.t_clk = kirkwood_tclk;
921 kirkwood_ge01_shared_data.t_clk = kirkwood_tclk;
922 kirkwood_spi_plat_data.tclk = kirkwood_tclk;
923 kirkwood_i2s_data.tclk = kirkwood_tclk;
924
925 /*
926 * Disable propagation of mbus errors to the CPU local bus,
927 * as this causes mbus errors (which can occur for example
928 * for PCI aborts) to throw CPU aborts, which we're not set
929 * up to deal with.
930 */
931 writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
932
933 kirkwood_setup_cpu_mbus();
934
935 #ifdef CONFIG_CACHE_FEROCEON_L2
936 kirkwood_l2_init();
937 #endif
938
939 /* internal devices that every board has */
940 kirkwood_rtc_init();
941 kirkwood_wdt_init();
942 kirkwood_xor0_init();
943 kirkwood_xor1_init();
944 kirkwood_crypto_init();
945
946 #ifdef CONFIG_KEXEC
947 kexec_reinit = kirkwood_enable_pcie;
948 #endif
949 }
950
951 static int __init kirkwood_clock_gate(void)
952 {
953 unsigned int curr = readl(CLOCK_GATING_CTRL);
954 u32 dev, rev;
955
956 kirkwood_pcie_id(&dev, &rev);
957 printk(KERN_DEBUG "Gating clock of unused units\n");
958 printk(KERN_DEBUG "before: 0x%08x\n", curr);
959
960 /* Make sure those units are accessible */
961 writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);
962
963 /* For SATA: first shutdown the phy */
964 if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
965 /* Disable PLL and IVREF */
966 writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2);
967 /* Disable PHY */
968 writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL);
969 }
970 if (!(kirkwood_clk_ctrl & CGC_SATA1)) {
971 /* Disable PLL and IVREF */
972 writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2);
973 /* Disable PHY */
974 writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
975 }
976
977 /* For PCIe: first shutdown the phy */
978 if (!(kirkwood_clk_ctrl & CGC_PEX0)) {
979 writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
980 while (1)
981 if (readl(PCIE_STATUS) & 0x1)
982 break;
983 writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
984 }
985
986 /* For PCIe 1: first shutdown the phy */
987 if (dev == MV88F6282_DEV_ID) {
988 if (!(kirkwood_clk_ctrl & CGC_PEX1)) {
989 writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
990 while (1)
991 if (readl(PCIE1_STATUS) & 0x1)
992 break;
993 writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
994 }
995 } else /* keep this bit set for devices that don't have PCIe1 */
996 kirkwood_clk_ctrl |= CGC_PEX1;
997
998 /* Now gate clock the required units */
999 writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);
1000 printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));
1001
1002 return 0;
1003 }
1004 late_initcall(kirkwood_clock_gate);
Linus' kernel tree