drivers/memory/tegra30-mc.c

   1 /*
   2  * Tegra30 Memory Controller
   3  *
   4  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/ratelimit.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26
  27 #define DRV_NAME "tegra30-mc"
  28
  29 #define MC_INTSTATUS                    0x0
  30 #define MC_INTMASK                      0x4
  31
  32 #define MC_INT_ERR_SHIFT                6
  33 #define MC_INT_ERR_MASK                 (0x1f << MC_INT_ERR_SHIFT)
  34 #define MC_INT_DECERR_EMEM              BIT(MC_INT_ERR_SHIFT)
  35 #define MC_INT_SECURITY_VIOLATION       BIT(MC_INT_ERR_SHIFT + 2)
  36 #define MC_INT_ARBITRATION_EMEM         BIT(MC_INT_ERR_SHIFT + 3)
  37 #define MC_INT_INVALID_SMMU_PAGE        BIT(MC_INT_ERR_SHIFT + 4)
  38
  39 #define MC_ERR_STATUS                   0x8
  40 #define MC_ERR_ADR                      0xc
  41
  42 #define MC_ERR_TYPE_SHIFT               28
  43 #define MC_ERR_TYPE_MASK                (7 << MC_ERR_TYPE_SHIFT)
  44 #define MC_ERR_TYPE_DECERR_EMEM         2
  45 #define MC_ERR_TYPE_SECURITY_TRUSTZONE  3
  46 #define MC_ERR_TYPE_SECURITY_CARVEOUT   4
  47 #define MC_ERR_TYPE_INVALID_SMMU_PAGE   6
  48
  49 #define MC_ERR_INVALID_SMMU_PAGE_SHIFT  25
  50 #define MC_ERR_INVALID_SMMU_PAGE_MASK   (7 << MC_ERR_INVALID_SMMU_PAGE_SHIFT)
  51 #define MC_ERR_RW_SHIFT                 16
  52 #define MC_ERR_RW                       BIT(MC_ERR_RW_SHIFT)
  53 #define MC_ERR_SECURITY                 BIT(MC_ERR_RW_SHIFT + 1)
  54
  55 #define SECURITY_VIOLATION_TYPE         BIT(30) /* 0=TRUSTZONE, 1=CARVEOUT */
  56
  57 #define MC_EMEM_ARB_CFG                 0x90
  58 #define MC_EMEM_ARB_OUTSTANDING_REQ     0x94
  59 #define MC_EMEM_ARB_TIMING_RCD          0x98
  60 #define MC_EMEM_ARB_TIMING_RP           0x9c
  61 #define MC_EMEM_ARB_TIMING_RC           0xa0
  62 #define MC_EMEM_ARB_TIMING_RAS          0xa4
  63 #define MC_EMEM_ARB_TIMING_FAW          0xa8
  64 #define MC_EMEM_ARB_TIMING_RRD          0xac
  65 #define MC_EMEM_ARB_TIMING_RAP2PRE      0xb0
  66 #define MC_EMEM_ARB_TIMING_WAP2PRE      0xb4
  67 #define MC_EMEM_ARB_TIMING_R2R          0xb8
  68 #define MC_EMEM_ARB_TIMING_W2W          0xbc
  69 #define MC_EMEM_ARB_TIMING_R2W          0xc0
  70 #define MC_EMEM_ARB_TIMING_W2R          0xc4
  71
  72 #define MC_EMEM_ARB_DA_TURNS            0xd0
  73 #define MC_EMEM_ARB_DA_COVERS           0xd4
  74 #define MC_EMEM_ARB_MISC0               0xd8
  75 #define MC_EMEM_ARB_MISC1               0xdc
  76
  77 #define MC_EMEM_ARB_RING3_THROTTLE      0xe4
  78 #define MC_EMEM_ARB_OVERRIDE            0xe8
  79
  80 #define MC_TIMING_CONTROL               0xfc
  81
  82 #define MC_CLIENT_ID_MASK               0x7f
  83
  84 #define NUM_MC_REG_BANKS                4
  85
  86 struct tegra30_mc {
  87         void __iomem *regs[NUM_MC_REG_BANKS];
  88         struct device *dev;
  89         u32 ctx[0];
  90 };
  91
  92 static inline u32 mc_readl(struct tegra30_mc *mc, u32 offs)
  93 {
  94         u32 val = 0;
  95
  96         if (offs < 0x10)
  97                 val = readl(mc->regs[0] + offs);
  98         else if (offs < 0x1f0)
  99                 val = readl(mc->regs[1] + offs - 0x3c);
 100         else if (offs < 0x228)
 101                 val = readl(mc->regs[2] + offs - 0x200);
 102         else if (offs < 0x400)
 103                 val = readl(mc->regs[3] + offs - 0x284);
 104
 105         return val;
 106 }
 107
 108 static inline void mc_writel(struct tegra30_mc *mc, u32 val, u32 offs)
 109 {
 110         if (offs < 0x10)
 111                 writel(val, mc->regs[0] + offs);
 112         else if (offs < 0x1f0)
 113                 writel(val, mc->regs[1] + offs - 0x3c);
 114         else if (offs < 0x228)
 115                 writel(val, mc->regs[2] + offs - 0x200);
 116         else if (offs < 0x400)
 117                 writel(val, mc->regs[3] + offs - 0x284);
 118 }
 119
 120 static const char * const tegra30_mc_client[] = {
 121         "csr_ptcr",
 122         "cbr_display0a",
 123         "cbr_display0ab",
 124         "cbr_display0b",
 125         "cbr_display0bb",
 126         "cbr_display0c",
 127         "cbr_display0cb",
 128         "cbr_display1b",
 129         "cbr_display1bb",
 130         "cbr_eppup",
 131         "cbr_g2pr",
 132         "cbr_g2sr",
 133         "cbr_mpeunifbr",
 134         "cbr_viruv",
 135         "csr_afir",
 136         "csr_avpcarm7r",
 137         "csr_displayhc",
 138         "csr_displayhcb",
 139         "csr_fdcdrd",
 140         "csr_fdcdrd2",
 141         "csr_g2dr",
 142         "csr_hdar",
 143         "csr_host1xdmar",
 144         "csr_host1xr",
 145         "csr_idxsrd",
 146         "csr_idxsrd2",
 147         "csr_mpe_ipred",
 148         "csr_mpeamemrd",
 149         "csr_mpecsrd",
 150         "csr_ppcsahbdmar",
 151         "csr_ppcsahbslvr",
 152         "csr_satar",
 153         "csr_texsrd",
 154         "csr_texsrd2",
 155         "csr_vdebsevr",
 156         "csr_vdember",
 157         "csr_vdemcer",
 158         "csr_vdetper",
 159         "csr_mpcorelpr",
 160         "csr_mpcorer",
 161         "cbw_eppu",
 162         "cbw_eppv",
 163         "cbw_eppy",
 164         "cbw_mpeunifbw",
 165         "cbw_viwsb",
 166         "cbw_viwu",
 167         "cbw_viwv",
 168         "cbw_viwy",
 169         "ccw_g2dw",
 170         "csw_afiw",
 171         "csw_avpcarm7w",
 172         "csw_fdcdwr",
 173         "csw_fdcdwr2",
 174         "csw_hdaw",
 175         "csw_host1xw",
 176         "csw_ispw",
 177         "csw_mpcorelpw",
 178         "csw_mpcorew",
 179         "csw_mpecswr",
 180         "csw_ppcsahbdmaw",
 181         "csw_ppcsahbslvw",
 182         "csw_sataw",
 183         "csw_vdebsevw",
 184         "csw_vdedbgw",
 185         "csw_vdembew",
 186         "csw_vdetpmw",
 187 };
 188
 189 static void tegra30_mc_decode(struct tegra30_mc *mc, int n)
 190 {
 191         u32 err, addr;
 192         const char * const mc_int_err[] = {
 193                 "MC_DECERR",
 194                 "Unknown",
 195                 "MC_SECURITY_ERR",
 196                 "MC_ARBITRATION_EMEM",
 197                 "MC_SMMU_ERR",
 198         };
 199         const char * const err_type[] = {
 200                 "Unknown",
 201                 "Unknown",
 202                 "DECERR_EMEM",
 203                 "SECURITY_TRUSTZONE",
 204                 "SECURITY_CARVEOUT",
 205                 "Unknown",
 206                 "INVALID_SMMU_PAGE",
 207                 "Unknown",
 208         };
 209         char attr[6];
 210         int cid, perm, type, idx;
 211         const char *client = "Unknown";
 212
 213         idx = n - MC_INT_ERR_SHIFT;
 214         if ((idx < 0) || (idx >= ARRAY_SIZE(mc_int_err)) || (idx == 1)) {
 215                 dev_err_ratelimited(mc->dev, "Unknown interrupt status %08lx\n",
 216                                     BIT(n));
 217                 return;
 218         }
 219
 220         err = readl(mc + MC_ERR_STATUS);
 221
 222         type = (err & MC_ERR_TYPE_MASK) >> MC_ERR_TYPE_SHIFT;
 223         perm = (err & MC_ERR_INVALID_SMMU_PAGE_MASK) >>
 224                 MC_ERR_INVALID_SMMU_PAGE_SHIFT;
 225         if (type == MC_ERR_TYPE_INVALID_SMMU_PAGE)
 226                 sprintf(attr, "%c-%c-%c",
 227                         (perm & BIT(2)) ? 'R' : '-',
 228                         (perm & BIT(1)) ? 'W' : '-',
 229                         (perm & BIT(0)) ? 'S' : '-');
 230         else
 231                 attr[0] = '\0';
 232
 233         cid = err & MC_CLIENT_ID_MASK;
 234         if (cid < ARRAY_SIZE(tegra30_mc_client))
 235                 client = tegra30_mc_client[cid];
 236
 237         addr = readl(mc + MC_ERR_ADR);
 238
 239         dev_err_ratelimited(mc->dev, "%s (0x%08x): 0x%08x %s (%s %s %s %s)\n",
 240                            mc_int_err[idx], err, addr, client,
 241                            (err & MC_ERR_SECURITY) ? "secure" : "non-secure",
 242                            (err & MC_ERR_RW) ? "write" : "read",
 243                            err_type[type], attr);
 244 }
 245
 246 static const u32 tegra30_mc_ctx[] = {
 247         MC_EMEM_ARB_CFG,
 248         MC_EMEM_ARB_OUTSTANDING_REQ,
 249         MC_EMEM_ARB_TIMING_RCD,
 250         MC_EMEM_ARB_TIMING_RP,
 251         MC_EMEM_ARB_TIMING_RC,
 252         MC_EMEM_ARB_TIMING_RAS,
 253         MC_EMEM_ARB_TIMING_FAW,
 254         MC_EMEM_ARB_TIMING_RRD,
 255         MC_EMEM_ARB_TIMING_RAP2PRE,
 256         MC_EMEM_ARB_TIMING_WAP2PRE,
 257         MC_EMEM_ARB_TIMING_R2R,
 258         MC_EMEM_ARB_TIMING_W2W,
 259         MC_EMEM_ARB_TIMING_R2W,
 260         MC_EMEM_ARB_TIMING_W2R,
 261         MC_EMEM_ARB_DA_TURNS,
 262         MC_EMEM_ARB_DA_COVERS,
 263         MC_EMEM_ARB_MISC0,
 264         MC_EMEM_ARB_MISC1,
 265         MC_EMEM_ARB_RING3_THROTTLE,
 266         MC_EMEM_ARB_OVERRIDE,
 267         MC_INTMASK,
 268 };
 269
 270 static int tegra30_mc_suspend(struct device *dev)
 271 {
 272         int i;
 273         struct tegra30_mc *mc = dev_get_drvdata(dev);
 274
 275         for (i = 0; i < ARRAY_SIZE(tegra30_mc_ctx); i++)
 276                 mc->ctx[i] = mc_readl(mc, tegra30_mc_ctx[i]);
 277         return 0;
 278 }
 279
 280 static int tegra30_mc_resume(struct device *dev)
 281 {
 282         int i;
 283         struct tegra30_mc *mc = dev_get_drvdata(dev);
 284
 285         for (i = 0; i < ARRAY_SIZE(tegra30_mc_ctx); i++)
 286                 mc_writel(mc, mc->ctx[i], tegra30_mc_ctx[i]);
 287
 288         mc_writel(mc, 1, MC_TIMING_CONTROL);
 289         /* Read-back to ensure that write reached */
 290         mc_readl(mc, MC_TIMING_CONTROL);
 291         return 0;
 292 }
 293
 294 static UNIVERSAL_DEV_PM_OPS(tegra30_mc_pm,
 295                             tegra30_mc_suspend,
 296                             tegra30_mc_resume, NULL);
 297
 298 static const struct of_device_id tegra30_mc_of_match[] = {
 299         { .compatible = "nvidia,tegra30-mc", },
 300         {},
 301 };
 302
 303 static irqreturn_t tegra30_mc_isr(int irq, void *data)
 304 {
 305         u32 stat, mask, bit;
 306         struct tegra30_mc *mc = data;
 307
 308         stat = mc_readl(mc, MC_INTSTATUS);
 309         mask = mc_readl(mc, MC_INTMASK);
 310         mask &= stat;
 311         if (!mask)
 312                 return IRQ_NONE;
 313         while ((bit = ffs(mask)) != 0)
 314                 tegra30_mc_decode(mc, bit - 1);
 315         mc_writel(mc, stat, MC_INTSTATUS);
 316         return IRQ_HANDLED;
 317 }
 318
 319 static int tegra30_mc_probe(struct platform_device *pdev)
 320 {
 321         struct resource *irq;
 322         struct tegra30_mc *mc;
 323         size_t bytes;
 324         int err, i;
 325         u32 intmask;
 326
 327         bytes = sizeof(*mc) + sizeof(u32) * ARRAY_SIZE(tegra30_mc_ctx);
 328         mc = devm_kzalloc(&pdev->dev, bytes, GFP_KERNEL);
 329         if (!mc)
 330                 return -ENOMEM;
 331         mc->dev = &pdev->dev;
 332
 333         for (i = 0; i < ARRAY_SIZE(mc->regs); i++) {
 334                 struct resource *res;
 335
 336                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
 337                 if (!res)
 338                         return -ENODEV;
 339                 mc->regs[i] = devm_request_and_ioremap(&pdev->dev, res);
 340                 if (!mc->regs[i])
 341                         return -EBUSY;
 342         }
 343
 344         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 345         if (!irq)
 346                 return -ENODEV;
 347         err = devm_request_irq(&pdev->dev, irq->start, tegra30_mc_isr,
 348                                IRQF_SHARED, dev_name(&pdev->dev), mc);
 349         if (err)
 350                 return -ENODEV;
 351
 352         platform_set_drvdata(pdev, mc);
 353
 354         intmask = MC_INT_INVALID_SMMU_PAGE |
 355                 MC_INT_DECERR_EMEM | MC_INT_SECURITY_VIOLATION;
 356         mc_writel(mc, intmask, MC_INTMASK);
 357         return 0;
 358 }
 359
 360 static struct platform_driver tegra30_mc_driver = {
 361         .probe = tegra30_mc_probe,
 362         .driver = {
 363                 .name = DRV_NAME,
 364                 .owner = THIS_MODULE,
 365                 .of_match_table = tegra30_mc_of_match,
 366                 .pm = &tegra30_mc_pm,
 367         },
 368 };
 369 module_platform_driver(tegra30_mc_driver);
 370
 371 MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
 372 MODULE_DESCRIPTION("Tegra30 MC driver");
 373 MODULE_LICENSE("GPL v2");
 374 MODULE_ALIAS("platform:" DRV_NAME);