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b43: Put multicast frames on the mcast queue
[linux-2.6.git] / drivers / net / wireless / b43 / main.c
blob345ac3862e11e61ff002df073f905ff203438d37
1 /*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29 */
30
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
42 #include <asm/unaligned.h>
43
44 #include "b43.h"
45 #include "main.h"
46 #include "debugfs.h"
47 #include "phy.h"
48 #include "dma.h"
49 #include "sysfs.h"
50 #include "xmit.h"
51 #include "lo.h"
52 #include "pcmcia.h"
53
54 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
55 MODULE_AUTHOR("Martin Langer");
56 MODULE_AUTHOR("Stefano Brivio");
57 MODULE_AUTHOR("Michael Buesch");
58 MODULE_LICENSE("GPL");
59
60
61 static int modparam_bad_frames_preempt;
62 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
63 MODULE_PARM_DESC(bad_frames_preempt,
64 "enable(1) / disable(0) Bad Frames Preemption");
65
66 static char modparam_fwpostfix[16];
67 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
68 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
69
70 static int modparam_hwpctl;
71 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
72 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
73
74 static int modparam_nohwcrypt;
75 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
76 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
77
78 static const struct ssb_device_id b43_ssb_tbl[] = {
79 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
80 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
81 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
82 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
83 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
84 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
85 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
86 SSB_DEVTABLE_END
87 };
88
89 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
90
91 /* Channel and ratetables are shared for all devices.
92 * They can't be const, because ieee80211 puts some precalculated
93 * data in there. This data is the same for all devices, so we don't
94 * get concurrency issues */
95 #define RATETAB_ENT(_rateid, _flags) \
96 { \
97 .rate = B43_RATE_TO_BASE100KBPS(_rateid), \
98 .val = (_rateid), \
99 .val2 = (_rateid), \
100 .flags = (_flags), \
101 }
102 static struct ieee80211_rate __b43_ratetable[] = {
103 RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK),
104 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
105 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
106 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
107 RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
108 RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
109 RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
110 RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
111 RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
112 RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
113 RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
114 RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
115 };
116
117 #define b43_a_ratetable (__b43_ratetable + 4)
118 #define b43_a_ratetable_size 8
119 #define b43_b_ratetable (__b43_ratetable + 0)
120 #define b43_b_ratetable_size 4
121 #define b43_g_ratetable (__b43_ratetable + 0)
122 #define b43_g_ratetable_size 12
123
124 #define CHANTAB_ENT(_chanid, _freq) \
125 { \
126 .chan = (_chanid), \
127 .freq = (_freq), \
128 .val = (_chanid), \
129 .flag = IEEE80211_CHAN_W_SCAN | \
130 IEEE80211_CHAN_W_ACTIVE_SCAN | \
131 IEEE80211_CHAN_W_IBSS, \
132 .power_level = 0xFF, \
133 .antenna_max = 0xFF, \
134 }
135 static struct ieee80211_channel b43_2ghz_chantable[] = {
136 CHANTAB_ENT(1, 2412),
137 CHANTAB_ENT(2, 2417),
138 CHANTAB_ENT(3, 2422),
139 CHANTAB_ENT(4, 2427),
140 CHANTAB_ENT(5, 2432),
141 CHANTAB_ENT(6, 2437),
142 CHANTAB_ENT(7, 2442),
143 CHANTAB_ENT(8, 2447),
144 CHANTAB_ENT(9, 2452),
145 CHANTAB_ENT(10, 2457),
146 CHANTAB_ENT(11, 2462),
147 CHANTAB_ENT(12, 2467),
148 CHANTAB_ENT(13, 2472),
149 CHANTAB_ENT(14, 2484),
150 };
151 #define b43_2ghz_chantable_size ARRAY_SIZE(b43_2ghz_chantable)
152
153 #if 0
154 static struct ieee80211_channel b43_5ghz_chantable[] = {
155 CHANTAB_ENT(36, 5180),
156 CHANTAB_ENT(40, 5200),
157 CHANTAB_ENT(44, 5220),
158 CHANTAB_ENT(48, 5240),
159 CHANTAB_ENT(52, 5260),
160 CHANTAB_ENT(56, 5280),
161 CHANTAB_ENT(60, 5300),
162 CHANTAB_ENT(64, 5320),
163 CHANTAB_ENT(149, 5745),
164 CHANTAB_ENT(153, 5765),
165 CHANTAB_ENT(157, 5785),
166 CHANTAB_ENT(161, 5805),
167 CHANTAB_ENT(165, 5825),
168 };
169 #define b43_5ghz_chantable_size ARRAY_SIZE(b43_5ghz_chantable)
170 #endif
171
172 static void b43_wireless_core_exit(struct b43_wldev *dev);
173 static int b43_wireless_core_init(struct b43_wldev *dev);
174 static void b43_wireless_core_stop(struct b43_wldev *dev);
175 static int b43_wireless_core_start(struct b43_wldev *dev);
176
177 static int b43_ratelimit(struct b43_wl *wl)
178 {
179 if (!wl || !wl->current_dev)
180 return 1;
181 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
182 return 1;
183 /* We are up and running.
184 * Ratelimit the messages to avoid DoS over the net. */
185 return net_ratelimit();
186 }
187
188 void b43info(struct b43_wl *wl, const char *fmt, ...)
189 {
190 va_list args;
191
192 if (!b43_ratelimit(wl))
193 return;
194 va_start(args, fmt);
195 printk(KERN_INFO "b43-%s: ",
196 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
197 vprintk(fmt, args);
198 va_end(args);
199 }
200
201 void b43err(struct b43_wl *wl, const char *fmt, ...)
202 {
203 va_list args;
204
205 if (!b43_ratelimit(wl))
206 return;
207 va_start(args, fmt);
208 printk(KERN_ERR "b43-%s ERROR: ",
209 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
210 vprintk(fmt, args);
211 va_end(args);
212 }
213
214 void b43warn(struct b43_wl *wl, const char *fmt, ...)
215 {
216 va_list args;
217
218 if (!b43_ratelimit(wl))
219 return;
220 va_start(args, fmt);
221 printk(KERN_WARNING "b43-%s warning: ",
222 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
223 vprintk(fmt, args);
224 va_end(args);
225 }
226
227 #if B43_DEBUG
228 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
229 {
230 va_list args;
231
232 va_start(args, fmt);
233 printk(KERN_DEBUG "b43-%s debug: ",
234 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
235 vprintk(fmt, args);
236 va_end(args);
237 }
238 #endif /* DEBUG */
239
240 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
241 {
242 u32 macctl;
243
244 B43_WARN_ON(offset % 4 != 0);
245
246 macctl = b43_read32(dev, B43_MMIO_MACCTL);
247 if (macctl & B43_MACCTL_BE)
248 val = swab32(val);
249
250 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
251 mmiowb();
252 b43_write32(dev, B43_MMIO_RAM_DATA, val);
253 }
254
255 static inline void b43_shm_control_word(struct b43_wldev *dev,
256 u16 routing, u16 offset)
257 {
258 u32 control;
259
260 /* "offset" is the WORD offset. */
261 control = routing;
262 control <<= 16;
263 control |= offset;
264 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
265 }
266
267 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
268 {
269 struct b43_wl *wl = dev->wl;
270 unsigned long flags;
271 u32 ret;
272
273 spin_lock_irqsave(&wl->shm_lock, flags);
274 if (routing == B43_SHM_SHARED) {
275 B43_WARN_ON(offset & 0x0001);
276 if (offset & 0x0003) {
277 /* Unaligned access */
278 b43_shm_control_word(dev, routing, offset >> 2);
279 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
280 ret <<= 16;
281 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
282 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
283
284 goto out;
285 }
286 offset >>= 2;
287 }
288 b43_shm_control_word(dev, routing, offset);
289 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
290 out:
291 spin_unlock_irqrestore(&wl->shm_lock, flags);
292
293 return ret;
294 }
295
296 u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
297 {
298 struct b43_wl *wl = dev->wl;
299 unsigned long flags;
300 u16 ret;
301
302 spin_lock_irqsave(&wl->shm_lock, flags);
303 if (routing == B43_SHM_SHARED) {
304 B43_WARN_ON(offset & 0x0001);
305 if (offset & 0x0003) {
306 /* Unaligned access */
307 b43_shm_control_word(dev, routing, offset >> 2);
308 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
309
310 goto out;
311 }
312 offset >>= 2;
313 }
314 b43_shm_control_word(dev, routing, offset);
315 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
316 out:
317 spin_unlock_irqrestore(&wl->shm_lock, flags);
318
319 return ret;
320 }
321
322 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
323 {
324 struct b43_wl *wl = dev->wl;
325 unsigned long flags;
326
327 spin_lock_irqsave(&wl->shm_lock, flags);
328 if (routing == B43_SHM_SHARED) {
329 B43_WARN_ON(offset & 0x0001);
330 if (offset & 0x0003) {
331 /* Unaligned access */
332 b43_shm_control_word(dev, routing, offset >> 2);
333 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
334 (value >> 16) & 0xffff);
335 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
336 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
337 goto out;
338 }
339 offset >>= 2;
340 }
341 b43_shm_control_word(dev, routing, offset);
342 b43_write32(dev, B43_MMIO_SHM_DATA, value);
343 out:
344 spin_unlock_irqrestore(&wl->shm_lock, flags);
345 }
346
347 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
348 {
349 struct b43_wl *wl = dev->wl;
350 unsigned long flags;
351
352 spin_lock_irqsave(&wl->shm_lock, flags);
353 if (routing == B43_SHM_SHARED) {
354 B43_WARN_ON(offset & 0x0001);
355 if (offset & 0x0003) {
356 /* Unaligned access */
357 b43_shm_control_word(dev, routing, offset >> 2);
358 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
359 goto out;
360 }
361 offset >>= 2;
362 }
363 b43_shm_control_word(dev, routing, offset);
364 b43_write16(dev, B43_MMIO_SHM_DATA, value);
365 out:
366 spin_unlock_irqrestore(&wl->shm_lock, flags);
367 }
368
369 /* Read HostFlags */
370 u32 b43_hf_read(struct b43_wldev * dev)
371 {
372 u32 ret;
373
374 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
375 ret <<= 16;
376 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
377
378 return ret;
379 }
380
381 /* Write HostFlags */
382 void b43_hf_write(struct b43_wldev *dev, u32 value)
383 {
384 b43_shm_write16(dev, B43_SHM_SHARED,
385 B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF));
386 b43_shm_write16(dev, B43_SHM_SHARED,
387 B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16));
388 }
389
390 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
391 {
392 /* We need to be careful. As we read the TSF from multiple
393 * registers, we should take care of register overflows.
394 * In theory, the whole tsf read process should be atomic.
395 * We try to be atomic here, by restaring the read process,
396 * if any of the high registers changed (overflew).
397 */
398 if (dev->dev->id.revision >= 3) {
399 u32 low, high, high2;
400
401 do {
402 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
403 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
404 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
405 } while (unlikely(high != high2));
406
407 *tsf = high;
408 *tsf <<= 32;
409 *tsf |= low;
410 } else {
411 u64 tmp;
412 u16 v0, v1, v2, v3;
413 u16 test1, test2, test3;
414
415 do {
416 v3 = b43_read16(dev, B43_MMIO_TSF_3);
417 v2 = b43_read16(dev, B43_MMIO_TSF_2);
418 v1 = b43_read16(dev, B43_MMIO_TSF_1);
419 v0 = b43_read16(dev, B43_MMIO_TSF_0);
420
421 test3 = b43_read16(dev, B43_MMIO_TSF_3);
422 test2 = b43_read16(dev, B43_MMIO_TSF_2);
423 test1 = b43_read16(dev, B43_MMIO_TSF_1);
424 } while (v3 != test3 || v2 != test2 || v1 != test1);
425
426 *tsf = v3;
427 *tsf <<= 48;
428 tmp = v2;
429 tmp <<= 32;
430 *tsf |= tmp;
431 tmp = v1;
432 tmp <<= 16;
433 *tsf |= tmp;
434 *tsf |= v0;
435 }
436 }
437
438 static void b43_time_lock(struct b43_wldev *dev)
439 {
440 u32 macctl;
441
442 macctl = b43_read32(dev, B43_MMIO_MACCTL);
443 macctl |= B43_MACCTL_TBTTHOLD;
444 b43_write32(dev, B43_MMIO_MACCTL, macctl);
445 /* Commit the write */
446 b43_read32(dev, B43_MMIO_MACCTL);
447 }
448
449 static void b43_time_unlock(struct b43_wldev *dev)
450 {
451 u32 macctl;
452
453 macctl = b43_read32(dev, B43_MMIO_MACCTL);
454 macctl &= ~B43_MACCTL_TBTTHOLD;
455 b43_write32(dev, B43_MMIO_MACCTL, macctl);
456 /* Commit the write */
457 b43_read32(dev, B43_MMIO_MACCTL);
458 }
459
460 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
461 {
462 /* Be careful with the in-progress timer.
463 * First zero out the low register, so we have a full
464 * register-overflow duration to complete the operation.
465 */
466 if (dev->dev->id.revision >= 3) {
467 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
468 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
469
470 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
471 mmiowb();
472 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
473 mmiowb();
474 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
475 } else {
476 u16 v0 = (tsf & 0x000000000000FFFFULL);
477 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
478 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
479 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
480
481 b43_write16(dev, B43_MMIO_TSF_0, 0);
482 mmiowb();
483 b43_write16(dev, B43_MMIO_TSF_3, v3);
484 mmiowb();
485 b43_write16(dev, B43_MMIO_TSF_2, v2);
486 mmiowb();
487 b43_write16(dev, B43_MMIO_TSF_1, v1);
488 mmiowb();
489 b43_write16(dev, B43_MMIO_TSF_0, v0);
490 }
491 }
492
493 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
494 {
495 b43_time_lock(dev);
496 b43_tsf_write_locked(dev, tsf);
497 b43_time_unlock(dev);
498 }
499
500 static
501 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
502 {
503 static const u8 zero_addr[ETH_ALEN] = { 0 };
504 u16 data;
505
506 if (!mac)
507 mac = zero_addr;
508
509 offset |= 0x0020;
510 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
511
512 data = mac[0];
513 data |= mac[1] << 8;
514 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
515 data = mac[2];
516 data |= mac[3] << 8;
517 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
518 data = mac[4];
519 data |= mac[5] << 8;
520 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
521 }
522
523 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
524 {
525 const u8 *mac;
526 const u8 *bssid;
527 u8 mac_bssid[ETH_ALEN * 2];
528 int i;
529 u32 tmp;
530
531 bssid = dev->wl->bssid;
532 mac = dev->wl->mac_addr;
533
534 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
535
536 memcpy(mac_bssid, mac, ETH_ALEN);
537 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
538
539 /* Write our MAC address and BSSID to template ram */
540 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
541 tmp = (u32) (mac_bssid[i + 0]);
542 tmp |= (u32) (mac_bssid[i + 1]) << 8;
543 tmp |= (u32) (mac_bssid[i + 2]) << 16;
544 tmp |= (u32) (mac_bssid[i + 3]) << 24;
545 b43_ram_write(dev, 0x20 + i, tmp);
546 }
547 }
548
549 static void b43_upload_card_macaddress(struct b43_wldev *dev)
550 {
551 b43_write_mac_bssid_templates(dev);
552 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
553 }
554
555 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
556 {
557 /* slot_time is in usec. */
558 if (dev->phy.type != B43_PHYTYPE_G)
559 return;
560 b43_write16(dev, 0x684, 510 + slot_time);
561 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
562 }
563
564 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
565 {
566 b43_set_slot_time(dev, 9);
567 dev->short_slot = 1;
568 }
569
570 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
571 {
572 b43_set_slot_time(dev, 20);
573 dev->short_slot = 0;
574 }
575
576 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
577 * Returns the _previously_ enabled IRQ mask.
578 */
579 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
580 {
581 u32 old_mask;
582
583 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
584 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
585
586 return old_mask;
587 }
588
589 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
590 * Returns the _previously_ enabled IRQ mask.
591 */
592 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
593 {
594 u32 old_mask;
595
596 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
597 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
598
599 return old_mask;
600 }
601
602 /* Synchronize IRQ top- and bottom-half.
603 * IRQs must be masked before calling this.
604 * This must not be called with the irq_lock held.
605 */
606 static void b43_synchronize_irq(struct b43_wldev *dev)
607 {
608 synchronize_irq(dev->dev->irq);
609 tasklet_kill(&dev->isr_tasklet);
610 }
611
612 /* DummyTransmission function, as documented on
613 * http://bcm-specs.sipsolutions.net/DummyTransmission
614 */
615 void b43_dummy_transmission(struct b43_wldev *dev)
616 {
617 struct b43_phy *phy = &dev->phy;
618 unsigned int i, max_loop;
619 u16 value;
620 u32 buffer[5] = {
621 0x00000000,
622 0x00D40000,
623 0x00000000,
624 0x01000000,
625 0x00000000,
626 };
627
628 switch (phy->type) {
629 case B43_PHYTYPE_A:
630 max_loop = 0x1E;
631 buffer[0] = 0x000201CC;
632 break;
633 case B43_PHYTYPE_B:
634 case B43_PHYTYPE_G:
635 max_loop = 0xFA;
636 buffer[0] = 0x000B846E;
637 break;
638 default:
639 B43_WARN_ON(1);
640 return;
641 }
642
643 for (i = 0; i < 5; i++)
644 b43_ram_write(dev, i * 4, buffer[i]);
645
646 /* Commit writes */
647 b43_read32(dev, B43_MMIO_MACCTL);
648
649 b43_write16(dev, 0x0568, 0x0000);
650 b43_write16(dev, 0x07C0, 0x0000);
651 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
652 b43_write16(dev, 0x050C, value);
653 b43_write16(dev, 0x0508, 0x0000);
654 b43_write16(dev, 0x050A, 0x0000);
655 b43_write16(dev, 0x054C, 0x0000);
656 b43_write16(dev, 0x056A, 0x0014);
657 b43_write16(dev, 0x0568, 0x0826);
658 b43_write16(dev, 0x0500, 0x0000);
659 b43_write16(dev, 0x0502, 0x0030);
660
661 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
662 b43_radio_write16(dev, 0x0051, 0x0017);
663 for (i = 0x00; i < max_loop; i++) {
664 value = b43_read16(dev, 0x050E);
665 if (value & 0x0080)
666 break;
667 udelay(10);
668 }
669 for (i = 0x00; i < 0x0A; i++) {
670 value = b43_read16(dev, 0x050E);
671 if (value & 0x0400)
672 break;
673 udelay(10);
674 }
675 for (i = 0x00; i < 0x0A; i++) {
676 value = b43_read16(dev, 0x0690);
677 if (!(value & 0x0100))
678 break;
679 udelay(10);
680 }
681 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
682 b43_radio_write16(dev, 0x0051, 0x0037);
683 }
684
685 static void key_write(struct b43_wldev *dev,
686 u8 index, u8 algorithm, const u8 * key)
687 {
688 unsigned int i;
689 u32 offset;
690 u16 value;
691 u16 kidx;
692
693 /* Key index/algo block */
694 kidx = b43_kidx_to_fw(dev, index);
695 value = ((kidx << 4) | algorithm);
696 b43_shm_write16(dev, B43_SHM_SHARED,
697 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
698
699 /* Write the key to the Key Table Pointer offset */
700 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
701 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
702 value = key[i];
703 value |= (u16) (key[i + 1]) << 8;
704 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
705 }
706 }
707
708 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
709 {
710 u32 addrtmp[2] = { 0, 0, };
711 u8 per_sta_keys_start = 8;
712
713 if (b43_new_kidx_api(dev))
714 per_sta_keys_start = 4;
715
716 B43_WARN_ON(index < per_sta_keys_start);
717 /* We have two default TX keys and possibly two default RX keys.
718 * Physical mac 0 is mapped to physical key 4 or 8, depending
719 * on the firmware version.
720 * So we must adjust the index here.
721 */
722 index -= per_sta_keys_start;
723
724 if (addr) {
725 addrtmp[0] = addr[0];
726 addrtmp[0] |= ((u32) (addr[1]) << 8);
727 addrtmp[0] |= ((u32) (addr[2]) << 16);
728 addrtmp[0] |= ((u32) (addr[3]) << 24);
729 addrtmp[1] = addr[4];
730 addrtmp[1] |= ((u32) (addr[5]) << 8);
731 }
732
733 if (dev->dev->id.revision >= 5) {
734 /* Receive match transmitter address mechanism */
735 b43_shm_write32(dev, B43_SHM_RCMTA,
736 (index * 2) + 0, addrtmp[0]);
737 b43_shm_write16(dev, B43_SHM_RCMTA,
738 (index * 2) + 1, addrtmp[1]);
739 } else {
740 /* RXE (Receive Engine) and
741 * PSM (Programmable State Machine) mechanism
742 */
743 if (index < 8) {
744 /* TODO write to RCM 16, 19, 22 and 25 */
745 } else {
746 b43_shm_write32(dev, B43_SHM_SHARED,
747 B43_SHM_SH_PSM + (index * 6) + 0,
748 addrtmp[0]);
749 b43_shm_write16(dev, B43_SHM_SHARED,
750 B43_SHM_SH_PSM + (index * 6) + 4,
751 addrtmp[1]);
752 }
753 }
754 }
755
756 static void do_key_write(struct b43_wldev *dev,
757 u8 index, u8 algorithm,
758 const u8 * key, size_t key_len, const u8 * mac_addr)
759 {
760 u8 buf[B43_SEC_KEYSIZE] = { 0, };
761 u8 per_sta_keys_start = 8;
762
763 if (b43_new_kidx_api(dev))
764 per_sta_keys_start = 4;
765
766 B43_WARN_ON(index >= dev->max_nr_keys);
767 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
768
769 if (index >= per_sta_keys_start)
770 keymac_write(dev, index, NULL); /* First zero out mac. */
771 if (key)
772 memcpy(buf, key, key_len);
773 key_write(dev, index, algorithm, buf);
774 if (index >= per_sta_keys_start)
775 keymac_write(dev, index, mac_addr);
776
777 dev->key[index].algorithm = algorithm;
778 }
779
780 static int b43_key_write(struct b43_wldev *dev,
781 int index, u8 algorithm,
782 const u8 * key, size_t key_len,
783 const u8 * mac_addr,
784 struct ieee80211_key_conf *keyconf)
785 {
786 int i;
787 int sta_keys_start;
788
789 if (key_len > B43_SEC_KEYSIZE)
790 return -EINVAL;
791 for (i = 0; i < dev->max_nr_keys; i++) {
792 /* Check that we don't already have this key. */
793 B43_WARN_ON(dev->key[i].keyconf == keyconf);
794 }
795 if (index < 0) {
796 /* Either pairwise key or address is 00:00:00:00:00:00
797 * for transmit-only keys. Search the index. */
798 if (b43_new_kidx_api(dev))
799 sta_keys_start = 4;
800 else
801 sta_keys_start = 8;
802 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
803 if (!dev->key[i].keyconf) {
804 /* found empty */
805 index = i;
806 break;
807 }
808 }
809 if (index < 0) {
810 b43err(dev->wl, "Out of hardware key memory\n");
811 return -ENOSPC;
812 }
813 } else
814 B43_WARN_ON(index > 3);
815
816 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
817 if ((index <= 3) && !b43_new_kidx_api(dev)) {
818 /* Default RX key */
819 B43_WARN_ON(mac_addr);
820 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
821 }
822 keyconf->hw_key_idx = index;
823 dev->key[index].keyconf = keyconf;
824
825 return 0;
826 }
827
828 static int b43_key_clear(struct b43_wldev *dev, int index)
829 {
830 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
831 return -EINVAL;
832 do_key_write(dev, index, B43_SEC_ALGO_NONE,
833 NULL, B43_SEC_KEYSIZE, NULL);
834 if ((index <= 3) && !b43_new_kidx_api(dev)) {
835 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
836 NULL, B43_SEC_KEYSIZE, NULL);
837 }
838 dev->key[index].keyconf = NULL;
839
840 return 0;
841 }
842
843 static void b43_clear_keys(struct b43_wldev *dev)
844 {
845 int i;
846
847 for (i = 0; i < dev->max_nr_keys; i++)
848 b43_key_clear(dev, i);
849 }
850
851 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
852 {
853 u32 macctl;
854 u16 ucstat;
855 bool hwps;
856 bool awake;
857 int i;
858
859 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
860 (ps_flags & B43_PS_DISABLED));
861 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
862
863 if (ps_flags & B43_PS_ENABLED) {
864 hwps = 1;
865 } else if (ps_flags & B43_PS_DISABLED) {
866 hwps = 0;
867 } else {
868 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
869 // and thus is not an AP and we are associated, set bit 25
870 }
871 if (ps_flags & B43_PS_AWAKE) {
872 awake = 1;
873 } else if (ps_flags & B43_PS_ASLEEP) {
874 awake = 0;
875 } else {
876 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
877 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
878 // successful, set bit26
879 }
880
881 /* FIXME: For now we force awake-on and hwps-off */
882 hwps = 0;
883 awake = 1;
884
885 macctl = b43_read32(dev, B43_MMIO_MACCTL);
886 if (hwps)
887 macctl |= B43_MACCTL_HWPS;
888 else
889 macctl &= ~B43_MACCTL_HWPS;
890 if (awake)
891 macctl |= B43_MACCTL_AWAKE;
892 else
893 macctl &= ~B43_MACCTL_AWAKE;
894 b43_write32(dev, B43_MMIO_MACCTL, macctl);
895 /* Commit write */
896 b43_read32(dev, B43_MMIO_MACCTL);
897 if (awake && dev->dev->id.revision >= 5) {
898 /* Wait for the microcode to wake up. */
899 for (i = 0; i < 100; i++) {
900 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
901 B43_SHM_SH_UCODESTAT);
902 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
903 break;
904 udelay(10);
905 }
906 }
907 }
908
909 /* Turn the Analog ON/OFF */
910 static void b43_switch_analog(struct b43_wldev *dev, int on)
911 {
912 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
913 }
914
915 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
916 {
917 u32 tmslow;
918 u32 macctl;
919
920 flags |= B43_TMSLOW_PHYCLKEN;
921 flags |= B43_TMSLOW_PHYRESET;
922 ssb_device_enable(dev->dev, flags);
923 msleep(2); /* Wait for the PLL to turn on. */
924
925 /* Now take the PHY out of Reset again */
926 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
927 tmslow |= SSB_TMSLOW_FGC;
928 tmslow &= ~B43_TMSLOW_PHYRESET;
929 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
930 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
931 msleep(1);
932 tmslow &= ~SSB_TMSLOW_FGC;
933 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
934 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
935 msleep(1);
936
937 /* Turn Analog ON */
938 b43_switch_analog(dev, 1);
939
940 macctl = b43_read32(dev, B43_MMIO_MACCTL);
941 macctl &= ~B43_MACCTL_GMODE;
942 if (flags & B43_TMSLOW_GMODE)
943 macctl |= B43_MACCTL_GMODE;
944 macctl |= B43_MACCTL_IHR_ENABLED;
945 b43_write32(dev, B43_MMIO_MACCTL, macctl);
946 }
947
948 static void handle_irq_transmit_status(struct b43_wldev *dev)
949 {
950 u32 v0, v1;
951 u16 tmp;
952 struct b43_txstatus stat;
953
954 while (1) {
955 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
956 if (!(v0 & 0x00000001))
957 break;
958 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
959
960 stat.cookie = (v0 >> 16);
961 stat.seq = (v1 & 0x0000FFFF);
962 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
963 tmp = (v0 & 0x0000FFFF);
964 stat.frame_count = ((tmp & 0xF000) >> 12);
965 stat.rts_count = ((tmp & 0x0F00) >> 8);
966 stat.supp_reason = ((tmp & 0x001C) >> 2);
967 stat.pm_indicated = !!(tmp & 0x0080);
968 stat.intermediate = !!(tmp & 0x0040);
969 stat.for_ampdu = !!(tmp & 0x0020);
970 stat.acked = !!(tmp & 0x0002);
971
972 b43_handle_txstatus(dev, &stat);
973 }
974 }
975
976 static void drain_txstatus_queue(struct b43_wldev *dev)
977 {
978 u32 dummy;
979
980 if (dev->dev->id.revision < 5)
981 return;
982 /* Read all entries from the microcode TXstatus FIFO
983 * and throw them away.
984 */
985 while (1) {
986 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
987 if (!(dummy & 0x00000001))
988 break;
989 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
990 }
991 }
992
993 static u32 b43_jssi_read(struct b43_wldev *dev)
994 {
995 u32 val = 0;
996
997 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
998 val <<= 16;
999 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1000
1001 return val;
1002 }
1003
1004 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1005 {
1006 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1007 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1008 }
1009
1010 static void b43_generate_noise_sample(struct b43_wldev *dev)
1011 {
1012 b43_jssi_write(dev, 0x7F7F7F7F);
1013 b43_write32(dev, B43_MMIO_MACCMD,
1014 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1015 B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1016 }
1017
1018 static void b43_calculate_link_quality(struct b43_wldev *dev)
1019 {
1020 /* Top half of Link Quality calculation. */
1021
1022 if (dev->noisecalc.calculation_running)
1023 return;
1024 dev->noisecalc.channel_at_start = dev->phy.channel;
1025 dev->noisecalc.calculation_running = 1;
1026 dev->noisecalc.nr_samples = 0;
1027
1028 b43_generate_noise_sample(dev);
1029 }
1030
1031 static void handle_irq_noise(struct b43_wldev *dev)
1032 {
1033 struct b43_phy *phy = &dev->phy;
1034 u16 tmp;
1035 u8 noise[4];
1036 u8 i, j;
1037 s32 average;
1038
1039 /* Bottom half of Link Quality calculation. */
1040
1041 B43_WARN_ON(!dev->noisecalc.calculation_running);
1042 if (dev->noisecalc.channel_at_start != phy->channel)
1043 goto drop_calculation;
1044 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1045 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1046 noise[2] == 0x7F || noise[3] == 0x7F)
1047 goto generate_new;
1048
1049 /* Get the noise samples. */
1050 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1051 i = dev->noisecalc.nr_samples;
1052 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1053 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1054 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1055 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1056 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1057 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1058 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1059 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1060 dev->noisecalc.nr_samples++;
1061 if (dev->noisecalc.nr_samples == 8) {
1062 /* Calculate the Link Quality by the noise samples. */
1063 average = 0;
1064 for (i = 0; i < 8; i++) {
1065 for (j = 0; j < 4; j++)
1066 average += dev->noisecalc.samples[i][j];
1067 }
1068 average /= (8 * 4);
1069 average *= 125;
1070 average += 64;
1071 average /= 128;
1072 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1073 tmp = (tmp / 128) & 0x1F;
1074 if (tmp >= 8)
1075 average += 2;
1076 else
1077 average -= 25;
1078 if (tmp == 8)
1079 average -= 72;
1080 else
1081 average -= 48;
1082
1083 dev->stats.link_noise = average;
1084 drop_calculation:
1085 dev->noisecalc.calculation_running = 0;
1086 return;
1087 }
1088 generate_new:
1089 b43_generate_noise_sample(dev);
1090 }
1091
1092 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1093 {
1094 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1095 ///TODO: PS TBTT
1096 } else {
1097 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1098 b43_power_saving_ctl_bits(dev, 0);
1099 }
1100 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1101 dev->dfq_valid = 1;
1102 }
1103
1104 static void handle_irq_atim_end(struct b43_wldev *dev)
1105 {
1106 if (dev->dfq_valid) {
1107 b43_write32(dev, B43_MMIO_MACCMD,
1108 b43_read32(dev, B43_MMIO_MACCMD)
1109 | B43_MACCMD_DFQ_VALID);
1110 dev->dfq_valid = 0;
1111 }
1112 }
1113
1114 static void handle_irq_pmq(struct b43_wldev *dev)
1115 {
1116 u32 tmp;
1117
1118 //TODO: AP mode.
1119
1120 while (1) {
1121 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1122 if (!(tmp & 0x00000008))
1123 break;
1124 }
1125 /* 16bit write is odd, but correct. */
1126 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1127 }
1128
1129 static void b43_write_template_common(struct b43_wldev *dev,
1130 const u8 * data, u16 size,
1131 u16 ram_offset,
1132 u16 shm_size_offset, u8 rate)
1133 {
1134 u32 i, tmp;
1135 struct b43_plcp_hdr4 plcp;
1136
1137 plcp.data = 0;
1138 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1139 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1140 ram_offset += sizeof(u32);
1141 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1142 * So leave the first two bytes of the next write blank.
1143 */
1144 tmp = (u32) (data[0]) << 16;
1145 tmp |= (u32) (data[1]) << 24;
1146 b43_ram_write(dev, ram_offset, tmp);
1147 ram_offset += sizeof(u32);
1148 for (i = 2; i < size; i += sizeof(u32)) {
1149 tmp = (u32) (data[i + 0]);
1150 if (i + 1 < size)
1151 tmp |= (u32) (data[i + 1]) << 8;
1152 if (i + 2 < size)
1153 tmp |= (u32) (data[i + 2]) << 16;
1154 if (i + 3 < size)
1155 tmp |= (u32) (data[i + 3]) << 24;
1156 b43_ram_write(dev, ram_offset + i - 2, tmp);
1157 }
1158 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1159 size + sizeof(struct b43_plcp_hdr6));
1160 }
1161
1162 static void b43_write_beacon_template(struct b43_wldev *dev,
1163 u16 ram_offset,
1164 u16 shm_size_offset, u8 rate)
1165 {
1166 int i, len;
1167 const struct ieee80211_mgmt *bcn;
1168 const u8 *ie;
1169 bool tim_found = 0;
1170
1171 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1172 len = min((size_t) dev->wl->current_beacon->len,
1173 0x200 - sizeof(struct b43_plcp_hdr6));
1174
1175 b43_write_template_common(dev, (const u8 *)bcn,
1176 len, ram_offset, shm_size_offset, rate);
1177
1178 /* Find the position of the TIM and the DTIM_period value
1179 * and write them to SHM. */
1180 ie = bcn->u.beacon.variable;
1181 for (i = 0; i < len - 2; ) {
1182 uint8_t ie_id, ie_len;
1183
1184 ie_id = ie[i];
1185 ie_len = ie[i + 1];
1186 if (ie_id == 5) {
1187 u16 tim_position;
1188 u16 dtim_period;
1189 /* This is the TIM Information Element */
1190
1191 /* Check whether the ie_len is in the beacon data range. */
1192 if (len < ie_len + 2 + i)
1193 break;
1194 /* A valid TIM is at least 4 bytes long. */
1195 if (ie_len < 4)
1196 break;
1197 tim_found = 1;
1198
1199 tim_position = sizeof(struct b43_plcp_hdr6);
1200 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1201 tim_position += i;
1202
1203 dtim_period = ie[i + 3];
1204
1205 b43_shm_write16(dev, B43_SHM_SHARED,
1206 B43_SHM_SH_TIMBPOS, tim_position);
1207 b43_shm_write16(dev, B43_SHM_SHARED,
1208 B43_SHM_SH_DTIMPER, dtim_period);
1209 break;
1210 }
1211 i += ie_len + 2;
1212 }
1213 if (!tim_found) {
1214 b43warn(dev->wl, "Did not find a valid TIM IE in "
1215 "the beacon template packet. AP or IBSS operation "
1216 "may be broken.\n");
1217 }
1218 }
1219
1220 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1221 u16 shm_offset, u16 size, u8 rate)
1222 {
1223 struct b43_plcp_hdr4 plcp;
1224 u32 tmp;
1225 __le16 dur;
1226
1227 plcp.data = 0;
1228 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1229 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1230 dev->wl->vif, size,
1231 B43_RATE_TO_BASE100KBPS(rate));
1232 /* Write PLCP in two parts and timing for packet transfer */
1233 tmp = le32_to_cpu(plcp.data);
1234 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1235 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1236 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1237 }
1238
1239 /* Instead of using custom probe response template, this function
1240 * just patches custom beacon template by:
1241 * 1) Changing packet type
1242 * 2) Patching duration field
1243 * 3) Stripping TIM
1244 */
1245 static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
1246 u16 *dest_size, u8 rate)
1247 {
1248 const u8 *src_data;
1249 u8 *dest_data;
1250 u16 src_size, elem_size, src_pos, dest_pos;
1251 __le16 dur;
1252 struct ieee80211_hdr *hdr;
1253 size_t ie_start;
1254
1255 src_size = dev->wl->current_beacon->len;
1256 src_data = (const u8 *)dev->wl->current_beacon->data;
1257
1258 /* Get the start offset of the variable IEs in the packet. */
1259 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1260 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
1261
1262 if (B43_WARN_ON(src_size < ie_start))
1263 return NULL;
1264
1265 dest_data = kmalloc(src_size, GFP_ATOMIC);
1266 if (unlikely(!dest_data))
1267 return NULL;
1268
1269 /* Copy the static data and all Information Elements, except the TIM. */
1270 memcpy(dest_data, src_data, ie_start);
1271 src_pos = ie_start;
1272 dest_pos = ie_start;
1273 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1274 elem_size = src_data[src_pos + 1] + 2;
1275 if (src_data[src_pos] == 5) {
1276 /* This is the TIM. */
1277 continue;
1278 }
1279 memcpy(dest_data + dest_pos, src_data + src_pos,
1280 elem_size);
1281 dest_pos += elem_size;
1282 }
1283 *dest_size = dest_pos;
1284 hdr = (struct ieee80211_hdr *)dest_data;
1285
1286 /* Set the frame control. */
1287 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1288 IEEE80211_STYPE_PROBE_RESP);
1289 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1290 dev->wl->vif, *dest_size,
1291 B43_RATE_TO_BASE100KBPS(rate));
1292 hdr->duration_id = dur;
1293
1294 return dest_data;
1295 }
1296
1297 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1298 u16 ram_offset,
1299 u16 shm_size_offset, u8 rate)
1300 {
1301 const u8 *probe_resp_data;
1302 u16 size;
1303
1304 size = dev->wl->current_beacon->len;
1305 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1306 if (unlikely(!probe_resp_data))
1307 return;
1308
1309 /* Looks like PLCP headers plus packet timings are stored for
1310 * all possible basic rates
1311 */
1312 b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB);
1313 b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB);
1314 b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB);
1315 b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB);
1316
1317 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1318 b43_write_template_common(dev, probe_resp_data,
1319 size, ram_offset, shm_size_offset, rate);
1320 kfree(probe_resp_data);
1321 }
1322
1323 /* Asynchronously update the packet templates in template RAM.
1324 * Locking: Requires wl->irq_lock to be locked. */
1325 static void b43_update_templates(struct b43_wl *wl, struct sk_buff *beacon)
1326 {
1327 /* This is the top half of the ansynchronous beacon update.
1328 * The bottom half is the beacon IRQ.
1329 * Beacon update must be asynchronous to avoid sending an
1330 * invalid beacon. This can happen for example, if the firmware
1331 * transmits a beacon while we are updating it. */
1332
1333 if (wl->current_beacon)
1334 dev_kfree_skb_any(wl->current_beacon);
1335 wl->current_beacon = beacon;
1336 wl->beacon0_uploaded = 0;
1337 wl->beacon1_uploaded = 0;
1338 }
1339
1340 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1341 {
1342 u32 tmp;
1343 u16 i, len;
1344
1345 len = min((u16) ssid_len, (u16) 0x100);
1346 for (i = 0; i < len; i += sizeof(u32)) {
1347 tmp = (u32) (ssid[i + 0]);
1348 if (i + 1 < len)
1349 tmp |= (u32) (ssid[i + 1]) << 8;
1350 if (i + 2 < len)
1351 tmp |= (u32) (ssid[i + 2]) << 16;
1352 if (i + 3 < len)
1353 tmp |= (u32) (ssid[i + 3]) << 24;
1354 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1355 }
1356 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1357 }
1358
1359 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1360 {
1361 b43_time_lock(dev);
1362 if (dev->dev->id.revision >= 3) {
1363 b43_write32(dev, 0x188, (beacon_int << 16));
1364 } else {
1365 b43_write16(dev, 0x606, (beacon_int >> 6));
1366 b43_write16(dev, 0x610, beacon_int);
1367 }
1368 b43_time_unlock(dev);
1369 }
1370
1371 static void handle_irq_beacon(struct b43_wldev *dev)
1372 {
1373 struct b43_wl *wl = dev->wl;
1374 u32 cmd;
1375
1376 if (!b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
1377 return;
1378
1379 /* This is the bottom half of the asynchronous beacon update. */
1380
1381 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1382 if (!(cmd & B43_MACCMD_BEACON0_VALID)) {
1383 if (!wl->beacon0_uploaded) {
1384 b43_write_beacon_template(dev, 0x68, 0x18,
1385 B43_CCK_RATE_1MB);
1386 b43_write_probe_resp_template(dev, 0x268, 0x4A,
1387 B43_CCK_RATE_11MB);
1388 wl->beacon0_uploaded = 1;
1389 }
1390 cmd |= B43_MACCMD_BEACON0_VALID;
1391 }
1392 if (!(cmd & B43_MACCMD_BEACON1_VALID)) {
1393 if (!wl->beacon1_uploaded) {
1394 b43_write_beacon_template(dev, 0x468, 0x1A,
1395 B43_CCK_RATE_1MB);
1396 wl->beacon1_uploaded = 1;
1397 }
1398 cmd |= B43_MACCMD_BEACON1_VALID;
1399 }
1400 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1401 }
1402
1403 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1404 {
1405 //TODO
1406 }
1407
1408 /* Interrupt handler bottom-half */
1409 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1410 {
1411 u32 reason;
1412 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1413 u32 merged_dma_reason = 0;
1414 int i;
1415 unsigned long flags;
1416
1417 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1418
1419 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1420
1421 reason = dev->irq_reason;
1422 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1423 dma_reason[i] = dev->dma_reason[i];
1424 merged_dma_reason |= dma_reason[i];
1425 }
1426
1427 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1428 b43err(dev->wl, "MAC transmission error\n");
1429
1430 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1431 b43err(dev->wl, "PHY transmission error\n");
1432 rmb();
1433 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1434 atomic_set(&dev->phy.txerr_cnt,
1435 B43_PHY_TX_BADNESS_LIMIT);
1436 b43err(dev->wl, "Too many PHY TX errors, "
1437 "restarting the controller\n");
1438 b43_controller_restart(dev, "PHY TX errors");
1439 }
1440 }
1441
1442 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1443 B43_DMAIRQ_NONFATALMASK))) {
1444 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1445 b43err(dev->wl, "Fatal DMA error: "
1446 "0x%08X, 0x%08X, 0x%08X, "
1447 "0x%08X, 0x%08X, 0x%08X\n",
1448 dma_reason[0], dma_reason[1],
1449 dma_reason[2], dma_reason[3],
1450 dma_reason[4], dma_reason[5]);
1451 b43_controller_restart(dev, "DMA error");
1452 mmiowb();
1453 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1454 return;
1455 }
1456 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1457 b43err(dev->wl, "DMA error: "
1458 "0x%08X, 0x%08X, 0x%08X, "
1459 "0x%08X, 0x%08X, 0x%08X\n",
1460 dma_reason[0], dma_reason[1],
1461 dma_reason[2], dma_reason[3],
1462 dma_reason[4], dma_reason[5]);
1463 }
1464 }
1465
1466 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1467 handle_irq_ucode_debug(dev);
1468 if (reason & B43_IRQ_TBTT_INDI)
1469 handle_irq_tbtt_indication(dev);
1470 if (reason & B43_IRQ_ATIM_END)
1471 handle_irq_atim_end(dev);
1472 if (reason & B43_IRQ_BEACON)
1473 handle_irq_beacon(dev);
1474 if (reason & B43_IRQ_PMQ)
1475 handle_irq_pmq(dev);
1476 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1477 ;/* TODO */
1478 if (reason & B43_IRQ_NOISESAMPLE_OK)
1479 handle_irq_noise(dev);
1480
1481 /* Check the DMA reason registers for received data. */
1482 if (dma_reason[0] & B43_DMAIRQ_RX_DONE)
1483 b43_dma_rx(dev->dma.rx_ring0);
1484 if (dma_reason[3] & B43_DMAIRQ_RX_DONE)
1485 b43_dma_rx(dev->dma.rx_ring3);
1486 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1487 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1488 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1489 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1490
1491 if (reason & B43_IRQ_TX_OK)
1492 handle_irq_transmit_status(dev);
1493
1494 b43_interrupt_enable(dev, dev->irq_savedstate);
1495 mmiowb();
1496 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1497 }
1498
1499 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1500 {
1501 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1502
1503 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1504 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1505 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1506 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1507 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1508 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1509 }
1510
1511 /* Interrupt handler top-half */
1512 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1513 {
1514 irqreturn_t ret = IRQ_NONE;
1515 struct b43_wldev *dev = dev_id;
1516 u32 reason;
1517
1518 if (!dev)
1519 return IRQ_NONE;
1520
1521 spin_lock(&dev->wl->irq_lock);
1522
1523 if (b43_status(dev) < B43_STAT_STARTED)
1524 goto out;
1525 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1526 if (reason == 0xffffffff) /* shared IRQ */
1527 goto out;
1528 ret = IRQ_HANDLED;
1529 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1530 if (!reason)
1531 goto out;
1532
1533 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1534 & 0x0001DC00;
1535 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1536 & 0x0000DC00;
1537 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1538 & 0x0000DC00;
1539 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1540 & 0x0001DC00;
1541 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1542 & 0x0000DC00;
1543 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1544 & 0x0000DC00;
1545
1546 b43_interrupt_ack(dev, reason);
1547 /* disable all IRQs. They are enabled again in the bottom half. */
1548 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1549 /* save the reason code and call our bottom half. */
1550 dev->irq_reason = reason;
1551 tasklet_schedule(&dev->isr_tasklet);
1552 out:
1553 mmiowb();
1554 spin_unlock(&dev->wl->irq_lock);
1555
1556 return ret;
1557 }
1558
1559 static void b43_release_firmware(struct b43_wldev *dev)
1560 {
1561 release_firmware(dev->fw.ucode);
1562 dev->fw.ucode = NULL;
1563 release_firmware(dev->fw.pcm);
1564 dev->fw.pcm = NULL;
1565 release_firmware(dev->fw.initvals);
1566 dev->fw.initvals = NULL;
1567 release_firmware(dev->fw.initvals_band);
1568 dev->fw.initvals_band = NULL;
1569 }
1570
1571 static void b43_print_fw_helptext(struct b43_wl *wl)
1572 {
1573 b43err(wl, "You must go to "
1574 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1575 "and download the correct firmware (version 4).\n");
1576 }
1577
1578 static int do_request_fw(struct b43_wldev *dev,
1579 const char *name,
1580 const struct firmware **fw)
1581 {
1582 char path[sizeof(modparam_fwpostfix) + 32];
1583 struct b43_fw_header *hdr;
1584 u32 size;
1585 int err;
1586
1587 if (!name)
1588 return 0;
1589
1590 snprintf(path, ARRAY_SIZE(path),
1591 "b43%s/%s.fw",
1592 modparam_fwpostfix, name);
1593 err = request_firmware(fw, path, dev->dev->dev);
1594 if (err) {
1595 b43err(dev->wl, "Firmware file \"%s\" not found "
1596 "or load failed.\n", path);
1597 return err;
1598 }
1599 if ((*fw)->size < sizeof(struct b43_fw_header))
1600 goto err_format;
1601 hdr = (struct b43_fw_header *)((*fw)->data);
1602 switch (hdr->type) {
1603 case B43_FW_TYPE_UCODE:
1604 case B43_FW_TYPE_PCM:
1605 size = be32_to_cpu(hdr->size);
1606 if (size != (*fw)->size - sizeof(struct b43_fw_header))
1607 goto err_format;
1608 /* fallthrough */
1609 case B43_FW_TYPE_IV:
1610 if (hdr->ver != 1)
1611 goto err_format;
1612 break;
1613 default:
1614 goto err_format;
1615 }
1616
1617 return err;
1618
1619 err_format:
1620 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1621 return -EPROTO;
1622 }
1623
1624 static int b43_request_firmware(struct b43_wldev *dev)
1625 {
1626 struct b43_firmware *fw = &dev->fw;
1627 const u8 rev = dev->dev->id.revision;
1628 const char *filename;
1629 u32 tmshigh;
1630 int err;
1631
1632 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1633 if (!fw->ucode) {
1634 if ((rev >= 5) && (rev <= 10))
1635 filename = "ucode5";
1636 else if ((rev >= 11) && (rev <= 12))
1637 filename = "ucode11";
1638 else if (rev >= 13)
1639 filename = "ucode13";
1640 else
1641 goto err_no_ucode;
1642 err = do_request_fw(dev, filename, &fw->ucode);
1643 if (err)
1644 goto err_load;
1645 }
1646 if (!fw->pcm) {
1647 if ((rev >= 5) && (rev <= 10))
1648 filename = "pcm5";
1649 else if (rev >= 11)
1650 filename = NULL;
1651 else
1652 goto err_no_pcm;
1653 err = do_request_fw(dev, filename, &fw->pcm);
1654 if (err)
1655 goto err_load;
1656 }
1657 if (!fw->initvals) {
1658 switch (dev->phy.type) {
1659 case B43_PHYTYPE_A:
1660 if ((rev >= 5) && (rev <= 10)) {
1661 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1662 filename = "a0g1initvals5";
1663 else
1664 filename = "a0g0initvals5";
1665 } else
1666 goto err_no_initvals;
1667 break;
1668 case B43_PHYTYPE_G:
1669 if ((rev >= 5) && (rev <= 10))
1670 filename = "b0g0initvals5";
1671 else if (rev >= 13)
1672 filename = "lp0initvals13";
1673 else
1674 goto err_no_initvals;
1675 break;
1676 default:
1677 goto err_no_initvals;
1678 }
1679 err = do_request_fw(dev, filename, &fw->initvals);
1680 if (err)
1681 goto err_load;
1682 }
1683 if (!fw->initvals_band) {
1684 switch (dev->phy.type) {
1685 case B43_PHYTYPE_A:
1686 if ((rev >= 5) && (rev <= 10)) {
1687 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1688 filename = "a0g1bsinitvals5";
1689 else
1690 filename = "a0g0bsinitvals5";
1691 } else if (rev >= 11)
1692 filename = NULL;
1693 else
1694 goto err_no_initvals;
1695 break;
1696 case B43_PHYTYPE_G:
1697 if ((rev >= 5) && (rev <= 10))
1698 filename = "b0g0bsinitvals5";
1699 else if (rev >= 11)
1700 filename = NULL;
1701 else
1702 goto err_no_initvals;
1703 break;
1704 default:
1705 goto err_no_initvals;
1706 }
1707 err = do_request_fw(dev, filename, &fw->initvals_band);
1708 if (err)
1709 goto err_load;
1710 }
1711
1712 return 0;
1713
1714 err_load:
1715 b43_print_fw_helptext(dev->wl);
1716 goto error;
1717
1718 err_no_ucode:
1719 err = -ENODEV;
1720 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1721 goto error;
1722
1723 err_no_pcm:
1724 err = -ENODEV;
1725 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1726 goto error;
1727
1728 err_no_initvals:
1729 err = -ENODEV;
1730 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1731 "core rev %u\n", dev->phy.type, rev);
1732 goto error;
1733
1734 error:
1735 b43_release_firmware(dev);
1736 return err;
1737 }
1738
1739 static int b43_upload_microcode(struct b43_wldev *dev)
1740 {
1741 const size_t hdr_len = sizeof(struct b43_fw_header);
1742 const __be32 *data;
1743 unsigned int i, len;
1744 u16 fwrev, fwpatch, fwdate, fwtime;
1745 u32 tmp;
1746 int err = 0;
1747
1748 /* Upload Microcode. */
1749 data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1750 len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1751 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1752 for (i = 0; i < len; i++) {
1753 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1754 udelay(10);
1755 }
1756
1757 if (dev->fw.pcm) {
1758 /* Upload PCM data. */
1759 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1760 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1761 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1762 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1763 /* No need for autoinc bit in SHM_HW */
1764 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1765 for (i = 0; i < len; i++) {
1766 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1767 udelay(10);
1768 }
1769 }
1770
1771 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1772 b43_write32(dev, B43_MMIO_MACCTL,
1773 B43_MACCTL_PSM_RUN |
1774 B43_MACCTL_IHR_ENABLED | B43_MACCTL_INFRA);
1775
1776 /* Wait for the microcode to load and respond */
1777 i = 0;
1778 while (1) {
1779 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1780 if (tmp == B43_IRQ_MAC_SUSPENDED)
1781 break;
1782 i++;
1783 if (i >= 50) {
1784 b43err(dev->wl, "Microcode not responding\n");
1785 b43_print_fw_helptext(dev->wl);
1786 err = -ENODEV;
1787 goto out;
1788 }
1789 udelay(10);
1790 }
1791 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
1792
1793 /* Get and check the revisions. */
1794 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
1795 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
1796 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
1797 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
1798
1799 if (fwrev <= 0x128) {
1800 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1801 "binary drivers older than version 4.x is unsupported. "
1802 "You must upgrade your firmware files.\n");
1803 b43_print_fw_helptext(dev->wl);
1804 b43_write32(dev, B43_MMIO_MACCTL, 0);
1805 err = -EOPNOTSUPP;
1806 goto out;
1807 }
1808 b43dbg(dev->wl, "Loading firmware version %u.%u "
1809 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1810 fwrev, fwpatch,
1811 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1812 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1813
1814 dev->fw.rev = fwrev;
1815 dev->fw.patch = fwpatch;
1816
1817 out:
1818 return err;
1819 }
1820
1821 static int b43_write_initvals(struct b43_wldev *dev,
1822 const struct b43_iv *ivals,
1823 size_t count,
1824 size_t array_size)
1825 {
1826 const struct b43_iv *iv;
1827 u16 offset;
1828 size_t i;
1829 bool bit32;
1830
1831 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
1832 iv = ivals;
1833 for (i = 0; i < count; i++) {
1834 if (array_size < sizeof(iv->offset_size))
1835 goto err_format;
1836 array_size -= sizeof(iv->offset_size);
1837 offset = be16_to_cpu(iv->offset_size);
1838 bit32 = !!(offset & B43_IV_32BIT);
1839 offset &= B43_IV_OFFSET_MASK;
1840 if (offset >= 0x1000)
1841 goto err_format;
1842 if (bit32) {
1843 u32 value;
1844
1845 if (array_size < sizeof(iv->data.d32))
1846 goto err_format;
1847 array_size -= sizeof(iv->data.d32);
1848
1849 value = be32_to_cpu(get_unaligned(&iv->data.d32));
1850 b43_write32(dev, offset, value);
1851
1852 iv = (const struct b43_iv *)((const uint8_t *)iv +
1853 sizeof(__be16) +
1854 sizeof(__be32));
1855 } else {
1856 u16 value;
1857
1858 if (array_size < sizeof(iv->data.d16))
1859 goto err_format;
1860 array_size -= sizeof(iv->data.d16);
1861
1862 value = be16_to_cpu(iv->data.d16);
1863 b43_write16(dev, offset, value);
1864
1865 iv = (const struct b43_iv *)((const uint8_t *)iv +
1866 sizeof(__be16) +
1867 sizeof(__be16));
1868 }
1869 }
1870 if (array_size)
1871 goto err_format;
1872
1873 return 0;
1874
1875 err_format:
1876 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
1877 b43_print_fw_helptext(dev->wl);
1878
1879 return -EPROTO;
1880 }
1881
1882 static int b43_upload_initvals(struct b43_wldev *dev)
1883 {
1884 const size_t hdr_len = sizeof(struct b43_fw_header);
1885 const struct b43_fw_header *hdr;
1886 struct b43_firmware *fw = &dev->fw;
1887 const struct b43_iv *ivals;
1888 size_t count;
1889 int err;
1890
1891 hdr = (const struct b43_fw_header *)(fw->initvals->data);
1892 ivals = (const struct b43_iv *)(fw->initvals->data + hdr_len);
1893 count = be32_to_cpu(hdr->size);
1894 err = b43_write_initvals(dev, ivals, count,
1895 fw->initvals->size - hdr_len);
1896 if (err)
1897 goto out;
1898 if (fw->initvals_band) {
1899 hdr = (const struct b43_fw_header *)(fw->initvals_band->data);
1900 ivals = (const struct b43_iv *)(fw->initvals_band->data + hdr_len);
1901 count = be32_to_cpu(hdr->size);
1902 err = b43_write_initvals(dev, ivals, count,
1903 fw->initvals_band->size - hdr_len);
1904 if (err)
1905 goto out;
1906 }
1907 out:
1908
1909 return err;
1910 }
1911
1912 /* Initialize the GPIOs
1913 * http://bcm-specs.sipsolutions.net/GPIO
1914 */
1915 static int b43_gpio_init(struct b43_wldev *dev)
1916 {
1917 struct ssb_bus *bus = dev->dev->bus;
1918 struct ssb_device *gpiodev, *pcidev = NULL;
1919 u32 mask, set;
1920
1921 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
1922 & ~B43_MACCTL_GPOUTSMSK);
1923
1924 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
1925 | 0x000F);
1926
1927 mask = 0x0000001F;
1928 set = 0x0000000F;
1929 if (dev->dev->bus->chip_id == 0x4301) {
1930 mask |= 0x0060;
1931 set |= 0x0060;
1932 }
1933 if (0 /* FIXME: conditional unknown */ ) {
1934 b43_write16(dev, B43_MMIO_GPIO_MASK,
1935 b43_read16(dev, B43_MMIO_GPIO_MASK)
1936 | 0x0100);
1937 mask |= 0x0180;
1938 set |= 0x0180;
1939 }
1940 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
1941 b43_write16(dev, B43_MMIO_GPIO_MASK,
1942 b43_read16(dev, B43_MMIO_GPIO_MASK)
1943 | 0x0200);
1944 mask |= 0x0200;
1945 set |= 0x0200;
1946 }
1947 if (dev->dev->id.revision >= 2)
1948 mask |= 0x0010; /* FIXME: This is redundant. */
1949
1950 #ifdef CONFIG_SSB_DRIVER_PCICORE
1951 pcidev = bus->pcicore.dev;
1952 #endif
1953 gpiodev = bus->chipco.dev ? : pcidev;
1954 if (!gpiodev)
1955 return 0;
1956 ssb_write32(gpiodev, B43_GPIO_CONTROL,
1957 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
1958 & mask) | set);
1959
1960 return 0;
1961 }
1962
1963 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1964 static void b43_gpio_cleanup(struct b43_wldev *dev)
1965 {
1966 struct ssb_bus *bus = dev->dev->bus;
1967 struct ssb_device *gpiodev, *pcidev = NULL;
1968
1969 #ifdef CONFIG_SSB_DRIVER_PCICORE
1970 pcidev = bus->pcicore.dev;
1971 #endif
1972 gpiodev = bus->chipco.dev ? : pcidev;
1973 if (!gpiodev)
1974 return;
1975 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
1976 }
1977
1978 /* http://bcm-specs.sipsolutions.net/EnableMac */
1979 void b43_mac_enable(struct b43_wldev *dev)
1980 {
1981 dev->mac_suspended--;
1982 B43_WARN_ON(dev->mac_suspended < 0);
1983 B43_WARN_ON(irqs_disabled());
1984 if (dev->mac_suspended == 0) {
1985 b43_write32(dev, B43_MMIO_MACCTL,
1986 b43_read32(dev, B43_MMIO_MACCTL)
1987 | B43_MACCTL_ENABLED);
1988 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
1989 B43_IRQ_MAC_SUSPENDED);
1990 /* Commit writes */
1991 b43_read32(dev, B43_MMIO_MACCTL);
1992 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1993 b43_power_saving_ctl_bits(dev, 0);
1994
1995 /* Re-enable IRQs. */
1996 spin_lock_irq(&dev->wl->irq_lock);
1997 b43_interrupt_enable(dev, dev->irq_savedstate);
1998 spin_unlock_irq(&dev->wl->irq_lock);
1999 }
2000 }
2001
2002 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2003 void b43_mac_suspend(struct b43_wldev *dev)
2004 {
2005 int i;
2006 u32 tmp;
2007
2008 might_sleep();
2009 B43_WARN_ON(irqs_disabled());
2010 B43_WARN_ON(dev->mac_suspended < 0);
2011
2012 if (dev->mac_suspended == 0) {
2013 /* Mask IRQs before suspending MAC. Otherwise
2014 * the MAC stays busy and won't suspend. */
2015 spin_lock_irq(&dev->wl->irq_lock);
2016 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
2017 spin_unlock_irq(&dev->wl->irq_lock);
2018 b43_synchronize_irq(dev);
2019 dev->irq_savedstate = tmp;
2020
2021 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2022 b43_write32(dev, B43_MMIO_MACCTL,
2023 b43_read32(dev, B43_MMIO_MACCTL)
2024 & ~B43_MACCTL_ENABLED);
2025 /* force pci to flush the write */
2026 b43_read32(dev, B43_MMIO_MACCTL);
2027 for (i = 40; i; i--) {
2028 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2029 if (tmp & B43_IRQ_MAC_SUSPENDED)
2030 goto out;
2031 msleep(1);
2032 }
2033 b43err(dev->wl, "MAC suspend failed\n");
2034 }
2035 out:
2036 dev->mac_suspended++;
2037 }
2038
2039 static void b43_adjust_opmode(struct b43_wldev *dev)
2040 {
2041 struct b43_wl *wl = dev->wl;
2042 u32 ctl;
2043 u16 cfp_pretbtt;
2044
2045 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2046 /* Reset status to STA infrastructure mode. */
2047 ctl &= ~B43_MACCTL_AP;
2048 ctl &= ~B43_MACCTL_KEEP_CTL;
2049 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2050 ctl &= ~B43_MACCTL_KEEP_BAD;
2051 ctl &= ~B43_MACCTL_PROMISC;
2052 ctl &= ~B43_MACCTL_BEACPROMISC;
2053 ctl |= B43_MACCTL_INFRA;
2054
2055 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2056 ctl |= B43_MACCTL_AP;
2057 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2058 ctl &= ~B43_MACCTL_INFRA;
2059
2060 if (wl->filter_flags & FIF_CONTROL)
2061 ctl |= B43_MACCTL_KEEP_CTL;
2062 if (wl->filter_flags & FIF_FCSFAIL)
2063 ctl |= B43_MACCTL_KEEP_BAD;
2064 if (wl->filter_flags & FIF_PLCPFAIL)
2065 ctl |= B43_MACCTL_KEEP_BADPLCP;
2066 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2067 ctl |= B43_MACCTL_PROMISC;
2068 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2069 ctl |= B43_MACCTL_BEACPROMISC;
2070
2071 /* Workaround: On old hardware the HW-MAC-address-filter
2072 * doesn't work properly, so always run promisc in filter
2073 * it in software. */
2074 if (dev->dev->id.revision <= 4)
2075 ctl |= B43_MACCTL_PROMISC;
2076
2077 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2078
2079 cfp_pretbtt = 2;
2080 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2081 if (dev->dev->bus->chip_id == 0x4306 &&
2082 dev->dev->bus->chip_rev == 3)
2083 cfp_pretbtt = 100;
2084 else
2085 cfp_pretbtt = 50;
2086 }
2087 b43_write16(dev, 0x612, cfp_pretbtt);
2088 }
2089
2090 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2091 {
2092 u16 offset;
2093
2094 if (is_ofdm) {
2095 offset = 0x480;
2096 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2097 } else {
2098 offset = 0x4C0;
2099 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2100 }
2101 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2102 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2103 }
2104
2105 static void b43_rate_memory_init(struct b43_wldev *dev)
2106 {
2107 switch (dev->phy.type) {
2108 case B43_PHYTYPE_A:
2109 case B43_PHYTYPE_G:
2110 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2111 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2112 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2113 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2114 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2115 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2116 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2117 if (dev->phy.type == B43_PHYTYPE_A)
2118 break;
2119 /* fallthrough */
2120 case B43_PHYTYPE_B:
2121 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2122 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2123 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2124 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2125 break;
2126 default:
2127 B43_WARN_ON(1);
2128 }
2129 }
2130
2131 /* Set the TX-Antenna for management frames sent by firmware. */
2132 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2133 {
2134 u16 ant = 0;
2135 u16 tmp;
2136
2137 switch (antenna) {
2138 case B43_ANTENNA0:
2139 ant |= B43_TX4_PHY_ANT0;
2140 break;
2141 case B43_ANTENNA1:
2142 ant |= B43_TX4_PHY_ANT1;
2143 break;
2144 case B43_ANTENNA_AUTO:
2145 ant |= B43_TX4_PHY_ANTLAST;
2146 break;
2147 default:
2148 B43_WARN_ON(1);
2149 }
2150
2151 /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2152
2153 /* For Beacons */
2154 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
2155 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2156 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2157 /* For ACK/CTS */
2158 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2159 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2160 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2161 /* For Probe Resposes */
2162 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2163 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2164 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2165 }
2166
2167 /* This is the opposite of b43_chip_init() */
2168 static void b43_chip_exit(struct b43_wldev *dev)
2169 {
2170 b43_radio_turn_off(dev, 1);
2171 b43_gpio_cleanup(dev);
2172 /* firmware is released later */
2173 }
2174
2175 /* Initialize the chip
2176 * http://bcm-specs.sipsolutions.net/ChipInit
2177 */
2178 static int b43_chip_init(struct b43_wldev *dev)
2179 {
2180 struct b43_phy *phy = &dev->phy;
2181 int err, tmp;
2182 u32 value32;
2183 u16 value16;
2184
2185 b43_write32(dev, B43_MMIO_MACCTL,
2186 B43_MACCTL_PSM_JMP0 | B43_MACCTL_IHR_ENABLED);
2187
2188 err = b43_request_firmware(dev);
2189 if (err)
2190 goto out;
2191 err = b43_upload_microcode(dev);
2192 if (err)
2193 goto out; /* firmware is released later */
2194
2195 err = b43_gpio_init(dev);
2196 if (err)
2197 goto out; /* firmware is released later */
2198
2199 err = b43_upload_initvals(dev);
2200 if (err)
2201 goto err_gpio_clean;
2202 b43_radio_turn_on(dev);
2203
2204 b43_write16(dev, 0x03E6, 0x0000);
2205 err = b43_phy_init(dev);
2206 if (err)
2207 goto err_radio_off;
2208
2209 /* Select initial Interference Mitigation. */
2210 tmp = phy->interfmode;
2211 phy->interfmode = B43_INTERFMODE_NONE;
2212 b43_radio_set_interference_mitigation(dev, tmp);
2213
2214 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2215 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2216
2217 if (phy->type == B43_PHYTYPE_B) {
2218 value16 = b43_read16(dev, 0x005E);
2219 value16 |= 0x0004;
2220 b43_write16(dev, 0x005E, value16);
2221 }
2222 b43_write32(dev, 0x0100, 0x01000000);
2223 if (dev->dev->id.revision < 5)
2224 b43_write32(dev, 0x010C, 0x01000000);
2225
2226 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2227 & ~B43_MACCTL_INFRA);
2228 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2229 | B43_MACCTL_INFRA);
2230
2231 /* Probe Response Timeout value */
2232 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2233 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2234
2235 /* Initially set the wireless operation mode. */
2236 b43_adjust_opmode(dev);
2237
2238 if (dev->dev->id.revision < 3) {
2239 b43_write16(dev, 0x060E, 0x0000);
2240 b43_write16(dev, 0x0610, 0x8000);
2241 b43_write16(dev, 0x0604, 0x0000);
2242 b43_write16(dev, 0x0606, 0x0200);
2243 } else {
2244 b43_write32(dev, 0x0188, 0x80000000);
2245 b43_write32(dev, 0x018C, 0x02000000);
2246 }
2247 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2248 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2249 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2250 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2251 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2252 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2253 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2254
2255 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2256 value32 |= 0x00100000;
2257 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2258
2259 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2260 dev->dev->bus->chipco.fast_pwrup_delay);
2261
2262 err = 0;
2263 b43dbg(dev->wl, "Chip initialized\n");
2264 out:
2265 return err;
2266
2267 err_radio_off:
2268 b43_radio_turn_off(dev, 1);
2269 err_gpio_clean:
2270 b43_gpio_cleanup(dev);
2271 return err;
2272 }
2273
2274 static void b43_periodic_every120sec(struct b43_wldev *dev)
2275 {
2276 struct b43_phy *phy = &dev->phy;
2277
2278 if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2279 return;
2280
2281 b43_mac_suspend(dev);
2282 b43_lo_g_measure(dev);
2283 b43_mac_enable(dev);
2284 if (b43_has_hardware_pctl(phy))
2285 b43_lo_g_ctl_mark_all_unused(dev);
2286 }
2287
2288 static void b43_periodic_every60sec(struct b43_wldev *dev)
2289 {
2290 struct b43_phy *phy = &dev->phy;
2291
2292 if (!b43_has_hardware_pctl(phy))
2293 b43_lo_g_ctl_mark_all_unused(dev);
2294 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
2295 b43_mac_suspend(dev);
2296 b43_calc_nrssi_slope(dev);
2297 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2298 u8 old_chan = phy->channel;
2299
2300 /* VCO Calibration */
2301 if (old_chan >= 8)
2302 b43_radio_selectchannel(dev, 1, 0);
2303 else
2304 b43_radio_selectchannel(dev, 13, 0);
2305 b43_radio_selectchannel(dev, old_chan, 0);
2306 }
2307 b43_mac_enable(dev);
2308 }
2309 }
2310
2311 static void b43_periodic_every30sec(struct b43_wldev *dev)
2312 {
2313 /* Update device statistics. */
2314 b43_calculate_link_quality(dev);
2315 }
2316
2317 static void b43_periodic_every15sec(struct b43_wldev *dev)
2318 {
2319 struct b43_phy *phy = &dev->phy;
2320
2321 if (phy->type == B43_PHYTYPE_G) {
2322 //TODO: update_aci_moving_average
2323 if (phy->aci_enable && phy->aci_wlan_automatic) {
2324 b43_mac_suspend(dev);
2325 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2326 if (0 /*TODO: bunch of conditions */ ) {
2327 b43_radio_set_interference_mitigation
2328 (dev, B43_INTERFMODE_MANUALWLAN);
2329 }
2330 } else if (1 /*TODO*/) {
2331 /*
2332 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2333 b43_radio_set_interference_mitigation(dev,
2334 B43_INTERFMODE_NONE);
2335 }
2336 */
2337 }
2338 b43_mac_enable(dev);
2339 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2340 phy->rev == 1) {
2341 //TODO: implement rev1 workaround
2342 }
2343 }
2344 b43_phy_xmitpower(dev); //FIXME: unless scanning?
2345 //TODO for APHY (temperature?)
2346
2347 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2348 wmb();
2349 }
2350
2351 static void do_periodic_work(struct b43_wldev *dev)
2352 {
2353 unsigned int state;
2354
2355 state = dev->periodic_state;
2356 if (state % 8 == 0)
2357 b43_periodic_every120sec(dev);
2358 if (state % 4 == 0)
2359 b43_periodic_every60sec(dev);
2360 if (state % 2 == 0)
2361 b43_periodic_every30sec(dev);
2362 b43_periodic_every15sec(dev);
2363 }
2364
2365 /* Periodic work locking policy:
2366 * The whole periodic work handler is protected by
2367 * wl->mutex. If another lock is needed somewhere in the
2368 * pwork callchain, it's aquired in-place, where it's needed.
2369 */
2370 static void b43_periodic_work_handler(struct work_struct *work)
2371 {
2372 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2373 periodic_work.work);
2374 struct b43_wl *wl = dev->wl;
2375 unsigned long delay;
2376
2377 mutex_lock(&wl->mutex);
2378
2379 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2380 goto out;
2381 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2382 goto out_requeue;
2383
2384 do_periodic_work(dev);
2385
2386 dev->periodic_state++;
2387 out_requeue:
2388 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2389 delay = msecs_to_jiffies(50);
2390 else
2391 delay = round_jiffies_relative(HZ * 15);
2392 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2393 out:
2394 mutex_unlock(&wl->mutex);
2395 }
2396
2397 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2398 {
2399 struct delayed_work *work = &dev->periodic_work;
2400
2401 dev->periodic_state = 0;
2402 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2403 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2404 }
2405
2406 /* Check if communication with the device works correctly. */
2407 static int b43_validate_chipaccess(struct b43_wldev *dev)
2408 {
2409 u32 v, backup;
2410
2411 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2412
2413 /* Check for read/write and endianness problems. */
2414 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2415 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2416 goto error;
2417 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2418 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2419 goto error;
2420
2421 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2422
2423 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2424 /* The 32bit register shadows the two 16bit registers
2425 * with update sideeffects. Validate this. */
2426 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2427 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2428 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2429 goto error;
2430 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2431 goto error;
2432 }
2433 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2434
2435 v = b43_read32(dev, B43_MMIO_MACCTL);
2436 v |= B43_MACCTL_GMODE;
2437 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2438 goto error;
2439
2440 return 0;
2441 error:
2442 b43err(dev->wl, "Failed to validate the chipaccess\n");
2443 return -ENODEV;
2444 }
2445
2446 static void b43_security_init(struct b43_wldev *dev)
2447 {
2448 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2449 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2450 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2451 /* KTP is a word address, but we address SHM bytewise.
2452 * So multiply by two.
2453 */
2454 dev->ktp *= 2;
2455 if (dev->dev->id.revision >= 5) {
2456 /* Number of RCMTA address slots */
2457 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2458 }
2459 b43_clear_keys(dev);
2460 }
2461
2462 static int b43_rng_read(struct hwrng *rng, u32 * data)
2463 {
2464 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2465 unsigned long flags;
2466
2467 /* Don't take wl->mutex here, as it could deadlock with
2468 * hwrng internal locking. It's not needed to take
2469 * wl->mutex here, anyway. */
2470
2471 spin_lock_irqsave(&wl->irq_lock, flags);
2472 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2473 spin_unlock_irqrestore(&wl->irq_lock, flags);
2474
2475 return (sizeof(u16));
2476 }
2477
2478 static void b43_rng_exit(struct b43_wl *wl)
2479 {
2480 if (wl->rng_initialized)
2481 hwrng_unregister(&wl->rng);
2482 }
2483
2484 static int b43_rng_init(struct b43_wl *wl)
2485 {
2486 int err;
2487
2488 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2489 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2490 wl->rng.name = wl->rng_name;
2491 wl->rng.data_read = b43_rng_read;
2492 wl->rng.priv = (unsigned long)wl;
2493 wl->rng_initialized = 1;
2494 err = hwrng_register(&wl->rng);
2495 if (err) {
2496 wl->rng_initialized = 0;
2497 b43err(wl, "Failed to register the random "
2498 "number generator (%d)\n", err);
2499 }
2500
2501 return err;
2502 }
2503
2504 static int b43_op_tx(struct ieee80211_hw *hw,
2505 struct sk_buff *skb,
2506 struct ieee80211_tx_control *ctl)
2507 {
2508 struct b43_wl *wl = hw_to_b43_wl(hw);
2509 struct b43_wldev *dev = wl->current_dev;
2510 int err = -ENODEV;
2511
2512 if (unlikely(!dev))
2513 goto out;
2514 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2515 goto out;
2516 /* DMA-TX is done without a global lock. */
2517 err = b43_dma_tx(dev, skb, ctl);
2518 out:
2519 if (unlikely(err))
2520 return NETDEV_TX_BUSY;
2521 return NETDEV_TX_OK;
2522 }
2523
2524 static int b43_op_conf_tx(struct ieee80211_hw *hw,
2525 int queue,
2526 const struct ieee80211_tx_queue_params *params)
2527 {
2528 return 0;
2529 }
2530
2531 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
2532 struct ieee80211_tx_queue_stats *stats)
2533 {
2534 struct b43_wl *wl = hw_to_b43_wl(hw);
2535 struct b43_wldev *dev = wl->current_dev;
2536 unsigned long flags;
2537 int err = -ENODEV;
2538
2539 if (!dev)
2540 goto out;
2541 spin_lock_irqsave(&wl->irq_lock, flags);
2542 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2543 b43_dma_get_tx_stats(dev, stats);
2544 err = 0;
2545 }
2546 spin_unlock_irqrestore(&wl->irq_lock, flags);
2547 out:
2548 return err;
2549 }
2550
2551 static int b43_op_get_stats(struct ieee80211_hw *hw,
2552 struct ieee80211_low_level_stats *stats)
2553 {
2554 struct b43_wl *wl = hw_to_b43_wl(hw);
2555 unsigned long flags;
2556
2557 spin_lock_irqsave(&wl->irq_lock, flags);
2558 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2559 spin_unlock_irqrestore(&wl->irq_lock, flags);
2560
2561 return 0;
2562 }
2563
2564 static const char *phymode_to_string(unsigned int phymode)
2565 {
2566 switch (phymode) {
2567 case B43_PHYMODE_A:
2568 return "A";
2569 case B43_PHYMODE_B:
2570 return "B";
2571 case B43_PHYMODE_G:
2572 return "G";
2573 default:
2574 B43_WARN_ON(1);
2575 }
2576 return "";
2577 }
2578
2579 static int find_wldev_for_phymode(struct b43_wl *wl,
2580 unsigned int phymode,
2581 struct b43_wldev **dev, bool * gmode)
2582 {
2583 struct b43_wldev *d;
2584
2585 list_for_each_entry(d, &wl->devlist, list) {
2586 if (d->phy.possible_phymodes & phymode) {
2587 /* Ok, this device supports the PHY-mode.
2588 * Now figure out how the gmode bit has to be
2589 * set to support it. */
2590 if (phymode == B43_PHYMODE_A)
2591 *gmode = 0;
2592 else
2593 *gmode = 1;
2594 *dev = d;
2595
2596 return 0;
2597 }
2598 }
2599
2600 return -ESRCH;
2601 }
2602
2603 static void b43_put_phy_into_reset(struct b43_wldev *dev)
2604 {
2605 struct ssb_device *sdev = dev->dev;
2606 u32 tmslow;
2607
2608 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2609 tmslow &= ~B43_TMSLOW_GMODE;
2610 tmslow |= B43_TMSLOW_PHYRESET;
2611 tmslow |= SSB_TMSLOW_FGC;
2612 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2613 msleep(1);
2614
2615 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2616 tmslow &= ~SSB_TMSLOW_FGC;
2617 tmslow |= B43_TMSLOW_PHYRESET;
2618 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2619 msleep(1);
2620 }
2621
2622 /* Expects wl->mutex locked */
2623 static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode)
2624 {
2625 struct b43_wldev *up_dev;
2626 struct b43_wldev *down_dev;
2627 int err;
2628 bool gmode = 0;
2629 int prev_status;
2630
2631 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2632 if (err) {
2633 b43err(wl, "Could not find a device for %s-PHY mode\n",
2634 phymode_to_string(new_mode));
2635 return err;
2636 }
2637 if ((up_dev == wl->current_dev) &&
2638 (!!wl->current_dev->phy.gmode == !!gmode)) {
2639 /* This device is already running. */
2640 return 0;
2641 }
2642 b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2643 phymode_to_string(new_mode));
2644 down_dev = wl->current_dev;
2645
2646 prev_status = b43_status(down_dev);
2647 /* Shutdown the currently running core. */
2648 if (prev_status >= B43_STAT_STARTED)
2649 b43_wireless_core_stop(down_dev);
2650 if (prev_status >= B43_STAT_INITIALIZED)
2651 b43_wireless_core_exit(down_dev);
2652
2653 if (down_dev != up_dev) {
2654 /* We switch to a different core, so we put PHY into
2655 * RESET on the old core. */
2656 b43_put_phy_into_reset(down_dev);
2657 }
2658
2659 /* Now start the new core. */
2660 up_dev->phy.gmode = gmode;
2661 if (prev_status >= B43_STAT_INITIALIZED) {
2662 err = b43_wireless_core_init(up_dev);
2663 if (err) {
2664 b43err(wl, "Fatal: Could not initialize device for "
2665 "newly selected %s-PHY mode\n",
2666 phymode_to_string(new_mode));
2667 goto init_failure;
2668 }
2669 }
2670 if (prev_status >= B43_STAT_STARTED) {
2671 err = b43_wireless_core_start(up_dev);
2672 if (err) {
2673 b43err(wl, "Fatal: Coult not start device for "
2674 "newly selected %s-PHY mode\n",
2675 phymode_to_string(new_mode));
2676 b43_wireless_core_exit(up_dev);
2677 goto init_failure;
2678 }
2679 }
2680 B43_WARN_ON(b43_status(up_dev) != prev_status);
2681
2682 wl->current_dev = up_dev;
2683
2684 return 0;
2685 init_failure:
2686 /* Whoops, failed to init the new core. No core is operating now. */
2687 wl->current_dev = NULL;
2688 return err;
2689 }
2690
2691 /* Check if the use of the antenna that ieee80211 told us to
2692 * use is possible. This will fall back to DEFAULT.
2693 * "antenna_nr" is the antenna identifier we got from ieee80211. */
2694 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
2695 u8 antenna_nr)
2696 {
2697 u8 antenna_mask;
2698
2699 if (antenna_nr == 0) {
2700 /* Zero means "use default antenna". That's always OK. */
2701 return 0;
2702 }
2703
2704 /* Get the mask of available antennas. */
2705 if (dev->phy.gmode)
2706 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
2707 else
2708 antenna_mask = dev->dev->bus->sprom.ant_available_a;
2709
2710 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
2711 /* This antenna is not available. Fall back to default. */
2712 return 0;
2713 }
2714
2715 return antenna_nr;
2716 }
2717
2718 static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
2719 {
2720 antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
2721 switch (antenna) {
2722 case 0: /* default/diversity */
2723 return B43_ANTENNA_DEFAULT;
2724 case 1: /* Antenna 0 */
2725 return B43_ANTENNA0;
2726 case 2: /* Antenna 1 */
2727 return B43_ANTENNA1;
2728 default:
2729 return B43_ANTENNA_DEFAULT;
2730 }
2731 }
2732
2733 static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
2734 {
2735 struct b43_wl *wl = hw_to_b43_wl(hw);
2736 struct b43_wldev *dev;
2737 struct b43_phy *phy;
2738 unsigned long flags;
2739 unsigned int new_phymode = 0xFFFF;
2740 int antenna;
2741 int err = 0;
2742 u32 savedirqs;
2743
2744 mutex_lock(&wl->mutex);
2745
2746 /* Switch the PHY mode (if necessary). */
2747 switch (conf->phymode) {
2748 case MODE_IEEE80211A:
2749 new_phymode = B43_PHYMODE_A;
2750 break;
2751 case MODE_IEEE80211B:
2752 new_phymode = B43_PHYMODE_B;
2753 break;
2754 case MODE_IEEE80211G:
2755 new_phymode = B43_PHYMODE_G;
2756 break;
2757 default:
2758 B43_WARN_ON(1);
2759 }
2760 err = b43_switch_phymode(wl, new_phymode);
2761 if (err)
2762 goto out_unlock_mutex;
2763 dev = wl->current_dev;
2764 phy = &dev->phy;
2765
2766 /* Disable IRQs while reconfiguring the device.
2767 * This makes it possible to drop the spinlock throughout
2768 * the reconfiguration process. */
2769 spin_lock_irqsave(&wl->irq_lock, flags);
2770 if (b43_status(dev) < B43_STAT_STARTED) {
2771 spin_unlock_irqrestore(&wl->irq_lock, flags);
2772 goto out_unlock_mutex;
2773 }
2774 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2775 spin_unlock_irqrestore(&wl->irq_lock, flags);
2776 b43_synchronize_irq(dev);
2777
2778 /* Switch to the requested channel.
2779 * The firmware takes care of races with the TX handler. */
2780 if (conf->channel_val != phy->channel)
2781 b43_radio_selectchannel(dev, conf->channel_val, 0);
2782
2783 /* Enable/Disable ShortSlot timing. */
2784 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
2785 dev->short_slot) {
2786 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2787 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2788 b43_short_slot_timing_enable(dev);
2789 else
2790 b43_short_slot_timing_disable(dev);
2791 }
2792
2793 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
2794
2795 /* Adjust the desired TX power level. */
2796 if (conf->power_level != 0) {
2797 if (conf->power_level != phy->power_level) {
2798 phy->power_level = conf->power_level;
2799 b43_phy_xmitpower(dev);
2800 }
2801 }
2802
2803 /* Antennas for RX and management frame TX. */
2804 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
2805 b43_mgmtframe_txantenna(dev, antenna);
2806 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
2807 b43_set_rx_antenna(dev, antenna);
2808
2809 /* Update templates for AP mode. */
2810 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2811 b43_set_beacon_int(dev, conf->beacon_int);
2812
2813 if (!!conf->radio_enabled != phy->radio_on) {
2814 if (conf->radio_enabled) {
2815 b43_radio_turn_on(dev);
2816 b43info(dev->wl, "Radio turned on by software\n");
2817 if (!dev->radio_hw_enable) {
2818 b43info(dev->wl, "The hardware RF-kill button "
2819 "still turns the radio physically off. "
2820 "Press the button to turn it on.\n");
2821 }
2822 } else {
2823 b43_radio_turn_off(dev, 0);
2824 b43info(dev->wl, "Radio turned off by software\n");
2825 }
2826 }
2827
2828 spin_lock_irqsave(&wl->irq_lock, flags);
2829 b43_interrupt_enable(dev, savedirqs);
2830 mmiowb();
2831 spin_unlock_irqrestore(&wl->irq_lock, flags);
2832 out_unlock_mutex:
2833 mutex_unlock(&wl->mutex);
2834
2835 return err;
2836 }
2837
2838 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2839 const u8 *local_addr, const u8 *addr,
2840 struct ieee80211_key_conf *key)
2841 {
2842 struct b43_wl *wl = hw_to_b43_wl(hw);
2843 struct b43_wldev *dev;
2844 unsigned long flags;
2845 u8 algorithm;
2846 u8 index;
2847 int err;
2848 DECLARE_MAC_BUF(mac);
2849
2850 if (modparam_nohwcrypt)
2851 return -ENOSPC; /* User disabled HW-crypto */
2852
2853 mutex_lock(&wl->mutex);
2854 spin_lock_irqsave(&wl->irq_lock, flags);
2855
2856 dev = wl->current_dev;
2857 err = -ENODEV;
2858 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
2859 goto out_unlock;
2860
2861 err = -EINVAL;
2862 switch (key->alg) {
2863 case ALG_WEP:
2864 if (key->keylen == 5)
2865 algorithm = B43_SEC_ALGO_WEP40;
2866 else
2867 algorithm = B43_SEC_ALGO_WEP104;
2868 break;
2869 case ALG_TKIP:
2870 algorithm = B43_SEC_ALGO_TKIP;
2871 break;
2872 case ALG_CCMP:
2873 algorithm = B43_SEC_ALGO_AES;
2874 break;
2875 default:
2876 B43_WARN_ON(1);
2877 goto out_unlock;
2878 }
2879 index = (u8) (key->keyidx);
2880 if (index > 3)
2881 goto out_unlock;
2882
2883 switch (cmd) {
2884 case SET_KEY:
2885 if (algorithm == B43_SEC_ALGO_TKIP) {
2886 /* FIXME: No TKIP hardware encryption for now. */
2887 err = -EOPNOTSUPP;
2888 goto out_unlock;
2889 }
2890
2891 if (is_broadcast_ether_addr(addr)) {
2892 /* addr is FF:FF:FF:FF:FF:FF for default keys */
2893 err = b43_key_write(dev, index, algorithm,
2894 key->key, key->keylen, NULL, key);
2895 } else {
2896 /*
2897 * either pairwise key or address is 00:00:00:00:00:00
2898 * for transmit-only keys
2899 */
2900 err = b43_key_write(dev, -1, algorithm,
2901 key->key, key->keylen, addr, key);
2902 }
2903 if (err)
2904 goto out_unlock;
2905
2906 if (algorithm == B43_SEC_ALGO_WEP40 ||
2907 algorithm == B43_SEC_ALGO_WEP104) {
2908 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
2909 } else {
2910 b43_hf_write(dev,
2911 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
2912 }
2913 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2914 break;
2915 case DISABLE_KEY: {
2916 err = b43_key_clear(dev, key->hw_key_idx);
2917 if (err)
2918 goto out_unlock;
2919 break;
2920 }
2921 default:
2922 B43_WARN_ON(1);
2923 }
2924 out_unlock:
2925 spin_unlock_irqrestore(&wl->irq_lock, flags);
2926 mutex_unlock(&wl->mutex);
2927 if (!err) {
2928 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
2929 "mac: %s\n",
2930 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
2931 print_mac(mac, addr));
2932 }
2933 return err;
2934 }
2935
2936 static void b43_op_configure_filter(struct ieee80211_hw *hw,
2937 unsigned int changed, unsigned int *fflags,
2938 int mc_count, struct dev_addr_list *mc_list)
2939 {
2940 struct b43_wl *wl = hw_to_b43_wl(hw);
2941 struct b43_wldev *dev = wl->current_dev;
2942 unsigned long flags;
2943
2944 if (!dev) {
2945 *fflags = 0;
2946 return;
2947 }
2948
2949 spin_lock_irqsave(&wl->irq_lock, flags);
2950 *fflags &= FIF_PROMISC_IN_BSS |
2951 FIF_ALLMULTI |
2952 FIF_FCSFAIL |
2953 FIF_PLCPFAIL |
2954 FIF_CONTROL |
2955 FIF_OTHER_BSS |
2956 FIF_BCN_PRBRESP_PROMISC;
2957
2958 changed &= FIF_PROMISC_IN_BSS |
2959 FIF_ALLMULTI |
2960 FIF_FCSFAIL |
2961 FIF_PLCPFAIL |
2962 FIF_CONTROL |
2963 FIF_OTHER_BSS |
2964 FIF_BCN_PRBRESP_PROMISC;
2965
2966 wl->filter_flags = *fflags;
2967
2968 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
2969 b43_adjust_opmode(dev);
2970 spin_unlock_irqrestore(&wl->irq_lock, flags);
2971 }
2972
2973 static int b43_op_config_interface(struct ieee80211_hw *hw,
2974 struct ieee80211_vif *vif,
2975 struct ieee80211_if_conf *conf)
2976 {
2977 struct b43_wl *wl = hw_to_b43_wl(hw);
2978 struct b43_wldev *dev = wl->current_dev;
2979 unsigned long flags;
2980
2981 if (!dev)
2982 return -ENODEV;
2983 mutex_lock(&wl->mutex);
2984 spin_lock_irqsave(&wl->irq_lock, flags);
2985 B43_WARN_ON(wl->vif != vif);
2986 if (conf->bssid)
2987 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2988 else
2989 memset(wl->bssid, 0, ETH_ALEN);
2990 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
2991 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
2992 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
2993 b43_set_ssid(dev, conf->ssid, conf->ssid_len);
2994 if (conf->beacon)
2995 b43_update_templates(wl, conf->beacon);
2996 }
2997 b43_write_mac_bssid_templates(dev);
2998 }
2999 spin_unlock_irqrestore(&wl->irq_lock, flags);
3000 mutex_unlock(&wl->mutex);
3001
3002 return 0;
3003 }
3004
3005 /* Locking: wl->mutex */
3006 static void b43_wireless_core_stop(struct b43_wldev *dev)
3007 {
3008 struct b43_wl *wl = dev->wl;
3009 unsigned long flags;
3010
3011 if (b43_status(dev) < B43_STAT_STARTED)
3012 return;
3013
3014 /* Disable and sync interrupts. We must do this before than
3015 * setting the status to INITIALIZED, as the interrupt handler
3016 * won't care about IRQs then. */
3017 spin_lock_irqsave(&wl->irq_lock, flags);
3018 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3019 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3020 spin_unlock_irqrestore(&wl->irq_lock, flags);
3021 b43_synchronize_irq(dev);
3022
3023 b43_set_status(dev, B43_STAT_INITIALIZED);
3024
3025 mutex_unlock(&wl->mutex);
3026 /* Must unlock as it would otherwise deadlock. No races here.
3027 * Cancel the possibly running self-rearming periodic work. */
3028 cancel_delayed_work_sync(&dev->periodic_work);
3029 mutex_lock(&wl->mutex);
3030
3031 ieee80211_stop_queues(wl->hw); //FIXME this could cause a deadlock, as mac80211 seems buggy.
3032
3033 b43_mac_suspend(dev);
3034 free_irq(dev->dev->irq, dev);
3035 b43dbg(wl, "Wireless interface stopped\n");
3036 }
3037
3038 /* Locking: wl->mutex */
3039 static int b43_wireless_core_start(struct b43_wldev *dev)
3040 {
3041 int err;
3042
3043 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3044
3045 drain_txstatus_queue(dev);
3046 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3047 IRQF_SHARED, KBUILD_MODNAME, dev);
3048 if (err) {
3049 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3050 goto out;
3051 }
3052
3053 /* We are ready to run. */
3054 b43_set_status(dev, B43_STAT_STARTED);
3055
3056 /* Start data flow (TX/RX). */
3057 b43_mac_enable(dev);
3058 b43_interrupt_enable(dev, dev->irq_savedstate);
3059 ieee80211_start_queues(dev->wl->hw);
3060
3061 /* Start maintainance work */
3062 b43_periodic_tasks_setup(dev);
3063
3064 b43dbg(dev->wl, "Wireless interface started\n");
3065 out:
3066 return err;
3067 }
3068
3069 /* Get PHY and RADIO versioning numbers */
3070 static int b43_phy_versioning(struct b43_wldev *dev)
3071 {
3072 struct b43_phy *phy = &dev->phy;
3073 u32 tmp;
3074 u8 analog_type;
3075 u8 phy_type;
3076 u8 phy_rev;
3077 u16 radio_manuf;
3078 u16 radio_ver;
3079 u16 radio_rev;
3080 int unsupported = 0;
3081
3082 /* Get PHY versioning */
3083 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3084 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3085 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3086 phy_rev = (tmp & B43_PHYVER_VERSION);
3087 switch (phy_type) {
3088 case B43_PHYTYPE_A:
3089 if (phy_rev >= 4)
3090 unsupported = 1;
3091 break;
3092 case B43_PHYTYPE_B:
3093 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3094 && phy_rev != 7)
3095 unsupported = 1;
3096 break;
3097 case B43_PHYTYPE_G:
3098 if (phy_rev > 9)
3099 unsupported = 1;
3100 break;
3101 #ifdef CONFIG_B43_NPHY
3102 case B43_PHYTYPE_N:
3103 if (phy_rev > 1)
3104 unsupported = 1;
3105 break;
3106 #endif
3107 default:
3108 unsupported = 1;
3109 };
3110 if (unsupported) {
3111 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3112 "(Analog %u, Type %u, Revision %u)\n",
3113 analog_type, phy_type, phy_rev);
3114 return -EOPNOTSUPP;
3115 }
3116 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3117 analog_type, phy_type, phy_rev);
3118
3119 /* Get RADIO versioning */
3120 if (dev->dev->bus->chip_id == 0x4317) {
3121 if (dev->dev->bus->chip_rev == 0)
3122 tmp = 0x3205017F;
3123 else if (dev->dev->bus->chip_rev == 1)
3124 tmp = 0x4205017F;
3125 else
3126 tmp = 0x5205017F;
3127 } else {
3128 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3129 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH);
3130 tmp <<= 16;
3131 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3132 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3133 }
3134 radio_manuf = (tmp & 0x00000FFF);
3135 radio_ver = (tmp & 0x0FFFF000) >> 12;
3136 radio_rev = (tmp & 0xF0000000) >> 28;
3137 if (radio_manuf != 0x17F /* Broadcom */)
3138 unsupported = 1;
3139 switch (phy_type) {
3140 case B43_PHYTYPE_A:
3141 if (radio_ver != 0x2060)
3142 unsupported = 1;
3143 if (radio_rev != 1)
3144 unsupported = 1;
3145 if (radio_manuf != 0x17F)
3146 unsupported = 1;
3147 break;
3148 case B43_PHYTYPE_B:
3149 if ((radio_ver & 0xFFF0) != 0x2050)
3150 unsupported = 1;
3151 break;
3152 case B43_PHYTYPE_G:
3153 if (radio_ver != 0x2050)
3154 unsupported = 1;
3155 break;
3156 case B43_PHYTYPE_N:
3157 if (radio_ver != 5)
3158 unsupported = 1;
3159 break;
3160 default:
3161 B43_WARN_ON(1);
3162 }
3163 if (unsupported) {
3164 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3165 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3166 radio_manuf, radio_ver, radio_rev);
3167 return -EOPNOTSUPP;
3168 }
3169 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3170 radio_manuf, radio_ver, radio_rev);
3171
3172 phy->radio_manuf = radio_manuf;
3173 phy->radio_ver = radio_ver;
3174 phy->radio_rev = radio_rev;
3175
3176 phy->analog = analog_type;
3177 phy->type = phy_type;
3178 phy->rev = phy_rev;
3179
3180 return 0;
3181 }
3182
3183 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3184 struct b43_phy *phy)
3185 {
3186 struct b43_txpower_lo_control *lo;
3187 int i;
3188
3189 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3190 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3191
3192 phy->aci_enable = 0;
3193 phy->aci_wlan_automatic = 0;
3194 phy->aci_hw_rssi = 0;
3195
3196 phy->radio_off_context.valid = 0;
3197
3198 lo = phy->lo_control;
3199 if (lo) {
3200 memset(lo, 0, sizeof(*(phy->lo_control)));
3201 lo->rebuild = 1;
3202 lo->tx_bias = 0xFF;
3203 }
3204 phy->max_lb_gain = 0;
3205 phy->trsw_rx_gain = 0;
3206 phy->txpwr_offset = 0;
3207
3208 /* NRSSI */
3209 phy->nrssislope = 0;
3210 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3211 phy->nrssi[i] = -1000;
3212 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3213 phy->nrssi_lt[i] = i;
3214
3215 phy->lofcal = 0xFFFF;
3216 phy->initval = 0xFFFF;
3217
3218 phy->interfmode = B43_INTERFMODE_NONE;
3219 phy->channel = 0xFF;
3220
3221 phy->hardware_power_control = !!modparam_hwpctl;
3222
3223 /* PHY TX errors counter. */
3224 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3225
3226 /* OFDM-table address caching. */
3227 phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
3228 }
3229
3230 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3231 {
3232 dev->dfq_valid = 0;
3233
3234 /* Assume the radio is enabled. If it's not enabled, the state will
3235 * immediately get fixed on the first periodic work run. */
3236 dev->radio_hw_enable = 1;
3237
3238 /* Stats */
3239 memset(&dev->stats, 0, sizeof(dev->stats));
3240
3241 setup_struct_phy_for_init(dev, &dev->phy);
3242
3243 /* IRQ related flags */
3244 dev->irq_reason = 0;
3245 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3246 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3247
3248 dev->mac_suspended = 1;
3249
3250 /* Noise calculation context */
3251 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3252 }
3253
3254 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3255 {
3256 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3257 u32 hf;
3258
3259 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
3260 return;
3261 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3262 return;
3263
3264 hf = b43_hf_read(dev);
3265 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
3266 hf |= B43_HF_BTCOEXALT;
3267 else
3268 hf |= B43_HF_BTCOEX;
3269 b43_hf_write(dev, hf);
3270 //TODO
3271 }
3272
3273 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3274 { //TODO
3275 }
3276
3277 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3278 {
3279 #ifdef CONFIG_SSB_DRIVER_PCICORE
3280 struct ssb_bus *bus = dev->dev->bus;
3281 u32 tmp;
3282
3283 if (bus->pcicore.dev &&
3284 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3285 bus->pcicore.dev->id.revision <= 5) {
3286 /* IMCFGLO timeouts workaround. */
3287 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3288 tmp &= ~SSB_IMCFGLO_REQTO;
3289 tmp &= ~SSB_IMCFGLO_SERTO;
3290 switch (bus->bustype) {
3291 case SSB_BUSTYPE_PCI:
3292 case SSB_BUSTYPE_PCMCIA:
3293 tmp |= 0x32;
3294 break;
3295 case SSB_BUSTYPE_SSB:
3296 tmp |= 0x53;
3297 break;
3298 }
3299 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3300 }
3301 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3302 }
3303
3304 /* Write the short and long frame retry limit values. */
3305 static void b43_set_retry_limits(struct b43_wldev *dev,
3306 unsigned int short_retry,
3307 unsigned int long_retry)
3308 {
3309 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3310 * the chip-internal counter. */
3311 short_retry = min(short_retry, (unsigned int)0xF);
3312 long_retry = min(long_retry, (unsigned int)0xF);
3313
3314 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3315 short_retry);
3316 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3317 long_retry);
3318 }
3319
3320 /* Shutdown a wireless core */
3321 /* Locking: wl->mutex */
3322 static void b43_wireless_core_exit(struct b43_wldev *dev)
3323 {
3324 struct b43_phy *phy = &dev->phy;
3325
3326 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3327 if (b43_status(dev) != B43_STAT_INITIALIZED)
3328 return;
3329 b43_set_status(dev, B43_STAT_UNINIT);
3330
3331 b43_leds_exit(dev);
3332 b43_rng_exit(dev->wl);
3333 b43_dma_free(dev);
3334 b43_chip_exit(dev);
3335 b43_radio_turn_off(dev, 1);
3336 b43_switch_analog(dev, 0);
3337 if (phy->dyn_tssi_tbl)
3338 kfree(phy->tssi2dbm);
3339 kfree(phy->lo_control);
3340 phy->lo_control = NULL;
3341 if (dev->wl->current_beacon) {
3342 dev_kfree_skb_any(dev->wl->current_beacon);
3343 dev->wl->current_beacon = NULL;
3344 }
3345
3346 ssb_device_disable(dev->dev, 0);
3347 ssb_bus_may_powerdown(dev->dev->bus);
3348 }
3349
3350 /* Initialize a wireless core */
3351 static int b43_wireless_core_init(struct b43_wldev *dev)
3352 {
3353 struct b43_wl *wl = dev->wl;
3354 struct ssb_bus *bus = dev->dev->bus;
3355 struct ssb_sprom *sprom = &bus->sprom;
3356 struct b43_phy *phy = &dev->phy;
3357 int err;
3358 u32 hf, tmp;
3359
3360 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3361
3362 err = ssb_bus_powerup(bus, 0);
3363 if (err)
3364 goto out;
3365 if (!ssb_device_is_enabled(dev->dev)) {
3366 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3367 b43_wireless_core_reset(dev, tmp);
3368 }
3369
3370 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3371 phy->lo_control =
3372 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3373 if (!phy->lo_control) {
3374 err = -ENOMEM;
3375 goto err_busdown;
3376 }
3377 }
3378 setup_struct_wldev_for_init(dev);
3379
3380 err = b43_phy_init_tssi2dbm_table(dev);
3381 if (err)
3382 goto err_kfree_lo_control;
3383
3384 /* Enable IRQ routing to this device. */
3385 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3386
3387 b43_imcfglo_timeouts_workaround(dev);
3388 b43_bluetooth_coext_disable(dev);
3389 b43_phy_early_init(dev);
3390 err = b43_chip_init(dev);
3391 if (err)
3392 goto err_kfree_tssitbl;
3393 b43_shm_write16(dev, B43_SHM_SHARED,
3394 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3395 hf = b43_hf_read(dev);
3396 if (phy->type == B43_PHYTYPE_G) {
3397 hf |= B43_HF_SYMW;
3398 if (phy->rev == 1)
3399 hf |= B43_HF_GDCW;
3400 if (sprom->boardflags_lo & B43_BFL_PACTRL)
3401 hf |= B43_HF_OFDMPABOOST;
3402 } else if (phy->type == B43_PHYTYPE_B) {
3403 hf |= B43_HF_SYMW;
3404 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3405 hf &= ~B43_HF_GDCW;
3406 }
3407 b43_hf_write(dev, hf);
3408
3409 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
3410 B43_DEFAULT_LONG_RETRY_LIMIT);
3411 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3412 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3413
3414 /* Disable sending probe responses from firmware.
3415 * Setting the MaxTime to one usec will always trigger
3416 * a timeout, so we never send any probe resp.
3417 * A timeout of zero is infinite. */
3418 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3419
3420 b43_rate_memory_init(dev);
3421
3422 /* Minimum Contention Window */
3423 if (phy->type == B43_PHYTYPE_B) {
3424 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3425 } else {
3426 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3427 }
3428 /* Maximum Contention Window */
3429 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3430
3431 err = b43_dma_init(dev);
3432 if (err)
3433 goto err_chip_exit;
3434 b43_qos_init(dev);
3435
3436 //FIXME
3437 #if 1
3438 b43_write16(dev, 0x0612, 0x0050);
3439 b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050);
3440 b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4);
3441 #endif
3442
3443 b43_bluetooth_coext_enable(dev);
3444
3445 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
3446 memset(wl->bssid, 0, ETH_ALEN);
3447 memset(wl->mac_addr, 0, ETH_ALEN);
3448 b43_upload_card_macaddress(dev);
3449 b43_security_init(dev);
3450 b43_rng_init(wl);
3451
3452 b43_set_status(dev, B43_STAT_INITIALIZED);
3453
3454 b43_leds_init(dev);
3455 out:
3456 return err;
3457
3458 err_chip_exit:
3459 b43_chip_exit(dev);
3460 err_kfree_tssitbl:
3461 if (phy->dyn_tssi_tbl)
3462 kfree(phy->tssi2dbm);
3463 err_kfree_lo_control:
3464 kfree(phy->lo_control);
3465 phy->lo_control = NULL;
3466 err_busdown:
3467 ssb_bus_may_powerdown(bus);
3468 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3469 return err;
3470 }
3471
3472 static int b43_op_add_interface(struct ieee80211_hw *hw,
3473 struct ieee80211_if_init_conf *conf)
3474 {
3475 struct b43_wl *wl = hw_to_b43_wl(hw);
3476 struct b43_wldev *dev;
3477 unsigned long flags;
3478 int err = -EOPNOTSUPP;
3479
3480 /* TODO: allow WDS/AP devices to coexist */
3481
3482 if (conf->type != IEEE80211_IF_TYPE_AP &&
3483 conf->type != IEEE80211_IF_TYPE_STA &&
3484 conf->type != IEEE80211_IF_TYPE_WDS &&
3485 conf->type != IEEE80211_IF_TYPE_IBSS)
3486 return -EOPNOTSUPP;
3487
3488 mutex_lock(&wl->mutex);
3489 if (wl->operating)
3490 goto out_mutex_unlock;
3491
3492 b43dbg(wl, "Adding Interface type %d\n", conf->type);
3493
3494 dev = wl->current_dev;
3495 wl->operating = 1;
3496 wl->vif = conf->vif;
3497 wl->if_type = conf->type;
3498 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3499
3500 spin_lock_irqsave(&wl->irq_lock, flags);
3501 b43_adjust_opmode(dev);
3502 b43_upload_card_macaddress(dev);
3503 spin_unlock_irqrestore(&wl->irq_lock, flags);
3504
3505 err = 0;
3506 out_mutex_unlock:
3507 mutex_unlock(&wl->mutex);
3508
3509 return err;
3510 }
3511
3512 static void b43_op_remove_interface(struct ieee80211_hw *hw,
3513 struct ieee80211_if_init_conf *conf)
3514 {
3515 struct b43_wl *wl = hw_to_b43_wl(hw);
3516 struct b43_wldev *dev = wl->current_dev;
3517 unsigned long flags;
3518
3519 b43dbg(wl, "Removing Interface type %d\n", conf->type);
3520
3521 mutex_lock(&wl->mutex);
3522
3523 B43_WARN_ON(!wl->operating);
3524 B43_WARN_ON(wl->vif != conf->vif);
3525 wl->vif = NULL;
3526
3527 wl->operating = 0;
3528
3529 spin_lock_irqsave(&wl->irq_lock, flags);
3530 b43_adjust_opmode(dev);
3531 memset(wl->mac_addr, 0, ETH_ALEN);
3532 b43_upload_card_macaddress(dev);
3533 spin_unlock_irqrestore(&wl->irq_lock, flags);
3534
3535 mutex_unlock(&wl->mutex);
3536 }
3537
3538 static int b43_op_start(struct ieee80211_hw *hw)
3539 {
3540 struct b43_wl *wl = hw_to_b43_wl(hw);
3541 struct b43_wldev *dev = wl->current_dev;
3542 int did_init = 0;
3543 int err = 0;
3544
3545 /* First register RFkill.
3546 * LEDs that are registered later depend on it. */
3547 b43_rfkill_init(dev);
3548
3549 mutex_lock(&wl->mutex);
3550
3551 if (b43_status(dev) < B43_STAT_INITIALIZED) {
3552 err = b43_wireless_core_init(dev);
3553 if (err)
3554 goto out_mutex_unlock;
3555 did_init = 1;
3556 }
3557
3558 if (b43_status(dev) < B43_STAT_STARTED) {
3559 err = b43_wireless_core_start(dev);
3560 if (err) {
3561 if (did_init)
3562 b43_wireless_core_exit(dev);
3563 goto out_mutex_unlock;
3564 }
3565 }
3566
3567 out_mutex_unlock:
3568 mutex_unlock(&wl->mutex);
3569
3570 return err;
3571 }
3572
3573 static void b43_op_stop(struct ieee80211_hw *hw)
3574 {
3575 struct b43_wl *wl = hw_to_b43_wl(hw);
3576 struct b43_wldev *dev = wl->current_dev;
3577
3578 b43_rfkill_exit(dev);
3579
3580 mutex_lock(&wl->mutex);
3581 if (b43_status(dev) >= B43_STAT_STARTED)
3582 b43_wireless_core_stop(dev);
3583 b43_wireless_core_exit(dev);
3584 mutex_unlock(&wl->mutex);
3585 }
3586
3587 static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
3588 u32 short_retry_limit, u32 long_retry_limit)
3589 {
3590 struct b43_wl *wl = hw_to_b43_wl(hw);
3591 struct b43_wldev *dev;
3592 int err = 0;
3593
3594 mutex_lock(&wl->mutex);
3595 dev = wl->current_dev;
3596 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
3597 err = -ENODEV;
3598 goto out_unlock;
3599 }
3600 b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
3601 out_unlock:
3602 mutex_unlock(&wl->mutex);
3603
3604 return err;
3605 }
3606
3607 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, int aid, int set)
3608 {
3609 struct b43_wl *wl = hw_to_b43_wl(hw);
3610 struct sk_buff *beacon;
3611 unsigned long flags;
3612
3613 /* We could modify the existing beacon and set the aid bit in
3614 * the TIM field, but that would probably require resizing and
3615 * moving of data within the beacon template.
3616 * Simply request a new beacon and let mac80211 do the hard work. */
3617 beacon = ieee80211_beacon_get(hw, wl->vif, NULL);
3618 if (unlikely(!beacon))
3619 return -ENOMEM;
3620 spin_lock_irqsave(&wl->irq_lock, flags);
3621 b43_update_templates(wl, beacon);
3622 spin_unlock_irqrestore(&wl->irq_lock, flags);
3623
3624 return 0;
3625 }
3626
3627 static int b43_op_ibss_beacon_update(struct ieee80211_hw *hw,
3628 struct sk_buff *beacon,
3629 struct ieee80211_tx_control *ctl)
3630 {
3631 struct b43_wl *wl = hw_to_b43_wl(hw);
3632 unsigned long flags;
3633
3634 spin_lock_irqsave(&wl->irq_lock, flags);
3635 b43_update_templates(wl, beacon);
3636 spin_unlock_irqrestore(&wl->irq_lock, flags);
3637
3638 return 0;
3639 }
3640
3641 static const struct ieee80211_ops b43_hw_ops = {
3642 .tx = b43_op_tx,
3643 .conf_tx = b43_op_conf_tx,
3644 .add_interface = b43_op_add_interface,
3645 .remove_interface = b43_op_remove_interface,
3646 .config = b43_op_config,
3647 .config_interface = b43_op_config_interface,
3648 .configure_filter = b43_op_configure_filter,
3649 .set_key = b43_op_set_key,
3650 .get_stats = b43_op_get_stats,
3651 .get_tx_stats = b43_op_get_tx_stats,
3652 .start = b43_op_start,
3653 .stop = b43_op_stop,
3654 .set_retry_limit = b43_op_set_retry_limit,
3655 .set_tim = b43_op_beacon_set_tim,
3656 .beacon_update = b43_op_ibss_beacon_update,
3657 };
3658
3659 /* Hard-reset the chip. Do not call this directly.
3660 * Use b43_controller_restart()
3661 */
3662 static void b43_chip_reset(struct work_struct *work)
3663 {
3664 struct b43_wldev *dev =
3665 container_of(work, struct b43_wldev, restart_work);
3666 struct b43_wl *wl = dev->wl;
3667 int err = 0;
3668 int prev_status;
3669
3670 mutex_lock(&wl->mutex);
3671
3672 prev_status = b43_status(dev);
3673 /* Bring the device down... */
3674 if (prev_status >= B43_STAT_STARTED)
3675 b43_wireless_core_stop(dev);
3676 if (prev_status >= B43_STAT_INITIALIZED)
3677 b43_wireless_core_exit(dev);
3678
3679 /* ...and up again. */
3680 if (prev_status >= B43_STAT_INITIALIZED) {
3681 err = b43_wireless_core_init(dev);
3682 if (err)
3683 goto out;
3684 }
3685 if (prev_status >= B43_STAT_STARTED) {
3686 err = b43_wireless_core_start(dev);
3687 if (err) {
3688 b43_wireless_core_exit(dev);
3689 goto out;
3690 }
3691 }
3692 out:
3693 mutex_unlock(&wl->mutex);
3694 if (err)
3695 b43err(wl, "Controller restart FAILED\n");
3696 else
3697 b43info(wl, "Controller restarted\n");
3698 }
3699
3700 static int b43_setup_modes(struct b43_wldev *dev,
3701 bool have_2ghz_phy, bool have_5ghz_phy)
3702 {
3703 struct ieee80211_hw *hw = dev->wl->hw;
3704 struct ieee80211_hw_mode *mode;
3705 struct b43_phy *phy = &dev->phy;
3706 int err;
3707
3708 /* XXX: This function will go away soon, when mac80211
3709 * band stuff is rewritten. So this is just a hack.
3710 * For now we always claim GPHY mode, as there is no
3711 * support for NPHY and APHY in the device, yet.
3712 * This assumption is OK, as any B, N or A PHY will already
3713 * have died a horrible sanity check death earlier. */
3714
3715 mode = &phy->hwmodes[0];
3716 mode->mode = MODE_IEEE80211G;
3717 mode->num_channels = b43_2ghz_chantable_size;
3718 mode->channels = b43_2ghz_chantable;
3719 mode->num_rates = b43_g_ratetable_size;
3720 mode->rates = b43_g_ratetable;
3721 err = ieee80211_register_hwmode(hw, mode);
3722 if (err)
3723 return err;
3724 phy->possible_phymodes |= B43_PHYMODE_G;
3725
3726 return 0;
3727 }
3728
3729 static void b43_wireless_core_detach(struct b43_wldev *dev)
3730 {
3731 /* We release firmware that late to not be required to re-request
3732 * is all the time when we reinit the core. */
3733 b43_release_firmware(dev);
3734 }
3735
3736 static int b43_wireless_core_attach(struct b43_wldev *dev)
3737 {
3738 struct b43_wl *wl = dev->wl;
3739 struct ssb_bus *bus = dev->dev->bus;
3740 struct pci_dev *pdev = bus->host_pci;
3741 int err;
3742 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
3743 u32 tmp;
3744
3745 /* Do NOT do any device initialization here.
3746 * Do it in wireless_core_init() instead.
3747 * This function is for gathering basic information about the HW, only.
3748 * Also some structs may be set up here. But most likely you want to have
3749 * that in core_init(), too.
3750 */
3751
3752 err = ssb_bus_powerup(bus, 0);
3753 if (err) {
3754 b43err(wl, "Bus powerup failed\n");
3755 goto out;
3756 }
3757 /* Get the PHY type. */
3758 if (dev->dev->id.revision >= 5) {
3759 u32 tmshigh;
3760
3761 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3762 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
3763 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
3764 } else
3765 B43_WARN_ON(1);
3766
3767 dev->phy.gmode = have_2ghz_phy;
3768 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3769 b43_wireless_core_reset(dev, tmp);
3770
3771 err = b43_phy_versioning(dev);
3772 if (err)
3773 goto err_powerdown;
3774 /* Check if this device supports multiband. */
3775 if (!pdev ||
3776 (pdev->device != 0x4312 &&
3777 pdev->device != 0x4319 && pdev->device != 0x4324)) {
3778 /* No multiband support. */
3779 have_2ghz_phy = 0;
3780 have_5ghz_phy = 0;
3781 switch (dev->phy.type) {
3782 case B43_PHYTYPE_A:
3783 have_5ghz_phy = 1;
3784 break;
3785 case B43_PHYTYPE_G:
3786 case B43_PHYTYPE_N:
3787 have_2ghz_phy = 1;
3788 break;
3789 default:
3790 B43_WARN_ON(1);
3791 }
3792 }
3793 if (dev->phy.type == B43_PHYTYPE_A) {
3794 /* FIXME */
3795 b43err(wl, "IEEE 802.11a devices are unsupported\n");
3796 err = -EOPNOTSUPP;
3797 goto err_powerdown;
3798 }
3799 dev->phy.gmode = have_2ghz_phy;
3800 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3801 b43_wireless_core_reset(dev, tmp);
3802
3803 err = b43_validate_chipaccess(dev);
3804 if (err)
3805 goto err_powerdown;
3806 err = b43_setup_modes(dev, have_2ghz_phy, have_5ghz_phy);
3807 if (err)
3808 goto err_powerdown;
3809
3810 /* Now set some default "current_dev" */
3811 if (!wl->current_dev)
3812 wl->current_dev = dev;
3813 INIT_WORK(&dev->restart_work, b43_chip_reset);
3814
3815 b43_radio_turn_off(dev, 1);
3816 b43_switch_analog(dev, 0);
3817 ssb_device_disable(dev->dev, 0);
3818 ssb_bus_may_powerdown(bus);
3819
3820 out:
3821 return err;
3822
3823 err_powerdown:
3824 ssb_bus_may_powerdown(bus);
3825 return err;
3826 }
3827
3828 static void b43_one_core_detach(struct ssb_device *dev)
3829 {
3830 struct b43_wldev *wldev;
3831 struct b43_wl *wl;
3832
3833 wldev = ssb_get_drvdata(dev);
3834 wl = wldev->wl;
3835 cancel_work_sync(&wldev->restart_work);
3836 b43_debugfs_remove_device(wldev);
3837 b43_wireless_core_detach(wldev);
3838 list_del(&wldev->list);
3839 wl->nr_devs--;
3840 ssb_set_drvdata(dev, NULL);
3841 kfree(wldev);
3842 }
3843
3844 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
3845 {
3846 struct b43_wldev *wldev;
3847 struct pci_dev *pdev;
3848 int err = -ENOMEM;
3849
3850 if (!list_empty(&wl->devlist)) {
3851 /* We are not the first core on this chip. */
3852 pdev = dev->bus->host_pci;
3853 /* Only special chips support more than one wireless
3854 * core, although some of the other chips have more than
3855 * one wireless core as well. Check for this and
3856 * bail out early.
3857 */
3858 if (!pdev ||
3859 ((pdev->device != 0x4321) &&
3860 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
3861 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
3862 return -ENODEV;
3863 }
3864 }
3865
3866 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3867 if (!wldev)
3868 goto out;
3869
3870 wldev->dev = dev;
3871 wldev->wl = wl;
3872 b43_set_status(wldev, B43_STAT_UNINIT);
3873 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3874 tasklet_init(&wldev->isr_tasklet,
3875 (void (*)(unsigned long))b43_interrupt_tasklet,
3876 (unsigned long)wldev);
3877 INIT_LIST_HEAD(&wldev->list);
3878
3879 err = b43_wireless_core_attach(wldev);
3880 if (err)
3881 goto err_kfree_wldev;
3882
3883 list_add(&wldev->list, &wl->devlist);
3884 wl->nr_devs++;
3885 ssb_set_drvdata(dev, wldev);
3886 b43_debugfs_add_device(wldev);
3887
3888 out:
3889 return err;
3890
3891 err_kfree_wldev:
3892 kfree(wldev);
3893 return err;
3894 }
3895
3896 static void b43_sprom_fixup(struct ssb_bus *bus)
3897 {
3898 /* boardflags workarounds */
3899 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
3900 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
3901 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
3902 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3903 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
3904 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
3905 }
3906
3907 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
3908 {
3909 struct ieee80211_hw *hw = wl->hw;
3910
3911 ssb_set_devtypedata(dev, NULL);
3912 ieee80211_free_hw(hw);
3913 }
3914
3915 static int b43_wireless_init(struct ssb_device *dev)
3916 {
3917 struct ssb_sprom *sprom = &dev->bus->sprom;
3918 struct ieee80211_hw *hw;
3919 struct b43_wl *wl;
3920 int err = -ENOMEM;
3921
3922 b43_sprom_fixup(dev->bus);
3923
3924 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
3925 if (!hw) {
3926 b43err(NULL, "Could not allocate ieee80211 device\n");
3927 goto out;
3928 }
3929
3930 /* fill hw info */
3931 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
3932 IEEE80211_HW_RX_INCLUDES_FCS;
3933 hw->max_signal = 100;
3934 hw->max_rssi = -110;
3935 hw->max_noise = -110;
3936 hw->queues = 1; /* FIXME: hardware has more queues */
3937 SET_IEEE80211_DEV(hw, dev->dev);
3938 if (is_valid_ether_addr(sprom->et1mac))
3939 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
3940 else
3941 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
3942
3943 /* Get and initialize struct b43_wl */
3944 wl = hw_to_b43_wl(hw);
3945 memset(wl, 0, sizeof(*wl));
3946 wl->hw = hw;
3947 spin_lock_init(&wl->irq_lock);
3948 spin_lock_init(&wl->leds_lock);
3949 spin_lock_init(&wl->shm_lock);
3950 mutex_init(&wl->mutex);
3951 INIT_LIST_HEAD(&wl->devlist);
3952
3953 ssb_set_devtypedata(dev, wl);
3954 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3955 err = 0;
3956 out:
3957 return err;
3958 }
3959
3960 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
3961 {
3962 struct b43_wl *wl;
3963 int err;
3964 int first = 0;
3965
3966 wl = ssb_get_devtypedata(dev);
3967 if (!wl) {
3968 /* Probing the first core. Must setup common struct b43_wl */
3969 first = 1;
3970 err = b43_wireless_init(dev);
3971 if (err)
3972 goto out;
3973 wl = ssb_get_devtypedata(dev);
3974 B43_WARN_ON(!wl);
3975 }
3976 err = b43_one_core_attach(dev, wl);
3977 if (err)
3978 goto err_wireless_exit;
3979
3980 if (first) {
3981 err = ieee80211_register_hw(wl->hw);
3982 if (err)
3983 goto err_one_core_detach;
3984 }
3985
3986 out:
3987 return err;
3988
3989 err_one_core_detach:
3990 b43_one_core_detach(dev);
3991 err_wireless_exit:
3992 if (first)
3993 b43_wireless_exit(dev, wl);
3994 return err;
3995 }
3996
3997 static void b43_remove(struct ssb_device *dev)
3998 {
3999 struct b43_wl *wl = ssb_get_devtypedata(dev);
4000 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4001
4002 B43_WARN_ON(!wl);
4003 if (wl->current_dev == wldev)
4004 ieee80211_unregister_hw(wl->hw);
4005
4006 b43_one_core_detach(dev);
4007
4008 if (list_empty(&wl->devlist)) {
4009 /* Last core on the chip unregistered.
4010 * We can destroy common struct b43_wl.
4011 */
4012 b43_wireless_exit(dev, wl);
4013 }
4014 }
4015
4016 /* Perform a hardware reset. This can be called from any context. */
4017 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4018 {
4019 /* Must avoid requeueing, if we are in shutdown. */
4020 if (b43_status(dev) < B43_STAT_INITIALIZED)
4021 return;
4022 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4023 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4024 }
4025
4026 #ifdef CONFIG_PM
4027
4028 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4029 {
4030 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4031 struct b43_wl *wl = wldev->wl;
4032
4033 b43dbg(wl, "Suspending...\n");
4034
4035 mutex_lock(&wl->mutex);
4036 wldev->suspend_init_status = b43_status(wldev);
4037 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4038 b43_wireless_core_stop(wldev);
4039 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4040 b43_wireless_core_exit(wldev);
4041 mutex_unlock(&wl->mutex);
4042
4043 b43dbg(wl, "Device suspended.\n");
4044
4045 return 0;
4046 }
4047
4048 static int b43_resume(struct ssb_device *dev)
4049 {
4050 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4051 struct b43_wl *wl = wldev->wl;
4052 int err = 0;
4053
4054 b43dbg(wl, "Resuming...\n");
4055
4056 mutex_lock(&wl->mutex);
4057 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4058 err = b43_wireless_core_init(wldev);
4059 if (err) {
4060 b43err(wl, "Resume failed at core init\n");
4061 goto out;
4062 }
4063 }
4064 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4065 err = b43_wireless_core_start(wldev);
4066 if (err) {
4067 b43_wireless_core_exit(wldev);
4068 b43err(wl, "Resume failed at core start\n");
4069 goto out;
4070 }
4071 }
4072 mutex_unlock(&wl->mutex);
4073
4074 b43dbg(wl, "Device resumed.\n");
4075 out:
4076 return err;
4077 }
4078
4079 #else /* CONFIG_PM */
4080 # define b43_suspend NULL
4081 # define b43_resume NULL
4082 #endif /* CONFIG_PM */
4083
4084 static struct ssb_driver b43_ssb_driver = {
4085 .name = KBUILD_MODNAME,
4086 .id_table = b43_ssb_tbl,
4087 .probe = b43_probe,
4088 .remove = b43_remove,
4089 .suspend = b43_suspend,
4090 .resume = b43_resume,
4091 };
4092
4093 static int __init b43_init(void)
4094 {
4095 int err;
4096
4097 b43_debugfs_init();
4098 err = b43_pcmcia_init();
4099 if (err)
4100 goto err_dfs_exit;
4101 err = ssb_driver_register(&b43_ssb_driver);
4102 if (err)
4103 goto err_pcmcia_exit;
4104
4105 return err;
4106
4107 err_pcmcia_exit:
4108 b43_pcmcia_exit();
4109 err_dfs_exit:
4110 b43_debugfs_exit();
4111 return err;
4112 }
4113
4114 static void __exit b43_exit(void)
4115 {
4116 ssb_driver_unregister(&b43_ssb_driver);
4117 b43_pcmcia_exit();
4118 b43_debugfs_exit();
4119 }
4120
4121 module_init(b43_init)
4122 module_exit(b43_exit)
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