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x86/uv: Implement UV BAU runtime enable and disable control via /proc/sgi_uv/
[linux-2.6.git] / arch / x86 / include / asm / uv / uv_bau.h
blob847c00b721b2f938e6306fa9eb2a88205cbf7b46
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV Broadcast Assist Unit definitions
7 *
8 * Copyright (C) 2008-2011 Silicon Graphics, Inc. All rights reserved.
9 */
10
11 #ifndef _ASM_X86_UV_UV_BAU_H
12 #define _ASM_X86_UV_UV_BAU_H
13
14 #include <linux/bitmap.h>
15 #define BITSPERBYTE 8
16
17 /*
18 * Broadcast Assist Unit messaging structures
19 *
20 * Selective Broadcast activations are induced by software action
21 * specifying a particular 8-descriptor "set" via a 6-bit index written
22 * to an MMR.
23 * Thus there are 64 unique 512-byte sets of SB descriptors - one set for
24 * each 6-bit index value. These descriptor sets are mapped in sequence
25 * starting with set 0 located at the address specified in the
26 * BAU_SB_DESCRIPTOR_BASE register, set 1 is located at BASE + 512,
27 * set 2 is at BASE + 2*512, set 3 at BASE + 3*512, and so on.
28 *
29 * We will use one set for sending BAU messages from each of the
30 * cpu's on the uvhub.
31 *
32 * TLB shootdown will use the first of the 8 descriptors of each set.
33 * Each of the descriptors is 64 bytes in size (8*64 = 512 bytes in a set).
34 */
35
36 #define MAX_CPUS_PER_UVHUB 64
37 #define MAX_CPUS_PER_SOCKET 32
38 #define ADP_SZ 64 /* hardware-provided max. */
39 #define UV_CPUS_PER_AS 32 /* hardware-provided max. */
40 #define ITEMS_PER_DESC 8
41 /* the 'throttle' to prevent the hardware stay-busy bug */
42 #define MAX_BAU_CONCURRENT 3
43 #define UV_ACT_STATUS_MASK 0x3
44 #define UV_ACT_STATUS_SIZE 2
45 #define UV_DISTRIBUTION_SIZE 256
46 #define UV_SW_ACK_NPENDING 8
47 #define UV1_NET_ENDPOINT_INTD 0x38
48 #define UV2_NET_ENDPOINT_INTD 0x28
49 #define UV_NET_ENDPOINT_INTD (is_uv1_hub() ? \
50 UV1_NET_ENDPOINT_INTD : UV2_NET_ENDPOINT_INTD)
51 #define UV_DESC_PSHIFT 49
52 #define UV_PAYLOADQ_PNODE_SHIFT 49
53 #define UV_PTC_BASENAME "sgi_uv/ptc_statistics"
54 #define UV_BAU_BASENAME "sgi_uv/bau_tunables"
55 #define UV_BAU_TUNABLES_DIR "sgi_uv"
56 #define UV_BAU_TUNABLES_FILE "bau_tunables"
57 #define WHITESPACE " \t\n"
58 #define uv_mmask ((1UL << uv_hub_info->m_val) - 1)
59 #define uv_physnodeaddr(x) ((__pa((unsigned long)(x)) & uv_mmask))
60 #define cpubit_isset(cpu, bau_local_cpumask) \
61 test_bit((cpu), (bau_local_cpumask).bits)
62
63 /* [19:16] SOFT_ACK timeout period 19: 1 is urgency 7 17:16 1 is multiplier */
64 /*
65 * UV2: Bit 19 selects between
66 * (0): 10 microsecond timebase and
67 * (1): 80 microseconds
68 * we're using 560us, similar to UV1: 65 units of 10us
69 */
70 #define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL)
71 #define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (15UL)
72
73 #define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD (is_uv1_hub() ? \
74 UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD : \
75 UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD)
76
77 #define BAU_MISC_CONTROL_MULT_MASK 3
78
79 #define UVH_AGING_PRESCALE_SEL 0x000000b000UL
80 /* [30:28] URGENCY_7 an index into a table of times */
81 #define BAU_URGENCY_7_SHIFT 28
82 #define BAU_URGENCY_7_MASK 7
83
84 #define UVH_TRANSACTION_TIMEOUT 0x000000b200UL
85 /* [45:40] BAU - BAU transaction timeout select - a multiplier */
86 #define BAU_TRANS_SHIFT 40
87 #define BAU_TRANS_MASK 0x3f
88
89 /*
90 * shorten some awkward names
91 */
92 #define AS_PUSH_SHIFT UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT
93 #define SOFTACK_MSHIFT UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT
94 #define SOFTACK_PSHIFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
95 #define SOFTACK_TIMEOUT_PERIOD UV_INTD_SOFT_ACK_TIMEOUT_PERIOD
96 #define write_gmmr uv_write_global_mmr64
97 #define write_lmmr uv_write_local_mmr
98 #define read_lmmr uv_read_local_mmr
99 #define read_gmmr uv_read_global_mmr64
100
101 /*
102 * bits in UVH_LB_BAU_SB_ACTIVATION_STATUS_0/1
103 */
104 #define DS_IDLE 0
105 #define DS_ACTIVE 1
106 #define DS_DESTINATION_TIMEOUT 2
107 #define DS_SOURCE_TIMEOUT 3
108 /*
109 * bits put together from HRP_LB_BAU_SB_ACTIVATION_STATUS_0/1/2
110 * values 1 and 3 will not occur
111 * Decoded meaning ERROR BUSY AUX ERR
112 * ------------------------------- ---- ----- -------
113 * IDLE 0 0 0
114 * BUSY (active) 0 1 0
115 * SW Ack Timeout (destination) 1 0 0
116 * SW Ack INTD rejected (strong NACK) 1 0 1
117 * Source Side Time Out Detected 1 1 0
118 * Destination Side PUT Failed 1 1 1
119 */
120 #define UV2H_DESC_IDLE 0
121 #define UV2H_DESC_BUSY 2
122 #define UV2H_DESC_DEST_TIMEOUT 4
123 #define UV2H_DESC_DEST_STRONG_NACK 5
124 #define UV2H_DESC_SOURCE_TIMEOUT 6
125 #define UV2H_DESC_DEST_PUT_ERR 7
126
127 /*
128 * delay for 'plugged' timeout retries, in microseconds
129 */
130 #define PLUGGED_DELAY 10
131
132 /*
133 * threshholds at which to use IPI to free resources
134 */
135 /* after this # consecutive 'plugged' timeouts, use IPI to release resources */
136 #define PLUGSB4RESET 100
137 /* after this many consecutive timeouts, use IPI to release resources */
138 #define TIMEOUTSB4RESET 1
139 /* at this number uses of IPI to release resources, giveup the request */
140 #define IPI_RESET_LIMIT 1
141 /* after this # consecutive successes, bump up the throttle if it was lowered */
142 #define COMPLETE_THRESHOLD 5
143
144 #define UV_LB_SUBNODEID 0x10
145
146 /* these two are the same for UV1 and UV2: */
147 #define UV_SA_SHFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
148 #define UV_SA_MASK UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK
149 /* 4 bits of software ack period */
150 #define UV2_ACK_MASK 0x7UL
151 #define UV2_ACK_UNITS_SHFT 3
152 #define UV2_EXT_SHFT UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
153
154 /*
155 * number of entries in the destination side payload queue
156 */
157 #define DEST_Q_SIZE 20
158 /*
159 * number of destination side software ack resources
160 */
161 #define DEST_NUM_RESOURCES 8
162 /*
163 * completion statuses for sending a TLB flush message
164 */
165 #define FLUSH_RETRY_PLUGGED 1
166 #define FLUSH_RETRY_TIMEOUT 2
167 #define FLUSH_GIVEUP 3
168 #define FLUSH_COMPLETE 4
169 #define FLUSH_RETRY_BUSYBUG 5
170
171 /*
172 * tuning the action when the numalink network is extremely delayed
173 */
174 #define CONGESTED_RESPONSE_US 1000 /* 'long' response time, in
175 microseconds */
176 #define CONGESTED_REPS 10 /* long delays averaged over
177 this many broadcasts */
178 #define CONGESTED_PERIOD 30 /* time for the bau to be
179 disabled, in seconds */
180 /* see msg_type: */
181 #define MSG_NOOP 0
182 #define MSG_REGULAR 1
183 #define MSG_RETRY 2
184
185 /*
186 * Distribution: 32 bytes (256 bits) (bytes 0-0x1f of descriptor)
187 * If the 'multilevel' flag in the header portion of the descriptor
188 * has been set to 0, then endpoint multi-unicast mode is selected.
189 * The distribution specification (32 bytes) is interpreted as a 256-bit
190 * distribution vector. Adjacent bits correspond to consecutive even numbered
191 * nodeIDs. The result of adding the index of a given bit to the 15-bit
192 * 'base_dest_nasid' field of the header corresponds to the
193 * destination nodeID associated with that specified bit.
194 */
195 struct pnmask {
196 unsigned long bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)];
197 };
198
199 /*
200 * mask of cpu's on a uvhub
201 * (during initialization we need to check that unsigned long has
202 * enough bits for max. cpu's per uvhub)
203 */
204 struct bau_local_cpumask {
205 unsigned long bits;
206 };
207
208 /*
209 * Payload: 16 bytes (128 bits) (bytes 0x20-0x2f of descriptor)
210 * only 12 bytes (96 bits) of the payload area are usable.
211 * An additional 3 bytes (bits 27:4) of the header address are carried
212 * to the next bytes of the destination payload queue.
213 * And an additional 2 bytes of the header Suppl_A field are also
214 * carried to the destination payload queue.
215 * But the first byte of the Suppl_A becomes bits 127:120 (the 16th byte)
216 * of the destination payload queue, which is written by the hardware
217 * with the s/w ack resource bit vector.
218 * [ effective message contents (16 bytes (128 bits) maximum), not counting
219 * the s/w ack bit vector ]
220 */
221
222 /*
223 * The payload is software-defined for INTD transactions
224 */
225 struct bau_msg_payload {
226 unsigned long address; /* signifies a page or all
227 TLB's of the cpu */
228 /* 64 bits */
229 unsigned short sending_cpu; /* filled in by sender */
230 /* 16 bits */
231 unsigned short acknowledge_count; /* filled in by destination */
232 /* 16 bits */
233 unsigned int reserved1:32; /* not usable */
234 };
235
236
237 /*
238 * UV1 Message header: 16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)
239 * see table 4.2.3.0.1 in broacast_assist spec.
240 */
241 struct uv1_bau_msg_header {
242 unsigned int dest_subnodeid:6; /* must be 0x10, for the LB */
243 /* bits 5:0 */
244 unsigned int base_dest_nasid:15; /* nasid of the first bit */
245 /* bits 20:6 */ /* in uvhub map */
246 unsigned int command:8; /* message type */
247 /* bits 28:21 */
248 /* 0x38: SN3net EndPoint Message */
249 unsigned int rsvd_1:3; /* must be zero */
250 /* bits 31:29 */
251 /* int will align on 32 bits */
252 unsigned int rsvd_2:9; /* must be zero */
253 /* bits 40:32 */
254 /* Suppl_A is 56-41 */
255 unsigned int sequence:16; /* message sequence number */
256 /* bits 56:41 */ /* becomes bytes 16-17 of msg */
257 /* Address field (96:57) is
258 never used as an address
259 (these are address bits
260 42:3) */
261
262 unsigned int rsvd_3:1; /* must be zero */
263 /* bit 57 */
264 /* address bits 27:4 are payload */
265 /* these next 24 (58-81) bits become bytes 12-14 of msg */
266 /* bits 65:58 land in byte 12 */
267 unsigned int replied_to:1; /* sent as 0 by the source to
268 byte 12 */
269 /* bit 58 */
270 unsigned int msg_type:3; /* software type of the
271 message */
272 /* bits 61:59 */
273 unsigned int canceled:1; /* message canceled, resource
274 is to be freed*/
275 /* bit 62 */
276 unsigned int payload_1a:1; /* not currently used */
277 /* bit 63 */
278 unsigned int payload_1b:2; /* not currently used */
279 /* bits 65:64 */
280
281 /* bits 73:66 land in byte 13 */
282 unsigned int payload_1ca:6; /* not currently used */
283 /* bits 71:66 */
284 unsigned int payload_1c:2; /* not currently used */
285 /* bits 73:72 */
286
287 /* bits 81:74 land in byte 14 */
288 unsigned int payload_1d:6; /* not currently used */
289 /* bits 79:74 */
290 unsigned int payload_1e:2; /* not currently used */
291 /* bits 81:80 */
292
293 unsigned int rsvd_4:7; /* must be zero */
294 /* bits 88:82 */
295 unsigned int swack_flag:1; /* software acknowledge flag */
296 /* bit 89 */
297 /* INTD trasactions at
298 destination are to wait for
299 software acknowledge */
300 unsigned int rsvd_5:6; /* must be zero */
301 /* bits 95:90 */
302 unsigned int rsvd_6:5; /* must be zero */
303 /* bits 100:96 */
304 unsigned int int_both:1; /* if 1, interrupt both sockets
305 on the uvhub */
306 /* bit 101*/
307 unsigned int fairness:3; /* usually zero */
308 /* bits 104:102 */
309 unsigned int multilevel:1; /* multi-level multicast
310 format */
311 /* bit 105 */
312 /* 0 for TLB: endpoint multi-unicast messages */
313 unsigned int chaining:1; /* next descriptor is part of
314 this activation*/
315 /* bit 106 */
316 unsigned int rsvd_7:21; /* must be zero */
317 /* bits 127:107 */
318 };
319
320 /*
321 * UV2 Message header: 16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)
322 * see figure 9-2 of harp_sys.pdf
323 */
324 struct uv2_bau_msg_header {
325 unsigned int base_dest_nasid:15; /* nasid of the first bit */
326 /* bits 14:0 */ /* in uvhub map */
327 unsigned int dest_subnodeid:5; /* must be 0x10, for the LB */
328 /* bits 19:15 */
329 unsigned int rsvd_1:1; /* must be zero */
330 /* bit 20 */
331 /* Address bits 59:21 */
332 /* bits 25:2 of address (44:21) are payload */
333 /* these next 24 bits become bytes 12-14 of msg */
334 /* bits 28:21 land in byte 12 */
335 unsigned int replied_to:1; /* sent as 0 by the source to
336 byte 12 */
337 /* bit 21 */
338 unsigned int msg_type:3; /* software type of the
339 message */
340 /* bits 24:22 */
341 unsigned int canceled:1; /* message canceled, resource
342 is to be freed*/
343 /* bit 25 */
344 unsigned int payload_1:3; /* not currently used */
345 /* bits 28:26 */
346
347 /* bits 36:29 land in byte 13 */
348 unsigned int payload_2a:3; /* not currently used */
349 unsigned int payload_2b:5; /* not currently used */
350 /* bits 36:29 */
351
352 /* bits 44:37 land in byte 14 */
353 unsigned int payload_3:8; /* not currently used */
354 /* bits 44:37 */
355
356 unsigned int rsvd_2:7; /* reserved */
357 /* bits 51:45 */
358 unsigned int swack_flag:1; /* software acknowledge flag */
359 /* bit 52 */
360 unsigned int rsvd_3a:3; /* must be zero */
361 unsigned int rsvd_3b:8; /* must be zero */
362 unsigned int rsvd_3c:8; /* must be zero */
363 unsigned int rsvd_3d:3; /* must be zero */
364 /* bits 74:53 */
365 unsigned int fairness:3; /* usually zero */
366 /* bits 77:75 */
367
368 unsigned int sequence:16; /* message sequence number */
369 /* bits 93:78 Suppl_A */
370 unsigned int chaining:1; /* next descriptor is part of
371 this activation*/
372 /* bit 94 */
373 unsigned int multilevel:1; /* multi-level multicast
374 format */
375 /* bit 95 */
376 unsigned int rsvd_4:24; /* ordered / source node /
377 source subnode / aging
378 must be zero */
379 /* bits 119:96 */
380 unsigned int command:8; /* message type */
381 /* bits 127:120 */
382 };
383
384 /*
385 * The activation descriptor:
386 * The format of the message to send, plus all accompanying control
387 * Should be 64 bytes
388 */
389 struct bau_desc {
390 struct pnmask distribution;
391 /*
392 * message template, consisting of header and payload:
393 */
394 union bau_msg_header {
395 struct uv1_bau_msg_header uv1_hdr;
396 struct uv2_bau_msg_header uv2_hdr;
397 } header;
398
399 struct bau_msg_payload payload;
400 };
401 /* UV1:
402 * -payload-- ---------header------
403 * bytes 0-11 bits 41-56 bits 58-81
404 * A B (2) C (3)
405 *
406 * A/B/C are moved to:
407 * A C B
408 * bytes 0-11 bytes 12-14 bytes 16-17 (byte 15 filled in by hw as vector)
409 * ------------payload queue-----------
410 */
411 /* UV2:
412 * -payload-- ---------header------
413 * bytes 0-11 bits 70-78 bits 21-44
414 * A B (2) C (3)
415 *
416 * A/B/C are moved to:
417 * A C B
418 * bytes 0-11 bytes 12-14 bytes 16-17 (byte 15 filled in by hw as vector)
419 * ------------payload queue-----------
420 */
421
422 /*
423 * The payload queue on the destination side is an array of these.
424 * With BAU_MISC_CONTROL set for software acknowledge mode, the messages
425 * are 32 bytes (2 micropackets) (256 bits) in length, but contain only 17
426 * bytes of usable data, including the sw ack vector in byte 15 (bits 127:120)
427 * (12 bytes come from bau_msg_payload, 3 from payload_1, 2 from
428 * swack_vec and payload_2)
429 * "Enabling Software Acknowledgment mode (see Section 4.3.3 Software
430 * Acknowledge Processing) also selects 32 byte (17 bytes usable) payload
431 * operation."
432 */
433 struct bau_pq_entry {
434 unsigned long address; /* signifies a page or all TLB's
435 of the cpu */
436 /* 64 bits, bytes 0-7 */
437 unsigned short sending_cpu; /* cpu that sent the message */
438 /* 16 bits, bytes 8-9 */
439 unsigned short acknowledge_count; /* filled in by destination */
440 /* 16 bits, bytes 10-11 */
441 /* these next 3 bytes come from bits 58-81 of the message header */
442 unsigned short replied_to:1; /* sent as 0 by the source */
443 unsigned short msg_type:3; /* software message type */
444 unsigned short canceled:1; /* sent as 0 by the source */
445 unsigned short unused1:3; /* not currently using */
446 /* byte 12 */
447 unsigned char unused2a; /* not currently using */
448 /* byte 13 */
449 unsigned char unused2; /* not currently using */
450 /* byte 14 */
451 unsigned char swack_vec; /* filled in by the hardware */
452 /* byte 15 (bits 127:120) */
453 unsigned short sequence; /* message sequence number */
454 /* bytes 16-17 */
455 unsigned char unused4[2]; /* not currently using bytes 18-19 */
456 /* bytes 18-19 */
457 int number_of_cpus; /* filled in at destination */
458 /* 32 bits, bytes 20-23 (aligned) */
459 unsigned char unused5[8]; /* not using */
460 /* bytes 24-31 */
461 };
462
463 struct msg_desc {
464 struct bau_pq_entry *msg;
465 int msg_slot;
466 struct bau_pq_entry *queue_first;
467 struct bau_pq_entry *queue_last;
468 };
469
470 struct reset_args {
471 int sender;
472 };
473
474 /*
475 * This structure is allocated per_cpu for UV TLB shootdown statistics.
476 */
477 struct ptc_stats {
478 /* sender statistics */
479 unsigned long s_giveup; /* number of fall backs to
480 IPI-style flushes */
481 unsigned long s_requestor; /* number of shootdown
482 requests */
483 unsigned long s_stimeout; /* source side timeouts */
484 unsigned long s_dtimeout; /* destination side timeouts */
485 unsigned long s_strongnacks; /* number of strong nack's */
486 unsigned long s_time; /* time spent in sending side */
487 unsigned long s_retriesok; /* successful retries */
488 unsigned long s_ntargcpu; /* total number of cpu's
489 targeted */
490 unsigned long s_ntargself; /* times the sending cpu was
491 targeted */
492 unsigned long s_ntarglocals; /* targets of cpus on the local
493 blade */
494 unsigned long s_ntargremotes; /* targets of cpus on remote
495 blades */
496 unsigned long s_ntarglocaluvhub; /* targets of the local hub */
497 unsigned long s_ntargremoteuvhub; /* remotes hubs targeted */
498 unsigned long s_ntarguvhub; /* total number of uvhubs
499 targeted */
500 unsigned long s_ntarguvhub16; /* number of times target
501 hubs >= 16*/
502 unsigned long s_ntarguvhub8; /* number of times target
503 hubs >= 8 */
504 unsigned long s_ntarguvhub4; /* number of times target
505 hubs >= 4 */
506 unsigned long s_ntarguvhub2; /* number of times target
507 hubs >= 2 */
508 unsigned long s_ntarguvhub1; /* number of times target
509 hubs == 1 */
510 unsigned long s_resets_plug; /* ipi-style resets from plug
511 state */
512 unsigned long s_resets_timeout; /* ipi-style resets from
513 timeouts */
514 unsigned long s_busy; /* status stayed busy past
515 s/w timer */
516 unsigned long s_throttles; /* waits in throttle */
517 unsigned long s_retry_messages; /* retry broadcasts */
518 unsigned long s_bau_reenabled; /* for bau enable/disable */
519 unsigned long s_bau_disabled; /* for bau enable/disable */
520 unsigned long s_uv2_wars; /* uv2 workaround, perm. busy */
521 unsigned long s_uv2_wars_hw; /* uv2 workaround, hiwater */
522 unsigned long s_uv2_war_waits; /* uv2 workaround, long waits */
523 unsigned long s_enters; /* entries to the driver */
524 /* destination statistics */
525 unsigned long d_alltlb; /* times all tlb's on this
526 cpu were flushed */
527 unsigned long d_onetlb; /* times just one tlb on this
528 cpu was flushed */
529 unsigned long d_multmsg; /* interrupts with multiple
530 messages */
531 unsigned long d_nomsg; /* interrupts with no message */
532 unsigned long d_time; /* time spent on destination
533 side */
534 unsigned long d_requestee; /* number of messages
535 processed */
536 unsigned long d_retries; /* number of retry messages
537 processed */
538 unsigned long d_canceled; /* number of messages canceled
539 by retries */
540 unsigned long d_nocanceled; /* retries that found nothing
541 to cancel */
542 unsigned long d_resets; /* number of ipi-style requests
543 processed */
544 unsigned long d_rcanceled; /* number of messages canceled
545 by resets */
546 };
547
548 struct tunables {
549 int *tunp;
550 int deflt;
551 };
552
553 struct hub_and_pnode {
554 short uvhub;
555 short pnode;
556 };
557
558 struct socket_desc {
559 short num_cpus;
560 short cpu_number[MAX_CPUS_PER_SOCKET];
561 };
562
563 struct uvhub_desc {
564 unsigned short socket_mask;
565 short num_cpus;
566 short uvhub;
567 short pnode;
568 struct socket_desc socket[2];
569 };
570
571 /*
572 * one per-cpu; to locate the software tables
573 */
574 struct bau_control {
575 struct bau_desc *descriptor_base;
576 struct bau_pq_entry *queue_first;
577 struct bau_pq_entry *queue_last;
578 struct bau_pq_entry *bau_msg_head;
579 struct bau_control *uvhub_master;
580 struct bau_control *socket_master;
581 struct ptc_stats *statp;
582 cpumask_t *cpumask;
583 unsigned long timeout_interval;
584 unsigned long set_bau_on_time;
585 atomic_t active_descriptor_count;
586 int plugged_tries;
587 int timeout_tries;
588 int ipi_attempts;
589 int conseccompletes;
590 short nobau;
591 int baudisabled;
592 int set_bau_off;
593 short cpu;
594 short osnode;
595 short uvhub_cpu;
596 short uvhub;
597 short uvhub_version;
598 short cpus_in_socket;
599 short cpus_in_uvhub;
600 short partition_base_pnode;
601 short using_desc; /* an index, like uvhub_cpu */
602 unsigned int inuse_map;
603 unsigned short message_number;
604 unsigned short uvhub_quiesce;
605 short socket_acknowledge_count[DEST_Q_SIZE];
606 cycles_t send_message;
607 spinlock_t uvhub_lock;
608 spinlock_t queue_lock;
609 /* tunables */
610 int max_concurr;
611 int max_concurr_const;
612 int plugged_delay;
613 int plugsb4reset;
614 int timeoutsb4reset;
615 int ipi_reset_limit;
616 int complete_threshold;
617 int cong_response_us;
618 int cong_reps;
619 int cong_period;
620 unsigned long clocks_per_100_usec;
621 cycles_t period_time;
622 long period_requests;
623 struct hub_and_pnode *thp;
624 };
625
626 static inline unsigned long read_mmr_uv2_status(void)
627 {
628 return read_lmmr(UV2H_LB_BAU_SB_ACTIVATION_STATUS_2);
629 }
630
631 static inline void write_mmr_data_broadcast(int pnode, unsigned long mmr_image)
632 {
633 write_gmmr(pnode, UVH_BAU_DATA_BROADCAST, mmr_image);
634 }
635
636 static inline void write_mmr_descriptor_base(int pnode, unsigned long mmr_image)
637 {
638 write_gmmr(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, mmr_image);
639 }
640
641 static inline void write_mmr_activation(unsigned long index)
642 {
643 write_lmmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
644 }
645
646 static inline void write_gmmr_activation(int pnode, unsigned long mmr_image)
647 {
648 write_gmmr(pnode, UVH_LB_BAU_SB_ACTIVATION_CONTROL, mmr_image);
649 }
650
651 static inline void write_mmr_payload_first(int pnode, unsigned long mmr_image)
652 {
653 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, mmr_image);
654 }
655
656 static inline void write_mmr_payload_tail(int pnode, unsigned long mmr_image)
657 {
658 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, mmr_image);
659 }
660
661 static inline void write_mmr_payload_last(int pnode, unsigned long mmr_image)
662 {
663 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, mmr_image);
664 }
665
666 static inline void write_mmr_misc_control(int pnode, unsigned long mmr_image)
667 {
668 write_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
669 }
670
671 static inline unsigned long read_mmr_misc_control(int pnode)
672 {
673 return read_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL);
674 }
675
676 static inline void write_mmr_sw_ack(unsigned long mr)
677 {
678 uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
679 }
680
681 static inline void write_gmmr_sw_ack(int pnode, unsigned long mr)
682 {
683 write_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
684 }
685
686 static inline unsigned long read_mmr_sw_ack(void)
687 {
688 return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
689 }
690
691 static inline unsigned long read_gmmr_sw_ack(int pnode)
692 {
693 return read_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
694 }
695
696 static inline void write_mmr_data_config(int pnode, unsigned long mr)
697 {
698 uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, mr);
699 }
700
701 static inline int bau_uvhub_isset(int uvhub, struct pnmask *dstp)
702 {
703 return constant_test_bit(uvhub, &dstp->bits[0]);
704 }
705 static inline void bau_uvhub_set(int pnode, struct pnmask *dstp)
706 {
707 __set_bit(pnode, &dstp->bits[0]);
708 }
709 static inline void bau_uvhubs_clear(struct pnmask *dstp,
710 int nbits)
711 {
712 bitmap_zero(&dstp->bits[0], nbits);
713 }
714 static inline int bau_uvhub_weight(struct pnmask *dstp)
715 {
716 return bitmap_weight((unsigned long *)&dstp->bits[0],
717 UV_DISTRIBUTION_SIZE);
718 }
719
720 static inline void bau_cpubits_clear(struct bau_local_cpumask *dstp, int nbits)
721 {
722 bitmap_zero(&dstp->bits, nbits);
723 }
724
725 extern void uv_bau_message_intr1(void);
726 extern void uv_bau_timeout_intr1(void);
727
728 struct atomic_short {
729 short counter;
730 };
731
732 /*
733 * atomic_read_short - read a short atomic variable
734 * @v: pointer of type atomic_short
735 *
736 * Atomically reads the value of @v.
737 */
738 static inline int atomic_read_short(const struct atomic_short *v)
739 {
740 return v->counter;
741 }
742
743 /*
744 * atom_asr - add and return a short int
745 * @i: short value to add
746 * @v: pointer of type atomic_short
747 *
748 * Atomically adds @i to @v and returns @i + @v
749 */
750 static inline int atom_asr(short i, struct atomic_short *v)
751 {
752 return i + xadd(&v->counter, i);
753 }
754
755 /*
756 * conditionally add 1 to *v, unless *v is >= u
757 * return 0 if we cannot add 1 to *v because it is >= u
758 * return 1 if we can add 1 to *v because it is < u
759 * the add is atomic
760 *
761 * This is close to atomic_add_unless(), but this allows the 'u' value
762 * to be lowered below the current 'v'. atomic_add_unless can only stop
763 * on equal.
764 */
765 static inline int atomic_inc_unless_ge(spinlock_t *lock, atomic_t *v, int u)
766 {
767 spin_lock(lock);
768 if (atomic_read(v) >= u) {
769 spin_unlock(lock);
770 return 0;
771 }
772 atomic_inc(v);
773 spin_unlock(lock);
774 return 1;
775 }
776
777 #endif /* _ASM_X86_UV_UV_BAU_H */
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