2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #include <linux/slab.h>
41 #include <acpi/acpi_bus.h>
43 #include <linux/bootmem.h>
44 #include <linux/dmar.h>
45 #include <linux/hpet.h>
52 #include <asm/proto.h>
55 #include <asm/timer.h>
56 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
66 #define __apicdebuginit(type) static type __init
67 #define for_each_irq_pin(entry, head) \
68 for (entry = head; entry; entry = entry->next)
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug
= -1;
76 static DEFINE_RAW_SPINLOCK(ioapic_lock
);
77 static DEFINE_RAW_SPINLOCK(vector_lock
);
80 * # of IRQ routing registers
82 int nr_ioapic_registers
[MAX_IO_APICS
];
84 /* I/O APIC entries */
85 struct mpc_ioapic mp_ioapics
[MAX_IO_APICS
];
88 /* IO APIC gsi routing info */
89 struct mp_ioapic_gsi mp_gsi_routing
[MAX_IO_APICS
];
91 /* The one past the highest gsi number used */
94 /* MP IRQ source entries */
95 struct mpc_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
97 /* # of MP IRQ source entries */
101 static int nr_irqs_gsi
= NR_IRQS_LEGACY
;
103 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
104 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
107 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
109 int skip_ioapic_setup
;
112 * disable_ioapic_support() - disables ioapic support at runtime
114 void disable_ioapic_support(void)
118 noioapicreroute
= -1;
120 skip_ioapic_setup
= 1;
123 static int __init
parse_noapic(char *str
)
125 /* disable IO-APIC */
126 disable_ioapic_support();
129 early_param("noapic", parse_noapic
);
131 static int io_apic_setup_irq_pin_once(unsigned int irq
, int node
,
132 struct io_apic_irq_attr
*attr
);
134 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
135 void mp_save_irq(struct mpc_intsrc
*m
)
139 apic_printk(APIC_VERBOSE
, "Int: type %d, pol %d, trig %d, bus %02x,"
140 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
141 m
->irqtype
, m
->irqflag
& 3, (m
->irqflag
>> 2) & 3, m
->srcbus
,
142 m
->srcbusirq
, m
->dstapic
, m
->dstirq
);
144 for (i
= 0; i
< mp_irq_entries
; i
++) {
145 if (!memcmp(&mp_irqs
[i
], m
, sizeof(*m
)))
149 memcpy(&mp_irqs
[mp_irq_entries
], m
, sizeof(*m
));
150 if (++mp_irq_entries
== MAX_IRQ_SOURCES
)
151 panic("Max # of irq sources exceeded!!\n");
154 struct irq_pin_list
{
156 struct irq_pin_list
*next
;
159 static struct irq_pin_list
*alloc_irq_pin_list(int node
)
161 return kzalloc_node(sizeof(struct irq_pin_list
), GFP_KERNEL
, node
);
165 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
166 #ifdef CONFIG_SPARSE_IRQ
167 static struct irq_cfg irq_cfgx
[NR_IRQS_LEGACY
];
169 static struct irq_cfg irq_cfgx
[NR_IRQS
];
172 int __init
arch_early_irq_init(void)
177 if (!legacy_pic
->nr_legacy_irqs
) {
183 count
= ARRAY_SIZE(irq_cfgx
);
184 node
= cpu_to_node(0);
186 /* Make sure the legacy interrupts are marked in the bitmap */
187 irq_reserve_irqs(0, legacy_pic
->nr_legacy_irqs
);
189 for (i
= 0; i
< count
; i
++) {
190 irq_set_chip_data(i
, &cfg
[i
]);
191 zalloc_cpumask_var_node(&cfg
[i
].domain
, GFP_KERNEL
, node
);
192 zalloc_cpumask_var_node(&cfg
[i
].old_domain
, GFP_KERNEL
, node
);
194 * For legacy IRQ's, start with assigning irq0 to irq15 to
195 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
197 if (i
< legacy_pic
->nr_legacy_irqs
) {
198 cfg
[i
].vector
= IRQ0_VECTOR
+ i
;
199 cpumask_set_cpu(0, cfg
[i
].domain
);
206 #ifdef CONFIG_SPARSE_IRQ
207 static struct irq_cfg
*irq_cfg(unsigned int irq
)
209 return irq_get_chip_data(irq
);
212 static struct irq_cfg
*alloc_irq_cfg(unsigned int irq
, int node
)
216 cfg
= kzalloc_node(sizeof(*cfg
), GFP_KERNEL
, node
);
219 if (!zalloc_cpumask_var_node(&cfg
->domain
, GFP_KERNEL
, node
))
221 if (!zalloc_cpumask_var_node(&cfg
->old_domain
, GFP_KERNEL
, node
))
225 free_cpumask_var(cfg
->domain
);
231 static void free_irq_cfg(unsigned int at
, struct irq_cfg
*cfg
)
235 irq_set_chip_data(at
, NULL
);
236 free_cpumask_var(cfg
->domain
);
237 free_cpumask_var(cfg
->old_domain
);
243 struct irq_cfg
*irq_cfg(unsigned int irq
)
245 return irq
< nr_irqs
? irq_cfgx
+ irq
: NULL
;
248 static struct irq_cfg
*alloc_irq_cfg(unsigned int irq
, int node
)
250 return irq_cfgx
+ irq
;
253 static inline void free_irq_cfg(unsigned int at
, struct irq_cfg
*cfg
) { }
257 static struct irq_cfg
*alloc_irq_and_cfg_at(unsigned int at
, int node
)
259 int res
= irq_alloc_desc_at(at
, node
);
265 cfg
= irq_get_chip_data(at
);
270 cfg
= alloc_irq_cfg(at
, node
);
272 irq_set_chip_data(at
, cfg
);
278 static int alloc_irq_from(unsigned int from
, int node
)
280 return irq_alloc_desc_from(from
, node
);
283 static void free_irq_at(unsigned int at
, struct irq_cfg
*cfg
)
285 free_irq_cfg(at
, cfg
);
291 unsigned int unused
[3];
293 unsigned int unused2
[11];
297 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
299 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
300 + (mp_ioapics
[idx
].apicaddr
& ~PAGE_MASK
);
303 static inline void io_apic_eoi(unsigned int apic
, unsigned int vector
)
305 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
306 writel(vector
, &io_apic
->eoi
);
309 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
311 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
312 writel(reg
, &io_apic
->index
);
313 return readl(&io_apic
->data
);
316 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
318 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
319 writel(reg
, &io_apic
->index
);
320 writel(value
, &io_apic
->data
);
324 * Re-write a value: to be used for read-modify-write
325 * cycles where the read already set up the index register.
327 * Older SiS APIC requires we rewrite the index register
329 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
331 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
334 writel(reg
, &io_apic
->index
);
335 writel(value
, &io_apic
->data
);
338 static bool io_apic_level_ack_pending(struct irq_cfg
*cfg
)
340 struct irq_pin_list
*entry
;
343 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
344 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
349 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
350 /* Is the remote IRR bit set? */
351 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
352 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
356 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
362 struct { u32 w1
, w2
; };
363 struct IO_APIC_route_entry entry
;
366 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
368 union entry_union eu
;
370 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
371 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
372 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
373 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
378 * When we write a new IO APIC routing entry, we need to write the high
379 * word first! If the mask bit in the low word is clear, we will enable
380 * the interrupt, and we need to make sure the entry is fully populated
381 * before that happens.
384 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
386 union entry_union eu
= {{0, 0}};
389 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
390 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
393 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
396 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
397 __ioapic_write_entry(apic
, pin
, e
);
398 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
402 * When we mask an IO APIC routing entry, we need to write the low
403 * word first, in order to set the mask bit before we change the
406 static void ioapic_mask_entry(int apic
, int pin
)
409 union entry_union eu
= { .entry
.mask
= 1 };
411 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
412 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
413 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
414 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
418 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
419 * shared ISA-space IRQs, so we have to support them. We are super
420 * fast in the common case, and fast for shared ISA-space IRQs.
423 __add_pin_to_irq_node(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
425 struct irq_pin_list
**last
, *entry
;
427 /* don't allow duplicates */
428 last
= &cfg
->irq_2_pin
;
429 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
430 if (entry
->apic
== apic
&& entry
->pin
== pin
)
435 entry
= alloc_irq_pin_list(node
);
437 printk(KERN_ERR
"can not alloc irq_pin_list (%d,%d,%d)\n",
448 static void add_pin_to_irq_node(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
450 if (__add_pin_to_irq_node(cfg
, node
, apic
, pin
))
451 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
455 * Reroute an IRQ to a different pin.
457 static void __init
replace_pin_at_irq_node(struct irq_cfg
*cfg
, int node
,
458 int oldapic
, int oldpin
,
459 int newapic
, int newpin
)
461 struct irq_pin_list
*entry
;
463 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
464 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
465 entry
->apic
= newapic
;
467 /* every one is different, right? */
472 /* old apic/pin didn't exist, so just add new ones */
473 add_pin_to_irq_node(cfg
, node
, newapic
, newpin
);
476 static void __io_apic_modify_irq(struct irq_pin_list
*entry
,
477 int mask_and
, int mask_or
,
478 void (*final
)(struct irq_pin_list
*entry
))
480 unsigned int reg
, pin
;
483 reg
= io_apic_read(entry
->apic
, 0x10 + pin
* 2);
486 io_apic_modify(entry
->apic
, 0x10 + pin
* 2, reg
);
491 static void io_apic_modify_irq(struct irq_cfg
*cfg
,
492 int mask_and
, int mask_or
,
493 void (*final
)(struct irq_pin_list
*entry
))
495 struct irq_pin_list
*entry
;
497 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
498 __io_apic_modify_irq(entry
, mask_and
, mask_or
, final
);
501 static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list
*entry
)
503 __io_apic_modify_irq(entry
, ~IO_APIC_REDIR_LEVEL_TRIGGER
,
504 IO_APIC_REDIR_MASKED
, NULL
);
507 static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list
*entry
)
509 __io_apic_modify_irq(entry
, ~IO_APIC_REDIR_MASKED
,
510 IO_APIC_REDIR_LEVEL_TRIGGER
, NULL
);
513 static void io_apic_sync(struct irq_pin_list
*entry
)
516 * Synchronize the IO-APIC and the CPU by doing
517 * a dummy read from the IO-APIC
519 struct io_apic __iomem
*io_apic
;
520 io_apic
= io_apic_base(entry
->apic
);
521 readl(&io_apic
->data
);
524 static void mask_ioapic(struct irq_cfg
*cfg
)
528 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
529 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, &io_apic_sync
);
530 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
533 static void mask_ioapic_irq(struct irq_data
*data
)
535 mask_ioapic(data
->chip_data
);
538 static void __unmask_ioapic(struct irq_cfg
*cfg
)
540 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
, 0, NULL
);
543 static void unmask_ioapic(struct irq_cfg
*cfg
)
547 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
548 __unmask_ioapic(cfg
);
549 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
552 static void unmask_ioapic_irq(struct irq_data
*data
)
554 unmask_ioapic(data
->chip_data
);
557 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
559 struct IO_APIC_route_entry entry
;
561 /* Check delivery_mode to be sure we're not clearing an SMI pin */
562 entry
= ioapic_read_entry(apic
, pin
);
563 if (entry
.delivery_mode
== dest_SMI
)
566 * Disable it in the IO-APIC irq-routing table:
568 ioapic_mask_entry(apic
, pin
);
571 static void clear_IO_APIC (void)
575 for (apic
= 0; apic
< nr_ioapics
; apic
++)
576 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
577 clear_IO_APIC_pin(apic
, pin
);
582 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
583 * specific CPU-side IRQs.
587 static int pirq_entries
[MAX_PIRQS
] = {
588 [0 ... MAX_PIRQS
- 1] = -1
591 static int __init
ioapic_pirq_setup(char *str
)
594 int ints
[MAX_PIRQS
+1];
596 get_options(str
, ARRAY_SIZE(ints
), ints
);
598 apic_printk(APIC_VERBOSE
, KERN_INFO
599 "PIRQ redirection, working around broken MP-BIOS.\n");
601 if (ints
[0] < MAX_PIRQS
)
604 for (i
= 0; i
< max
; i
++) {
605 apic_printk(APIC_VERBOSE
, KERN_DEBUG
606 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
608 * PIRQs are mapped upside down, usually.
610 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
615 __setup("pirq=", ioapic_pirq_setup
);
616 #endif /* CONFIG_X86_32 */
618 struct IO_APIC_route_entry
**alloc_ioapic_entries(void)
621 struct IO_APIC_route_entry
**ioapic_entries
;
623 ioapic_entries
= kzalloc(sizeof(*ioapic_entries
) * nr_ioapics
,
628 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
629 ioapic_entries
[apic
] =
630 kzalloc(sizeof(struct IO_APIC_route_entry
) *
631 nr_ioapic_registers
[apic
], GFP_KERNEL
);
632 if (!ioapic_entries
[apic
])
636 return ioapic_entries
;
640 kfree(ioapic_entries
[apic
]);
641 kfree(ioapic_entries
);
647 * Saves all the IO-APIC RTE's
649 int save_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
656 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
657 if (!ioapic_entries
[apic
])
660 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
661 ioapic_entries
[apic
][pin
] =
662 ioapic_read_entry(apic
, pin
);
669 * Mask all IO APIC entries.
671 void mask_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
678 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
679 if (!ioapic_entries
[apic
])
682 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
683 struct IO_APIC_route_entry entry
;
685 entry
= ioapic_entries
[apic
][pin
];
688 ioapic_write_entry(apic
, pin
, entry
);
695 * Restore IO APIC entries which was saved in ioapic_entries.
697 int restore_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
704 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
705 if (!ioapic_entries
[apic
])
708 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
709 ioapic_write_entry(apic
, pin
,
710 ioapic_entries
[apic
][pin
]);
715 void free_ioapic_entries(struct IO_APIC_route_entry
**ioapic_entries
)
719 for (apic
= 0; apic
< nr_ioapics
; apic
++)
720 kfree(ioapic_entries
[apic
]);
722 kfree(ioapic_entries
);
726 * Find the IRQ entry number of a certain pin.
728 static int find_irq_entry(int apic
, int pin
, int type
)
732 for (i
= 0; i
< mp_irq_entries
; i
++)
733 if (mp_irqs
[i
].irqtype
== type
&&
734 (mp_irqs
[i
].dstapic
== mp_ioapics
[apic
].apicid
||
735 mp_irqs
[i
].dstapic
== MP_APIC_ALL
) &&
736 mp_irqs
[i
].dstirq
== pin
)
743 * Find the pin to which IRQ[irq] (ISA) is connected
745 static int __init
find_isa_irq_pin(int irq
, int type
)
749 for (i
= 0; i
< mp_irq_entries
; i
++) {
750 int lbus
= mp_irqs
[i
].srcbus
;
752 if (test_bit(lbus
, mp_bus_not_pci
) &&
753 (mp_irqs
[i
].irqtype
== type
) &&
754 (mp_irqs
[i
].srcbusirq
== irq
))
756 return mp_irqs
[i
].dstirq
;
761 static int __init
find_isa_irq_apic(int irq
, int type
)
765 for (i
= 0; i
< mp_irq_entries
; i
++) {
766 int lbus
= mp_irqs
[i
].srcbus
;
768 if (test_bit(lbus
, mp_bus_not_pci
) &&
769 (mp_irqs
[i
].irqtype
== type
) &&
770 (mp_irqs
[i
].srcbusirq
== irq
))
773 if (i
< mp_irq_entries
) {
775 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
776 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
)
784 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
786 * EISA Edge/Level control register, ELCR
788 static int EISA_ELCR(unsigned int irq
)
790 if (irq
< legacy_pic
->nr_legacy_irqs
) {
791 unsigned int port
= 0x4d0 + (irq
>> 3);
792 return (inb(port
) >> (irq
& 7)) & 1;
794 apic_printk(APIC_VERBOSE
, KERN_INFO
795 "Broken MPtable reports ISA irq %d\n", irq
);
801 /* ISA interrupts are always polarity zero edge triggered,
802 * when listed as conforming in the MP table. */
804 #define default_ISA_trigger(idx) (0)
805 #define default_ISA_polarity(idx) (0)
807 /* EISA interrupts are always polarity zero and can be edge or level
808 * trigger depending on the ELCR value. If an interrupt is listed as
809 * EISA conforming in the MP table, that means its trigger type must
810 * be read in from the ELCR */
812 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
813 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
815 /* PCI interrupts are always polarity one level triggered,
816 * when listed as conforming in the MP table. */
818 #define default_PCI_trigger(idx) (1)
819 #define default_PCI_polarity(idx) (1)
821 /* MCA interrupts are always polarity zero level triggered,
822 * when listed as conforming in the MP table. */
824 #define default_MCA_trigger(idx) (1)
825 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
827 static int irq_polarity(int idx
)
829 int bus
= mp_irqs
[idx
].srcbus
;
833 * Determine IRQ line polarity (high active or low active):
835 switch (mp_irqs
[idx
].irqflag
& 3)
837 case 0: /* conforms, ie. bus-type dependent polarity */
838 if (test_bit(bus
, mp_bus_not_pci
))
839 polarity
= default_ISA_polarity(idx
);
841 polarity
= default_PCI_polarity(idx
);
843 case 1: /* high active */
848 case 2: /* reserved */
850 printk(KERN_WARNING
"broken BIOS!!\n");
854 case 3: /* low active */
859 default: /* invalid */
861 printk(KERN_WARNING
"broken BIOS!!\n");
869 static int irq_trigger(int idx
)
871 int bus
= mp_irqs
[idx
].srcbus
;
875 * Determine IRQ trigger mode (edge or level sensitive):
877 switch ((mp_irqs
[idx
].irqflag
>>2) & 3)
879 case 0: /* conforms, ie. bus-type dependent */
880 if (test_bit(bus
, mp_bus_not_pci
))
881 trigger
= default_ISA_trigger(idx
);
883 trigger
= default_PCI_trigger(idx
);
884 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
885 switch (mp_bus_id_to_type
[bus
]) {
886 case MP_BUS_ISA
: /* ISA pin */
888 /* set before the switch */
891 case MP_BUS_EISA
: /* EISA pin */
893 trigger
= default_EISA_trigger(idx
);
896 case MP_BUS_PCI
: /* PCI pin */
898 /* set before the switch */
901 case MP_BUS_MCA
: /* MCA pin */
903 trigger
= default_MCA_trigger(idx
);
908 printk(KERN_WARNING
"broken BIOS!!\n");
920 case 2: /* reserved */
922 printk(KERN_WARNING
"broken BIOS!!\n");
931 default: /* invalid */
933 printk(KERN_WARNING
"broken BIOS!!\n");
941 static int pin_2_irq(int idx
, int apic
, int pin
)
944 int bus
= mp_irqs
[idx
].srcbus
;
947 * Debugging check, we are in big trouble if this message pops up!
949 if (mp_irqs
[idx
].dstirq
!= pin
)
950 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
952 if (test_bit(bus
, mp_bus_not_pci
)) {
953 irq
= mp_irqs
[idx
].srcbusirq
;
955 u32 gsi
= mp_gsi_routing
[apic
].gsi_base
+ pin
;
957 if (gsi
>= NR_IRQS_LEGACY
)
965 * PCI IRQ command line redirection. Yes, limits are hardcoded.
967 if ((pin
>= 16) && (pin
<= 23)) {
968 if (pirq_entries
[pin
-16] != -1) {
969 if (!pirq_entries
[pin
-16]) {
970 apic_printk(APIC_VERBOSE
, KERN_DEBUG
971 "disabling PIRQ%d\n", pin
-16);
973 irq
= pirq_entries
[pin
-16];
974 apic_printk(APIC_VERBOSE
, KERN_DEBUG
975 "using PIRQ%d -> IRQ %d\n",
986 * Find a specific PCI IRQ entry.
987 * Not an __init, possibly needed by modules
989 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
,
990 struct io_apic_irq_attr
*irq_attr
)
992 int apic
, i
, best_guess
= -1;
994 apic_printk(APIC_DEBUG
,
995 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
997 if (test_bit(bus
, mp_bus_not_pci
)) {
998 apic_printk(APIC_VERBOSE
,
999 "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
1002 for (i
= 0; i
< mp_irq_entries
; i
++) {
1003 int lbus
= mp_irqs
[i
].srcbus
;
1005 for (apic
= 0; apic
< nr_ioapics
; apic
++)
1006 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
||
1007 mp_irqs
[i
].dstapic
== MP_APIC_ALL
)
1010 if (!test_bit(lbus
, mp_bus_not_pci
) &&
1011 !mp_irqs
[i
].irqtype
&&
1013 (slot
== ((mp_irqs
[i
].srcbusirq
>> 2) & 0x1f))) {
1014 int irq
= pin_2_irq(i
, apic
, mp_irqs
[i
].dstirq
);
1016 if (!(apic
|| IO_APIC_IRQ(irq
)))
1019 if (pin
== (mp_irqs
[i
].srcbusirq
& 3)) {
1020 set_io_apic_irq_attr(irq_attr
, apic
,
1027 * Use the first all-but-pin matching entry as a
1028 * best-guess fuzzy result for broken mptables.
1030 if (best_guess
< 0) {
1031 set_io_apic_irq_attr(irq_attr
, apic
,
1041 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
1043 void lock_vector_lock(void)
1045 /* Used to the online set of cpus does not change
1046 * during assign_irq_vector.
1048 raw_spin_lock(&vector_lock
);
1051 void unlock_vector_lock(void)
1053 raw_spin_unlock(&vector_lock
);
1057 __assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1060 * NOTE! The local APIC isn't very good at handling
1061 * multiple interrupts at the same interrupt level.
1062 * As the interrupt level is determined by taking the
1063 * vector number and shifting that right by 4, we
1064 * want to spread these out a bit so that they don't
1065 * all fall in the same interrupt level.
1067 * Also, we've got to be careful not to trash gate
1068 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1070 static int current_vector
= FIRST_EXTERNAL_VECTOR
+ VECTOR_OFFSET_START
;
1071 static int current_offset
= VECTOR_OFFSET_START
% 8;
1072 unsigned int old_vector
;
1074 cpumask_var_t tmp_mask
;
1076 if (cfg
->move_in_progress
)
1079 if (!alloc_cpumask_var(&tmp_mask
, GFP_ATOMIC
))
1082 old_vector
= cfg
->vector
;
1084 cpumask_and(tmp_mask
, mask
, cpu_online_mask
);
1085 cpumask_and(tmp_mask
, cfg
->domain
, tmp_mask
);
1086 if (!cpumask_empty(tmp_mask
)) {
1087 free_cpumask_var(tmp_mask
);
1092 /* Only try and allocate irqs on cpus that are present */
1094 for_each_cpu_and(cpu
, mask
, cpu_online_mask
) {
1098 apic
->vector_allocation_domain(cpu
, tmp_mask
);
1100 vector
= current_vector
;
1101 offset
= current_offset
;
1104 if (vector
>= first_system_vector
) {
1105 /* If out of vectors on large boxen, must share them. */
1106 offset
= (offset
+ 1) % 8;
1107 vector
= FIRST_EXTERNAL_VECTOR
+ offset
;
1109 if (unlikely(current_vector
== vector
))
1112 if (test_bit(vector
, used_vectors
))
1115 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1116 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1119 current_vector
= vector
;
1120 current_offset
= offset
;
1122 cfg
->move_in_progress
= 1;
1123 cpumask_copy(cfg
->old_domain
, cfg
->domain
);
1125 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1126 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1127 cfg
->vector
= vector
;
1128 cpumask_copy(cfg
->domain
, tmp_mask
);
1132 free_cpumask_var(tmp_mask
);
1136 int assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1139 unsigned long flags
;
1141 raw_spin_lock_irqsave(&vector_lock
, flags
);
1142 err
= __assign_irq_vector(irq
, cfg
, mask
);
1143 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
1147 static void __clear_irq_vector(int irq
, struct irq_cfg
*cfg
)
1151 BUG_ON(!cfg
->vector
);
1153 vector
= cfg
->vector
;
1154 for_each_cpu_and(cpu
, cfg
->domain
, cpu_online_mask
)
1155 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1158 cpumask_clear(cfg
->domain
);
1160 if (likely(!cfg
->move_in_progress
))
1162 for_each_cpu_and(cpu
, cfg
->old_domain
, cpu_online_mask
) {
1163 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
;
1165 if (per_cpu(vector_irq
, cpu
)[vector
] != irq
)
1167 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1171 cfg
->move_in_progress
= 0;
1174 void __setup_vector_irq(int cpu
)
1176 /* Initialize vector_irq on a new cpu */
1178 struct irq_cfg
*cfg
;
1181 * vector_lock will make sure that we don't run into irq vector
1182 * assignments that might be happening on another cpu in parallel,
1183 * while we setup our initial vector to irq mappings.
1185 raw_spin_lock(&vector_lock
);
1186 /* Mark the inuse vectors */
1187 for_each_active_irq(irq
) {
1188 cfg
= irq_get_chip_data(irq
);
1192 * If it is a legacy IRQ handled by the legacy PIC, this cpu
1193 * will be part of the irq_cfg's domain.
1195 if (irq
< legacy_pic
->nr_legacy_irqs
&& !IO_APIC_IRQ(irq
))
1196 cpumask_set_cpu(cpu
, cfg
->domain
);
1198 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1200 vector
= cfg
->vector
;
1201 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1203 /* Mark the free vectors */
1204 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1205 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1210 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1211 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1213 raw_spin_unlock(&vector_lock
);
1216 static struct irq_chip ioapic_chip
;
1217 static struct irq_chip ir_ioapic_chip
;
1219 #ifdef CONFIG_X86_32
1220 static inline int IO_APIC_irq_trigger(int irq
)
1224 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1225 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1226 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1227 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1228 return irq_trigger(idx
);
1232 * nonexistent IRQs are edge default
1237 static inline int IO_APIC_irq_trigger(int irq
)
1243 static void ioapic_register_intr(unsigned int irq
, struct irq_cfg
*cfg
,
1244 unsigned long trigger
)
1246 struct irq_chip
*chip
= &ioapic_chip
;
1247 irq_flow_handler_t hdl
;
1250 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1251 trigger
== IOAPIC_LEVEL
) {
1252 irq_set_status_flags(irq
, IRQ_LEVEL
);
1255 irq_clear_status_flags(irq
, IRQ_LEVEL
);
1259 if (irq_remapped(cfg
)) {
1260 irq_set_status_flags(irq
, IRQ_MOVE_PCNTXT
);
1261 chip
= &ir_ioapic_chip
;
1262 fasteoi
= trigger
!= 0;
1265 hdl
= fasteoi
? handle_fasteoi_irq
: handle_edge_irq
;
1266 irq_set_chip_and_handler_name(irq
, chip
, hdl
,
1267 fasteoi
? "fasteoi" : "edge");
1270 static int setup_ioapic_entry(int apic_id
, int irq
,
1271 struct IO_APIC_route_entry
*entry
,
1272 unsigned int destination
, int trigger
,
1273 int polarity
, int vector
, int pin
)
1276 * add it to the IO-APIC irq-routing table:
1278 memset(entry
,0,sizeof(*entry
));
1280 if (intr_remapping_enabled
) {
1281 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic_id
);
1283 struct IR_IO_APIC_route_entry
*ir_entry
=
1284 (struct IR_IO_APIC_route_entry
*) entry
;
1288 panic("No mapping iommu for ioapic %d\n", apic_id
);
1290 index
= alloc_irte(iommu
, irq
, 1);
1292 panic("Failed to allocate IRTE for ioapic %d\n", apic_id
);
1294 prepare_irte(&irte
, vector
, destination
);
1296 /* Set source-id of interrupt request */
1297 set_ioapic_sid(&irte
, apic_id
);
1299 modify_irte(irq
, &irte
);
1301 ir_entry
->index2
= (index
>> 15) & 0x1;
1303 ir_entry
->format
= 1;
1304 ir_entry
->index
= (index
& 0x7fff);
1306 * IO-APIC RTE will be configured with virtual vector.
1307 * irq handler will do the explicit EOI to the io-apic.
1309 ir_entry
->vector
= pin
;
1311 entry
->delivery_mode
= apic
->irq_delivery_mode
;
1312 entry
->dest_mode
= apic
->irq_dest_mode
;
1313 entry
->dest
= destination
;
1314 entry
->vector
= vector
;
1317 entry
->mask
= 0; /* enable IRQ */
1318 entry
->trigger
= trigger
;
1319 entry
->polarity
= polarity
;
1321 /* Mask level triggered irqs.
1322 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1329 static void setup_ioapic_irq(int apic_id
, int pin
, unsigned int irq
,
1330 struct irq_cfg
*cfg
, int trigger
, int polarity
)
1332 struct IO_APIC_route_entry entry
;
1335 if (!IO_APIC_IRQ(irq
))
1338 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1339 * controllers like 8259. Now that IO-APIC can handle this irq, update
1342 if (irq
< legacy_pic
->nr_legacy_irqs
&& cpumask_test_cpu(0, cfg
->domain
))
1343 apic
->vector_allocation_domain(0, cfg
->domain
);
1345 if (assign_irq_vector(irq
, cfg
, apic
->target_cpus()))
1348 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
1350 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1351 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1352 "IRQ %d Mode:%i Active:%i)\n",
1353 apic_id
, mp_ioapics
[apic_id
].apicid
, pin
, cfg
->vector
,
1354 irq
, trigger
, polarity
);
1357 if (setup_ioapic_entry(mp_ioapics
[apic_id
].apicid
, irq
, &entry
,
1358 dest
, trigger
, polarity
, cfg
->vector
, pin
)) {
1359 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1360 mp_ioapics
[apic_id
].apicid
, pin
);
1361 __clear_irq_vector(irq
, cfg
);
1365 ioapic_register_intr(irq
, cfg
, trigger
);
1366 if (irq
< legacy_pic
->nr_legacy_irqs
)
1367 legacy_pic
->mask(irq
);
1369 ioapic_write_entry(apic_id
, pin
, entry
);
1373 DECLARE_BITMAP(pin_programmed
, MP_MAX_IOAPIC_PIN
+ 1);
1374 } mp_ioapic_routing
[MAX_IO_APICS
];
1376 static bool __init
io_apic_pin_not_connected(int idx
, int apic_id
, int pin
)
1381 apic_printk(APIC_VERBOSE
, KERN_DEBUG
" apic %d pin %d not connected\n",
1382 mp_ioapics
[apic_id
].apicid
, pin
);
1386 static void __init
__io_apic_setup_irqs(unsigned int apic_id
)
1388 int idx
, node
= cpu_to_node(0);
1389 struct io_apic_irq_attr attr
;
1390 unsigned int pin
, irq
;
1392 for (pin
= 0; pin
< nr_ioapic_registers
[apic_id
]; pin
++) {
1393 idx
= find_irq_entry(apic_id
, pin
, mp_INT
);
1394 if (io_apic_pin_not_connected(idx
, apic_id
, pin
))
1397 irq
= pin_2_irq(idx
, apic_id
, pin
);
1399 if ((apic_id
> 0) && (irq
> 16))
1403 * Skip the timer IRQ if there's a quirk handler
1404 * installed and if it returns 1:
1406 if (apic
->multi_timer_check
&&
1407 apic
->multi_timer_check(apic_id
, irq
))
1410 set_io_apic_irq_attr(&attr
, apic_id
, pin
, irq_trigger(idx
),
1413 io_apic_setup_irq_pin(irq
, node
, &attr
);
1417 static void __init
setup_IO_APIC_irqs(void)
1419 unsigned int apic_id
;
1421 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1423 for (apic_id
= 0; apic_id
< nr_ioapics
; apic_id
++)
1424 __io_apic_setup_irqs(apic_id
);
1428 * for the gsit that is not in first ioapic
1429 * but could not use acpi_register_gsi()
1430 * like some special sci in IBM x3330
1432 void setup_IO_APIC_irq_extra(u32 gsi
)
1434 int apic_id
= 0, pin
, idx
, irq
, node
= cpu_to_node(0);
1435 struct io_apic_irq_attr attr
;
1438 * Convert 'gsi' to 'ioapic.pin'.
1440 apic_id
= mp_find_ioapic(gsi
);
1444 pin
= mp_find_ioapic_pin(apic_id
, gsi
);
1445 idx
= find_irq_entry(apic_id
, pin
, mp_INT
);
1449 irq
= pin_2_irq(idx
, apic_id
, pin
);
1451 /* Only handle the non legacy irqs on secondary ioapics */
1452 if (apic_id
== 0 || irq
< NR_IRQS_LEGACY
)
1455 set_io_apic_irq_attr(&attr
, apic_id
, pin
, irq_trigger(idx
),
1458 io_apic_setup_irq_pin_once(irq
, node
, &attr
);
1462 * Set up the timer pin, possibly with the 8259A-master behind.
1464 static void __init
setup_timer_IRQ0_pin(unsigned int apic_id
, unsigned int pin
,
1467 struct IO_APIC_route_entry entry
;
1469 if (intr_remapping_enabled
)
1472 memset(&entry
, 0, sizeof(entry
));
1475 * We use logical delivery to get the timer IRQ
1478 entry
.dest_mode
= apic
->irq_dest_mode
;
1479 entry
.mask
= 0; /* don't mask IRQ for edge */
1480 entry
.dest
= apic
->cpu_mask_to_apicid(apic
->target_cpus());
1481 entry
.delivery_mode
= apic
->irq_delivery_mode
;
1484 entry
.vector
= vector
;
1487 * The timer IRQ doesn't have to know that behind the
1488 * scene we may have a 8259A-master in AEOI mode ...
1490 irq_set_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
,
1494 * Add it to the IO-APIC irq-routing table:
1496 ioapic_write_entry(apic_id
, pin
, entry
);
1500 __apicdebuginit(void) print_IO_APIC(void)
1503 union IO_APIC_reg_00 reg_00
;
1504 union IO_APIC_reg_01 reg_01
;
1505 union IO_APIC_reg_02 reg_02
;
1506 union IO_APIC_reg_03 reg_03
;
1507 unsigned long flags
;
1508 struct irq_cfg
*cfg
;
1511 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1512 for (i
= 0; i
< nr_ioapics
; i
++)
1513 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1514 mp_ioapics
[i
].apicid
, nr_ioapic_registers
[i
]);
1517 * We are a bit conservative about what we expect. We have to
1518 * know about every hardware change ASAP.
1520 printk(KERN_INFO
"testing the IO APIC.......................\n");
1522 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1524 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1525 reg_00
.raw
= io_apic_read(apic
, 0);
1526 reg_01
.raw
= io_apic_read(apic
, 1);
1527 if (reg_01
.bits
.version
>= 0x10)
1528 reg_02
.raw
= io_apic_read(apic
, 2);
1529 if (reg_01
.bits
.version
>= 0x20)
1530 reg_03
.raw
= io_apic_read(apic
, 3);
1531 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1534 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].apicid
);
1535 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1536 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1537 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1538 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1540 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1541 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1543 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1544 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1547 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1548 * but the value of reg_02 is read as the previous read register
1549 * value, so ignore it if reg_02 == reg_01.
1551 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1552 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1553 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1557 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1558 * or reg_03, but the value of reg_0[23] is read as the previous read
1559 * register value, so ignore it if reg_03 == reg_0[12].
1561 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1562 reg_03
.raw
!= reg_01
.raw
) {
1563 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1564 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1567 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1569 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1570 " Stat Dmod Deli Vect:\n");
1572 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1573 struct IO_APIC_route_entry entry
;
1575 entry
= ioapic_read_entry(apic
, i
);
1577 printk(KERN_DEBUG
" %02x %03X ",
1582 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1587 entry
.delivery_status
,
1589 entry
.delivery_mode
,
1594 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1595 for_each_active_irq(irq
) {
1596 struct irq_pin_list
*entry
;
1598 cfg
= irq_get_chip_data(irq
);
1601 entry
= cfg
->irq_2_pin
;
1604 printk(KERN_DEBUG
"IRQ%d ", irq
);
1605 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
1606 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1610 printk(KERN_INFO
".................................... done.\n");
1615 __apicdebuginit(void) print_APIC_field(int base
)
1621 for (i
= 0; i
< 8; i
++)
1622 printk(KERN_CONT
"%08x", apic_read(base
+ i
*0x10));
1624 printk(KERN_CONT
"\n");
1627 __apicdebuginit(void) print_local_APIC(void *dummy
)
1629 unsigned int i
, v
, ver
, maxlvt
;
1632 printk(KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1633 smp_processor_id(), hard_smp_processor_id());
1634 v
= apic_read(APIC_ID
);
1635 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1636 v
= apic_read(APIC_LVR
);
1637 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1638 ver
= GET_APIC_VERSION(v
);
1639 maxlvt
= lapic_get_maxlvt();
1641 v
= apic_read(APIC_TASKPRI
);
1642 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1644 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1645 if (!APIC_XAPIC(ver
)) {
1646 v
= apic_read(APIC_ARBPRI
);
1647 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1648 v
& APIC_ARBPRI_MASK
);
1650 v
= apic_read(APIC_PROCPRI
);
1651 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1655 * Remote read supported only in the 82489DX and local APIC for
1656 * Pentium processors.
1658 if (!APIC_INTEGRATED(ver
) || maxlvt
== 3) {
1659 v
= apic_read(APIC_RRR
);
1660 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1663 v
= apic_read(APIC_LDR
);
1664 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1665 if (!x2apic_enabled()) {
1666 v
= apic_read(APIC_DFR
);
1667 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1669 v
= apic_read(APIC_SPIV
);
1670 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1672 printk(KERN_DEBUG
"... APIC ISR field:\n");
1673 print_APIC_field(APIC_ISR
);
1674 printk(KERN_DEBUG
"... APIC TMR field:\n");
1675 print_APIC_field(APIC_TMR
);
1676 printk(KERN_DEBUG
"... APIC IRR field:\n");
1677 print_APIC_field(APIC_IRR
);
1679 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1680 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1681 apic_write(APIC_ESR
, 0);
1683 v
= apic_read(APIC_ESR
);
1684 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1687 icr
= apic_icr_read();
1688 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1689 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1691 v
= apic_read(APIC_LVTT
);
1692 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1694 if (maxlvt
> 3) { /* PC is LVT#4. */
1695 v
= apic_read(APIC_LVTPC
);
1696 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1698 v
= apic_read(APIC_LVT0
);
1699 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1700 v
= apic_read(APIC_LVT1
);
1701 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1703 if (maxlvt
> 2) { /* ERR is LVT#3. */
1704 v
= apic_read(APIC_LVTERR
);
1705 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1708 v
= apic_read(APIC_TMICT
);
1709 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1710 v
= apic_read(APIC_TMCCT
);
1711 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1712 v
= apic_read(APIC_TDCR
);
1713 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1715 if (boot_cpu_has(X86_FEATURE_EXTAPIC
)) {
1716 v
= apic_read(APIC_EFEAT
);
1717 maxlvt
= (v
>> 16) & 0xff;
1718 printk(KERN_DEBUG
"... APIC EFEAT: %08x\n", v
);
1719 v
= apic_read(APIC_ECTRL
);
1720 printk(KERN_DEBUG
"... APIC ECTRL: %08x\n", v
);
1721 for (i
= 0; i
< maxlvt
; i
++) {
1722 v
= apic_read(APIC_EILVTn(i
));
1723 printk(KERN_DEBUG
"... APIC EILVT%d: %08x\n", i
, v
);
1729 __apicdebuginit(void) print_local_APICs(int maxcpu
)
1737 for_each_online_cpu(cpu
) {
1740 smp_call_function_single(cpu
, print_local_APIC
, NULL
, 1);
1745 __apicdebuginit(void) print_PIC(void)
1748 unsigned long flags
;
1750 if (!legacy_pic
->nr_legacy_irqs
)
1753 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1755 raw_spin_lock_irqsave(&i8259A_lock
, flags
);
1757 v
= inb(0xa1) << 8 | inb(0x21);
1758 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1760 v
= inb(0xa0) << 8 | inb(0x20);
1761 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1765 v
= inb(0xa0) << 8 | inb(0x20);
1769 raw_spin_unlock_irqrestore(&i8259A_lock
, flags
);
1771 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1773 v
= inb(0x4d1) << 8 | inb(0x4d0);
1774 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1777 static int __initdata show_lapic
= 1;
1778 static __init
int setup_show_lapic(char *arg
)
1782 if (strcmp(arg
, "all") == 0) {
1783 show_lapic
= CONFIG_NR_CPUS
;
1785 get_option(&arg
, &num
);
1792 __setup("show_lapic=", setup_show_lapic
);
1794 __apicdebuginit(int) print_ICs(void)
1796 if (apic_verbosity
== APIC_QUIET
)
1801 /* don't print out if apic is not there */
1802 if (!cpu_has_apic
&& !apic_from_smp_config())
1805 print_local_APICs(show_lapic
);
1811 fs_initcall(print_ICs
);
1814 /* Where if anywhere is the i8259 connect in external int mode */
1815 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1817 void __init
enable_IO_APIC(void)
1819 int i8259_apic
, i8259_pin
;
1822 if (!legacy_pic
->nr_legacy_irqs
)
1825 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1827 /* See if any of the pins is in ExtINT mode */
1828 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1829 struct IO_APIC_route_entry entry
;
1830 entry
= ioapic_read_entry(apic
, pin
);
1832 /* If the interrupt line is enabled and in ExtInt mode
1833 * I have found the pin where the i8259 is connected.
1835 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1836 ioapic_i8259
.apic
= apic
;
1837 ioapic_i8259
.pin
= pin
;
1843 /* Look to see what if the MP table has reported the ExtINT */
1844 /* If we could not find the appropriate pin by looking at the ioapic
1845 * the i8259 probably is not connected the ioapic but give the
1846 * mptable a chance anyway.
1848 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1849 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1850 /* Trust the MP table if nothing is setup in the hardware */
1851 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1852 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1853 ioapic_i8259
.pin
= i8259_pin
;
1854 ioapic_i8259
.apic
= i8259_apic
;
1856 /* Complain if the MP table and the hardware disagree */
1857 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1858 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1860 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1864 * Do not trust the IO-APIC being empty at bootup
1870 * Not an __init, needed by the reboot code
1872 void disable_IO_APIC(void)
1875 * Clear the IO-APIC before rebooting:
1879 if (!legacy_pic
->nr_legacy_irqs
)
1883 * If the i8259 is routed through an IOAPIC
1884 * Put that IOAPIC in virtual wire mode
1885 * so legacy interrupts can be delivered.
1887 * With interrupt-remapping, for now we will use virtual wire A mode,
1888 * as virtual wire B is little complex (need to configure both
1889 * IOAPIC RTE as well as interrupt-remapping table entry).
1890 * As this gets called during crash dump, keep this simple for now.
1892 if (ioapic_i8259
.pin
!= -1 && !intr_remapping_enabled
) {
1893 struct IO_APIC_route_entry entry
;
1895 memset(&entry
, 0, sizeof(entry
));
1896 entry
.mask
= 0; /* Enabled */
1897 entry
.trigger
= 0; /* Edge */
1899 entry
.polarity
= 0; /* High */
1900 entry
.delivery_status
= 0;
1901 entry
.dest_mode
= 0; /* Physical */
1902 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1904 entry
.dest
= read_apic_id();
1907 * Add it to the IO-APIC irq-routing table:
1909 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1913 * Use virtual wire A mode when interrupt remapping is enabled.
1915 if (cpu_has_apic
|| apic_from_smp_config())
1916 disconnect_bsp_APIC(!intr_remapping_enabled
&&
1917 ioapic_i8259
.pin
!= -1);
1920 #ifdef CONFIG_X86_32
1922 * function to set the IO-APIC physical IDs based on the
1923 * values stored in the MPC table.
1925 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1927 void __init
setup_ioapic_ids_from_mpc_nocheck(void)
1929 union IO_APIC_reg_00 reg_00
;
1930 physid_mask_t phys_id_present_map
;
1933 unsigned char old_id
;
1934 unsigned long flags
;
1937 * This is broken; anything with a real cpu count has to
1938 * circumvent this idiocy regardless.
1940 apic
->ioapic_phys_id_map(&phys_cpu_present_map
, &phys_id_present_map
);
1943 * Set the IOAPIC ID to the value stored in the MPC table.
1945 for (apic_id
= 0; apic_id
< nr_ioapics
; apic_id
++) {
1947 /* Read the register 0 value */
1948 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1949 reg_00
.raw
= io_apic_read(apic_id
, 0);
1950 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1952 old_id
= mp_ioapics
[apic_id
].apicid
;
1954 if (mp_ioapics
[apic_id
].apicid
>= get_physical_broadcast()) {
1955 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1956 apic_id
, mp_ioapics
[apic_id
].apicid
);
1957 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1959 mp_ioapics
[apic_id
].apicid
= reg_00
.bits
.ID
;
1963 * Sanity check, is the ID really free? Every APIC in a
1964 * system must have a unique ID or we get lots of nice
1965 * 'stuck on smp_invalidate_needed IPI wait' messages.
1967 if (apic
->check_apicid_used(&phys_id_present_map
,
1968 mp_ioapics
[apic_id
].apicid
)) {
1969 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1970 apic_id
, mp_ioapics
[apic_id
].apicid
);
1971 for (i
= 0; i
< get_physical_broadcast(); i
++)
1972 if (!physid_isset(i
, phys_id_present_map
))
1974 if (i
>= get_physical_broadcast())
1975 panic("Max APIC ID exceeded!\n");
1976 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1978 physid_set(i
, phys_id_present_map
);
1979 mp_ioapics
[apic_id
].apicid
= i
;
1982 apic
->apicid_to_cpu_present(mp_ioapics
[apic_id
].apicid
, &tmp
);
1983 apic_printk(APIC_VERBOSE
, "Setting %d in the "
1984 "phys_id_present_map\n",
1985 mp_ioapics
[apic_id
].apicid
);
1986 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
1990 * We need to adjust the IRQ routing table
1991 * if the ID changed.
1993 if (old_id
!= mp_ioapics
[apic_id
].apicid
)
1994 for (i
= 0; i
< mp_irq_entries
; i
++)
1995 if (mp_irqs
[i
].dstapic
== old_id
)
1997 = mp_ioapics
[apic_id
].apicid
;
2000 * Update the ID register according to the right value
2001 * from the MPC table if they are different.
2003 if (mp_ioapics
[apic_id
].apicid
== reg_00
.bits
.ID
)
2006 apic_printk(APIC_VERBOSE
, KERN_INFO
2007 "...changing IO-APIC physical APIC ID to %d ...",
2008 mp_ioapics
[apic_id
].apicid
);
2010 reg_00
.bits
.ID
= mp_ioapics
[apic_id
].apicid
;
2011 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2012 io_apic_write(apic_id
, 0, reg_00
.raw
);
2013 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2018 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2019 reg_00
.raw
= io_apic_read(apic_id
, 0);
2020 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2021 if (reg_00
.bits
.ID
!= mp_ioapics
[apic_id
].apicid
)
2022 printk("could not set ID!\n");
2024 apic_printk(APIC_VERBOSE
, " ok.\n");
2028 void __init
setup_ioapic_ids_from_mpc(void)
2034 * Don't check I/O APIC IDs for xAPIC systems. They have
2035 * no meaning without the serial APIC bus.
2037 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
2038 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
2040 setup_ioapic_ids_from_mpc_nocheck();
2044 int no_timer_check __initdata
;
2046 static int __init
notimercheck(char *s
)
2051 __setup("no_timer_check", notimercheck
);
2054 * There is a nasty bug in some older SMP boards, their mptable lies
2055 * about the timer IRQ. We do the following to work around the situation:
2057 * - timer IRQ defaults to IO-APIC IRQ
2058 * - if this function detects that timer IRQs are defunct, then we fall
2059 * back to ISA timer IRQs
2061 static int __init
timer_irq_works(void)
2063 unsigned long t1
= jiffies
;
2064 unsigned long flags
;
2069 local_save_flags(flags
);
2071 /* Let ten ticks pass... */
2072 mdelay((10 * 1000) / HZ
);
2073 local_irq_restore(flags
);
2076 * Expect a few ticks at least, to be sure some possible
2077 * glue logic does not lock up after one or two first
2078 * ticks in a non-ExtINT mode. Also the local APIC
2079 * might have cached one ExtINT interrupt. Finally, at
2080 * least one tick may be lost due to delays.
2084 if (time_after(jiffies
, t1
+ 4))
2090 * In the SMP+IOAPIC case it might happen that there are an unspecified
2091 * number of pending IRQ events unhandled. These cases are very rare,
2092 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2093 * better to do it this way as thus we do not have to be aware of
2094 * 'pending' interrupts in the IRQ path, except at this point.
2097 * Edge triggered needs to resend any interrupt
2098 * that was delayed but this is now handled in the device
2103 * Starting up a edge-triggered IO-APIC interrupt is
2104 * nasty - we need to make sure that we get the edge.
2105 * If it is already asserted for some reason, we need
2106 * return 1 to indicate that is was pending.
2108 * This is not complete - we should be able to fake
2109 * an edge even if it isn't on the 8259A...
2112 static unsigned int startup_ioapic_irq(struct irq_data
*data
)
2114 int was_pending
= 0, irq
= data
->irq
;
2115 unsigned long flags
;
2117 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2118 if (irq
< legacy_pic
->nr_legacy_irqs
) {
2119 legacy_pic
->mask(irq
);
2120 if (legacy_pic
->irq_pending(irq
))
2123 __unmask_ioapic(data
->chip_data
);
2124 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2129 static int ioapic_retrigger_irq(struct irq_data
*data
)
2131 struct irq_cfg
*cfg
= data
->chip_data
;
2132 unsigned long flags
;
2134 raw_spin_lock_irqsave(&vector_lock
, flags
);
2135 apic
->send_IPI_mask(cpumask_of(cpumask_first(cfg
->domain
)), cfg
->vector
);
2136 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
2142 * Level and edge triggered IO-APIC interrupts need different handling,
2143 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2144 * handled with the level-triggered descriptor, but that one has slightly
2145 * more overhead. Level-triggered interrupts cannot be handled with the
2146 * edge-triggered handler, without risking IRQ storms and other ugly
2151 void send_cleanup_vector(struct irq_cfg
*cfg
)
2153 cpumask_var_t cleanup_mask
;
2155 if (unlikely(!alloc_cpumask_var(&cleanup_mask
, GFP_ATOMIC
))) {
2157 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
2158 apic
->send_IPI_mask(cpumask_of(i
), IRQ_MOVE_CLEANUP_VECTOR
);
2160 cpumask_and(cleanup_mask
, cfg
->old_domain
, cpu_online_mask
);
2161 apic
->send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2162 free_cpumask_var(cleanup_mask
);
2164 cfg
->move_in_progress
= 0;
2167 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, struct irq_cfg
*cfg
)
2170 struct irq_pin_list
*entry
;
2171 u8 vector
= cfg
->vector
;
2173 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
2179 * With interrupt-remapping, destination information comes
2180 * from interrupt-remapping table entry.
2182 if (!irq_remapped(cfg
))
2183 io_apic_write(apic
, 0x11 + pin
*2, dest
);
2184 reg
= io_apic_read(apic
, 0x10 + pin
*2);
2185 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
2187 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
2192 * Either sets data->affinity to a valid value, and returns
2193 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2194 * leaves data->affinity untouched.
2196 int __ioapic_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
2197 unsigned int *dest_id
)
2199 struct irq_cfg
*cfg
= data
->chip_data
;
2201 if (!cpumask_intersects(mask
, cpu_online_mask
))
2204 if (assign_irq_vector(data
->irq
, data
->chip_data
, mask
))
2207 cpumask_copy(data
->affinity
, mask
);
2209 *dest_id
= apic
->cpu_mask_to_apicid_and(mask
, cfg
->domain
);
2214 ioapic_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
2217 unsigned int dest
, irq
= data
->irq
;
2218 unsigned long flags
;
2221 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2222 ret
= __ioapic_set_affinity(data
, mask
, &dest
);
2224 /* Only the high 8 bits are valid. */
2225 dest
= SET_APIC_LOGICAL_ID(dest
);
2226 __target_IO_APIC_irq(irq
, dest
, data
->chip_data
);
2228 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2232 #ifdef CONFIG_INTR_REMAP
2235 * Migrate the IO-APIC irq in the presence of intr-remapping.
2237 * For both level and edge triggered, irq migration is a simple atomic
2238 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2240 * For level triggered, we eliminate the io-apic RTE modification (with the
2241 * updated vector information), by using a virtual vector (io-apic pin number).
2242 * Real vector that is used for interrupting cpu will be coming from
2243 * the interrupt-remapping table entry.
2246 ir_ioapic_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
2249 struct irq_cfg
*cfg
= data
->chip_data
;
2250 unsigned int dest
, irq
= data
->irq
;
2253 if (!cpumask_intersects(mask
, cpu_online_mask
))
2256 if (get_irte(irq
, &irte
))
2259 if (assign_irq_vector(irq
, cfg
, mask
))
2262 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, mask
);
2264 irte
.vector
= cfg
->vector
;
2265 irte
.dest_id
= IRTE_DEST(dest
);
2268 * Modified the IRTE and flushes the Interrupt entry cache.
2270 modify_irte(irq
, &irte
);
2272 if (cfg
->move_in_progress
)
2273 send_cleanup_vector(cfg
);
2275 cpumask_copy(data
->affinity
, mask
);
2281 ir_ioapic_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
2288 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
2290 unsigned vector
, me
;
2296 me
= smp_processor_id();
2297 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
2300 struct irq_desc
*desc
;
2301 struct irq_cfg
*cfg
;
2302 irq
= __this_cpu_read(vector_irq
[vector
]);
2307 desc
= irq_to_desc(irq
);
2312 raw_spin_lock(&desc
->lock
);
2315 * Check if the irq migration is in progress. If so, we
2316 * haven't received the cleanup request yet for this irq.
2318 if (cfg
->move_in_progress
)
2321 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2324 irr
= apic_read(APIC_IRR
+ (vector
/ 32 * 0x10));
2326 * Check if the vector that needs to be cleanedup is
2327 * registered at the cpu's IRR. If so, then this is not
2328 * the best time to clean it up. Lets clean it up in the
2329 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2332 if (irr
& (1 << (vector
% 32))) {
2333 apic
->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR
);
2336 __this_cpu_write(vector_irq
[vector
], -1);
2338 raw_spin_unlock(&desc
->lock
);
2344 static void __irq_complete_move(struct irq_cfg
*cfg
, unsigned vector
)
2348 if (likely(!cfg
->move_in_progress
))
2351 me
= smp_processor_id();
2353 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2354 send_cleanup_vector(cfg
);
2357 static void irq_complete_move(struct irq_cfg
*cfg
)
2359 __irq_complete_move(cfg
, ~get_irq_regs()->orig_ax
);
2362 void irq_force_complete_move(int irq
)
2364 struct irq_cfg
*cfg
= irq_get_chip_data(irq
);
2369 __irq_complete_move(cfg
, cfg
->vector
);
2372 static inline void irq_complete_move(struct irq_cfg
*cfg
) { }
2375 static void ack_apic_edge(struct irq_data
*data
)
2377 irq_complete_move(data
->chip_data
);
2382 atomic_t irq_mis_count
;
2385 * IO-APIC versions below 0x20 don't support EOI register.
2386 * For the record, here is the information about various versions:
2388 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
2389 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
2392 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
2393 * version as 0x2. This is an error with documentation and these ICH chips
2394 * use io-apic's of version 0x20.
2396 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
2397 * Otherwise, we simulate the EOI message manually by changing the trigger
2398 * mode to edge and then back to level, with RTE being masked during this.
2400 static void eoi_ioapic_irq(unsigned int irq
, struct irq_cfg
*cfg
)
2402 struct irq_pin_list
*entry
;
2403 unsigned long flags
;
2405 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2406 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
2407 if (mp_ioapics
[entry
->apic
].apicver
>= 0x20) {
2409 * Intr-remapping uses pin number as the virtual vector
2410 * in the RTE. Actual vector is programmed in
2411 * intr-remapping table entry. Hence for the io-apic
2412 * EOI we use the pin number.
2414 if (irq_remapped(cfg
))
2415 io_apic_eoi(entry
->apic
, entry
->pin
);
2417 io_apic_eoi(entry
->apic
, cfg
->vector
);
2419 __mask_and_edge_IO_APIC_irq(entry
);
2420 __unmask_and_level_IO_APIC_irq(entry
);
2423 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2426 static void ack_apic_level(struct irq_data
*data
)
2428 struct irq_cfg
*cfg
= data
->chip_data
;
2429 int i
, do_unmask_irq
= 0, irq
= data
->irq
;
2432 irq_complete_move(cfg
);
2433 #ifdef CONFIG_GENERIC_PENDING_IRQ
2434 /* If we are moving the irq we need to mask it */
2435 if (unlikely(irqd_is_setaffinity_pending(data
))) {
2442 * It appears there is an erratum which affects at least version 0x11
2443 * of I/O APIC (that's the 82093AA and cores integrated into various
2444 * chipsets). Under certain conditions a level-triggered interrupt is
2445 * erroneously delivered as edge-triggered one but the respective IRR
2446 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2447 * message but it will never arrive and further interrupts are blocked
2448 * from the source. The exact reason is so far unknown, but the
2449 * phenomenon was observed when two consecutive interrupt requests
2450 * from a given source get delivered to the same CPU and the source is
2451 * temporarily disabled in between.
2453 * A workaround is to simulate an EOI message manually. We achieve it
2454 * by setting the trigger mode to edge and then to level when the edge
2455 * trigger mode gets detected in the TMR of a local APIC for a
2456 * level-triggered interrupt. We mask the source for the time of the
2457 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2458 * The idea is from Manfred Spraul. --macro
2460 * Also in the case when cpu goes offline, fixup_irqs() will forward
2461 * any unhandled interrupt on the offlined cpu to the new cpu
2462 * destination that is handling the corresponding interrupt. This
2463 * interrupt forwarding is done via IPI's. Hence, in this case also
2464 * level-triggered io-apic interrupt will be seen as an edge
2465 * interrupt in the IRR. And we can't rely on the cpu's EOI
2466 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2467 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2468 * supporting EOI register, we do an explicit EOI to clear the
2469 * remote IRR and on IO-APIC's which don't have an EOI register,
2470 * we use the above logic (mask+edge followed by unmask+level) from
2471 * Manfred Spraul to clear the remote IRR.
2474 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2477 * We must acknowledge the irq before we move it or the acknowledge will
2478 * not propagate properly.
2483 * Tail end of clearing remote IRR bit (either by delivering the EOI
2484 * message via io-apic EOI register write or simulating it using
2485 * mask+edge followed by unnask+level logic) manually when the
2486 * level triggered interrupt is seen as the edge triggered interrupt
2489 if (!(v
& (1 << (i
& 0x1f)))) {
2490 atomic_inc(&irq_mis_count
);
2492 eoi_ioapic_irq(irq
, cfg
);
2495 /* Now we can move and renable the irq */
2496 if (unlikely(do_unmask_irq
)) {
2497 /* Only migrate the irq if the ack has been received.
2499 * On rare occasions the broadcast level triggered ack gets
2500 * delayed going to ioapics, and if we reprogram the
2501 * vector while Remote IRR is still set the irq will never
2504 * To prevent this scenario we read the Remote IRR bit
2505 * of the ioapic. This has two effects.
2506 * - On any sane system the read of the ioapic will
2507 * flush writes (and acks) going to the ioapic from
2509 * - We get to see if the ACK has actually been delivered.
2511 * Based on failed experiments of reprogramming the
2512 * ioapic entry from outside of irq context starting
2513 * with masking the ioapic entry and then polling until
2514 * Remote IRR was clear before reprogramming the
2515 * ioapic I don't trust the Remote IRR bit to be
2516 * completey accurate.
2518 * However there appears to be no other way to plug
2519 * this race, so if the Remote IRR bit is not
2520 * accurate and is causing problems then it is a hardware bug
2521 * and you can go talk to the chipset vendor about it.
2523 if (!io_apic_level_ack_pending(cfg
))
2524 irq_move_masked_irq(data
);
2529 #ifdef CONFIG_INTR_REMAP
2530 static void ir_ack_apic_edge(struct irq_data
*data
)
2535 static void ir_ack_apic_level(struct irq_data
*data
)
2538 eoi_ioapic_irq(data
->irq
, data
->chip_data
);
2540 #endif /* CONFIG_INTR_REMAP */
2542 static struct irq_chip ioapic_chip __read_mostly
= {
2544 .irq_startup
= startup_ioapic_irq
,
2545 .irq_mask
= mask_ioapic_irq
,
2546 .irq_unmask
= unmask_ioapic_irq
,
2547 .irq_ack
= ack_apic_edge
,
2548 .irq_eoi
= ack_apic_level
,
2550 .irq_set_affinity
= ioapic_set_affinity
,
2552 .irq_retrigger
= ioapic_retrigger_irq
,
2555 static struct irq_chip ir_ioapic_chip __read_mostly
= {
2556 .name
= "IR-IO-APIC",
2557 .irq_startup
= startup_ioapic_irq
,
2558 .irq_mask
= mask_ioapic_irq
,
2559 .irq_unmask
= unmask_ioapic_irq
,
2560 #ifdef CONFIG_INTR_REMAP
2561 .irq_ack
= ir_ack_apic_edge
,
2562 .irq_eoi
= ir_ack_apic_level
,
2564 .irq_set_affinity
= ir_ioapic_set_affinity
,
2567 .irq_retrigger
= ioapic_retrigger_irq
,
2570 static inline void init_IO_APIC_traps(void)
2572 struct irq_cfg
*cfg
;
2576 * NOTE! The local APIC isn't very good at handling
2577 * multiple interrupts at the same interrupt level.
2578 * As the interrupt level is determined by taking the
2579 * vector number and shifting that right by 4, we
2580 * want to spread these out a bit so that they don't
2581 * all fall in the same interrupt level.
2583 * Also, we've got to be careful not to trash gate
2584 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2586 for_each_active_irq(irq
) {
2587 cfg
= irq_get_chip_data(irq
);
2588 if (IO_APIC_IRQ(irq
) && cfg
&& !cfg
->vector
) {
2590 * Hmm.. We don't have an entry for this,
2591 * so default to an old-fashioned 8259
2592 * interrupt if we can..
2594 if (irq
< legacy_pic
->nr_legacy_irqs
)
2595 legacy_pic
->make_irq(irq
);
2597 /* Strange. Oh, well.. */
2598 irq_set_chip(irq
, &no_irq_chip
);
2604 * The local APIC irq-chip implementation:
2607 static void mask_lapic_irq(struct irq_data
*data
)
2611 v
= apic_read(APIC_LVT0
);
2612 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2615 static void unmask_lapic_irq(struct irq_data
*data
)
2619 v
= apic_read(APIC_LVT0
);
2620 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2623 static void ack_lapic_irq(struct irq_data
*data
)
2628 static struct irq_chip lapic_chip __read_mostly
= {
2629 .name
= "local-APIC",
2630 .irq_mask
= mask_lapic_irq
,
2631 .irq_unmask
= unmask_lapic_irq
,
2632 .irq_ack
= ack_lapic_irq
,
2635 static void lapic_register_intr(int irq
)
2637 irq_clear_status_flags(irq
, IRQ_LEVEL
);
2638 irq_set_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2643 * This looks a bit hackish but it's about the only one way of sending
2644 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2645 * not support the ExtINT mode, unfortunately. We need to send these
2646 * cycles as some i82489DX-based boards have glue logic that keeps the
2647 * 8259A interrupt line asserted until INTA. --macro
2649 static inline void __init
unlock_ExtINT_logic(void)
2652 struct IO_APIC_route_entry entry0
, entry1
;
2653 unsigned char save_control
, save_freq_select
;
2655 pin
= find_isa_irq_pin(8, mp_INT
);
2660 apic
= find_isa_irq_apic(8, mp_INT
);
2666 entry0
= ioapic_read_entry(apic
, pin
);
2667 clear_IO_APIC_pin(apic
, pin
);
2669 memset(&entry1
, 0, sizeof(entry1
));
2671 entry1
.dest_mode
= 0; /* physical delivery */
2672 entry1
.mask
= 0; /* unmask IRQ now */
2673 entry1
.dest
= hard_smp_processor_id();
2674 entry1
.delivery_mode
= dest_ExtINT
;
2675 entry1
.polarity
= entry0
.polarity
;
2679 ioapic_write_entry(apic
, pin
, entry1
);
2681 save_control
= CMOS_READ(RTC_CONTROL
);
2682 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2683 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2685 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2690 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2694 CMOS_WRITE(save_control
, RTC_CONTROL
);
2695 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2696 clear_IO_APIC_pin(apic
, pin
);
2698 ioapic_write_entry(apic
, pin
, entry0
);
2701 static int disable_timer_pin_1 __initdata
;
2702 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2703 static int __init
disable_timer_pin_setup(char *arg
)
2705 disable_timer_pin_1
= 1;
2708 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2710 int timer_through_8259 __initdata
;
2713 * This code may look a bit paranoid, but it's supposed to cooperate with
2714 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2715 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2716 * fanatically on his truly buggy board.
2718 * FIXME: really need to revamp this for all platforms.
2720 static inline void __init
check_timer(void)
2722 struct irq_cfg
*cfg
= irq_get_chip_data(0);
2723 int node
= cpu_to_node(0);
2724 int apic1
, pin1
, apic2
, pin2
;
2725 unsigned long flags
;
2728 local_irq_save(flags
);
2731 * get/set the timer IRQ vector:
2733 legacy_pic
->mask(0);
2734 assign_irq_vector(0, cfg
, apic
->target_cpus());
2737 * As IRQ0 is to be enabled in the 8259A, the virtual
2738 * wire has to be disabled in the local APIC. Also
2739 * timer interrupts need to be acknowledged manually in
2740 * the 8259A for the i82489DX when using the NMI
2741 * watchdog as that APIC treats NMIs as level-triggered.
2742 * The AEOI mode will finish them in the 8259A
2745 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2746 legacy_pic
->init(1);
2748 pin1
= find_isa_irq_pin(0, mp_INT
);
2749 apic1
= find_isa_irq_apic(0, mp_INT
);
2750 pin2
= ioapic_i8259
.pin
;
2751 apic2
= ioapic_i8259
.apic
;
2753 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2754 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2755 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2758 * Some BIOS writers are clueless and report the ExtINTA
2759 * I/O APIC input from the cascaded 8259A as the timer
2760 * interrupt input. So just in case, if only one pin
2761 * was found above, try it both directly and through the
2765 if (intr_remapping_enabled
)
2766 panic("BIOS bug: timer not connected to IO-APIC");
2770 } else if (pin2
== -1) {
2777 * Ok, does IRQ0 through the IOAPIC work?
2780 add_pin_to_irq_node(cfg
, node
, apic1
, pin1
);
2781 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2783 /* for edge trigger, setup_ioapic_irq already
2784 * leave it unmasked.
2785 * so only need to unmask if it is level-trigger
2786 * do we really have level trigger timer?
2789 idx
= find_irq_entry(apic1
, pin1
, mp_INT
);
2790 if (idx
!= -1 && irq_trigger(idx
))
2793 if (timer_irq_works()) {
2794 if (disable_timer_pin_1
> 0)
2795 clear_IO_APIC_pin(0, pin1
);
2798 if (intr_remapping_enabled
)
2799 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2800 local_irq_disable();
2801 clear_IO_APIC_pin(apic1
, pin1
);
2803 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2804 "8254 timer not connected to IO-APIC\n");
2806 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2807 "(IRQ0) through the 8259A ...\n");
2808 apic_printk(APIC_QUIET
, KERN_INFO
2809 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2811 * legacy devices should be connected to IO APIC #0
2813 replace_pin_at_irq_node(cfg
, node
, apic1
, pin1
, apic2
, pin2
);
2814 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2815 legacy_pic
->unmask(0);
2816 if (timer_irq_works()) {
2817 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2818 timer_through_8259
= 1;
2822 * Cleanup, just in case ...
2824 local_irq_disable();
2825 legacy_pic
->mask(0);
2826 clear_IO_APIC_pin(apic2
, pin2
);
2827 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2830 apic_printk(APIC_QUIET
, KERN_INFO
2831 "...trying to set up timer as Virtual Wire IRQ...\n");
2833 lapic_register_intr(0);
2834 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2835 legacy_pic
->unmask(0);
2837 if (timer_irq_works()) {
2838 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2841 local_irq_disable();
2842 legacy_pic
->mask(0);
2843 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
2844 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2846 apic_printk(APIC_QUIET
, KERN_INFO
2847 "...trying to set up timer as ExtINT IRQ...\n");
2849 legacy_pic
->init(0);
2850 legacy_pic
->make_irq(0);
2851 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2853 unlock_ExtINT_logic();
2855 if (timer_irq_works()) {
2856 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2859 local_irq_disable();
2860 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
2861 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2862 "report. Then try booting with the 'noapic' option.\n");
2864 local_irq_restore(flags
);
2868 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2869 * to devices. However there may be an I/O APIC pin available for
2870 * this interrupt regardless. The pin may be left unconnected, but
2871 * typically it will be reused as an ExtINT cascade interrupt for
2872 * the master 8259A. In the MPS case such a pin will normally be
2873 * reported as an ExtINT interrupt in the MP table. With ACPI
2874 * there is no provision for ExtINT interrupts, and in the absence
2875 * of an override it would be treated as an ordinary ISA I/O APIC
2876 * interrupt, that is edge-triggered and unmasked by default. We
2877 * used to do this, but it caused problems on some systems because
2878 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2879 * the same ExtINT cascade interrupt to drive the local APIC of the
2880 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2881 * the I/O APIC in all cases now. No actual device should request
2882 * it anyway. --macro
2884 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2886 void __init
setup_IO_APIC(void)
2890 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2892 io_apic_irqs
= legacy_pic
->nr_legacy_irqs
? ~PIC_IRQS
: ~0UL;
2894 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
2896 * Set up IO-APIC IRQ routing.
2898 x86_init
.mpparse
.setup_ioapic_ids();
2901 setup_IO_APIC_irqs();
2902 init_IO_APIC_traps();
2903 if (legacy_pic
->nr_legacy_irqs
)
2908 * Called after all the initialization is done. If we didn't find any
2909 * APIC bugs then we can allow the modify fast path
2912 static int __init
io_apic_bug_finalize(void)
2914 if (sis_apic_bug
== -1)
2919 late_initcall(io_apic_bug_finalize
);
2921 struct sysfs_ioapic_data
{
2922 struct sys_device dev
;
2923 struct IO_APIC_route_entry entry
[0];
2925 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
2927 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2929 struct IO_APIC_route_entry
*entry
;
2930 struct sysfs_ioapic_data
*data
;
2933 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2934 entry
= data
->entry
;
2935 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
2936 *entry
= ioapic_read_entry(dev
->id
, i
);
2941 static int ioapic_resume(struct sys_device
*dev
)
2943 struct IO_APIC_route_entry
*entry
;
2944 struct sysfs_ioapic_data
*data
;
2945 unsigned long flags
;
2946 union IO_APIC_reg_00 reg_00
;
2949 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2950 entry
= data
->entry
;
2952 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2953 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2954 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].apicid
) {
2955 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].apicid
;
2956 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2958 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2959 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2960 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
2965 static struct sysdev_class ioapic_sysdev_class
= {
2967 .suspend
= ioapic_suspend
,
2968 .resume
= ioapic_resume
,
2971 static int __init
ioapic_init_sysfs(void)
2973 struct sys_device
* dev
;
2976 error
= sysdev_class_register(&ioapic_sysdev_class
);
2980 for (i
= 0; i
< nr_ioapics
; i
++ ) {
2981 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2982 * sizeof(struct IO_APIC_route_entry
);
2983 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
2984 if (!mp_ioapic_data
[i
]) {
2985 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2988 dev
= &mp_ioapic_data
[i
]->dev
;
2990 dev
->cls
= &ioapic_sysdev_class
;
2991 error
= sysdev_register(dev
);
2993 kfree(mp_ioapic_data
[i
]);
2994 mp_ioapic_data
[i
] = NULL
;
2995 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3003 device_initcall(ioapic_init_sysfs
);
3006 * Dynamic irq allocate and deallocation
3008 unsigned int create_irq_nr(unsigned int from
, int node
)
3010 struct irq_cfg
*cfg
;
3011 unsigned long flags
;
3012 unsigned int ret
= 0;
3015 if (from
< nr_irqs_gsi
)
3018 irq
= alloc_irq_from(from
, node
);
3021 cfg
= alloc_irq_cfg(irq
, node
);
3023 free_irq_at(irq
, NULL
);
3027 raw_spin_lock_irqsave(&vector_lock
, flags
);
3028 if (!__assign_irq_vector(irq
, cfg
, apic
->target_cpus()))
3030 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
3033 irq_set_chip_data(irq
, cfg
);
3034 irq_clear_status_flags(irq
, IRQ_NOREQUEST
);
3036 free_irq_at(irq
, cfg
);
3041 int create_irq(void)
3043 int node
= cpu_to_node(0);
3044 unsigned int irq_want
;
3047 irq_want
= nr_irqs_gsi
;
3048 irq
= create_irq_nr(irq_want
, node
);
3056 void destroy_irq(unsigned int irq
)
3058 struct irq_cfg
*cfg
= irq_get_chip_data(irq
);
3059 unsigned long flags
;
3061 irq_set_status_flags(irq
, IRQ_NOREQUEST
|IRQ_NOPROBE
);
3063 if (irq_remapped(cfg
))
3065 raw_spin_lock_irqsave(&vector_lock
, flags
);
3066 __clear_irq_vector(irq
, cfg
);
3067 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
3068 free_irq_at(irq
, cfg
);
3072 * MSI message composition
3074 #ifdef CONFIG_PCI_MSI
3075 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
,
3076 struct msi_msg
*msg
, u8 hpet_id
)
3078 struct irq_cfg
*cfg
;
3086 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3090 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
3092 if (irq_remapped(cfg
)) {
3097 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
3098 BUG_ON(ir_index
== -1);
3100 prepare_irte(&irte
, cfg
->vector
, dest
);
3102 /* Set source-id of interrupt request */
3104 set_msi_sid(&irte
, pdev
);
3106 set_hpet_sid(&irte
, hpet_id
);
3108 modify_irte(irq
, &irte
);
3110 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3111 msg
->data
= sub_handle
;
3112 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
3114 MSI_ADDR_IR_INDEX1(ir_index
) |
3115 MSI_ADDR_IR_INDEX2(ir_index
);
3117 if (x2apic_enabled())
3118 msg
->address_hi
= MSI_ADDR_BASE_HI
|
3119 MSI_ADDR_EXT_DEST_ID(dest
);
3121 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3125 ((apic
->irq_dest_mode
== 0) ?
3126 MSI_ADDR_DEST_MODE_PHYSICAL
:
3127 MSI_ADDR_DEST_MODE_LOGICAL
) |
3128 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3129 MSI_ADDR_REDIRECTION_CPU
:
3130 MSI_ADDR_REDIRECTION_LOWPRI
) |
3131 MSI_ADDR_DEST_ID(dest
);
3134 MSI_DATA_TRIGGER_EDGE
|
3135 MSI_DATA_LEVEL_ASSERT
|
3136 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3137 MSI_DATA_DELIVERY_FIXED
:
3138 MSI_DATA_DELIVERY_LOWPRI
) |
3139 MSI_DATA_VECTOR(cfg
->vector
);
3146 msi_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
, bool force
)
3148 struct irq_cfg
*cfg
= data
->chip_data
;
3152 if (__ioapic_set_affinity(data
, mask
, &dest
))
3155 __get_cached_msi_msg(data
->msi_desc
, &msg
);
3157 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3158 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3159 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3160 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3162 __write_msi_msg(data
->msi_desc
, &msg
);
3166 #ifdef CONFIG_INTR_REMAP
3168 * Migrate the MSI irq to another cpumask. This migration is
3169 * done in the process context using interrupt-remapping hardware.
3172 ir_msi_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
3175 struct irq_cfg
*cfg
= data
->chip_data
;
3176 unsigned int dest
, irq
= data
->irq
;
3179 if (get_irte(irq
, &irte
))
3182 if (__ioapic_set_affinity(data
, mask
, &dest
))
3185 irte
.vector
= cfg
->vector
;
3186 irte
.dest_id
= IRTE_DEST(dest
);
3189 * atomically update the IRTE with the new destination and vector.
3191 modify_irte(irq
, &irte
);
3194 * After this point, all the interrupts will start arriving
3195 * at the new destination. So, time to cleanup the previous
3196 * vector allocation.
3198 if (cfg
->move_in_progress
)
3199 send_cleanup_vector(cfg
);
3205 #endif /* CONFIG_SMP */
3208 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3209 * which implement the MSI or MSI-X Capability Structure.
3211 static struct irq_chip msi_chip
= {
3213 .irq_unmask
= unmask_msi_irq
,
3214 .irq_mask
= mask_msi_irq
,
3215 .irq_ack
= ack_apic_edge
,
3217 .irq_set_affinity
= msi_set_affinity
,
3219 .irq_retrigger
= ioapic_retrigger_irq
,
3222 static struct irq_chip msi_ir_chip
= {
3223 .name
= "IR-PCI-MSI",
3224 .irq_unmask
= unmask_msi_irq
,
3225 .irq_mask
= mask_msi_irq
,
3226 #ifdef CONFIG_INTR_REMAP
3227 .irq_ack
= ir_ack_apic_edge
,
3229 .irq_set_affinity
= ir_msi_set_affinity
,
3232 .irq_retrigger
= ioapic_retrigger_irq
,
3236 * Map the PCI dev to the corresponding remapping hardware unit
3237 * and allocate 'nvec' consecutive interrupt-remapping table entries
3240 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
3242 struct intel_iommu
*iommu
;
3245 iommu
= map_dev_to_ir(dev
);
3248 "Unable to map PCI %s to iommu\n", pci_name(dev
));
3252 index
= alloc_irte(iommu
, irq
, nvec
);
3255 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
3262 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*msidesc
, int irq
)
3264 struct irq_chip
*chip
= &msi_chip
;
3268 ret
= msi_compose_msg(dev
, irq
, &msg
, -1);
3272 irq_set_msi_desc(irq
, msidesc
);
3273 write_msi_msg(irq
, &msg
);
3275 if (irq_remapped(irq_get_chip_data(irq
))) {
3276 irq_set_status_flags(irq
, IRQ_MOVE_PCNTXT
);
3277 chip
= &msi_ir_chip
;
3280 irq_set_chip_and_handler_name(irq
, chip
, handle_edge_irq
, "edge");
3282 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for MSI/MSI-X\n", irq
);
3287 int native_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
3289 int node
, ret
, sub_handle
, index
= 0;
3290 unsigned int irq
, irq_want
;
3291 struct msi_desc
*msidesc
;
3292 struct intel_iommu
*iommu
= NULL
;
3294 /* x86 doesn't support multiple MSI yet */
3295 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
3298 node
= dev_to_node(&dev
->dev
);
3299 irq_want
= nr_irqs_gsi
;
3301 list_for_each_entry(msidesc
, &dev
->msi_list
, list
) {
3302 irq
= create_irq_nr(irq_want
, node
);
3306 if (!intr_remapping_enabled
)
3311 * allocate the consecutive block of IRTE's
3314 index
= msi_alloc_irte(dev
, irq
, nvec
);
3320 iommu
= map_dev_to_ir(dev
);
3326 * setup the mapping between the irq and the IRTE
3327 * base index, the sub_handle pointing to the
3328 * appropriate interrupt remap table entry.
3330 set_irte_irq(irq
, iommu
, index
, sub_handle
);
3333 ret
= setup_msi_irq(dev
, msidesc
, irq
);
3345 void native_teardown_msi_irq(unsigned int irq
)
3350 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3353 dmar_msi_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
3356 struct irq_cfg
*cfg
= data
->chip_data
;
3357 unsigned int dest
, irq
= data
->irq
;
3360 if (__ioapic_set_affinity(data
, mask
, &dest
))
3363 dmar_msi_read(irq
, &msg
);
3365 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3366 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3367 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3368 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3369 msg
.address_hi
= MSI_ADDR_BASE_HI
| MSI_ADDR_EXT_DEST_ID(dest
);
3371 dmar_msi_write(irq
, &msg
);
3376 #endif /* CONFIG_SMP */
3378 static struct irq_chip dmar_msi_type
= {
3380 .irq_unmask
= dmar_msi_unmask
,
3381 .irq_mask
= dmar_msi_mask
,
3382 .irq_ack
= ack_apic_edge
,
3384 .irq_set_affinity
= dmar_msi_set_affinity
,
3386 .irq_retrigger
= ioapic_retrigger_irq
,
3389 int arch_setup_dmar_msi(unsigned int irq
)
3394 ret
= msi_compose_msg(NULL
, irq
, &msg
, -1);
3397 dmar_msi_write(irq
, &msg
);
3398 irq_set_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3404 #ifdef CONFIG_HPET_TIMER
3407 static int hpet_msi_set_affinity(struct irq_data
*data
,
3408 const struct cpumask
*mask
, bool force
)
3410 struct irq_cfg
*cfg
= data
->chip_data
;
3414 if (__ioapic_set_affinity(data
, mask
, &dest
))
3417 hpet_msi_read(data
->handler_data
, &msg
);
3419 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3420 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3421 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3422 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3424 hpet_msi_write(data
->handler_data
, &msg
);
3429 #endif /* CONFIG_SMP */
3431 static struct irq_chip ir_hpet_msi_type
= {
3432 .name
= "IR-HPET_MSI",
3433 .irq_unmask
= hpet_msi_unmask
,
3434 .irq_mask
= hpet_msi_mask
,
3435 #ifdef CONFIG_INTR_REMAP
3436 .irq_ack
= ir_ack_apic_edge
,
3438 .irq_set_affinity
= ir_msi_set_affinity
,
3441 .irq_retrigger
= ioapic_retrigger_irq
,
3444 static struct irq_chip hpet_msi_type
= {
3446 .irq_unmask
= hpet_msi_unmask
,
3447 .irq_mask
= hpet_msi_mask
,
3448 .irq_ack
= ack_apic_edge
,
3450 .irq_set_affinity
= hpet_msi_set_affinity
,
3452 .irq_retrigger
= ioapic_retrigger_irq
,
3455 int arch_setup_hpet_msi(unsigned int irq
, unsigned int id
)
3457 struct irq_chip
*chip
= &hpet_msi_type
;
3461 if (intr_remapping_enabled
) {
3462 struct intel_iommu
*iommu
= map_hpet_to_ir(id
);
3468 index
= alloc_irte(iommu
, irq
, 1);
3473 ret
= msi_compose_msg(NULL
, irq
, &msg
, id
);
3477 hpet_msi_write(irq_get_handler_data(irq
), &msg
);
3478 irq_set_status_flags(irq
, IRQ_MOVE_PCNTXT
);
3479 if (irq_remapped(irq_get_chip_data(irq
)))
3480 chip
= &ir_hpet_msi_type
;
3482 irq_set_chip_and_handler_name(irq
, chip
, handle_edge_irq
, "edge");
3487 #endif /* CONFIG_PCI_MSI */
3489 * Hypertransport interrupt support
3491 #ifdef CONFIG_HT_IRQ
3495 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3497 struct ht_irq_msg msg
;
3498 fetch_ht_irq_msg(irq
, &msg
);
3500 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3501 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3503 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3504 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3506 write_ht_irq_msg(irq
, &msg
);
3510 ht_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
, bool force
)
3512 struct irq_cfg
*cfg
= data
->chip_data
;
3515 if (__ioapic_set_affinity(data
, mask
, &dest
))
3518 target_ht_irq(data
->irq
, dest
, cfg
->vector
);
3524 static struct irq_chip ht_irq_chip
= {
3526 .irq_mask
= mask_ht_irq
,
3527 .irq_unmask
= unmask_ht_irq
,
3528 .irq_ack
= ack_apic_edge
,
3530 .irq_set_affinity
= ht_set_affinity
,
3532 .irq_retrigger
= ioapic_retrigger_irq
,
3535 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3537 struct irq_cfg
*cfg
;
3544 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3546 struct ht_irq_msg msg
;
3549 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
,
3550 apic
->target_cpus());
3552 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3556 HT_IRQ_LOW_DEST_ID(dest
) |
3557 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3558 ((apic
->irq_dest_mode
== 0) ?
3559 HT_IRQ_LOW_DM_PHYSICAL
:
3560 HT_IRQ_LOW_DM_LOGICAL
) |
3561 HT_IRQ_LOW_RQEOI_EDGE
|
3562 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3563 HT_IRQ_LOW_MT_FIXED
:
3564 HT_IRQ_LOW_MT_ARBITRATED
) |
3565 HT_IRQ_LOW_IRQ_MASKED
;
3567 write_ht_irq_msg(irq
, &msg
);
3569 irq_set_chip_and_handler_name(irq
, &ht_irq_chip
,
3570 handle_edge_irq
, "edge");
3572 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for HT\n", irq
);
3576 #endif /* CONFIG_HT_IRQ */
3579 io_apic_setup_irq_pin(unsigned int irq
, int node
, struct io_apic_irq_attr
*attr
)
3581 struct irq_cfg
*cfg
= alloc_irq_and_cfg_at(irq
, node
);
3586 ret
= __add_pin_to_irq_node(cfg
, node
, attr
->ioapic
, attr
->ioapic_pin
);
3588 setup_ioapic_irq(attr
->ioapic
, attr
->ioapic_pin
, irq
, cfg
,
3589 attr
->trigger
, attr
->polarity
);
3593 static int io_apic_setup_irq_pin_once(unsigned int irq
, int node
,
3594 struct io_apic_irq_attr
*attr
)
3596 unsigned int id
= attr
->ioapic
, pin
= attr
->ioapic_pin
;
3599 /* Avoid redundant programming */
3600 if (test_bit(pin
, mp_ioapic_routing
[id
].pin_programmed
)) {
3601 pr_debug("Pin %d-%d already programmed\n",
3602 mp_ioapics
[id
].apicid
, pin
);
3605 ret
= io_apic_setup_irq_pin(irq
, node
, attr
);
3607 set_bit(pin
, mp_ioapic_routing
[id
].pin_programmed
);
3611 static int __init
io_apic_get_redir_entries(int ioapic
)
3613 union IO_APIC_reg_01 reg_01
;
3614 unsigned long flags
;
3616 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3617 reg_01
.raw
= io_apic_read(ioapic
, 1);
3618 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3620 /* The register returns the maximum index redir index
3621 * supported, which is one less than the total number of redir
3624 return reg_01
.bits
.entries
+ 1;
3627 static void __init
probe_nr_irqs_gsi(void)
3631 nr
= gsi_top
+ NR_IRQS_LEGACY
;
3632 if (nr
> nr_irqs_gsi
)
3635 printk(KERN_DEBUG
"nr_irqs_gsi: %d\n", nr_irqs_gsi
);
3638 int get_nr_irqs_gsi(void)
3643 #ifdef CONFIG_SPARSE_IRQ
3644 int __init
arch_probe_nr_irqs(void)
3648 if (nr_irqs
> (NR_VECTORS
* nr_cpu_ids
))
3649 nr_irqs
= NR_VECTORS
* nr_cpu_ids
;
3651 nr
= nr_irqs_gsi
+ 8 * nr_cpu_ids
;
3652 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3654 * for MSI and HT dyn irq
3656 nr
+= nr_irqs_gsi
* 16;
3661 return NR_IRQS_LEGACY
;
3665 int io_apic_set_pci_routing(struct device
*dev
, int irq
,
3666 struct io_apic_irq_attr
*irq_attr
)
3670 if (!IO_APIC_IRQ(irq
)) {
3671 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
3676 node
= dev
? dev_to_node(dev
) : cpu_to_node(0);
3678 return io_apic_setup_irq_pin_once(irq
, node
, irq_attr
);
3681 #ifdef CONFIG_X86_32
3682 static int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
3684 union IO_APIC_reg_00 reg_00
;
3685 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
3687 unsigned long flags
;
3691 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3692 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3693 * supports up to 16 on one shared APIC bus.
3695 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3696 * advantage of new APIC bus architecture.
3699 if (physids_empty(apic_id_map
))
3700 apic
->ioapic_phys_id_map(&phys_cpu_present_map
, &apic_id_map
);
3702 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3703 reg_00
.raw
= io_apic_read(ioapic
, 0);
3704 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3706 if (apic_id
>= get_physical_broadcast()) {
3707 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
3708 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
3709 apic_id
= reg_00
.bits
.ID
;
3713 * Every APIC in a system must have a unique ID or we get lots of nice
3714 * 'stuck on smp_invalidate_needed IPI wait' messages.
3716 if (apic
->check_apicid_used(&apic_id_map
, apic_id
)) {
3718 for (i
= 0; i
< get_physical_broadcast(); i
++) {
3719 if (!apic
->check_apicid_used(&apic_id_map
, i
))
3723 if (i
== get_physical_broadcast())
3724 panic("Max apic_id exceeded!\n");
3726 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
3727 "trying %d\n", ioapic
, apic_id
, i
);
3732 apic
->apicid_to_cpu_present(apic_id
, &tmp
);
3733 physids_or(apic_id_map
, apic_id_map
, tmp
);
3735 if (reg_00
.bits
.ID
!= apic_id
) {
3736 reg_00
.bits
.ID
= apic_id
;
3738 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3739 io_apic_write(ioapic
, 0, reg_00
.raw
);
3740 reg_00
.raw
= io_apic_read(ioapic
, 0);
3741 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3744 if (reg_00
.bits
.ID
!= apic_id
) {
3745 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
3750 apic_printk(APIC_VERBOSE
, KERN_INFO
3751 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
3756 static u8 __init
io_apic_unique_id(u8 id
)
3758 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
3759 !APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
3760 return io_apic_get_unique_id(nr_ioapics
, id
);
3765 static u8 __init
io_apic_unique_id(u8 id
)
3768 DECLARE_BITMAP(used
, 256);
3770 bitmap_zero(used
, 256);
3771 for (i
= 0; i
< nr_ioapics
; i
++) {
3772 struct mpc_ioapic
*ia
= &mp_ioapics
[i
];
3773 __set_bit(ia
->apicid
, used
);
3775 if (!test_bit(id
, used
))
3777 return find_first_zero_bit(used
, 256);
3781 static int __init
io_apic_get_version(int ioapic
)
3783 union IO_APIC_reg_01 reg_01
;
3784 unsigned long flags
;
3786 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3787 reg_01
.raw
= io_apic_read(ioapic
, 1);
3788 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3790 return reg_01
.bits
.version
;
3793 int acpi_get_override_irq(u32 gsi
, int *trigger
, int *polarity
)
3795 int ioapic
, pin
, idx
;
3797 if (skip_ioapic_setup
)
3800 ioapic
= mp_find_ioapic(gsi
);
3804 pin
= mp_find_ioapic_pin(ioapic
, gsi
);
3808 idx
= find_irq_entry(ioapic
, pin
, mp_INT
);
3812 *trigger
= irq_trigger(idx
);
3813 *polarity
= irq_polarity(idx
);
3818 * This function currently is only a helper for the i386 smp boot process where
3819 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3820 * so mask in all cases should simply be apic->target_cpus()
3823 void __init
setup_ioapic_dest(void)
3825 int pin
, ioapic
, irq
, irq_entry
;
3826 const struct cpumask
*mask
;
3827 struct irq_data
*idata
;
3829 if (skip_ioapic_setup
== 1)
3832 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++)
3833 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
3834 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
3835 if (irq_entry
== -1)
3837 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
3839 if ((ioapic
> 0) && (irq
> 16))
3842 idata
= irq_get_irq_data(irq
);
3845 * Honour affinities which have been set in early boot
3847 if (!irqd_can_balance(idata
) || irqd_affinity_was_set(idata
))
3848 mask
= idata
->affinity
;
3850 mask
= apic
->target_cpus();
3852 if (intr_remapping_enabled
)
3853 ir_ioapic_set_affinity(idata
, mask
, false);
3855 ioapic_set_affinity(idata
, mask
, false);
3861 #define IOAPIC_RESOURCE_NAME_SIZE 11
3863 static struct resource
*ioapic_resources
;
3865 static struct resource
* __init
ioapic_setup_resources(int nr_ioapics
)
3868 struct resource
*res
;
3872 if (nr_ioapics
<= 0)
3875 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
3878 mem
= alloc_bootmem(n
);
3881 mem
+= sizeof(struct resource
) * nr_ioapics
;
3883 for (i
= 0; i
< nr_ioapics
; i
++) {
3885 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
3886 snprintf(mem
, IOAPIC_RESOURCE_NAME_SIZE
, "IOAPIC %u", i
);
3887 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
3890 ioapic_resources
= res
;
3895 void __init
ioapic_and_gsi_init(void)
3897 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
3898 struct resource
*ioapic_res
;
3901 ioapic_res
= ioapic_setup_resources(nr_ioapics
);
3902 for (i
= 0; i
< nr_ioapics
; i
++) {
3903 if (smp_found_config
) {
3904 ioapic_phys
= mp_ioapics
[i
].apicaddr
;
3905 #ifdef CONFIG_X86_32
3908 "WARNING: bogus zero IO-APIC "
3909 "address found in MPTABLE, "
3910 "disabling IO/APIC support!\n");
3911 smp_found_config
= 0;
3912 skip_ioapic_setup
= 1;
3913 goto fake_ioapic_page
;
3917 #ifdef CONFIG_X86_32
3920 ioapic_phys
= (unsigned long)alloc_bootmem_pages(PAGE_SIZE
);
3921 ioapic_phys
= __pa(ioapic_phys
);
3923 set_fixmap_nocache(idx
, ioapic_phys
);
3924 apic_printk(APIC_VERBOSE
, "mapped IOAPIC to %08lx (%08lx)\n",
3925 __fix_to_virt(idx
) + (ioapic_phys
& ~PAGE_MASK
),
3929 ioapic_res
->start
= ioapic_phys
;
3930 ioapic_res
->end
= ioapic_phys
+ IO_APIC_SLOT_SIZE
- 1;
3934 probe_nr_irqs_gsi();
3937 void __init
ioapic_insert_resources(void)
3940 struct resource
*r
= ioapic_resources
;
3945 "IO APIC resources couldn't be allocated.\n");
3949 for (i
= 0; i
< nr_ioapics
; i
++) {
3950 insert_resource(&iomem_resource
, r
);
3955 int mp_find_ioapic(u32 gsi
)
3959 if (nr_ioapics
== 0)
3962 /* Find the IOAPIC that manages this GSI. */
3963 for (i
= 0; i
< nr_ioapics
; i
++) {
3964 if ((gsi
>= mp_gsi_routing
[i
].gsi_base
)
3965 && (gsi
<= mp_gsi_routing
[i
].gsi_end
))
3969 printk(KERN_ERR
"ERROR: Unable to locate IOAPIC for GSI %d\n", gsi
);
3973 int mp_find_ioapic_pin(int ioapic
, u32 gsi
)
3975 if (WARN_ON(ioapic
== -1))
3977 if (WARN_ON(gsi
> mp_gsi_routing
[ioapic
].gsi_end
))
3980 return gsi
- mp_gsi_routing
[ioapic
].gsi_base
;
3983 static __init
int bad_ioapic(unsigned long address
)
3985 if (nr_ioapics
>= MAX_IO_APICS
) {
3986 printk(KERN_WARNING
"WARNING: Max # of I/O APICs (%d) exceeded "
3987 "(found %d), skipping\n", MAX_IO_APICS
, nr_ioapics
);
3991 printk(KERN_WARNING
"WARNING: Bogus (zero) I/O APIC address"
3992 " found in table, skipping!\n");
3998 void __init
mp_register_ioapic(int id
, u32 address
, u32 gsi_base
)
4003 if (bad_ioapic(address
))
4008 mp_ioapics
[idx
].type
= MP_IOAPIC
;
4009 mp_ioapics
[idx
].flags
= MPC_APIC_USABLE
;
4010 mp_ioapics
[idx
].apicaddr
= address
;
4012 set_fixmap_nocache(FIX_IO_APIC_BASE_0
+ idx
, address
);
4013 mp_ioapics
[idx
].apicid
= io_apic_unique_id(id
);
4014 mp_ioapics
[idx
].apicver
= io_apic_get_version(idx
);
4017 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4018 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4020 entries
= io_apic_get_redir_entries(idx
);
4021 mp_gsi_routing
[idx
].gsi_base
= gsi_base
;
4022 mp_gsi_routing
[idx
].gsi_end
= gsi_base
+ entries
- 1;
4025 * The number of IO-APIC IRQ registers (== #pins):
4027 nr_ioapic_registers
[idx
] = entries
;
4029 if (mp_gsi_routing
[idx
].gsi_end
>= gsi_top
)
4030 gsi_top
= mp_gsi_routing
[idx
].gsi_end
+ 1;
4032 printk(KERN_INFO
"IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4033 "GSI %d-%d\n", idx
, mp_ioapics
[idx
].apicid
,
4034 mp_ioapics
[idx
].apicver
, mp_ioapics
[idx
].apicaddr
,
4035 mp_gsi_routing
[idx
].gsi_base
, mp_gsi_routing
[idx
].gsi_end
);
4040 /* Enable IOAPIC early just for system timer */
4041 void __init
pre_init_apic_IRQ0(void)
4043 struct io_apic_irq_attr attr
= { 0, 0, 0, 0 };
4045 printk(KERN_INFO
"Early APIC setup for system timer0\n");
4047 physid_set_mask_of_physid(boot_cpu_physical_apicid
,
4048 &phys_cpu_present_map
);
4052 io_apic_setup_irq_pin(0, 0, &attr
);
4053 irq_set_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
,