2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/module.h>
27 #include <linux/sysdev.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/dmar.h>
31 #include <linux/init.h>
32 #include <linux/cpu.h>
33 #include <linux/dmi.h>
34 #include <linux/smp.h>
37 #include <asm/perf_event.h>
38 #include <asm/x86_init.h>
39 #include <asm/pgalloc.h>
40 #include <asm/atomic.h>
41 #include <asm/mpspec.h>
42 #include <asm/i8253.h>
43 #include <asm/i8259.h>
44 #include <asm/proto.h>
46 #include <asm/io_apic.h>
54 #include <asm/hypervisor.h>
56 unsigned int num_processors
;
58 unsigned disabled_cpus __cpuinitdata
;
60 /* Processor that is doing the boot up */
61 unsigned int boot_cpu_physical_apicid
= -1U;
64 * The highest APIC ID seen during enumeration.
66 unsigned int max_physical_apicid
;
69 * Bitmask of physically existing CPUs:
71 physid_mask_t phys_cpu_present_map
;
74 * Map cpu index to physical APIC ID
76 DEFINE_EARLY_PER_CPU(u16
, x86_cpu_to_apicid
, BAD_APICID
);
77 DEFINE_EARLY_PER_CPU(u16
, x86_bios_cpu_apicid
, BAD_APICID
);
78 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid
);
79 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid
);
84 * On x86_32, the mapping between cpu and logical apicid may vary
85 * depending on apic in use. The following early percpu variable is
86 * used for the mapping. This is where the behaviors of x86_64 and 32
87 * actually diverge. Let's keep it ugly for now.
89 DEFINE_EARLY_PER_CPU(int, x86_cpu_to_logical_apicid
, BAD_APICID
);
92 * Knob to control our willingness to enable the local APIC.
96 static int force_enable_local_apic __initdata
;
98 * APIC command line parameters
100 static int __init
parse_lapic(char *arg
)
102 force_enable_local_apic
= 1;
105 early_param("lapic", parse_lapic
);
106 /* Local APIC was disabled by the BIOS and enabled by the kernel */
107 static int enabled_via_apicbase
;
110 * Handle interrupt mode configuration register (IMCR).
111 * This register controls whether the interrupt signals
112 * that reach the BSP come from the master PIC or from the
113 * local APIC. Before entering Symmetric I/O Mode, either
114 * the BIOS or the operating system must switch out of
115 * PIC Mode by changing the IMCR.
117 static inline void imcr_pic_to_apic(void)
119 /* select IMCR register */
121 /* NMI and 8259 INTR go through APIC */
125 static inline void imcr_apic_to_pic(void)
127 /* select IMCR register */
129 /* NMI and 8259 INTR go directly to BSP */
135 static int apic_calibrate_pmtmr __initdata
;
136 static __init
int setup_apicpmtimer(char *s
)
138 apic_calibrate_pmtmr
= 1;
142 __setup("apicpmtimer", setup_apicpmtimer
);
146 #ifdef CONFIG_X86_X2APIC
147 /* x2apic enabled before OS handover */
148 static int x2apic_preenabled
;
149 static __init
int setup_nox2apic(char *str
)
151 if (x2apic_enabled()) {
152 pr_warning("Bios already enabled x2apic, "
153 "can't enforce nox2apic");
157 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
160 early_param("nox2apic", setup_nox2apic
);
163 unsigned long mp_lapic_addr
;
165 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
166 static int disable_apic_timer __initdata
;
167 /* Local APIC timer works in C2 */
168 int local_apic_timer_c2_ok
;
169 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
171 int first_system_vector
= 0xfe;
174 * Debug level, exported for io_apic.c
176 unsigned int apic_verbosity
;
180 /* Have we found an MP table */
181 int smp_found_config
;
183 static struct resource lapic_resource
= {
184 .name
= "Local APIC",
185 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
188 static unsigned int calibration_result
;
190 static void apic_pm_activate(void);
192 static unsigned long apic_phys
;
195 * Get the LAPIC version
197 static inline int lapic_get_version(void)
199 return GET_APIC_VERSION(apic_read(APIC_LVR
));
203 * Check, if the APIC is integrated or a separate chip
205 static inline int lapic_is_integrated(void)
210 return APIC_INTEGRATED(lapic_get_version());
215 * Check, whether this is a modern or a first generation APIC
217 static int modern_apic(void)
219 /* AMD systems use old APIC versions, so check the CPU */
220 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
221 boot_cpu_data
.x86
>= 0xf)
223 return lapic_get_version() >= 0x14;
227 * right after this call apic become NOOP driven
228 * so apic->write/read doesn't do anything
230 static void __init
apic_disable(void)
232 pr_info("APIC: switched to apic NOOP\n");
236 void native_apic_wait_icr_idle(void)
238 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
242 u32
native_safe_apic_wait_icr_idle(void)
249 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
253 } while (timeout
++ < 1000);
258 void native_apic_icr_write(u32 low
, u32 id
)
260 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
261 apic_write(APIC_ICR
, low
);
264 u64
native_apic_icr_read(void)
268 icr2
= apic_read(APIC_ICR2
);
269 icr1
= apic_read(APIC_ICR
);
271 return icr1
| ((u64
)icr2
<< 32);
276 * get_physical_broadcast - Get number of physical broadcast IDs
278 int get_physical_broadcast(void)
280 return modern_apic() ? 0xff : 0xf;
285 * lapic_get_maxlvt - get the maximum number of local vector table entries
287 int lapic_get_maxlvt(void)
291 v
= apic_read(APIC_LVR
);
293 * - we always have APIC integrated on 64bit mode
294 * - 82489DXs do not report # of LVT entries
296 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
304 #define APIC_DIVISOR 16
307 * This function sets up the local APIC timer, with a timeout of
308 * 'clocks' APIC bus clock. During calibration we actually call
309 * this function twice on the boot CPU, once with a bogus timeout
310 * value, second time for real. The other (noncalibrating) CPUs
311 * call this function only once, with the real, calibrated value.
313 * We do reads before writes even if unnecessary, to get around the
314 * P5 APIC double write bug.
316 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
318 unsigned int lvtt_value
, tmp_value
;
320 lvtt_value
= LOCAL_TIMER_VECTOR
;
322 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
323 if (!lapic_is_integrated())
324 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
327 lvtt_value
|= APIC_LVT_MASKED
;
329 apic_write(APIC_LVTT
, lvtt_value
);
334 tmp_value
= apic_read(APIC_TDCR
);
335 apic_write(APIC_TDCR
,
336 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
340 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
344 * Setup extended LVT, AMD specific
346 * Software should use the LVT offsets the BIOS provides. The offsets
347 * are determined by the subsystems using it like those for MCE
348 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
349 * are supported. Beginning with family 10h at least 4 offsets are
352 * Since the offsets must be consistent for all cores, we keep track
353 * of the LVT offsets in software and reserve the offset for the same
354 * vector also to be used on other cores. An offset is freed by
355 * setting the entry to APIC_EILVT_MASKED.
357 * If the BIOS is right, there should be no conflicts. Otherwise a
358 * "[Firmware Bug]: ..." error message is generated. However, if
359 * software does not properly determines the offsets, it is not
360 * necessarily a BIOS bug.
363 static atomic_t eilvt_offsets
[APIC_EILVT_NR_MAX
];
365 static inline int eilvt_entry_is_changeable(unsigned int old
, unsigned int new)
367 return (old
& APIC_EILVT_MASKED
)
368 || (new == APIC_EILVT_MASKED
)
369 || ((new & ~APIC_EILVT_MASKED
) == old
);
372 static unsigned int reserve_eilvt_offset(int offset
, unsigned int new)
374 unsigned int rsvd
; /* 0: uninitialized */
376 if (offset
>= APIC_EILVT_NR_MAX
)
379 rsvd
= atomic_read(&eilvt_offsets
[offset
]) & ~APIC_EILVT_MASKED
;
382 !eilvt_entry_is_changeable(rsvd
, new))
383 /* may not change if vectors are different */
385 rsvd
= atomic_cmpxchg(&eilvt_offsets
[offset
], rsvd
, new);
386 } while (rsvd
!= new);
392 * If mask=1, the LVT entry does not generate interrupts while mask=0
393 * enables the vector. See also the BKDGs.
396 int setup_APIC_eilvt(u8 offset
, u8 vector
, u8 msg_type
, u8 mask
)
398 unsigned long reg
= APIC_EILVTn(offset
);
399 unsigned int new, old
, reserved
;
401 new = (mask
<< 16) | (msg_type
<< 8) | vector
;
402 old
= apic_read(reg
);
403 reserved
= reserve_eilvt_offset(offset
, new);
405 if (reserved
!= new) {
406 pr_err(FW_BUG
"cpu %d, try to use APIC%lX (LVT offset %d) for "
407 "vector 0x%x, but the register is already in use for "
408 "vector 0x%x on another cpu\n",
409 smp_processor_id(), reg
, offset
, new, reserved
);
413 if (!eilvt_entry_is_changeable(old
, new)) {
414 pr_err(FW_BUG
"cpu %d, try to use APIC%lX (LVT offset %d) for "
415 "vector 0x%x, but the register is already in use for "
416 "vector 0x%x on this cpu\n",
417 smp_processor_id(), reg
, offset
, new, old
);
421 apic_write(reg
, new);
425 EXPORT_SYMBOL_GPL(setup_APIC_eilvt
);
428 * Program the next event, relative to now
430 static int lapic_next_event(unsigned long delta
,
431 struct clock_event_device
*evt
)
433 apic_write(APIC_TMICT
, delta
);
438 * Setup the lapic timer in periodic or oneshot mode
440 static void lapic_timer_setup(enum clock_event_mode mode
,
441 struct clock_event_device
*evt
)
446 /* Lapic used as dummy for broadcast ? */
447 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
450 local_irq_save(flags
);
453 case CLOCK_EVT_MODE_PERIODIC
:
454 case CLOCK_EVT_MODE_ONESHOT
:
455 __setup_APIC_LVTT(calibration_result
,
456 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
458 case CLOCK_EVT_MODE_UNUSED
:
459 case CLOCK_EVT_MODE_SHUTDOWN
:
460 v
= apic_read(APIC_LVTT
);
461 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
462 apic_write(APIC_LVTT
, v
);
463 apic_write(APIC_TMICT
, 0);
465 case CLOCK_EVT_MODE_RESUME
:
466 /* Nothing to do here */
470 local_irq_restore(flags
);
474 * Local APIC timer broadcast function
476 static void lapic_timer_broadcast(const struct cpumask
*mask
)
479 apic
->send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
485 * The local apic timer can be used for any function which is CPU local.
487 static struct clock_event_device lapic_clockevent
= {
489 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
490 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
492 .set_mode
= lapic_timer_setup
,
493 .set_next_event
= lapic_next_event
,
494 .broadcast
= lapic_timer_broadcast
,
498 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
501 * Setup the local APIC timer for this CPU. Copy the initialized values
502 * of the boot CPU and register the clock event in the framework.
504 static void __cpuinit
setup_APIC_timer(void)
506 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
508 if (cpu_has(__this_cpu_ptr(&cpu_info
), X86_FEATURE_ARAT
)) {
509 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_C3STOP
;
510 /* Make LAPIC timer preferrable over percpu HPET */
511 lapic_clockevent
.rating
= 150;
514 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
515 levt
->cpumask
= cpumask_of(smp_processor_id());
517 clockevents_register_device(levt
);
521 * In this functions we calibrate APIC bus clocks to the external timer.
523 * We want to do the calibration only once since we want to have local timer
524 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
527 * This was previously done by reading the PIT/HPET and waiting for a wrap
528 * around to find out, that a tick has elapsed. I have a box, where the PIT
529 * readout is broken, so it never gets out of the wait loop again. This was
530 * also reported by others.
532 * Monitoring the jiffies value is inaccurate and the clockevents
533 * infrastructure allows us to do a simple substitution of the interrupt
536 * The calibration routine also uses the pm_timer when possible, as the PIT
537 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
538 * back to normal later in the boot process).
541 #define LAPIC_CAL_LOOPS (HZ/10)
543 static __initdata
int lapic_cal_loops
= -1;
544 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
545 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
546 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
547 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
550 * Temporary interrupt handler.
552 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
554 unsigned long long tsc
= 0;
555 long tapic
= apic_read(APIC_TMCCT
);
556 unsigned long pm
= acpi_pm_read_early();
561 switch (lapic_cal_loops
++) {
563 lapic_cal_t1
= tapic
;
564 lapic_cal_tsc1
= tsc
;
566 lapic_cal_j1
= jiffies
;
569 case LAPIC_CAL_LOOPS
:
570 lapic_cal_t2
= tapic
;
571 lapic_cal_tsc2
= tsc
;
572 if (pm
< lapic_cal_pm1
)
573 pm
+= ACPI_PM_OVRRUN
;
575 lapic_cal_j2
= jiffies
;
581 calibrate_by_pmtimer(long deltapm
, long *delta
, long *deltatsc
)
583 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
584 const long pm_thresh
= pm_100ms
/ 100;
588 #ifndef CONFIG_X86_PM_TIMER
592 apic_printk(APIC_VERBOSE
, "... PM-Timer delta = %ld\n", deltapm
);
594 /* Check, if the PM timer is available */
598 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
600 if (deltapm
> (pm_100ms
- pm_thresh
) &&
601 deltapm
< (pm_100ms
+ pm_thresh
)) {
602 apic_printk(APIC_VERBOSE
, "... PM-Timer result ok\n");
606 res
= (((u64
)deltapm
) * mult
) >> 22;
607 do_div(res
, 1000000);
608 pr_warning("APIC calibration not consistent "
609 "with PM-Timer: %ldms instead of 100ms\n",(long)res
);
611 /* Correct the lapic counter value */
612 res
= (((u64
)(*delta
)) * pm_100ms
);
613 do_div(res
, deltapm
);
614 pr_info("APIC delta adjusted to PM-Timer: "
615 "%lu (%ld)\n", (unsigned long)res
, *delta
);
618 /* Correct the tsc counter value */
620 res
= (((u64
)(*deltatsc
)) * pm_100ms
);
621 do_div(res
, deltapm
);
622 apic_printk(APIC_VERBOSE
, "TSC delta adjusted to "
623 "PM-Timer: %lu (%ld)\n",
624 (unsigned long)res
, *deltatsc
);
625 *deltatsc
= (long)res
;
631 static int __init
calibrate_APIC_clock(void)
633 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
634 void (*real_handler
)(struct clock_event_device
*dev
);
635 unsigned long deltaj
;
636 long delta
, deltatsc
;
637 int pm_referenced
= 0;
641 /* Replace the global interrupt handler */
642 real_handler
= global_clock_event
->event_handler
;
643 global_clock_event
->event_handler
= lapic_cal_handler
;
646 * Setup the APIC counter to maximum. There is no way the lapic
647 * can underflow in the 100ms detection time frame
649 __setup_APIC_LVTT(0xffffffff, 0, 0);
651 /* Let the interrupts run */
654 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
659 /* Restore the real event handler */
660 global_clock_event
->event_handler
= real_handler
;
662 /* Build delta t1-t2 as apic timer counts down */
663 delta
= lapic_cal_t1
- lapic_cal_t2
;
664 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
666 deltatsc
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
668 /* we trust the PM based calibration if possible */
669 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
672 /* Calculate the scaled math multiplication factor */
673 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
674 lapic_clockevent
.shift
);
675 lapic_clockevent
.max_delta_ns
=
676 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent
);
677 lapic_clockevent
.min_delta_ns
=
678 clockevent_delta2ns(0xF, &lapic_clockevent
);
680 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
682 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
683 apic_printk(APIC_VERBOSE
, "..... mult: %u\n", lapic_clockevent
.mult
);
684 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
688 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
690 (deltatsc
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
691 (deltatsc
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
694 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
696 calibration_result
/ (1000000 / HZ
),
697 calibration_result
% (1000000 / HZ
));
700 * Do a sanity check on the APIC calibration result
702 if (calibration_result
< (1000000 / HZ
)) {
704 pr_warning("APIC frequency too slow, disabling apic timer\n");
708 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
711 * PM timer calibration failed or not turned on
712 * so lets try APIC timer based calibration
714 if (!pm_referenced
) {
715 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
718 * Setup the apic timer manually
720 levt
->event_handler
= lapic_cal_handler
;
721 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
722 lapic_cal_loops
= -1;
724 /* Let the interrupts run */
727 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
730 /* Stop the lapic timer */
731 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
734 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
735 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
737 /* Check, if the jiffies result is consistent */
738 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
739 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
741 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
745 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
746 pr_warning("APIC timer disabled due to verification failure\n");
754 * Setup the boot APIC
756 * Calibrate and verify the result.
758 void __init
setup_boot_APIC_clock(void)
761 * The local apic timer can be disabled via the kernel
762 * commandline or from the CPU detection code. Register the lapic
763 * timer as a dummy clock event source on SMP systems, so the
764 * broadcast mechanism is used. On UP systems simply ignore it.
766 if (disable_apic_timer
) {
767 pr_info("Disabling APIC timer\n");
768 /* No broadcast on UP ! */
769 if (num_possible_cpus() > 1) {
770 lapic_clockevent
.mult
= 1;
776 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
777 "calibrating APIC timer ...\n");
779 if (calibrate_APIC_clock()) {
780 /* No broadcast on UP ! */
781 if (num_possible_cpus() > 1)
787 * If nmi_watchdog is set to IO_APIC, we need the
788 * PIT/HPET going. Otherwise register lapic as a dummy
791 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
793 /* Setup the lapic or request the broadcast */
797 void __cpuinit
setup_secondary_APIC_clock(void)
803 * The guts of the apic timer interrupt
805 static void local_apic_timer_interrupt(void)
807 int cpu
= smp_processor_id();
808 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
811 * Normally we should not be here till LAPIC has been initialized but
812 * in some cases like kdump, its possible that there is a pending LAPIC
813 * timer interrupt from previous kernel's context and is delivered in
814 * new kernel the moment interrupts are enabled.
816 * Interrupts are enabled early and LAPIC is setup much later, hence
817 * its possible that when we get here evt->event_handler is NULL.
818 * Check for event_handler being NULL and discard the interrupt as
821 if (!evt
->event_handler
) {
822 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
824 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
829 * the NMI deadlock-detector uses this.
831 inc_irq_stat(apic_timer_irqs
);
833 evt
->event_handler(evt
);
837 * Local APIC timer interrupt. This is the most natural way for doing
838 * local interrupts, but local timer interrupts can be emulated by
839 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
841 * [ if a single-CPU system runs an SMP kernel then we call the local
842 * interrupt as well. Thus we cannot inline the local irq ... ]
844 void __irq_entry
smp_apic_timer_interrupt(struct pt_regs
*regs
)
846 struct pt_regs
*old_regs
= set_irq_regs(regs
);
849 * NOTE! We'd better ACK the irq immediately,
850 * because timer handling can be slow.
854 * update_process_times() expects us to have done irq_enter().
855 * Besides, if we don't timer interrupts ignore the global
856 * interrupt lock, which is the WrongThing (tm) to do.
860 local_apic_timer_interrupt();
863 set_irq_regs(old_regs
);
866 int setup_profiling_timer(unsigned int multiplier
)
872 * Local APIC start and shutdown
876 * clear_local_APIC - shutdown the local APIC
878 * This is called, when a CPU is disabled and before rebooting, so the state of
879 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
880 * leftovers during boot.
882 void clear_local_APIC(void)
887 /* APIC hasn't been mapped yet */
888 if (!x2apic_mode
&& !apic_phys
)
891 maxlvt
= lapic_get_maxlvt();
893 * Masking an LVT entry can trigger a local APIC error
894 * if the vector is zero. Mask LVTERR first to prevent this.
897 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
898 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
901 * Careful: we have to set masks only first to deassert
902 * any level-triggered sources.
904 v
= apic_read(APIC_LVTT
);
905 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
906 v
= apic_read(APIC_LVT0
);
907 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
908 v
= apic_read(APIC_LVT1
);
909 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
911 v
= apic_read(APIC_LVTPC
);
912 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
915 /* lets not touch this if we didn't frob it */
916 #ifdef CONFIG_X86_THERMAL_VECTOR
918 v
= apic_read(APIC_LVTTHMR
);
919 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
922 #ifdef CONFIG_X86_MCE_INTEL
924 v
= apic_read(APIC_LVTCMCI
);
925 if (!(v
& APIC_LVT_MASKED
))
926 apic_write(APIC_LVTCMCI
, v
| APIC_LVT_MASKED
);
931 * Clean APIC state for other OSs:
933 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
934 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
935 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
937 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
939 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
941 /* Integrated APIC (!82489DX) ? */
942 if (lapic_is_integrated()) {
944 /* Clear ESR due to Pentium errata 3AP and 11AP */
945 apic_write(APIC_ESR
, 0);
951 * disable_local_APIC - clear and disable the local APIC
953 void disable_local_APIC(void)
957 /* APIC hasn't been mapped yet */
958 if (!x2apic_mode
&& !apic_phys
)
964 * Disable APIC (implies clearing of registers
967 value
= apic_read(APIC_SPIV
);
968 value
&= ~APIC_SPIV_APIC_ENABLED
;
969 apic_write(APIC_SPIV
, value
);
973 * When LAPIC was disabled by the BIOS and enabled by the kernel,
974 * restore the disabled state.
976 if (enabled_via_apicbase
) {
979 rdmsr(MSR_IA32_APICBASE
, l
, h
);
980 l
&= ~MSR_IA32_APICBASE_ENABLE
;
981 wrmsr(MSR_IA32_APICBASE
, l
, h
);
987 * If Linux enabled the LAPIC against the BIOS default disable it down before
988 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
989 * not power-off. Additionally clear all LVT entries before disable_local_APIC
990 * for the case where Linux didn't enable the LAPIC.
992 void lapic_shutdown(void)
996 if (!cpu_has_apic
&& !apic_from_smp_config())
999 local_irq_save(flags
);
1001 #ifdef CONFIG_X86_32
1002 if (!enabled_via_apicbase
)
1006 disable_local_APIC();
1009 local_irq_restore(flags
);
1013 * This is to verify that we're looking at a real local APIC.
1014 * Check these against your board if the CPUs aren't getting
1015 * started for no apparent reason.
1017 int __init
verify_local_APIC(void)
1019 unsigned int reg0
, reg1
;
1022 * The version register is read-only in a real APIC.
1024 reg0
= apic_read(APIC_LVR
);
1025 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
1026 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
1027 reg1
= apic_read(APIC_LVR
);
1028 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
1031 * The two version reads above should print the same
1032 * numbers. If the second one is different, then we
1033 * poke at a non-APIC.
1039 * Check if the version looks reasonably.
1041 reg1
= GET_APIC_VERSION(reg0
);
1042 if (reg1
== 0x00 || reg1
== 0xff)
1044 reg1
= lapic_get_maxlvt();
1045 if (reg1
< 0x02 || reg1
== 0xff)
1049 * The ID register is read/write in a real APIC.
1051 reg0
= apic_read(APIC_ID
);
1052 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
1053 apic_write(APIC_ID
, reg0
^ apic
->apic_id_mask
);
1054 reg1
= apic_read(APIC_ID
);
1055 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
1056 apic_write(APIC_ID
, reg0
);
1057 if (reg1
!= (reg0
^ apic
->apic_id_mask
))
1061 * The next two are just to see if we have sane values.
1062 * They're only really relevant if we're in Virtual Wire
1063 * compatibility mode, but most boxes are anymore.
1065 reg0
= apic_read(APIC_LVT0
);
1066 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
1067 reg1
= apic_read(APIC_LVT1
);
1068 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
1074 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1076 void __init
sync_Arb_IDs(void)
1079 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1082 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1088 apic_wait_icr_idle();
1090 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1091 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1092 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1096 * An initial setup of the virtual wire mode.
1098 void __init
init_bsp_APIC(void)
1103 * Don't do the setup now if we have a SMP BIOS as the
1104 * through-I/O-APIC virtual wire mode might be active.
1106 if (smp_found_config
|| !cpu_has_apic
)
1110 * Do not trust the local APIC being empty at bootup.
1117 value
= apic_read(APIC_SPIV
);
1118 value
&= ~APIC_VECTOR_MASK
;
1119 value
|= APIC_SPIV_APIC_ENABLED
;
1121 #ifdef CONFIG_X86_32
1122 /* This bit is reserved on P4/Xeon and should be cleared */
1123 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1124 (boot_cpu_data
.x86
== 15))
1125 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1128 value
|= APIC_SPIV_FOCUS_DISABLED
;
1129 value
|= SPURIOUS_APIC_VECTOR
;
1130 apic_write(APIC_SPIV
, value
);
1133 * Set up the virtual wire mode.
1135 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1136 value
= APIC_DM_NMI
;
1137 if (!lapic_is_integrated()) /* 82489DX */
1138 value
|= APIC_LVT_LEVEL_TRIGGER
;
1139 apic_write(APIC_LVT1
, value
);
1142 static void __cpuinit
lapic_setup_esr(void)
1144 unsigned int oldvalue
, value
, maxlvt
;
1146 if (!lapic_is_integrated()) {
1147 pr_info("No ESR for 82489DX.\n");
1151 if (apic
->disable_esr
) {
1153 * Something untraceable is creating bad interrupts on
1154 * secondary quads ... for the moment, just leave the
1155 * ESR disabled - we can't do anything useful with the
1156 * errors anyway - mbligh
1158 pr_info("Leaving ESR disabled.\n");
1162 maxlvt
= lapic_get_maxlvt();
1163 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1164 apic_write(APIC_ESR
, 0);
1165 oldvalue
= apic_read(APIC_ESR
);
1167 /* enables sending errors */
1168 value
= ERROR_APIC_VECTOR
;
1169 apic_write(APIC_LVTERR
, value
);
1172 * spec says clear errors after enabling vector.
1175 apic_write(APIC_ESR
, 0);
1176 value
= apic_read(APIC_ESR
);
1177 if (value
!= oldvalue
)
1178 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1179 "vector: 0x%08x after: 0x%08x\n",
1184 * setup_local_APIC - setup the local APIC
1186 * Used to setup local APIC while initializing BSP or bringin up APs.
1187 * Always called with preemption disabled.
1189 void __cpuinit
setup_local_APIC(void)
1191 int cpu
= smp_processor_id();
1192 unsigned int value
, queued
;
1193 int i
, j
, acked
= 0;
1194 unsigned long long tsc
= 0, ntsc
;
1195 long long max_loops
= cpu_khz
;
1201 disable_ioapic_support();
1205 #ifdef CONFIG_X86_32
1206 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1207 if (lapic_is_integrated() && apic
->disable_esr
) {
1208 apic_write(APIC_ESR
, 0);
1209 apic_write(APIC_ESR
, 0);
1210 apic_write(APIC_ESR
, 0);
1211 apic_write(APIC_ESR
, 0);
1214 perf_events_lapic_init();
1217 * Double-check whether this APIC is really registered.
1218 * This is meaningless in clustered apic mode, so we skip it.
1220 BUG_ON(!apic
->apic_id_registered());
1223 * Intel recommends to set DFR, LDR and TPR before enabling
1224 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1225 * document number 292116). So here it goes...
1227 apic
->init_apic_ldr();
1229 #ifdef CONFIG_X86_32
1231 * APIC LDR is initialized. If logical_apicid mapping was
1232 * initialized during get_smp_config(), make sure it matches the
1235 i
= early_per_cpu(x86_cpu_to_logical_apicid
, cpu
);
1236 WARN_ON(i
!= BAD_APICID
&& i
!= logical_smp_processor_id());
1237 /* always use the value from LDR */
1238 early_per_cpu(x86_cpu_to_logical_apicid
, cpu
) =
1239 logical_smp_processor_id();
1243 * Set Task Priority to 'accept all'. We never change this
1246 value
= apic_read(APIC_TASKPRI
);
1247 value
&= ~APIC_TPRI_MASK
;
1248 apic_write(APIC_TASKPRI
, value
);
1251 * After a crash, we no longer service the interrupts and a pending
1252 * interrupt from previous kernel might still have ISR bit set.
1254 * Most probably by now CPU has serviced that pending interrupt and
1255 * it might not have done the ack_APIC_irq() because it thought,
1256 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1257 * does not clear the ISR bit and cpu thinks it has already serivced
1258 * the interrupt. Hence a vector might get locked. It was noticed
1259 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1263 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--)
1264 queued
|= apic_read(APIC_IRR
+ i
*0x10);
1266 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1267 value
= apic_read(APIC_ISR
+ i
*0x10);
1268 for (j
= 31; j
>= 0; j
--) {
1269 if (value
& (1<<j
)) {
1276 printk(KERN_ERR
"LAPIC pending interrupts after %d EOI\n",
1282 max_loops
= (cpu_khz
<< 10) - (ntsc
- tsc
);
1285 } while (queued
&& max_loops
> 0);
1286 WARN_ON(max_loops
<= 0);
1289 * Now that we are all set up, enable the APIC
1291 value
= apic_read(APIC_SPIV
);
1292 value
&= ~APIC_VECTOR_MASK
;
1296 value
|= APIC_SPIV_APIC_ENABLED
;
1298 #ifdef CONFIG_X86_32
1300 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1301 * certain networking cards. If high frequency interrupts are
1302 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1303 * entry is masked/unmasked at a high rate as well then sooner or
1304 * later IOAPIC line gets 'stuck', no more interrupts are received
1305 * from the device. If focus CPU is disabled then the hang goes
1308 * [ This bug can be reproduced easily with a level-triggered
1309 * PCI Ne2000 networking cards and PII/PIII processors, dual
1313 * Actually disabling the focus CPU check just makes the hang less
1314 * frequent as it makes the interrupt distributon model be more
1315 * like LRU than MRU (the short-term load is more even across CPUs).
1316 * See also the comment in end_level_ioapic_irq(). --macro
1320 * - enable focus processor (bit==0)
1321 * - 64bit mode always use processor focus
1322 * so no need to set it
1324 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1328 * Set spurious IRQ vector
1330 value
|= SPURIOUS_APIC_VECTOR
;
1331 apic_write(APIC_SPIV
, value
);
1334 * Set up LVT0, LVT1:
1336 * set up through-local-APIC on the BP's LINT0. This is not
1337 * strictly necessary in pure symmetric-IO mode, but sometimes
1338 * we delegate interrupts to the 8259A.
1341 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1343 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1344 if (!cpu
&& (pic_mode
|| !value
)) {
1345 value
= APIC_DM_EXTINT
;
1346 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n", cpu
);
1348 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1349 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n", cpu
);
1351 apic_write(APIC_LVT0
, value
);
1354 * only the BP should see the LINT1 NMI signal, obviously.
1357 value
= APIC_DM_NMI
;
1359 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1360 if (!lapic_is_integrated()) /* 82489DX */
1361 value
|= APIC_LVT_LEVEL_TRIGGER
;
1362 apic_write(APIC_LVT1
, value
);
1364 #ifdef CONFIG_X86_MCE_INTEL
1365 /* Recheck CMCI information after local APIC is up on CPU #0 */
1371 void __cpuinit
end_local_APIC_setup(void)
1375 #ifdef CONFIG_X86_32
1378 /* Disable the local apic timer */
1379 value
= apic_read(APIC_LVTT
);
1380 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1381 apic_write(APIC_LVTT
, value
);
1388 void __init
bsp_end_local_APIC_setup(void)
1390 end_local_APIC_setup();
1393 * Now that local APIC setup is completed for BP, configure the fault
1394 * handling for interrupt remapping.
1396 if (intr_remapping_enabled
)
1397 enable_drhd_fault_handling();
1401 #ifdef CONFIG_X86_X2APIC
1402 void check_x2apic(void)
1404 if (x2apic_enabled()) {
1405 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1406 x2apic_preenabled
= x2apic_mode
= 1;
1410 void enable_x2apic(void)
1417 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1418 if (!(msr
& X2APIC_ENABLE
)) {
1419 printk_once(KERN_INFO
"Enabling x2apic\n");
1420 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1423 #endif /* CONFIG_X86_X2APIC */
1425 int __init
enable_IR(void)
1427 #ifdef CONFIG_INTR_REMAP
1428 if (!intr_remapping_supported()) {
1429 pr_debug("intr-remapping not supported\n");
1433 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1434 pr_info("Skipped enabling intr-remap because of skipping "
1439 if (enable_intr_remapping(x2apic_supported()))
1442 pr_info("Enabled Interrupt-remapping\n");
1450 void __init
enable_IR_x2apic(void)
1452 unsigned long flags
;
1453 struct IO_APIC_route_entry
**ioapic_entries
;
1454 int ret
, x2apic_enabled
= 0;
1455 int dmar_table_init_ret
;
1457 dmar_table_init_ret
= dmar_table_init();
1458 if (dmar_table_init_ret
&& !x2apic_supported())
1461 ioapic_entries
= alloc_ioapic_entries();
1462 if (!ioapic_entries
) {
1463 pr_err("Allocate ioapic_entries failed\n");
1467 ret
= save_IO_APIC_setup(ioapic_entries
);
1469 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1473 local_irq_save(flags
);
1474 legacy_pic
->mask_all();
1475 mask_IO_APIC_setup(ioapic_entries
);
1477 if (dmar_table_init_ret
)
1483 /* IR is required if there is APIC ID > 255 even when running
1486 if (max_physical_apicid
> 255 ||
1487 !hypervisor_x2apic_available())
1490 * without IR all CPUs can be addressed by IOAPIC/MSI
1491 * only in physical mode
1493 x2apic_force_phys();
1498 if (x2apic_supported() && !x2apic_mode
) {
1501 pr_info("Enabled x2apic\n");
1505 if (!ret
) /* IR enabling failed */
1506 restore_IO_APIC_setup(ioapic_entries
);
1507 legacy_pic
->restore_mask();
1508 local_irq_restore(flags
);
1512 free_ioapic_entries(ioapic_entries
);
1517 if (x2apic_preenabled
)
1518 panic("x2apic: enabled by BIOS but kernel init failed.");
1519 else if (cpu_has_x2apic
)
1520 pr_info("Not enabling x2apic, Intr-remapping init failed.\n");
1523 #ifdef CONFIG_X86_64
1525 * Detect and enable local APICs on non-SMP boards.
1526 * Original code written by Keir Fraser.
1527 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1528 * not correctly set up (usually the APIC timer won't work etc.)
1530 static int __init
detect_init_APIC(void)
1532 if (!cpu_has_apic
) {
1533 pr_info("No local APIC present\n");
1537 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1542 static int __init
apic_verify(void)
1547 * The APIC feature bit should now be enabled
1550 features
= cpuid_edx(1);
1551 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1552 pr_warning("Could not enable APIC!\n");
1555 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1556 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1558 /* The BIOS may have set up the APIC at some other address */
1559 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1560 if (l
& MSR_IA32_APICBASE_ENABLE
)
1561 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1563 pr_info("Found and enabled local APIC!\n");
1567 int __init
apic_force_enable(unsigned long addr
)
1575 * Some BIOSes disable the local APIC in the APIC_BASE
1576 * MSR. This can only be done in software for Intel P6 or later
1577 * and AMD K7 (Model > 1) or later.
1579 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1580 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1581 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1582 l
&= ~MSR_IA32_APICBASE_BASE
;
1583 l
|= MSR_IA32_APICBASE_ENABLE
| addr
;
1584 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1585 enabled_via_apicbase
= 1;
1587 return apic_verify();
1591 * Detect and initialize APIC
1593 static int __init
detect_init_APIC(void)
1595 /* Disabled by kernel option? */
1599 switch (boot_cpu_data
.x86_vendor
) {
1600 case X86_VENDOR_AMD
:
1601 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1602 (boot_cpu_data
.x86
>= 15))
1605 case X86_VENDOR_INTEL
:
1606 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1607 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1614 if (!cpu_has_apic
) {
1616 * Over-ride BIOS and try to enable the local APIC only if
1617 * "lapic" specified.
1619 if (!force_enable_local_apic
) {
1620 pr_info("Local APIC disabled by BIOS -- "
1621 "you can enable it with \"lapic\"\n");
1624 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE
))
1636 pr_info("No local APIC present or hardware disabled\n");
1642 * init_apic_mappings - initialize APIC mappings
1644 void __init
init_apic_mappings(void)
1646 unsigned int new_apicid
;
1649 boot_cpu_physical_apicid
= read_apic_id();
1653 /* If no local APIC can be found return early */
1654 if (!smp_found_config
&& detect_init_APIC()) {
1655 /* lets NOP'ify apic operations */
1656 pr_info("APIC: disable apic facility\n");
1659 apic_phys
= mp_lapic_addr
;
1662 * acpi lapic path already maps that address in
1663 * acpi_register_lapic_address()
1665 if (!acpi_lapic
&& !smp_found_config
)
1666 register_lapic_address(apic_phys
);
1670 * Fetch the APIC ID of the BSP in case we have a
1671 * default configuration (or the MP table is broken).
1673 new_apicid
= read_apic_id();
1674 if (boot_cpu_physical_apicid
!= new_apicid
) {
1675 boot_cpu_physical_apicid
= new_apicid
;
1677 * yeah -- we lie about apic_version
1678 * in case if apic was disabled via boot option
1679 * but it's not a problem for SMP compiled kernel
1680 * since smp_sanity_check is prepared for such a case
1681 * and disable smp mode
1683 apic_version
[new_apicid
] =
1684 GET_APIC_VERSION(apic_read(APIC_LVR
));
1688 void __init
register_lapic_address(unsigned long address
)
1690 mp_lapic_addr
= address
;
1693 set_fixmap_nocache(FIX_APIC_BASE
, address
);
1694 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1695 APIC_BASE
, mp_lapic_addr
);
1697 if (boot_cpu_physical_apicid
== -1U) {
1698 boot_cpu_physical_apicid
= read_apic_id();
1699 apic_version
[boot_cpu_physical_apicid
] =
1700 GET_APIC_VERSION(apic_read(APIC_LVR
));
1705 * This initializes the IO-APIC and APIC hardware if this is
1708 int apic_version
[MAX_LOCAL_APIC
];
1710 int __init
APIC_init_uniprocessor(void)
1713 pr_info("Apic disabled\n");
1716 #ifdef CONFIG_X86_64
1717 if (!cpu_has_apic
) {
1719 pr_info("Apic disabled by BIOS\n");
1723 if (!smp_found_config
&& !cpu_has_apic
)
1727 * Complain if the BIOS pretends there is one.
1729 if (!cpu_has_apic
&&
1730 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1731 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1732 boot_cpu_physical_apicid
);
1737 default_setup_apic_routing();
1739 verify_local_APIC();
1742 #ifdef CONFIG_X86_64
1743 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1746 * Hack: In case of kdump, after a crash, kernel might be booting
1747 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1748 * might be zero if read from MP tables. Get it from LAPIC.
1750 # ifdef CONFIG_CRASH_DUMP
1751 boot_cpu_physical_apicid
= read_apic_id();
1754 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1757 #ifdef CONFIG_X86_IO_APIC
1759 * Now enable IO-APICs, actually call clear_IO_APIC
1760 * We need clear_IO_APIC before enabling error vector
1762 if (!skip_ioapic_setup
&& nr_ioapics
)
1766 bsp_end_local_APIC_setup();
1768 #ifdef CONFIG_X86_IO_APIC
1769 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1776 x86_init
.timers
.setup_percpu_clockev();
1781 * Local APIC interrupts
1785 * This interrupt should _never_ happen with our APIC/SMP architecture
1787 void smp_spurious_interrupt(struct pt_regs
*regs
)
1794 * Check if this really is a spurious interrupt and ACK it
1795 * if it is a vectored one. Just in case...
1796 * Spurious interrupts should not be ACKed.
1798 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1799 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1802 inc_irq_stat(irq_spurious_count
);
1804 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1805 pr_info("spurious APIC interrupt on CPU#%d, "
1806 "should never happen.\n", smp_processor_id());
1811 * This interrupt should never happen with our APIC/SMP architecture
1813 void smp_error_interrupt(struct pt_regs
*regs
)
1819 /* First tickle the hardware, only then report what went on. -- REW */
1820 v
= apic_read(APIC_ESR
);
1821 apic_write(APIC_ESR
, 0);
1822 v1
= apic_read(APIC_ESR
);
1824 atomic_inc(&irq_err_count
);
1827 * Here is what the APIC error bits mean:
1829 * 1: Receive CS error
1830 * 2: Send accept error
1831 * 3: Receive accept error
1833 * 5: Send illegal vector
1834 * 6: Received illegal vector
1835 * 7: Illegal register address
1837 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1838 smp_processor_id(), v
, v1
);
1843 * connect_bsp_APIC - attach the APIC to the interrupt system
1845 void __init
connect_bsp_APIC(void)
1847 #ifdef CONFIG_X86_32
1850 * Do not trust the local APIC being empty at bootup.
1854 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1855 * local APIC to INT and NMI lines.
1857 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1858 "enabling APIC mode.\n");
1862 if (apic
->enable_apic_mode
)
1863 apic
->enable_apic_mode();
1867 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1868 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1870 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1873 void disconnect_bsp_APIC(int virt_wire_setup
)
1877 #ifdef CONFIG_X86_32
1880 * Put the board back into PIC mode (has an effect only on
1881 * certain older boards). Note that APIC interrupts, including
1882 * IPIs, won't work beyond this point! The only exception are
1885 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1886 "entering PIC mode.\n");
1892 /* Go back to Virtual Wire compatibility mode */
1894 /* For the spurious interrupt use vector F, and enable it */
1895 value
= apic_read(APIC_SPIV
);
1896 value
&= ~APIC_VECTOR_MASK
;
1897 value
|= APIC_SPIV_APIC_ENABLED
;
1899 apic_write(APIC_SPIV
, value
);
1901 if (!virt_wire_setup
) {
1903 * For LVT0 make it edge triggered, active high,
1904 * external and enabled
1906 value
= apic_read(APIC_LVT0
);
1907 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1908 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1909 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1910 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1911 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1912 apic_write(APIC_LVT0
, value
);
1915 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1919 * For LVT1 make it edge triggered, active high,
1922 value
= apic_read(APIC_LVT1
);
1923 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1924 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1925 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1926 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1927 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1928 apic_write(APIC_LVT1
, value
);
1931 void __cpuinit
generic_processor_info(int apicid
, int version
)
1935 if (num_processors
>= nr_cpu_ids
) {
1936 int max
= nr_cpu_ids
;
1937 int thiscpu
= max
+ disabled_cpus
;
1940 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1941 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
1948 if (apicid
== boot_cpu_physical_apicid
) {
1950 * x86_bios_cpu_apicid is required to have processors listed
1951 * in same order as logical cpu numbers. Hence the first
1952 * entry is BSP, and so on.
1953 * boot_cpu_init() already hold bit 0 in cpu_present_mask
1958 cpu
= cpumask_next_zero(-1, cpu_present_mask
);
1963 if (version
== 0x0) {
1964 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
1968 apic_version
[apicid
] = version
;
1970 if (version
!= apic_version
[boot_cpu_physical_apicid
]) {
1971 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
1972 apic_version
[boot_cpu_physical_apicid
], cpu
, version
);
1975 physid_set(apicid
, phys_cpu_present_map
);
1976 if (apicid
> max_physical_apicid
)
1977 max_physical_apicid
= apicid
;
1979 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1980 early_per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1981 early_per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1983 #ifdef CONFIG_X86_32
1984 early_per_cpu(x86_cpu_to_logical_apicid
, cpu
) =
1985 apic
->x86_32_early_logical_apicid(cpu
);
1987 set_cpu_possible(cpu
, true);
1988 set_cpu_present(cpu
, true);
1991 int hard_smp_processor_id(void)
1993 return read_apic_id();
1996 void default_init_apic_ldr(void)
2000 apic_write(APIC_DFR
, APIC_DFR_VALUE
);
2001 val
= apic_read(APIC_LDR
) & ~APIC_LDR_MASK
;
2002 val
|= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2003 apic_write(APIC_LDR
, val
);
2006 #ifdef CONFIG_X86_32
2007 int default_x86_32_numa_cpu_node(int cpu
)
2010 int apicid
= early_per_cpu(x86_cpu_to_apicid
, cpu
);
2012 if (apicid
!= BAD_APICID
)
2013 return __apicid_to_node
[apicid
];
2014 return NUMA_NO_NODE
;
2028 * 'active' is true if the local APIC was enabled by us and
2029 * not the BIOS; this signifies that we are also responsible
2030 * for disabling it before entering apm/acpi suspend
2033 /* r/w apic fields */
2034 unsigned int apic_id
;
2035 unsigned int apic_taskpri
;
2036 unsigned int apic_ldr
;
2037 unsigned int apic_dfr
;
2038 unsigned int apic_spiv
;
2039 unsigned int apic_lvtt
;
2040 unsigned int apic_lvtpc
;
2041 unsigned int apic_lvt0
;
2042 unsigned int apic_lvt1
;
2043 unsigned int apic_lvterr
;
2044 unsigned int apic_tmict
;
2045 unsigned int apic_tdcr
;
2046 unsigned int apic_thmr
;
2049 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2051 unsigned long flags
;
2054 if (!apic_pm_state
.active
)
2057 maxlvt
= lapic_get_maxlvt();
2059 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
2060 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
2061 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
2062 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
2063 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
2064 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
2066 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
2067 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
2068 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
2069 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
2070 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
2071 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
2072 #ifdef CONFIG_X86_THERMAL_VECTOR
2074 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
2077 local_irq_save(flags
);
2078 disable_local_APIC();
2080 if (intr_remapping_enabled
)
2081 disable_intr_remapping();
2083 local_irq_restore(flags
);
2087 static int lapic_resume(struct sys_device
*dev
)
2090 unsigned long flags
;
2093 struct IO_APIC_route_entry
**ioapic_entries
= NULL
;
2095 if (!apic_pm_state
.active
)
2098 local_irq_save(flags
);
2099 if (intr_remapping_enabled
) {
2100 ioapic_entries
= alloc_ioapic_entries();
2101 if (!ioapic_entries
) {
2102 WARN(1, "Alloc ioapic_entries in lapic resume failed.");
2107 ret
= save_IO_APIC_setup(ioapic_entries
);
2109 WARN(1, "Saving IO-APIC state failed: %d\n", ret
);
2110 free_ioapic_entries(ioapic_entries
);
2114 mask_IO_APIC_setup(ioapic_entries
);
2115 legacy_pic
->mask_all();
2122 * Make sure the APICBASE points to the right address
2124 * FIXME! This will be wrong if we ever support suspend on
2125 * SMP! We'll need to do this as part of the CPU restore!
2127 rdmsr(MSR_IA32_APICBASE
, l
, h
);
2128 l
&= ~MSR_IA32_APICBASE_BASE
;
2129 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
2130 wrmsr(MSR_IA32_APICBASE
, l
, h
);
2133 maxlvt
= lapic_get_maxlvt();
2134 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
2135 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
2136 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
2137 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
2138 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
2139 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
2140 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
2141 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
2142 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2144 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2147 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2148 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2149 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2150 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2151 apic_write(APIC_ESR
, 0);
2152 apic_read(APIC_ESR
);
2153 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2154 apic_write(APIC_ESR
, 0);
2155 apic_read(APIC_ESR
);
2157 if (intr_remapping_enabled
) {
2158 reenable_intr_remapping(x2apic_mode
);
2159 legacy_pic
->restore_mask();
2160 restore_IO_APIC_setup(ioapic_entries
);
2161 free_ioapic_entries(ioapic_entries
);
2164 local_irq_restore(flags
);
2170 * This device has no shutdown method - fully functioning local APICs
2171 * are needed on every CPU up until machine_halt/restart/poweroff.
2174 static struct sysdev_class lapic_sysclass
= {
2176 .resume
= lapic_resume
,
2177 .suspend
= lapic_suspend
,
2180 static struct sys_device device_lapic
= {
2182 .cls
= &lapic_sysclass
,
2185 static void __cpuinit
apic_pm_activate(void)
2187 apic_pm_state
.active
= 1;
2190 static int __init
init_lapic_sysfs(void)
2196 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2198 error
= sysdev_class_register(&lapic_sysclass
);
2200 error
= sysdev_register(&device_lapic
);
2204 /* local apic needs to resume before other devices access its registers. */
2205 core_initcall(init_lapic_sysfs
);
2207 #else /* CONFIG_PM */
2209 static void apic_pm_activate(void) { }
2211 #endif /* CONFIG_PM */
2213 #ifdef CONFIG_X86_64
2215 static int __cpuinit
apic_cluster_num(void)
2217 int i
, clusters
, zeros
;
2219 u16
*bios_cpu_apicid
;
2220 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
2222 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
2223 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
2225 for (i
= 0; i
< nr_cpu_ids
; i
++) {
2226 /* are we being called early in kernel startup? */
2227 if (bios_cpu_apicid
) {
2228 id
= bios_cpu_apicid
[i
];
2229 } else if (i
< nr_cpu_ids
) {
2231 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2237 if (id
!= BAD_APICID
)
2238 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2241 /* Problem: Partially populated chassis may not have CPUs in some of
2242 * the APIC clusters they have been allocated. Only present CPUs have
2243 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2244 * Since clusters are allocated sequentially, count zeros only if
2245 * they are bounded by ones.
2249 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2250 if (test_bit(i
, clustermap
)) {
2251 clusters
+= 1 + zeros
;
2260 static int __cpuinitdata multi_checked
;
2261 static int __cpuinitdata multi
;
2263 static int __cpuinit
set_multi(const struct dmi_system_id
*d
)
2267 pr_info("APIC: %s detected, Multi Chassis\n", d
->ident
);
2272 static const __cpuinitconst
struct dmi_system_id multi_dmi_table
[] = {
2274 .callback
= set_multi
,
2275 .ident
= "IBM System Summit2",
2277 DMI_MATCH(DMI_SYS_VENDOR
, "IBM"),
2278 DMI_MATCH(DMI_PRODUCT_NAME
, "Summit2"),
2284 static void __cpuinit
dmi_check_multi(void)
2289 dmi_check_system(multi_dmi_table
);
2294 * apic_is_clustered_box() -- Check if we can expect good TSC
2296 * Thus far, the major user of this is IBM's Summit2 series:
2297 * Clustered boxes may have unsynced TSC problems if they are
2299 * Use DMI to check them
2301 __cpuinit
int apic_is_clustered_box(void)
2311 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2312 * not guaranteed to be synced between boards
2314 if (apic_cluster_num() > 1)
2322 * APIC command line parameters
2324 static int __init
setup_disableapic(char *arg
)
2327 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2330 early_param("disableapic", setup_disableapic
);
2332 /* same as disableapic, for compatibility */
2333 static int __init
setup_nolapic(char *arg
)
2335 return setup_disableapic(arg
);
2337 early_param("nolapic", setup_nolapic
);
2339 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2341 local_apic_timer_c2_ok
= 1;
2344 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2346 static int __init
parse_disable_apic_timer(char *arg
)
2348 disable_apic_timer
= 1;
2351 early_param("noapictimer", parse_disable_apic_timer
);
2353 static int __init
parse_nolapic_timer(char *arg
)
2355 disable_apic_timer
= 1;
2358 early_param("nolapic_timer", parse_nolapic_timer
);
2360 static int __init
apic_set_verbosity(char *arg
)
2363 #ifdef CONFIG_X86_64
2364 skip_ioapic_setup
= 0;
2370 if (strcmp("debug", arg
) == 0)
2371 apic_verbosity
= APIC_DEBUG
;
2372 else if (strcmp("verbose", arg
) == 0)
2373 apic_verbosity
= APIC_VERBOSE
;
2375 pr_warning("APIC Verbosity level %s not recognised"
2376 " use apic=verbose or apic=debug\n", arg
);
2382 early_param("apic", apic_set_verbosity
);
2384 static int __init
lapic_insert_resource(void)
2389 /* Put local APIC into the resource map. */
2390 lapic_resource
.start
= apic_phys
;
2391 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2392 insert_resource(&iomem_resource
, &lapic_resource
);
2398 * need call insert after e820_reserve_resources()
2399 * that is using request_resource
2401 late_initcall(lapic_insert_resource
);