2 * Shared support code for AMD K8 northbridges and derivates.
3 * Copyright 2006 Andi Kleen, SUSE Labs. Subject to GPLv2.
5 #include <linux/types.h>
6 #include <linux/slab.h>
7 #include <linux/init.h>
8 #include <linux/errno.h>
9 #include <linux/module.h>
10 #include <linux/spinlock.h>
11 #include <asm/amd_nb.h>
13 static u32
*flush_words
;
15 const struct pci_device_id amd_nb_misc_ids
[] = {
16 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_K8_NB_MISC
) },
17 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_10H_NB_MISC
) },
18 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_15H_NB_F3
) },
21 EXPORT_SYMBOL(amd_nb_misc_ids
);
23 static struct pci_device_id amd_nb_link_ids
[] = {
24 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_15H_NB_LINK
) },
28 const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges
[] __initconst
= {
35 struct amd_northbridge_info amd_northbridges
;
36 EXPORT_SYMBOL(amd_northbridges
);
38 static struct pci_dev
*next_northbridge(struct pci_dev
*dev
,
39 const struct pci_device_id
*ids
)
42 dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
);
45 } while (!pci_match_id(ids
, dev
));
49 int amd_cache_northbridges(void)
52 struct amd_northbridge
*nb
;
53 struct pci_dev
*misc
, *link
;
59 while ((misc
= next_northbridge(misc
, amd_nb_misc_ids
)) != NULL
)
65 nb
= kzalloc(i
* sizeof(struct amd_northbridge
), GFP_KERNEL
);
69 amd_northbridges
.nb
= nb
;
70 amd_northbridges
.num
= i
;
73 for (i
= 0; i
!= amd_nb_num(); i
++) {
74 node_to_amd_nb(i
)->misc
= misc
=
75 next_northbridge(misc
, amd_nb_misc_ids
);
76 node_to_amd_nb(i
)->link
= link
=
77 next_northbridge(link
, amd_nb_link_ids
);
80 /* some CPU families (e.g. family 0x11) do not support GART */
81 if (boot_cpu_data
.x86
== 0xf || boot_cpu_data
.x86
== 0x10 ||
82 boot_cpu_data
.x86
== 0x15)
83 amd_northbridges
.flags
|= AMD_NB_GART
;
86 * Some CPU families support L3 Cache Index Disable. There are some
87 * limitations because of E382 and E388 on family 0x10.
89 if (boot_cpu_data
.x86
== 0x10 &&
90 boot_cpu_data
.x86_model
>= 0x8 &&
91 (boot_cpu_data
.x86_model
> 0x9 ||
92 boot_cpu_data
.x86_mask
>= 0x1))
93 amd_northbridges
.flags
|= AMD_NB_L3_INDEX_DISABLE
;
95 if (boot_cpu_data
.x86
== 0x15)
96 amd_northbridges
.flags
|= AMD_NB_L3_INDEX_DISABLE
;
98 /* L3 cache partitioning is supported on family 0x15 */
99 if (boot_cpu_data
.x86
== 0x15)
100 amd_northbridges
.flags
|= AMD_NB_L3_PARTITIONING
;
104 EXPORT_SYMBOL_GPL(amd_cache_northbridges
);
107 * Ignores subdevice/subvendor but as far as I can figure out
108 * they're useless anyways
110 bool __init
early_is_amd_nb(u32 device
)
112 const struct pci_device_id
*id
;
113 u32 vendor
= device
& 0xffff;
116 for (id
= amd_nb_misc_ids
; id
->vendor
; id
++)
117 if (vendor
== id
->vendor
&& device
== id
->device
)
122 int amd_get_subcaches(int cpu
)
124 struct pci_dev
*link
= node_to_amd_nb(amd_get_nb_id(cpu
))->link
;
128 if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING
))
131 pci_read_config_dword(link
, 0x1d4, &mask
);
134 cuid
= cpu_data(cpu
).compute_unit_id
;
136 return (mask
>> (4 * cuid
)) & 0xf;
139 int amd_set_subcaches(int cpu
, int mask
)
141 static unsigned int reset
, ban
;
142 struct amd_northbridge
*nb
= node_to_amd_nb(amd_get_nb_id(cpu
));
146 if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING
) || mask
> 0xf)
149 /* if necessary, collect reset state of L3 partitioning and BAN mode */
151 pci_read_config_dword(nb
->link
, 0x1d4, &reset
);
152 pci_read_config_dword(nb
->misc
, 0x1b8, &ban
);
156 /* deactivate BAN mode if any subcaches are to be disabled */
158 pci_read_config_dword(nb
->misc
, 0x1b8, ®
);
159 pci_write_config_dword(nb
->misc
, 0x1b8, reg
& ~0x180000);
163 cuid
= cpu_data(cpu
).compute_unit_id
;
166 mask
|= (0xf ^ (1 << cuid
)) << 26;
168 pci_write_config_dword(nb
->link
, 0x1d4, mask
);
170 /* reset BAN mode if L3 partitioning returned to reset state */
171 pci_read_config_dword(nb
->link
, 0x1d4, ®
);
173 pci_read_config_dword(nb
->misc
, 0x1b8, ®
);
175 pci_write_config_dword(nb
->misc
, 0x1b8, reg
| ban
);
181 static int amd_cache_gart(void)
185 if (!amd_nb_has_feature(AMD_NB_GART
))
188 flush_words
= kmalloc(amd_nb_num() * sizeof(u32
), GFP_KERNEL
);
190 amd_northbridges
.flags
&= ~AMD_NB_GART
;
194 for (i
= 0; i
!= amd_nb_num(); i
++)
195 pci_read_config_dword(node_to_amd_nb(i
)->misc
, 0x9c,
201 void amd_flush_garts(void)
205 static DEFINE_SPINLOCK(gart_lock
);
207 if (!amd_nb_has_feature(AMD_NB_GART
))
210 /* Avoid races between AGP and IOMMU. In theory it's not needed
211 but I'm not sure if the hardware won't lose flush requests
212 when another is pending. This whole thing is so expensive anyways
213 that it doesn't matter to serialize more. -AK */
214 spin_lock_irqsave(&gart_lock
, flags
);
216 for (i
= 0; i
< amd_nb_num(); i
++) {
217 pci_write_config_dword(node_to_amd_nb(i
)->misc
, 0x9c,
221 for (i
= 0; i
< amd_nb_num(); i
++) {
223 /* Make sure the hardware actually executed the flush*/
225 pci_read_config_dword(node_to_amd_nb(i
)->misc
,
232 spin_unlock_irqrestore(&gart_lock
, flags
);
234 printk("nothing to flush?\n");
236 EXPORT_SYMBOL_GPL(amd_flush_garts
);
238 static __init
int init_amd_nbs(void)
242 err
= amd_cache_northbridges();
245 printk(KERN_NOTICE
"AMD NB: Cannot enumerate AMD northbridges.\n");
247 if (amd_cache_gart() < 0)
248 printk(KERN_NOTICE
"AMD NB: Cannot initialize GART flush words, "
249 "GART support disabled.\n");
254 /* This has to go after the PCI subsystem */
255 fs_initcall(init_amd_nbs
);