| blob | 5ef7af01373a9ee93c04be3227f9f03328a84f64 |
1 config ARM
2 bool
3 default y
4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_WANT_IPC_PARSE_VERSION
9 select BUILDTIME_EXTABLE_SORT if MMU
10 select CPU_PM if (SUSPEND || CPU_IDLE)
11 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
12 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
13 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
14 select GENERIC_IRQ_PROBE
15 select GENERIC_IRQ_SHOW
16 select GENERIC_PCI_IOMAP
17 select GENERIC_SCHED_CLOCK
18 select GENERIC_SMP_IDLE_THREAD
19 select GENERIC_IDLE_POLL_SETUP
20 select GENERIC_STRNCPY_FROM_USER
21 select GENERIC_STRNLEN_USER
22 select HARDIRQS_SW_RESEND
23 select HAVE_AOUT
24 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
25 select HAVE_ARCH_KGDB
26 select HAVE_ARCH_SECCOMP_FILTER
27 select HAVE_ARCH_TRACEHOOK
28 select HAVE_BPF_JIT
29 select HAVE_C_RECORDMCOUNT
30 select HAVE_DEBUG_KMEMLEAK
31 select HAVE_DMA_API_DEBUG
32 select HAVE_DMA_ATTRS
33 select HAVE_DMA_CONTIGUOUS if MMU
34 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
35 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
36 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
37 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
38 select HAVE_GENERIC_DMA_COHERENT
39 select HAVE_GENERIC_HARDIRQS
40 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
41 select HAVE_IDE if PCI || ISA || PCMCIA
42 select HAVE_IRQ_TIME_ACCOUNTING
43 select HAVE_KERNEL_GZIP
44 select HAVE_KERNEL_LZMA
45 select HAVE_KERNEL_LZO
46 select HAVE_KERNEL_XZ
47 select HAVE_KPROBES if !XIP_KERNEL
48 select HAVE_KRETPROBES if (HAVE_KPROBES)
49 select HAVE_MEMBLOCK
50 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
51 select HAVE_PERF_EVENTS
52 select HAVE_REGS_AND_STACK_ACCESS_API
53 select HAVE_SYSCALL_TRACEPOINTS
54 select HAVE_UID16
55 select KTIME_SCALAR
56 select PERF_USE_VMALLOC
57 select RTC_LIB
58 select SYS_SUPPORTS_APM_EMULATION
59 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
60 select MODULES_USE_ELF_REL
61 select CLONE_BACKWARDS
62 select OLD_SIGSUSPEND3
63 select OLD_SIGACTION
64 select HAVE_CONTEXT_TRACKING
65 help
66 The ARM series is a line of low-power-consumption RISC chip designs
67 licensed by ARM Ltd and targeted at embedded applications and
68 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
69 manufactured, but legacy ARM-based PC hardware remains popular in
70 Europe. There is an ARM Linux project with a web page at
71 <http://www.arm.linux.org.uk/>.
73 config ARM_HAS_SG_CHAIN
74 bool
76 config NEED_SG_DMA_LENGTH
77 bool
79 config ARM_DMA_USE_IOMMU
80 bool
81 select ARM_HAS_SG_CHAIN
82 select NEED_SG_DMA_LENGTH
84 if ARM_DMA_USE_IOMMU
86 config ARM_DMA_IOMMU_ALIGNMENT
87 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
88 range 4 9
89 default 8
90 help
91 DMA mapping framework by default aligns all buffers to the smallest
92 PAGE_SIZE order which is greater than or equal to the requested buffer
93 size. This works well for buffers up to a few hundreds kilobytes, but
94 for larger buffers it just a waste of address space. Drivers which has
95 relatively small addressing window (like 64Mib) might run out of
96 virtual space with just a few allocations.
98 With this parameter you can specify the maximum PAGE_SIZE order for
99 DMA IOMMU buffers. Larger buffers will be aligned only to this
100 specified order. The order is expressed as a power of two multiplied
101 by the PAGE_SIZE.
103 endif
105 config HAVE_PWM
106 bool
108 config MIGHT_HAVE_PCI
109 bool
111 config SYS_SUPPORTS_APM_EMULATION
112 bool
114 config HAVE_TCM
115 bool
116 select GENERIC_ALLOCATOR
118 config HAVE_PROC_CPU
119 bool
121 config NO_IOPORT
122 bool
124 config EISA
125 bool
126 ---help---
127 The Extended Industry Standard Architecture (EISA) bus was
128 developed as an open alternative to the IBM MicroChannel bus.
130 The EISA bus provided some of the features of the IBM MicroChannel
131 bus while maintaining backward compatibility with cards made for
132 the older ISA bus. The EISA bus saw limited use between 1988 and
133 1995 when it was made obsolete by the PCI bus.
135 Say Y here if you are building a kernel for an EISA-based machine.
137 Otherwise, say N.
139 config SBUS
140 bool
142 config STACKTRACE_SUPPORT
143 bool
144 default y
146 config HAVE_LATENCYTOP_SUPPORT
147 bool
148 depends on !SMP
149 default y
151 config LOCKDEP_SUPPORT
152 bool
153 default y
155 config TRACE_IRQFLAGS_SUPPORT
156 bool
157 default y
159 config RWSEM_GENERIC_SPINLOCK
160 bool
161 default y
163 config RWSEM_XCHGADD_ALGORITHM
164 bool
166 config ARCH_HAS_ILOG2_U32
167 bool
169 config ARCH_HAS_ILOG2_U64
170 bool
172 config ARCH_HAS_CPUFREQ
173 bool
174 help
175 Internal node to signify that the ARCH has CPUFREQ support
176 and that the relevant menu configurations are displayed for
177 it.
179 config ARCH_HAS_BANDGAP
180 bool
182 config GENERIC_HWEIGHT
183 bool
184 default y
186 config GENERIC_CALIBRATE_DELAY
187 bool
188 default y
190 config ARCH_MAY_HAVE_PC_FDC
191 bool
193 config ZONE_DMA
194 bool
196 config NEED_DMA_MAP_STATE
197 def_bool y
199 config ARCH_HAS_DMA_SET_COHERENT_MASK
200 bool
202 config GENERIC_ISA_DMA
203 bool
205 config FIQ
206 bool
208 config NEED_RET_TO_USER
209 bool
211 config ARCH_MTD_XIP
212 bool
214 config VECTORS_BASE
215 hex
216 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
217 default DRAM_BASE if REMAP_VECTORS_TO_RAM
218 default 0x00000000
219 help
220 The base address of exception vectors.
222 config ARM_PATCH_PHYS_VIRT
223 bool "Patch physical to virtual translations at runtime" if EMBEDDED
224 default y
225 depends on !XIP_KERNEL && MMU
226 depends on !ARCH_REALVIEW || !SPARSEMEM
227 help
228 Patch phys-to-virt and virt-to-phys translation functions at
229 boot and module load time according to the position of the
230 kernel in system memory.
232 This can only be used with non-XIP MMU kernels where the base
233 of physical memory is at a 16MB boundary.
235 Only disable this option if you know that you do not require
236 this feature (eg, building a kernel for a single machine) and
237 you need to shrink the kernel to the minimal size.
239 config NEED_MACH_GPIO_H
240 bool
241 help
242 Select this when mach/gpio.h is required to provide special
243 definitions for this platform. The need for mach/gpio.h should
244 be avoided when possible.
246 config NEED_MACH_IO_H
247 bool
248 help
249 Select this when mach/io.h is required to provide special
250 definitions for this platform. The need for mach/io.h should
251 be avoided when possible.
253 config NEED_MACH_MEMORY_H
254 bool
255 help
256 Select this when mach/memory.h is required to provide special
257 definitions for this platform. The need for mach/memory.h should
258 be avoided when possible.
260 config PHYS_OFFSET
261 hex "Physical address of main memory" if MMU
262 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
263 default DRAM_BASE if !MMU
264 help
265 Please provide the physical address corresponding to the
266 location of main memory in your system.
268 config GENERIC_BUG
269 def_bool y
270 depends on BUG
272 source "init/Kconfig"
274 source "kernel/Kconfig.freezer"
276 menu "System Type"
278 config MMU
279 bool "MMU-based Paged Memory Management Support"
280 default y
281 help
282 Select if you want MMU-based virtualised addressing space
283 support by paged memory management. If unsure, say 'Y'.
285 #
286 # The "ARM system type" choice list is ordered alphabetically by option
287 # text. Please add new entries in the option alphabetic order.
288 #
289 choice
290 prompt "ARM system type"
291 default ARCH_VERSATILE if !MMU
292 default ARCH_MULTIPLATFORM if MMU
294 config ARCH_MULTIPLATFORM
295 bool "Allow multiple platforms to be selected"
296 depends on MMU
297 select ARM_PATCH_PHYS_VIRT
298 select AUTO_ZRELADDR
299 select COMMON_CLK
300 select MULTI_IRQ_HANDLER
301 select SPARSE_IRQ
302 select USE_OF
304 config ARCH_INTEGRATOR
305 bool "ARM Ltd. Integrator family"
306 select ARCH_HAS_CPUFREQ
307 select ARM_AMBA
308 select COMMON_CLK
309 select COMMON_CLK_VERSATILE
310 select GENERIC_CLOCKEVENTS
311 select HAVE_TCM
312 select ICST
313 select MULTI_IRQ_HANDLER
314 select NEED_MACH_MEMORY_H
315 select PLAT_VERSATILE
316 select SPARSE_IRQ
317 select VERSATILE_FPGA_IRQ
318 help
319 Support for ARM's Integrator platform.
321 config ARCH_REALVIEW
322 bool "ARM Ltd. RealView family"
323 select ARCH_WANT_OPTIONAL_GPIOLIB
324 select ARM_AMBA
325 select ARM_TIMER_SP804
326 select COMMON_CLK
327 select COMMON_CLK_VERSATILE
328 select GENERIC_CLOCKEVENTS
329 select GPIO_PL061 if GPIOLIB
330 select ICST
331 select NEED_MACH_MEMORY_H
332 select PLAT_VERSATILE
333 select PLAT_VERSATILE_CLCD
334 help
335 This enables support for ARM Ltd RealView boards.
337 config ARCH_VERSATILE
338 bool "ARM Ltd. Versatile family"
339 select ARCH_WANT_OPTIONAL_GPIOLIB
340 select ARM_AMBA
341 select ARM_TIMER_SP804
342 select ARM_VIC
343 select CLKDEV_LOOKUP
344 select GENERIC_CLOCKEVENTS
345 select HAVE_MACH_CLKDEV
346 select ICST
347 select PLAT_VERSATILE
348 select PLAT_VERSATILE_CLCD
349 select PLAT_VERSATILE_CLOCK
350 select VERSATILE_FPGA_IRQ
351 help
352 This enables support for ARM Ltd Versatile board.
354 config ARCH_AT91
355 bool "Atmel AT91"
356 select ARCH_REQUIRE_GPIOLIB
357 select CLKDEV_LOOKUP
358 select HAVE_CLK
359 select IRQ_DOMAIN
360 select NEED_MACH_GPIO_H
361 select NEED_MACH_IO_H if PCCARD
362 select PINCTRL
363 select PINCTRL_AT91 if USE_OF
364 help
365 This enables support for systems based on Atmel
366 AT91RM9200 and AT91SAM9* processors.
368 config ARCH_CLPS711X
369 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
370 select ARCH_REQUIRE_GPIOLIB
371 select AUTO_ZRELADDR
372 select CLKDEV_LOOKUP
373 select CLKSRC_MMIO
374 select COMMON_CLK
375 select CPU_ARM720T
376 select GENERIC_CLOCKEVENTS
377 select MFD_SYSCON
378 select MULTI_IRQ_HANDLER
379 select SPARSE_IRQ
380 help
381 Support for Cirrus Logic 711x/721x/731x based boards.
383 config ARCH_GEMINI
384 bool "Cortina Systems Gemini"
385 select ARCH_REQUIRE_GPIOLIB
386 select ARCH_USES_GETTIMEOFFSET
387 select NEED_MACH_GPIO_H
388 select CPU_FA526
389 help
390 Support for the Cortina Systems Gemini family SoCs
392 config ARCH_EBSA110
393 bool "EBSA-110"
394 select ARCH_USES_GETTIMEOFFSET
395 select CPU_SA110
396 select ISA
397 select NEED_MACH_IO_H
398 select NEED_MACH_MEMORY_H
399 select NO_IOPORT
400 help
401 This is an evaluation board for the StrongARM processor available
402 from Digital. It has limited hardware on-board, including an
403 Ethernet interface, two PCMCIA sockets, two serial ports and a
404 parallel port.
406 config ARCH_EP93XX
407 bool "EP93xx-based"
408 select ARCH_HAS_HOLES_MEMORYMODEL
409 select ARCH_REQUIRE_GPIOLIB
410 select ARCH_USES_GETTIMEOFFSET
411 select ARM_AMBA
412 select ARM_VIC
413 select CLKDEV_LOOKUP
414 select CPU_ARM920T
415 select NEED_MACH_MEMORY_H
416 help
417 This enables support for the Cirrus EP93xx series of CPUs.
419 config ARCH_FOOTBRIDGE
420 bool "FootBridge"
421 select CPU_SA110
422 select FOOTBRIDGE
423 select GENERIC_CLOCKEVENTS
424 select HAVE_IDE
425 select NEED_MACH_IO_H if !MMU
426 select NEED_MACH_MEMORY_H
427 help
428 Support for systems based on the DC21285 companion chip
429 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
431 config ARCH_NETX
432 bool "Hilscher NetX based"
433 select ARM_VIC
434 select CLKSRC_MMIO
435 select CPU_ARM926T
436 select GENERIC_CLOCKEVENTS
437 help
438 This enables support for systems based on the Hilscher NetX Soc
440 config ARCH_IOP13XX
441 bool "IOP13xx-based"
442 depends on MMU
443 select ARCH_SUPPORTS_MSI
444 select CPU_XSC3
445 select NEED_MACH_MEMORY_H
446 select NEED_RET_TO_USER
447 select PCI
448 select PLAT_IOP
449 select VMSPLIT_1G
450 help
451 Support for Intel's IOP13XX (XScale) family of processors.
453 config ARCH_IOP32X
454 bool "IOP32x-based"
455 depends on MMU
456 select ARCH_REQUIRE_GPIOLIB
457 select CPU_XSCALE
458 select NEED_MACH_GPIO_H
459 select NEED_RET_TO_USER
460 select PCI
461 select PLAT_IOP
462 help
463 Support for Intel's 80219 and IOP32X (XScale) family of
464 processors.
466 config ARCH_IOP33X
467 bool "IOP33x-based"
468 depends on MMU
469 select ARCH_REQUIRE_GPIOLIB
470 select CPU_XSCALE
471 select NEED_MACH_GPIO_H
472 select NEED_RET_TO_USER
473 select PCI
474 select PLAT_IOP
475 help
476 Support for Intel's IOP33X (XScale) family of processors.
478 config ARCH_IXP4XX
479 bool "IXP4xx-based"
480 depends on MMU
481 select ARCH_HAS_DMA_SET_COHERENT_MASK
482 select ARCH_REQUIRE_GPIOLIB
483 select CLKSRC_MMIO
484 select CPU_XSCALE
485 select DMABOUNCE if PCI
486 select GENERIC_CLOCKEVENTS
487 select MIGHT_HAVE_PCI
488 select NEED_MACH_IO_H
489 select USB_EHCI_BIG_ENDIAN_MMIO
490 select USB_EHCI_BIG_ENDIAN_DESC
491 help
492 Support for Intel's IXP4XX (XScale) family of processors.
494 config ARCH_DOVE
495 bool "Marvell Dove"
496 select ARCH_REQUIRE_GPIOLIB
497 select CPU_PJ4
498 select GENERIC_CLOCKEVENTS
499 select MIGHT_HAVE_PCI
500 select PINCTRL
501 select PINCTRL_DOVE
502 select PLAT_ORION_LEGACY
503 select USB_ARCH_HAS_EHCI
504 select MVEBU_MBUS
505 help
506 Support for the Marvell Dove SoC 88AP510
508 config ARCH_KIRKWOOD
509 bool "Marvell Kirkwood"
510 select ARCH_HAS_CPUFREQ
511 select ARCH_REQUIRE_GPIOLIB
512 select CPU_FEROCEON
513 select GENERIC_CLOCKEVENTS
514 select PCI
515 select PCI_QUIRKS
516 select PINCTRL
517 select PINCTRL_KIRKWOOD
518 select PLAT_ORION_LEGACY
519 select MVEBU_MBUS
520 help
521 Support for the following Marvell Kirkwood series SoCs:
522 88F6180, 88F6192 and 88F6281.
524 config ARCH_MV78XX0
525 bool "Marvell MV78xx0"
526 select ARCH_REQUIRE_GPIOLIB
527 select CPU_FEROCEON
528 select GENERIC_CLOCKEVENTS
529 select PCI
530 select PLAT_ORION_LEGACY
531 select MVEBU_MBUS
532 help
533 Support for the following Marvell MV78xx0 series SoCs:
534 MV781x0, MV782x0.
536 config ARCH_ORION5X
537 bool "Marvell Orion"
538 depends on MMU
539 select ARCH_REQUIRE_GPIOLIB
540 select CPU_FEROCEON
541 select GENERIC_CLOCKEVENTS
542 select PCI
543 select PLAT_ORION_LEGACY
544 select MVEBU_MBUS
545 help
546 Support for the following Marvell Orion 5x series SoCs:
547 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
548 Orion-2 (5281), Orion-1-90 (6183).
550 config ARCH_MMP
551 bool "Marvell PXA168/910/MMP2"
552 depends on MMU
553 select ARCH_REQUIRE_GPIOLIB
554 select CLKDEV_LOOKUP
555 select GENERIC_ALLOCATOR
556 select GENERIC_CLOCKEVENTS
557 select GPIO_PXA
558 select IRQ_DOMAIN
559 select NEED_MACH_GPIO_H
560 select PINCTRL
561 select PLAT_PXA
562 select SPARSE_IRQ
563 help
564 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
566 config ARCH_KS8695
567 bool "Micrel/Kendin KS8695"
568 select ARCH_REQUIRE_GPIOLIB
569 select CLKSRC_MMIO
570 select CPU_ARM922T
571 select GENERIC_CLOCKEVENTS
572 select NEED_MACH_MEMORY_H
573 help
574 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
575 System-on-Chip devices.
577 config ARCH_W90X900
578 bool "Nuvoton W90X900 CPU"
579 select ARCH_REQUIRE_GPIOLIB
580 select CLKDEV_LOOKUP
581 select CLKSRC_MMIO
582 select CPU_ARM926T
583 select GENERIC_CLOCKEVENTS
584 help
585 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
586 At present, the w90x900 has been renamed nuc900, regarding
587 the ARM series product line, you can login the following
588 link address to know more.
590 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
591 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
593 config ARCH_LPC32XX
594 bool "NXP LPC32XX"
595 select ARCH_REQUIRE_GPIOLIB
596 select ARM_AMBA
597 select CLKDEV_LOOKUP
598 select CLKSRC_MMIO
599 select CPU_ARM926T
600 select GENERIC_CLOCKEVENTS
601 select HAVE_IDE
602 select HAVE_PWM
603 select USB_ARCH_HAS_OHCI
604 select USE_OF
605 help
606 Support for the NXP LPC32XX family of processors
608 config ARCH_PXA
609 bool "PXA2xx/PXA3xx-based"
610 depends on MMU
611 select ARCH_HAS_CPUFREQ
612 select ARCH_MTD_XIP
613 select ARCH_REQUIRE_GPIOLIB
614 select ARM_CPU_SUSPEND if PM
615 select AUTO_ZRELADDR
616 select CLKDEV_LOOKUP
617 select CLKSRC_MMIO
618 select GENERIC_CLOCKEVENTS
619 select GPIO_PXA
620 select HAVE_IDE
621 select MULTI_IRQ_HANDLER
622 select NEED_MACH_GPIO_H
623 select PLAT_PXA
624 select SPARSE_IRQ
625 help
626 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
628 config ARCH_MSM
629 bool "Qualcomm MSM"
630 select ARCH_REQUIRE_GPIOLIB
631 select CLKDEV_LOOKUP
632 select COMMON_CLK
633 select GENERIC_CLOCKEVENTS
634 help
635 Support for Qualcomm MSM/QSD based systems. This runs on the
636 apps processor of the MSM/QSD and depends on a shared memory
637 interface to the modem processor which runs the baseband
638 stack and controls some vital subsystems
639 (clock and power control, etc).
641 config ARCH_SHMOBILE
642 bool "Renesas SH-Mobile / R-Mobile"
643 select ARM_PATCH_PHYS_VIRT
644 select CLKDEV_LOOKUP
645 select GENERIC_CLOCKEVENTS
646 select HAVE_ARM_SCU if SMP
647 select HAVE_ARM_TWD if LOCAL_TIMERS
648 select HAVE_CLK
649 select HAVE_MACH_CLKDEV
650 select HAVE_SMP
651 select MIGHT_HAVE_CACHE_L2X0
652 select MULTI_IRQ_HANDLER
653 select NO_IOPORT
654 select PINCTRL
655 select PM_GENERIC_DOMAINS if PM
656 select SPARSE_IRQ
657 help
658 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
660 config ARCH_RPC
661 bool "RiscPC"
662 select ARCH_ACORN
663 select ARCH_MAY_HAVE_PC_FDC
664 select ARCH_SPARSEMEM_ENABLE
665 select ARCH_USES_GETTIMEOFFSET
666 select FIQ
667 select HAVE_IDE
668 select HAVE_PATA_PLATFORM
669 select ISA_DMA_API
670 select NEED_MACH_IO_H
671 select NEED_MACH_MEMORY_H
672 select NO_IOPORT
673 select VIRT_TO_BUS
674 help
675 On the Acorn Risc-PC, Linux can support the internal IDE disk and
676 CD-ROM interface, serial and parallel port, and the floppy drive.
678 config ARCH_SA1100
679 bool "SA1100-based"
680 select ARCH_HAS_CPUFREQ
681 select ARCH_MTD_XIP
682 select ARCH_REQUIRE_GPIOLIB
683 select ARCH_SPARSEMEM_ENABLE
684 select CLKDEV_LOOKUP
685 select CLKSRC_MMIO
686 select CPU_FREQ
687 select CPU_SA1100
688 select GENERIC_CLOCKEVENTS
689 select HAVE_IDE
690 select ISA
691 select NEED_MACH_GPIO_H
692 select NEED_MACH_MEMORY_H
693 select SPARSE_IRQ
694 help
695 Support for StrongARM 11x0 based boards.
697 config ARCH_S3C24XX
698 bool "Samsung S3C24XX SoCs"
699 select ARCH_HAS_CPUFREQ
700 select ARCH_REQUIRE_GPIOLIB
701 select CLKDEV_LOOKUP
702 select CLKSRC_MMIO
703 select GENERIC_CLOCKEVENTS
704 select GPIO_SAMSUNG
705 select HAVE_CLK
706 select HAVE_S3C2410_I2C if I2C
707 select HAVE_S3C2410_WATCHDOG if WATCHDOG
708 select HAVE_S3C_RTC if RTC_CLASS
709 select MULTI_IRQ_HANDLER
710 select NEED_MACH_GPIO_H
711 select NEED_MACH_IO_H
712 select SAMSUNG_ATAGS
713 help
714 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
715 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
716 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
717 Samsung SMDK2410 development board (and derivatives).
719 config ARCH_S3C64XX
720 bool "Samsung S3C64XX"
721 select ARCH_HAS_CPUFREQ
722 select ARCH_REQUIRE_GPIOLIB
723 select ARM_VIC
724 select CLKDEV_LOOKUP
725 select CLKSRC_MMIO
726 select CPU_V6
727 select GENERIC_CLOCKEVENTS
728 select GPIO_SAMSUNG
729 select HAVE_CLK
730 select HAVE_S3C2410_I2C if I2C
731 select HAVE_S3C2410_WATCHDOG if WATCHDOG
732 select HAVE_TCM
733 select NEED_MACH_GPIO_H
734 select NO_IOPORT
735 select PLAT_SAMSUNG
736 select S3C_DEV_NAND
737 select S3C_GPIO_TRACK
738 select SAMSUNG_ATAGS
739 select SAMSUNG_CLKSRC
740 select SAMSUNG_GPIOLIB_4BIT
741 select SAMSUNG_IRQ_VIC_TIMER
742 select SAMSUNG_WDT_RESET
743 select USB_ARCH_HAS_OHCI
744 help
745 Samsung S3C64XX series based systems
747 config ARCH_S5P64X0
748 bool "Samsung S5P6440 S5P6450"
749 select CLKDEV_LOOKUP
750 select CLKSRC_MMIO
751 select CPU_V6
752 select GENERIC_CLOCKEVENTS
753 select GPIO_SAMSUNG
754 select HAVE_CLK
755 select HAVE_S3C2410_I2C if I2C
756 select HAVE_S3C2410_WATCHDOG if WATCHDOG
757 select HAVE_S3C_RTC if RTC_CLASS
758 select NEED_MACH_GPIO_H
759 select SAMSUNG_WDT_RESET
760 select SAMSUNG_ATAGS
761 help
762 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
763 SMDK6450.
765 config ARCH_S5PC100
766 bool "Samsung S5PC100"
767 select ARCH_REQUIRE_GPIOLIB
768 select CLKDEV_LOOKUP
769 select CLKSRC_MMIO
770 select CPU_V7
771 select GENERIC_CLOCKEVENTS
772 select GPIO_SAMSUNG
773 select HAVE_CLK
774 select HAVE_S3C2410_I2C if I2C
775 select HAVE_S3C2410_WATCHDOG if WATCHDOG
776 select HAVE_S3C_RTC if RTC_CLASS
777 select NEED_MACH_GPIO_H
778 select SAMSUNG_WDT_RESET
779 select SAMSUNG_ATAGS
780 help
781 Samsung S5PC100 series based systems
783 config ARCH_S5PV210
784 bool "Samsung S5PV210/S5PC110"
785 select ARCH_HAS_CPUFREQ
786 select ARCH_HAS_HOLES_MEMORYMODEL
787 select ARCH_SPARSEMEM_ENABLE
788 select CLKDEV_LOOKUP
789 select CLKSRC_MMIO
790 select CPU_V7
791 select GENERIC_CLOCKEVENTS
792 select GPIO_SAMSUNG
793 select HAVE_CLK
794 select HAVE_S3C2410_I2C if I2C
795 select HAVE_S3C2410_WATCHDOG if WATCHDOG
796 select HAVE_S3C_RTC if RTC_CLASS
797 select NEED_MACH_GPIO_H
798 select NEED_MACH_MEMORY_H
799 select SAMSUNG_ATAGS
800 help
801 Samsung S5PV210/S5PC110 series based systems
803 config ARCH_EXYNOS
804 bool "Samsung EXYNOS"
805 select ARCH_HAS_CPUFREQ
806 select ARCH_HAS_HOLES_MEMORYMODEL
807 select ARCH_REQUIRE_GPIOLIB
808 select ARCH_SPARSEMEM_ENABLE
809 select ARM_GIC
810 select CLKDEV_LOOKUP
811 select COMMON_CLK
812 select CPU_V7
813 select GENERIC_CLOCKEVENTS
814 select HAVE_CLK
815 select HAVE_S3C2410_I2C if I2C
816 select HAVE_S3C2410_WATCHDOG if WATCHDOG
817 select HAVE_S3C_RTC if RTC_CLASS
818 select NEED_MACH_MEMORY_H
819 select SPARSE_IRQ
820 select USE_OF
821 help
822 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
824 config ARCH_SHARK
825 bool "Shark"
826 select ARCH_USES_GETTIMEOFFSET
827 select CPU_SA110
828 select ISA
829 select ISA_DMA
830 select NEED_MACH_MEMORY_H
831 select PCI
832 select VIRT_TO_BUS
833 select ZONE_DMA
834 help
835 Support for the StrongARM based Digital DNARD machine, also known
836 as "Shark" (<http://www.shark-linux.de/shark.html>).
838 config ARCH_DAVINCI
839 bool "TI DaVinci"
840 select ARCH_HAS_HOLES_MEMORYMODEL
841 select ARCH_REQUIRE_GPIOLIB
842 select CLKDEV_LOOKUP
843 select GENERIC_ALLOCATOR
844 select GENERIC_CLOCKEVENTS
845 select GENERIC_IRQ_CHIP
846 select HAVE_IDE
847 select NEED_MACH_GPIO_H
848 select TI_PRIV_EDMA
849 select USE_OF
850 select ZONE_DMA
851 help
852 Support for TI's DaVinci platform.
854 config ARCH_OMAP1
855 bool "TI OMAP1"
856 depends on MMU
857 select ARCH_HAS_CPUFREQ
858 select ARCH_HAS_HOLES_MEMORYMODEL
859 select ARCH_OMAP
860 select ARCH_REQUIRE_GPIOLIB
861 select CLKDEV_LOOKUP
862 select CLKSRC_MMIO
863 select GENERIC_CLOCKEVENTS
864 select GENERIC_IRQ_CHIP
865 select HAVE_CLK
866 select HAVE_IDE
867 select IRQ_DOMAIN
868 select NEED_MACH_IO_H if PCCARD
869 select NEED_MACH_MEMORY_H
870 help
871 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
873 endchoice
875 menu "Multiple platform selection"
876 depends on ARCH_MULTIPLATFORM
878 comment "CPU Core family selection"
880 config ARCH_MULTI_V4T
881 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
882 depends on !ARCH_MULTI_V6_V7
883 select ARCH_MULTI_V4_V5
884 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
885 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
886 CPU_ARM925T || CPU_ARM940T)
888 config ARCH_MULTI_V5
889 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
890 depends on !ARCH_MULTI_V6_V7
891 select ARCH_MULTI_V4_V5
892 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
893 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
894 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
896 config ARCH_MULTI_V4_V5
897 bool
899 config ARCH_MULTI_V6
900 bool "ARMv6 based platforms (ARM11)"
901 select ARCH_MULTI_V6_V7
902 select CPU_V6
904 config ARCH_MULTI_V7
905 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
906 default y
907 select ARCH_MULTI_V6_V7
908 select CPU_V7
910 config ARCH_MULTI_V6_V7
911 bool
913 config ARCH_MULTI_CPU_AUTO
914 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
915 select ARCH_MULTI_V5
917 endmenu
919 #
920 # This is sorted alphabetically by mach-* pathname. However, plat-*
921 # Kconfigs may be included either alphabetically (according to the
922 # plat- suffix) or along side the corresponding mach-* source.
923 #
924 source "arch/arm/mach-mvebu/Kconfig"
926 source "arch/arm/mach-at91/Kconfig"
928 source "arch/arm/mach-bcm/Kconfig"
930 source "arch/arm/mach-bcm2835/Kconfig"
932 source "arch/arm/mach-clps711x/Kconfig"
934 source "arch/arm/mach-cns3xxx/Kconfig"
936 source "arch/arm/mach-davinci/Kconfig"
938 source "arch/arm/mach-dove/Kconfig"
940 source "arch/arm/mach-ep93xx/Kconfig"
942 source "arch/arm/mach-footbridge/Kconfig"
944 source "arch/arm/mach-gemini/Kconfig"
946 source "arch/arm/mach-highbank/Kconfig"
948 source "arch/arm/mach-integrator/Kconfig"
950 source "arch/arm/mach-iop32x/Kconfig"
952 source "arch/arm/mach-iop33x/Kconfig"
954 source "arch/arm/mach-iop13xx/Kconfig"
956 source "arch/arm/mach-ixp4xx/Kconfig"
958 source "arch/arm/mach-keystone/Kconfig"
960 source "arch/arm/mach-kirkwood/Kconfig"
962 source "arch/arm/mach-ks8695/Kconfig"
964 source "arch/arm/mach-msm/Kconfig"
966 source "arch/arm/mach-mv78xx0/Kconfig"
968 source "arch/arm/mach-imx/Kconfig"
970 source "arch/arm/mach-mxs/Kconfig"
972 source "arch/arm/mach-netx/Kconfig"
974 source "arch/arm/mach-nomadik/Kconfig"
976 source "arch/arm/mach-nspire/Kconfig"
978 source "arch/arm/plat-omap/Kconfig"
980 source "arch/arm/mach-omap1/Kconfig"
982 source "arch/arm/mach-omap2/Kconfig"
984 source "arch/arm/mach-orion5x/Kconfig"
986 source "arch/arm/mach-picoxcell/Kconfig"
988 source "arch/arm/mach-pxa/Kconfig"
989 source "arch/arm/plat-pxa/Kconfig"
991 source "arch/arm/mach-mmp/Kconfig"
993 source "arch/arm/mach-realview/Kconfig"
995 source "arch/arm/mach-rockchip/Kconfig"
997 source "arch/arm/mach-sa1100/Kconfig"
999 source "arch/arm/plat-samsung/Kconfig"
1001 source "arch/arm/mach-socfpga/Kconfig"
1003 source "arch/arm/mach-spear/Kconfig"
1005 source "arch/arm/mach-sti/Kconfig"
1007 source "arch/arm/mach-s3c24xx/Kconfig"
1009 if ARCH_S3C64XX
1010 source "arch/arm/mach-s3c64xx/Kconfig"
1011 endif
1013 source "arch/arm/mach-s5p64x0/Kconfig"
1015 source "arch/arm/mach-s5pc100/Kconfig"
1017 source "arch/arm/mach-s5pv210/Kconfig"
1019 source "arch/arm/mach-exynos/Kconfig"
1021 source "arch/arm/mach-shmobile/Kconfig"
1023 source "arch/arm/mach-sunxi/Kconfig"
1025 source "arch/arm/mach-prima2/Kconfig"
1027 source "arch/arm/mach-tegra/Kconfig"
1029 source "arch/arm/mach-u300/Kconfig"
1031 source "arch/arm/mach-ux500/Kconfig"
1033 source "arch/arm/mach-versatile/Kconfig"
1035 source "arch/arm/mach-vexpress/Kconfig"
1036 source "arch/arm/plat-versatile/Kconfig"
1038 source "arch/arm/mach-virt/Kconfig"
1040 source "arch/arm/mach-vt8500/Kconfig"
1042 source "arch/arm/mach-w90x900/Kconfig"
1044 source "arch/arm/mach-zynq/Kconfig"
1046 # Definitions to make life easier
1047 config ARCH_ACORN
1048 bool
1050 config PLAT_IOP
1051 bool
1052 select GENERIC_CLOCKEVENTS
1054 config PLAT_ORION
1055 bool
1056 select CLKSRC_MMIO
1057 select COMMON_CLK
1058 select GENERIC_IRQ_CHIP
1059 select IRQ_DOMAIN
1061 config PLAT_ORION_LEGACY
1062 bool
1063 select PLAT_ORION
1065 config PLAT_PXA
1066 bool
1068 config PLAT_VERSATILE
1069 bool
1071 config ARM_TIMER_SP804
1072 bool
1073 select CLKSRC_MMIO
1074 select CLKSRC_OF if OF
1076 source arch/arm/mm/Kconfig
1078 config ARM_NR_BANKS
1079 int
1080 default 16 if ARCH_EP93XX
1081 default 8
1083 config IWMMXT
1084 bool "Enable iWMMXt support" if !CPU_PJ4
1085 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1086 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1087 help
1088 Enable support for iWMMXt context switching at run time if
1089 running on a CPU that supports it.
1091 config XSCALE_PMU
1092 bool
1093 depends on CPU_XSCALE
1094 default y
1096 config MULTI_IRQ_HANDLER
1097 bool
1098 help
1099 Allow each machine to specify it's own IRQ handler at run time.
1101 if !MMU
1102 source "arch/arm/Kconfig-nommu"
1103 endif
1105 config PJ4B_ERRATA_4742
1106 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1107 depends on CPU_PJ4B && MACH_ARMADA_370
1108 default y
1109 help
1110 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1111 Event (WFE) IDLE states, a specific timing sensitivity exists between
1112 the retiring WFI/WFE instructions and the newly issued subsequent
1113 instructions. This sensitivity can result in a CPU hang scenario.
1114 Workaround:
1115 The software must insert either a Data Synchronization Barrier (DSB)
1116 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1117 instruction
1119 config ARM_ERRATA_326103
1120 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1121 depends on CPU_V6
1122 help
1123 Executing a SWP instruction to read-only memory does not set bit 11
1124 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1125 treat the access as a read, preventing a COW from occurring and
1126 causing the faulting task to livelock.
1128 config ARM_ERRATA_411920
1129 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1130 depends on CPU_V6 || CPU_V6K
1131 help
1132 Invalidation of the Instruction Cache operation can
1133 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1134 It does not affect the MPCore. This option enables the ARM Ltd.
1135 recommended workaround.
1137 config ARM_ERRATA_430973
1138 bool "ARM errata: Stale prediction on replaced interworking branch"
1139 depends on CPU_V7
1140 help
1141 This option enables the workaround for the 430973 Cortex-A8
1142 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1143 interworking branch is replaced with another code sequence at the
1144 same virtual address, whether due to self-modifying code or virtual
1145 to physical address re-mapping, Cortex-A8 does not recover from the
1146 stale interworking branch prediction. This results in Cortex-A8
1147 executing the new code sequence in the incorrect ARM or Thumb state.
1148 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1149 and also flushes the branch target cache at every context switch.
1150 Note that setting specific bits in the ACTLR register may not be
1151 available in non-secure mode.
1153 config ARM_ERRATA_458693
1154 bool "ARM errata: Processor deadlock when a false hazard is created"
1155 depends on CPU_V7
1156 depends on !ARCH_MULTIPLATFORM
1157 help
1158 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1159 erratum. For very specific sequences of memory operations, it is
1160 possible for a hazard condition intended for a cache line to instead
1161 be incorrectly associated with a different cache line. This false
1162 hazard might then cause a processor deadlock. The workaround enables
1163 the L1 caching of the NEON accesses and disables the PLD instruction
1164 in the ACTLR register. Note that setting specific bits in the ACTLR
1165 register may not be available in non-secure mode.
1167 config ARM_ERRATA_460075
1168 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1169 depends on CPU_V7
1170 depends on !ARCH_MULTIPLATFORM
1171 help
1172 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1173 erratum. Any asynchronous access to the L2 cache may encounter a
1174 situation in which recent store transactions to the L2 cache are lost
1175 and overwritten with stale memory contents from external memory. The
1176 workaround disables the write-allocate mode for the L2 cache via the
1177 ACTLR register. Note that setting specific bits in the ACTLR register
1178 may not be available in non-secure mode.
1180 config ARM_ERRATA_742230
1181 bool "ARM errata: DMB operation may be faulty"
1182 depends on CPU_V7 && SMP
1183 depends on !ARCH_MULTIPLATFORM
1184 help
1185 This option enables the workaround for the 742230 Cortex-A9
1186 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1187 between two write operations may not ensure the correct visibility
1188 ordering of the two writes. This workaround sets a specific bit in
1189 the diagnostic register of the Cortex-A9 which causes the DMB
1190 instruction to behave as a DSB, ensuring the correct behaviour of
1191 the two writes.
1193 config ARM_ERRATA_742231
1194 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1195 depends on CPU_V7 && SMP
1196 depends on !ARCH_MULTIPLATFORM
1197 help
1198 This option enables the workaround for the 742231 Cortex-A9
1199 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1200 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1201 accessing some data located in the same cache line, may get corrupted
1202 data due to bad handling of the address hazard when the line gets
1203 replaced from one of the CPUs at the same time as another CPU is
1204 accessing it. This workaround sets specific bits in the diagnostic
1205 register of the Cortex-A9 which reduces the linefill issuing
1206 capabilities of the processor.
1208 config PL310_ERRATA_588369
1209 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1210 depends on CACHE_L2X0
1211 help
1212 The PL310 L2 cache controller implements three types of Clean &
1213 Invalidate maintenance operations: by Physical Address
1214 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1215 They are architecturally defined to behave as the execution of a
1216 clean operation followed immediately by an invalidate operation,
1217 both performing to the same memory location. This functionality
1218 is not correctly implemented in PL310 as clean lines are not
1219 invalidated as a result of these operations.
1221 config ARM_ERRATA_643719
1222 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1223 depends on CPU_V7 && SMP
1224 help
1225 This option enables the workaround for the 643719 Cortex-A9 (prior to
1226 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1227 register returns zero when it should return one. The workaround
1228 corrects this value, ensuring cache maintenance operations which use
1229 it behave as intended and avoiding data corruption.
1231 config ARM_ERRATA_720789
1232 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1233 depends on CPU_V7
1234 help
1235 This option enables the workaround for the 720789 Cortex-A9 (prior to
1236 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1237 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1238 As a consequence of this erratum, some TLB entries which should be
1239 invalidated are not, resulting in an incoherency in the system page
1240 tables. The workaround changes the TLB flushing routines to invalidate
1241 entries regardless of the ASID.
1243 config PL310_ERRATA_727915
1244 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1245 depends on CACHE_L2X0
1246 help
1247 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1248 operation (offset 0x7FC). This operation runs in background so that
1249 PL310 can handle normal accesses while it is in progress. Under very
1250 rare circumstances, due to this erratum, write data can be lost when
1251 PL310 treats a cacheable write transaction during a Clean &
1252 Invalidate by Way operation.
1254 config ARM_ERRATA_743622
1255 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1256 depends on CPU_V7
1257 depends on !ARCH_MULTIPLATFORM
1258 help
1259 This option enables the workaround for the 743622 Cortex-A9
1260 (r2p*) erratum. Under very rare conditions, a faulty
1261 optimisation in the Cortex-A9 Store Buffer may lead to data
1262 corruption. This workaround sets a specific bit in the diagnostic
1263 register of the Cortex-A9 which disables the Store Buffer
1264 optimisation, preventing the defect from occurring. This has no
1265 visible impact on the overall performance or power consumption of the
1266 processor.
1268 config ARM_ERRATA_751472
1269 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1270 depends on CPU_V7
1271 depends on !ARCH_MULTIPLATFORM
1272 help
1273 This option enables the workaround for the 751472 Cortex-A9 (prior
1274 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1275 completion of a following broadcasted operation if the second
1276 operation is received by a CPU before the ICIALLUIS has completed,
1277 potentially leading to corrupted entries in the cache or TLB.
1279 config PL310_ERRATA_753970
1280 bool "PL310 errata: cache sync operation may be faulty"
1281 depends on CACHE_PL310
1282 help
1283 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1285 Under some condition the effect of cache sync operation on
1286 the store buffer still remains when the operation completes.
1287 This means that the store buffer is always asked to drain and
1288 this prevents it from merging any further writes. The workaround
1289 is to replace the normal offset of cache sync operation (0x730)
1290 by another offset targeting an unmapped PL310 register 0x740.
1291 This has the same effect as the cache sync operation: store buffer
1292 drain and waiting for all buffers empty.
1294 config ARM_ERRATA_754322
1295 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1296 depends on CPU_V7
1297 help
1298 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1299 r3p*) erratum. A speculative memory access may cause a page table walk
1300 which starts prior to an ASID switch but completes afterwards. This
1301 can populate the micro-TLB with a stale entry which may be hit with
1302 the new ASID. This workaround places two dsb instructions in the mm
1303 switching code so that no page table walks can cross the ASID switch.
1305 config ARM_ERRATA_754327
1306 bool "ARM errata: no automatic Store Buffer drain"
1307 depends on CPU_V7 && SMP
1308 help
1309 This option enables the workaround for the 754327 Cortex-A9 (prior to
1310 r2p0) erratum. The Store Buffer does not have any automatic draining
1311 mechanism and therefore a livelock may occur if an external agent
1312 continuously polls a memory location waiting to observe an update.
1313 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1314 written polling loops from denying visibility of updates to memory.
1316 config ARM_ERRATA_364296
1317 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1318 depends on CPU_V6 && !SMP
1319 help
1320 This options enables the workaround for the 364296 ARM1136
1321 r0p2 erratum (possible cache data corruption with
1322 hit-under-miss enabled). It sets the undocumented bit 31 in
1323 the auxiliary control register and the FI bit in the control
1324 register, thus disabling hit-under-miss without putting the
1325 processor into full low interrupt latency mode. ARM11MPCore
1326 is not affected.
1328 config ARM_ERRATA_764369
1329 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1330 depends on CPU_V7 && SMP
1331 help
1332 This option enables the workaround for erratum 764369
1333 affecting Cortex-A9 MPCore with two or more processors (all
1334 current revisions). Under certain timing circumstances, a data
1335 cache line maintenance operation by MVA targeting an Inner
1336 Shareable memory region may fail to proceed up to either the
1337 Point of Coherency or to the Point of Unification of the
1338 system. This workaround adds a DSB instruction before the
1339 relevant cache maintenance functions and sets a specific bit
1340 in the diagnostic control register of the SCU.
1342 config PL310_ERRATA_769419
1343 bool "PL310 errata: no automatic Store Buffer drain"
1344 depends on CACHE_L2X0
1345 help
1346 On revisions of the PL310 prior to r3p2, the Store Buffer does
1347 not automatically drain. This can cause normal, non-cacheable
1348 writes to be retained when the memory system is idle, leading
1349 to suboptimal I/O performance for drivers using coherent DMA.
1350 This option adds a write barrier to the cpu_idle loop so that,
1351 on systems with an outer cache, the store buffer is drained
1352 explicitly.
1354 config ARM_ERRATA_775420
1355 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1356 depends on CPU_V7
1357 help
1358 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1359 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1360 operation aborts with MMU exception, it might cause the processor
1361 to deadlock. This workaround puts DSB before executing ISB if
1362 an abort may occur on cache maintenance.
1364 config ARM_ERRATA_798181
1365 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1366 depends on CPU_V7 && SMP
1367 help
1368 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1369 adequately shooting down all use of the old entries. This
1370 option enables the Linux kernel workaround for this erratum
1371 which sends an IPI to the CPUs that are running the same ASID
1372 as the one being invalidated.
1374 endmenu
1376 source "arch/arm/common/Kconfig"
1378 menu "Bus support"
1380 config ARM_AMBA
1381 bool
1383 config ISA
1384 bool
1385 help
1386 Find out whether you have ISA slots on your motherboard. ISA is the
1387 name of a bus system, i.e. the way the CPU talks to the other stuff
1388 inside your box. Other bus systems are PCI, EISA, MicroChannel
1389 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1390 newer boards don't support it. If you have ISA, say Y, otherwise N.
1392 # Select ISA DMA controller support
1393 config ISA_DMA
1394 bool
1395 select ISA_DMA_API
1397 # Select ISA DMA interface
1398 config ISA_DMA_API
1399 bool
1401 config PCI
1402 bool "PCI support" if MIGHT_HAVE_PCI
1403 help
1404 Find out whether you have a PCI motherboard. PCI is the name of a
1405 bus system, i.e. the way the CPU talks to the other stuff inside
1406 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1407 VESA. If you have PCI, say Y, otherwise N.
1409 config PCI_DOMAINS
1410 bool
1411 depends on PCI
1413 config PCI_NANOENGINE
1414 bool "BSE nanoEngine PCI support"
1415 depends on SA1100_NANOENGINE
1416 help
1417 Enable PCI on the BSE nanoEngine board.
1419 config PCI_SYSCALL
1420 def_bool PCI
1422 # Select the host bridge type
1423 config PCI_HOST_VIA82C505
1424 bool
1425 depends on PCI && ARCH_SHARK
1426 default y
1428 config PCI_HOST_ITE8152
1429 bool
1430 depends on PCI && MACH_ARMCORE
1431 default y
1432 select DMABOUNCE
1434 source "drivers/pci/Kconfig"
1435 source "drivers/pci/pcie/Kconfig"
1437 source "drivers/pcmcia/Kconfig"
1439 endmenu
1441 menu "Kernel Features"
1443 config HAVE_SMP
1444 bool
1445 help
1446 This option should be selected by machines which have an SMP-
1447 capable CPU.
1449 The only effect of this option is to make the SMP-related
1450 options available to the user for configuration.
1452 config SMP
1453 bool "Symmetric Multi-Processing"
1454 depends on CPU_V6K || CPU_V7
1455 depends on GENERIC_CLOCKEVENTS
1456 depends on HAVE_SMP
1457 depends on MMU || ARM_MPU
1458 select USE_GENERIC_SMP_HELPERS
1459 help
1460 This enables support for systems with more than one CPU. If you have
1461 a system with only one CPU, like most personal computers, say N. If
1462 you have a system with more than one CPU, say Y.
1464 If you say N here, the kernel will run on single and multiprocessor
1465 machines, but will use only one CPU of a multiprocessor machine. If
1466 you say Y here, the kernel will run on many, but not all, single
1467 processor machines. On a single processor machine, the kernel will
1468 run faster if you say N here.
1470 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1471 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1472 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1474 If you don't know what to do here, say N.
1476 config SMP_ON_UP
1477 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1478 depends on SMP && !XIP_KERNEL && MMU
1479 default y
1480 help
1481 SMP kernels contain instructions which fail on non-SMP processors.
1482 Enabling this option allows the kernel to modify itself to make
1483 these instructions safe. Disabling it allows about 1K of space
1484 savings.
1486 If you don't know what to do here, say Y.
1488 config ARM_CPU_TOPOLOGY
1489 bool "Support cpu topology definition"
1490 depends on SMP && CPU_V7
1491 default y
1492 help
1493 Support ARM cpu topology definition. The MPIDR register defines
1494 affinity between processors which is then used to describe the cpu
1495 topology of an ARM System.
1497 config SCHED_MC
1498 bool "Multi-core scheduler support"
1499 depends on ARM_CPU_TOPOLOGY
1500 help
1501 Multi-core scheduler support improves the CPU scheduler's decision
1502 making when dealing with multi-core CPU chips at a cost of slightly
1503 increased overhead in some places. If unsure say N here.
1505 config SCHED_SMT
1506 bool "SMT scheduler support"
1507 depends on ARM_CPU_TOPOLOGY
1508 help
1509 Improves the CPU scheduler's decision making when dealing with
1510 MultiThreading at a cost of slightly increased overhead in some
1511 places. If unsure say N here.
1513 config HAVE_ARM_SCU
1514 bool
1515 help
1516 This option enables support for the ARM system coherency unit
1518 config HAVE_ARM_ARCH_TIMER
1519 bool "Architected timer support"
1520 depends on CPU_V7
1521 select ARM_ARCH_TIMER
1522 help
1523 This option enables support for the ARM architected timer
1525 config HAVE_ARM_TWD
1526 bool
1527 depends on SMP
1528 select CLKSRC_OF if OF
1529 help
1530 This options enables support for the ARM timer and watchdog unit
1532 config MCPM
1533 bool "Multi-Cluster Power Management"
1534 depends on CPU_V7 && SMP
1535 help
1536 This option provides the common power management infrastructure
1537 for (multi-)cluster based systems, such as big.LITTLE based
1538 systems.
1540 choice
1541 prompt "Memory split"
1542 default VMSPLIT_3G
1543 help
1544 Select the desired split between kernel and user memory.
1546 If you are not absolutely sure what you are doing, leave this
1547 option alone!
1549 config VMSPLIT_3G
1550 bool "3G/1G user/kernel split"
1551 config VMSPLIT_2G
1552 bool "2G/2G user/kernel split"
1553 config VMSPLIT_1G
1554 bool "1G/3G user/kernel split"
1555 endchoice
1557 config PAGE_OFFSET
1558 hex
1559 default 0x40000000 if VMSPLIT_1G
1560 default 0x80000000 if VMSPLIT_2G
1561 default 0xC0000000
1563 config NR_CPUS
1564 int "Maximum number of CPUs (2-32)"
1565 range 2 32
1566 depends on SMP
1567 default "4"
1569 config HOTPLUG_CPU
1570 bool "Support for hot-pluggable CPUs"
1571 depends on SMP
1572 help
1573 Say Y here to experiment with turning CPUs off and on. CPUs
1574 can be controlled through /sys/devices/system/cpu.
1576 config ARM_PSCI
1577 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1578 depends on CPU_V7
1579 help
1580 Say Y here if you want Linux to communicate with system firmware
1581 implementing the PSCI specification for CPU-centric power
1582 management operations described in ARM document number ARM DEN
1583 0022A ("Power State Coordination Interface System Software on
1584 ARM processors").
1586 config LOCAL_TIMERS
1587 bool "Use local timer interrupts"
1588 depends on SMP
1589 default y
1590 help
1591 Enable support for local timers on SMP platforms, rather then the
1592 legacy IPI broadcast method. Local timers allows the system
1593 accounting to be spread across the timer interval, preventing a
1594 "thundering herd" at every timer tick.
1596 # The GPIO number here must be sorted by descending number. In case of
1597 # a multiplatform kernel, we just want the highest value required by the
1598 # selected platforms.
1599 config ARCH_NR_GPIO
1600 int
1601 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1602 default 512 if SOC_OMAP5
1603 default 512 if ARCH_KEYSTONE
1604 default 392 if ARCH_U8500
1605 default 352 if ARCH_VT8500
1606 default 288 if ARCH_SUNXI
1607 default 264 if MACH_H4700
1608 default 0
1609 help
1610 Maximum number of GPIOs in the system.
1612 If unsure, leave the default value.
1614 source kernel/Kconfig.preempt
1616 config HZ
1617 int
1618 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1619 ARCH_S5PV210 || ARCH_EXYNOS4
1620 default AT91_TIMER_HZ if ARCH_AT91
1621 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1622 default 100
1624 config SCHED_HRTICK
1625 def_bool HIGH_RES_TIMERS
1627 config THUMB2_KERNEL
1628 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1629 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1630 default y if CPU_THUMBONLY
1631 select AEABI
1632 select ARM_ASM_UNIFIED
1633 select ARM_UNWIND
1634 help
1635 By enabling this option, the kernel will be compiled in
1636 Thumb-2 mode. A compiler/assembler that understand the unified
1637 ARM-Thumb syntax is needed.
1639 If unsure, say N.
1641 config THUMB2_AVOID_R_ARM_THM_JUMP11
1642 bool "Work around buggy Thumb-2 short branch relocations in gas"
1643 depends on THUMB2_KERNEL && MODULES
1644 default y
1645 help
1646 Various binutils versions can resolve Thumb-2 branches to
1647 locally-defined, preemptible global symbols as short-range "b.n"
1648 branch instructions.
1650 This is a problem, because there's no guarantee the final
1651 destination of the symbol, or any candidate locations for a
1652 trampoline, are within range of the branch. For this reason, the
1653 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1654 relocation in modules at all, and it makes little sense to add
1655 support.
1657 The symptom is that the kernel fails with an "unsupported
1658 relocation" error when loading some modules.
1660 Until fixed tools are available, passing
1661 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1662 code which hits this problem, at the cost of a bit of extra runtime
1663 stack usage in some cases.
1665 The problem is described in more detail at:
1666 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1668 Only Thumb-2 kernels are affected.
1670 Unless you are sure your tools don't have this problem, say Y.
1672 config ARM_ASM_UNIFIED
1673 bool
1675 config AEABI
1676 bool "Use the ARM EABI to compile the kernel"
1677 help
1678 This option allows for the kernel to be compiled using the latest
1679 ARM ABI (aka EABI). This is only useful if you are using a user
1680 space environment that is also compiled with EABI.
1682 Since there are major incompatibilities between the legacy ABI and
1683 EABI, especially with regard to structure member alignment, this
1684 option also changes the kernel syscall calling convention to
1685 disambiguate both ABIs and allow for backward compatibility support
1686 (selected with CONFIG_OABI_COMPAT).
1688 To use this you need GCC version 4.0.0 or later.
1690 config OABI_COMPAT
1691 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1692 depends on AEABI && !THUMB2_KERNEL
1693 default y
1694 help
1695 This option preserves the old syscall interface along with the
1696 new (ARM EABI) one. It also provides a compatibility layer to
1697 intercept syscalls that have structure arguments which layout
1698 in memory differs between the legacy ABI and the new ARM EABI
1699 (only for non "thumb" binaries). This option adds a tiny
1700 overhead to all syscalls and produces a slightly larger kernel.
1701 If you know you'll be using only pure EABI user space then you
1702 can say N here. If this option is not selected and you attempt
1703 to execute a legacy ABI binary then the result will be
1704 UNPREDICTABLE (in fact it can be predicted that it won't work
1705 at all). If in doubt say Y.
1707 config ARCH_HAS_HOLES_MEMORYMODEL
1708 bool
1710 config ARCH_SPARSEMEM_ENABLE
1711 bool
1713 config ARCH_SPARSEMEM_DEFAULT
1714 def_bool ARCH_SPARSEMEM_ENABLE
1716 config ARCH_SELECT_MEMORY_MODEL
1717 def_bool ARCH_SPARSEMEM_ENABLE
1719 config HAVE_ARCH_PFN_VALID
1720 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1722 config HIGHMEM
1723 bool "High Memory Support"
1724 depends on MMU
1725 help
1726 The address space of ARM processors is only 4 Gigabytes large
1727 and it has to accommodate user address space, kernel address
1728 space as well as some memory mapped IO. That means that, if you
1729 have a large amount of physical memory and/or IO, not all of the
1730 memory can be "permanently mapped" by the kernel. The physical
1731 memory that is not permanently mapped is called "high memory".
1733 Depending on the selected kernel/user memory split, minimum
1734 vmalloc space and actual amount of RAM, you may not need this
1735 option which should result in a slightly faster kernel.
1737 If unsure, say n.
1739 config HIGHPTE
1740 bool "Allocate 2nd-level pagetables from highmem"
1741 depends on HIGHMEM
1743 config HW_PERF_EVENTS
1744 bool "Enable hardware performance counter support for perf events"
1745 depends on PERF_EVENTS
1746 default y
1747 help
1748 Enable hardware performance counter support for perf events. If
1749 disabled, perf events will use software events only.
1751 config SYS_SUPPORTS_HUGETLBFS
1752 def_bool y
1753 depends on ARM_LPAE
1755 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1756 def_bool y
1757 depends on ARM_LPAE
1759 source "mm/Kconfig"
1761 config FORCE_MAX_ZONEORDER
1762 int "Maximum zone order" if ARCH_SHMOBILE
1763 range 11 64 if ARCH_SHMOBILE
1764 default "12" if SOC_AM33XX
1765 default "9" if SA1111
1766 default "11"
1767 help
1768 The kernel memory allocator divides physically contiguous memory
1769 blocks into "zones", where each zone is a power of two number of
1770 pages. This option selects the largest power of two that the kernel
1771 keeps in the memory allocator. If you need to allocate very large
1772 blocks of physically contiguous memory, then you may need to
1773 increase this value.
1775 This config option is actually maximum order plus one. For example,
1776 a value of 11 means that the largest free memory block is 2^10 pages.
1778 config ALIGNMENT_TRAP
1779 bool
1780 depends on CPU_CP15_MMU
1781 default y if !ARCH_EBSA110
1782 select HAVE_PROC_CPU if PROC_FS
1783 help
1784 ARM processors cannot fetch/store information which is not
1785 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1786 address divisible by 4. On 32-bit ARM processors, these non-aligned
1787 fetch/store instructions will be emulated in software if you say
1788 here, which has a severe performance impact. This is necessary for
1789 correct operation of some network protocols. With an IP-only
1790 configuration it is safe to say N, otherwise say Y.
1792 config UACCESS_WITH_MEMCPY
1793 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1794 depends on MMU
1795 default y if CPU_FEROCEON
1796 help
1797 Implement faster copy_to_user and clear_user methods for CPU
1798 cores where a 8-word STM instruction give significantly higher
1799 memory write throughput than a sequence of individual 32bit stores.
1801 A possible side effect is a slight increase in scheduling latency
1802 between threads sharing the same address space if they invoke
1803 such copy operations with large buffers.
1805 However, if the CPU data cache is using a write-allocate mode,
1806 this option is unlikely to provide any performance gain.
1808 config SECCOMP
1809 bool
1810 prompt "Enable seccomp to safely compute untrusted bytecode"
1811 ---help---
1812 This kernel feature is useful for number crunching applications
1813 that may need to compute untrusted bytecode during their
1814 execution. By using pipes or other transports made available to
1815 the process as file descriptors supporting the read/write
1816 syscalls, it's possible to isolate those applications in
1817 their own address space using seccomp. Once seccomp is
1818 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1819 and the task is only allowed to execute a few safe syscalls
1820 defined by each seccomp mode.
1822 config CC_STACKPROTECTOR
1823 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1824 help
1825 This option turns on the -fstack-protector GCC feature. This
1826 feature puts, at the beginning of functions, a canary value on
1827 the stack just before the return address, and validates
1828 the value just before actually returning. Stack based buffer
1829 overflows (that need to overwrite this return address) now also
1830 overwrite the canary, which gets detected and the attack is then
1831 neutralized via a kernel panic.
1832 This feature requires gcc version 4.2 or above.
1834 config XEN_DOM0
1835 def_bool y
1836 depends on XEN
1838 config XEN
1839 bool "Xen guest support on ARM (EXPERIMENTAL)"
1840 depends on ARM && AEABI && OF
1841 depends on CPU_V7 && !CPU_V6
1842 depends on !GENERIC_ATOMIC64
1843 select ARM_PSCI
1844 help
1845 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1847 endmenu
1849 menu "Boot options"
1851 config USE_OF
1852 bool "Flattened Device Tree support"
1853 select IRQ_DOMAIN
1854 select OF
1855 select OF_EARLY_FLATTREE
1856 help
1857 Include support for flattened device tree machine descriptions.
1859 config ATAGS
1860 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1861 default y
1862 help
1863 This is the traditional way of passing data to the kernel at boot
1864 time. If you are solely relying on the flattened device tree (or
1865 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1866 to remove ATAGS support from your kernel binary. If unsure,
1867 leave this to y.
1869 config DEPRECATED_PARAM_STRUCT
1870 bool "Provide old way to pass kernel parameters"
1871 depends on ATAGS
1872 help
1873 This was deprecated in 2001 and announced to live on for 5 years.
1874 Some old boot loaders still use this way.
1876 # Compressed boot loader in ROM. Yes, we really want to ask about
1877 # TEXT and BSS so we preserve their values in the config files.
1878 config ZBOOT_ROM_TEXT
1879 hex "Compressed ROM boot loader base address"
1880 default "0"
1881 help
1882 The physical address at which the ROM-able zImage is to be
1883 placed in the target. Platforms which normally make use of
1884 ROM-able zImage formats normally set this to a suitable
1885 value in their defconfig file.
1887 If ZBOOT_ROM is not enabled, this has no effect.
1889 config ZBOOT_ROM_BSS
1890 hex "Compressed ROM boot loader BSS address"
1891 default "0"
1892 help
1893 The base address of an area of read/write memory in the target
1894 for the ROM-able zImage which must be available while the
1895 decompressor is running. It must be large enough to hold the
1896 entire decompressed kernel plus an additional 128 KiB.
1897 Platforms which normally make use of ROM-able zImage formats
1898 normally set this to a suitable value in their defconfig file.
1900 If ZBOOT_ROM is not enabled, this has no effect.
1902 config ZBOOT_ROM
1903 bool "Compressed boot loader in ROM/flash"
1904 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1905 help
1906 Say Y here if you intend to execute your compressed kernel image
1907 (zImage) directly from ROM or flash. If unsure, say N.
1909 choice
1910 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1911 depends on ZBOOT_ROM && ARCH_SH7372
1912 default ZBOOT_ROM_NONE
1913 help
1914 Include experimental SD/MMC loading code in the ROM-able zImage.
1915 With this enabled it is possible to write the ROM-able zImage
1916 kernel image to an MMC or SD card and boot the kernel straight
1917 from the reset vector. At reset the processor Mask ROM will load
1918 the first part of the ROM-able zImage which in turn loads the
1919 rest the kernel image to RAM.
1921 config ZBOOT_ROM_NONE
1922 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1923 help
1924 Do not load image from SD or MMC
1926 config ZBOOT_ROM_MMCIF
1927 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1928 help
1929 Load image from MMCIF hardware block.
1931 config ZBOOT_ROM_SH_MOBILE_SDHI
1932 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1933 help
1934 Load image from SDHI hardware block
1936 endchoice
1938 config ARM_APPENDED_DTB
1939 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1940 depends on OF && !ZBOOT_ROM
1941 help
1942 With this option, the boot code will look for a device tree binary
1943 (DTB) appended to zImage
1944 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1946 This is meant as a backward compatibility convenience for those
1947 systems with a bootloader that can't be upgraded to accommodate
1948 the documented boot protocol using a device tree.
1950 Beware that there is very little in terms of protection against
1951 this option being confused by leftover garbage in memory that might
1952 look like a DTB header after a reboot if no actual DTB is appended
1953 to zImage. Do not leave this option active in a production kernel
1954 if you don't intend to always append a DTB. Proper passing of the
1955 location into r2 of a bootloader provided DTB is always preferable
1956 to this option.
1958 config ARM_ATAG_DTB_COMPAT
1959 bool "Supplement the appended DTB with traditional ATAG information"
1960 depends on ARM_APPENDED_DTB
1961 help
1962 Some old bootloaders can't be updated to a DTB capable one, yet
1963 they provide ATAGs with memory configuration, the ramdisk address,
1964 the kernel cmdline string, etc. Such information is dynamically
1965 provided by the bootloader and can't always be stored in a static
1966 DTB. To allow a device tree enabled kernel to be used with such
1967 bootloaders, this option allows zImage to extract the information
1968 from the ATAG list and store it at run time into the appended DTB.
1970 choice
1971 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1972 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1974 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1975 bool "Use bootloader kernel arguments if available"
1976 help
1977 Uses the command-line options passed by the boot loader instead of
1978 the device tree bootargs property. If the boot loader doesn't provide
1979 any, the device tree bootargs property will be used.
1981 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1982 bool "Extend with bootloader kernel arguments"
1983 help
1984 The command-line arguments provided by the boot loader will be
1985 appended to the the device tree bootargs property.
1987 endchoice
1989 config CMDLINE
1990 string "Default kernel command string"
1991 default ""
1992 help
1993 On some architectures (EBSA110 and CATS), there is currently no way
1994 for the boot loader to pass arguments to the kernel. For these
1995 architectures, you should supply some command-line options at build
1996 time by entering them here. As a minimum, you should specify the
1997 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1999 choice
2000 prompt "Kernel command line type" if CMDLINE != ""
2001 default CMDLINE_FROM_BOOTLOADER
2002 depends on ATAGS
2004 config CMDLINE_FROM_BOOTLOADER
2005 bool "Use bootloader kernel arguments if available"
2006 help
2007 Uses the command-line options passed by the boot loader. If
2008 the boot loader doesn't provide any, the default kernel command
2009 string provided in CMDLINE will be used.
2011 config CMDLINE_EXTEND
2012 bool "Extend bootloader kernel arguments"
2013 help
2014 The command-line arguments provided by the boot loader will be
2015 appended to the default kernel command string.
2017 config CMDLINE_FORCE
2018 bool "Always use the default kernel command string"
2019 help
2020 Always use the default kernel command string, even if the boot
2021 loader passes other arguments to the kernel.
2022 This is useful if you cannot or don't want to change the
2023 command-line options your boot loader passes to the kernel.
2024 endchoice
2026 config XIP_KERNEL
2027 bool "Kernel Execute-In-Place from ROM"
2028 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2029 help
2030 Execute-In-Place allows the kernel to run from non-volatile storage
2031 directly addressable by the CPU, such as NOR flash. This saves RAM
2032 space since the text section of the kernel is not loaded from flash
2033 to RAM. Read-write sections, such as the data section and stack,
2034 are still copied to RAM. The XIP kernel is not compressed since
2035 it has to run directly from flash, so it will take more space to
2036 store it. The flash address used to link the kernel object files,
2037 and for storing it, is configuration dependent. Therefore, if you
2038 say Y here, you must know the proper physical address where to
2039 store the kernel image depending on your own flash memory usage.
2041 Also note that the make target becomes "make xipImage" rather than
2042 "make zImage" or "make Image". The final kernel binary to put in
2043 ROM memory will be arch/arm/boot/xipImage.
2045 If unsure, say N.
2047 config XIP_PHYS_ADDR
2048 hex "XIP Kernel Physical Location"
2049 depends on XIP_KERNEL
2050 default "0x00080000"
2051 help
2052 This is the physical address in your flash memory the kernel will
2053 be linked for and stored to. This address is dependent on your
2054 own flash usage.
2056 config KEXEC
2057 bool "Kexec system call (EXPERIMENTAL)"
2058 depends on (!SMP || PM_SLEEP_SMP)
2059 help
2060 kexec is a system call that implements the ability to shutdown your
2061 current kernel, and to start another kernel. It is like a reboot
2062 but it is independent of the system firmware. And like a reboot
2063 you can start any kernel with it, not just Linux.
2065 It is an ongoing process to be certain the hardware in a machine
2066 is properly shutdown, so do not be surprised if this code does not
2067 initially work for you. It may help to enable device hotplugging
2068 support.
2070 config ATAGS_PROC
2071 bool "Export atags in procfs"
2072 depends on ATAGS && KEXEC
2073 default y
2074 help
2075 Should the atags used to boot the kernel be exported in an "atags"
2076 file in procfs. Useful with kexec.
2078 config CRASH_DUMP
2079 bool "Build kdump crash kernel (EXPERIMENTAL)"
2080 help
2081 Generate crash dump after being started by kexec. This should
2082 be normally only set in special crash dump kernels which are
2083 loaded in the main kernel with kexec-tools into a specially
2084 reserved region and then later executed after a crash by
2085 kdump/kexec. The crash dump kernel must be compiled to a
2086 memory address not used by the main kernel
2088 For more details see Documentation/kdump/kdump.txt
2090 config AUTO_ZRELADDR
2091 bool "Auto calculation of the decompressed kernel image address"
2092 depends on !ZBOOT_ROM
2093 help
2094 ZRELADDR is the physical address where the decompressed kernel
2095 image will be placed. If AUTO_ZRELADDR is selected, the address
2096 will be determined at run-time by masking the current IP with
2097 0xf8000000. This assumes the zImage being placed in the first 128MB
2098 from start of memory.
2100 endmenu
2102 menu "CPU Power Management"
2104 if ARCH_HAS_CPUFREQ
2105 source "drivers/cpufreq/Kconfig"
2106 endif
2108 source "drivers/cpuidle/Kconfig"
2110 endmenu
2112 menu "Floating point emulation"
2114 comment "At least one emulation must be selected"
2116 config FPE_NWFPE
2117 bool "NWFPE math emulation"
2118 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2119 ---help---
2120 Say Y to include the NWFPE floating point emulator in the kernel.
2121 This is necessary to run most binaries. Linux does not currently
2122 support floating point hardware so you need to say Y here even if
2123 your machine has an FPA or floating point co-processor podule.
2125 You may say N here if you are going to load the Acorn FPEmulator
2126 early in the bootup.
2128 config FPE_NWFPE_XP
2129 bool "Support extended precision"
2130 depends on FPE_NWFPE
2131 help
2132 Say Y to include 80-bit support in the kernel floating-point
2133 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2134 Note that gcc does not generate 80-bit operations by default,
2135 so in most cases this option only enlarges the size of the
2136 floating point emulator without any good reason.
2138 You almost surely want to say N here.
2140 config FPE_FASTFPE
2141 bool "FastFPE math emulation (EXPERIMENTAL)"
2142 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2143 ---help---
2144 Say Y here to include the FAST floating point emulator in the kernel.
2145 This is an experimental much faster emulator which now also has full
2146 precision for the mantissa. It does not support any exceptions.
2147 It is very simple, and approximately 3-6 times faster than NWFPE.
2149 It should be sufficient for most programs. It may be not suitable
2150 for scientific calculations, but you have to check this for yourself.
2151 If you do not feel you need a faster FP emulation you should better
2152 choose NWFPE.
2154 config VFP
2155 bool "VFP-format floating point maths"
2156 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2157 help
2158 Say Y to include VFP support code in the kernel. This is needed
2159 if your hardware includes a VFP unit.
2161 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2162 release notes and additional status information.
2164 Say N if your target does not have VFP hardware.
2166 config VFPv3
2167 bool
2168 depends on VFP
2169 default y if CPU_V7
2171 config NEON
2172 bool "Advanced SIMD (NEON) Extension support"
2173 depends on VFPv3 && CPU_V7
2174 help
2175 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2176 Extension.
2178 endmenu
2180 menu "Userspace binary formats"
2182 source "fs/Kconfig.binfmt"
2184 config ARTHUR
2185 tristate "RISC OS personality"
2186 depends on !AEABI
2187 help
2188 Say Y here to include the kernel code necessary if you want to run
2189 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2190 experimental; if this sounds frightening, say N and sleep in peace.
2191 You can also say M here to compile this support as a module (which
2192 will be called arthur).
2194 endmenu
2196 menu "Power management options"
2198 source "kernel/power/Kconfig"
2200 config ARCH_SUSPEND_POSSIBLE
2201 depends on !ARCH_S5PC100
2202 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2203 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2204 def_bool y
2206 config ARM_CPU_SUSPEND
2207 def_bool PM_SLEEP
2209 endmenu
2211 source "net/Kconfig"
2213 source "drivers/Kconfig"
2215 source "fs/Kconfig"
2217 source "arch/arm/Kconfig.debug"
2219 source "security/Kconfig"
2221 source "crypto/Kconfig"
2223 source "lib/Kconfig"
2225 source "arch/arm/kvm/Kconfig"