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KVM: ignore reads to perfctr msrs
[linux-2.6.git] / arch / x86 / kvm / x86.c
blob132c5100d4f4f59607882fec59c426f6ecebb9f8
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
21 #include <linux/kvm_host.h>
22 #include "irq.h"
23 #include "mmu.h"
24 #include "i8254.h"
25 #include "tss.h"
26 #include "kvm_cache_regs.h"
27 #include "x86.h"
28
29 #include <linux/clocksource.h>
30 #include <linux/interrupt.h>
31 #include <linux/kvm.h>
32 #include <linux/fs.h>
33 #include <linux/vmalloc.h>
34 #include <linux/module.h>
35 #include <linux/mman.h>
36 #include <linux/highmem.h>
37 #include <linux/iommu.h>
38 #include <linux/intel-iommu.h>
39 #include <linux/cpufreq.h>
40 #include <trace/events/kvm.h>
41 #undef TRACE_INCLUDE_FILE
42 #define CREATE_TRACE_POINTS
43 #include "trace.h"
44
45 #include <asm/uaccess.h>
46 #include <asm/msr.h>
47 #include <asm/desc.h>
48 #include <asm/mtrr.h>
49 #include <asm/mce.h>
50
51 #define MAX_IO_MSRS 256
52 #define CR0_RESERVED_BITS \
53 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
54 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
55 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
56 #define CR4_RESERVED_BITS \
57 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
58 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
59 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
60 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
61
62 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
63
64 #define KVM_MAX_MCE_BANKS 32
65 #define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
66
67 /* EFER defaults:
68 * - enable syscall per default because its emulated by KVM
69 * - enable LME and LMA per default on 64 bit KVM
70 */
71 #ifdef CONFIG_X86_64
72 static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
73 #else
74 static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
75 #endif
76
77 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
78 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
79
80 static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
81 struct kvm_cpuid_entry2 __user *entries);
82
83 struct kvm_x86_ops *kvm_x86_ops;
84 EXPORT_SYMBOL_GPL(kvm_x86_ops);
85
86 int ignore_msrs = 0;
87 module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
88
89 struct kvm_stats_debugfs_item debugfs_entries[] = {
90 { "pf_fixed", VCPU_STAT(pf_fixed) },
91 { "pf_guest", VCPU_STAT(pf_guest) },
92 { "tlb_flush", VCPU_STAT(tlb_flush) },
93 { "invlpg", VCPU_STAT(invlpg) },
94 { "exits", VCPU_STAT(exits) },
95 { "io_exits", VCPU_STAT(io_exits) },
96 { "mmio_exits", VCPU_STAT(mmio_exits) },
97 { "signal_exits", VCPU_STAT(signal_exits) },
98 { "irq_window", VCPU_STAT(irq_window_exits) },
99 { "nmi_window", VCPU_STAT(nmi_window_exits) },
100 { "halt_exits", VCPU_STAT(halt_exits) },
101 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
102 { "hypercalls", VCPU_STAT(hypercalls) },
103 { "request_irq", VCPU_STAT(request_irq_exits) },
104 { "irq_exits", VCPU_STAT(irq_exits) },
105 { "host_state_reload", VCPU_STAT(host_state_reload) },
106 { "efer_reload", VCPU_STAT(efer_reload) },
107 { "fpu_reload", VCPU_STAT(fpu_reload) },
108 { "insn_emulation", VCPU_STAT(insn_emulation) },
109 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
110 { "irq_injections", VCPU_STAT(irq_injections) },
111 { "nmi_injections", VCPU_STAT(nmi_injections) },
112 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
113 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
114 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
115 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
116 { "mmu_flooded", VM_STAT(mmu_flooded) },
117 { "mmu_recycled", VM_STAT(mmu_recycled) },
118 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
119 { "mmu_unsync", VM_STAT(mmu_unsync) },
120 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
121 { "largepages", VM_STAT(lpages) },
122 { NULL }
123 };
124
125 unsigned long segment_base(u16 selector)
126 {
127 struct descriptor_table gdt;
128 struct desc_struct *d;
129 unsigned long table_base;
130 unsigned long v;
131
132 if (selector == 0)
133 return 0;
134
135 kvm_get_gdt(&gdt);
136 table_base = gdt.base;
137
138 if (selector & 4) { /* from ldt */
139 u16 ldt_selector = kvm_read_ldt();
140
141 table_base = segment_base(ldt_selector);
142 }
143 d = (struct desc_struct *)(table_base + (selector & ~7));
144 v = get_desc_base(d);
145 #ifdef CONFIG_X86_64
146 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
147 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
148 #endif
149 return v;
150 }
151 EXPORT_SYMBOL_GPL(segment_base);
152
153 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
154 {
155 if (irqchip_in_kernel(vcpu->kvm))
156 return vcpu->arch.apic_base;
157 else
158 return vcpu->arch.apic_base;
159 }
160 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
161
162 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
163 {
164 /* TODO: reserve bits check */
165 if (irqchip_in_kernel(vcpu->kvm))
166 kvm_lapic_set_base(vcpu, data);
167 else
168 vcpu->arch.apic_base = data;
169 }
170 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
171
172 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
173 {
174 WARN_ON(vcpu->arch.exception.pending);
175 vcpu->arch.exception.pending = true;
176 vcpu->arch.exception.has_error_code = false;
177 vcpu->arch.exception.nr = nr;
178 }
179 EXPORT_SYMBOL_GPL(kvm_queue_exception);
180
181 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
182 u32 error_code)
183 {
184 ++vcpu->stat.pf_guest;
185
186 if (vcpu->arch.exception.pending) {
187 switch(vcpu->arch.exception.nr) {
188 case DF_VECTOR:
189 /* triple fault -> shutdown */
190 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
191 return;
192 case PF_VECTOR:
193 vcpu->arch.exception.nr = DF_VECTOR;
194 vcpu->arch.exception.error_code = 0;
195 return;
196 default:
197 /* replace previous exception with a new one in a hope
198 that instruction re-execution will regenerate lost
199 exception */
200 vcpu->arch.exception.pending = false;
201 break;
202 }
203 }
204 vcpu->arch.cr2 = addr;
205 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
206 }
207
208 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
209 {
210 vcpu->arch.nmi_pending = 1;
211 }
212 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
213
214 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
215 {
216 WARN_ON(vcpu->arch.exception.pending);
217 vcpu->arch.exception.pending = true;
218 vcpu->arch.exception.has_error_code = true;
219 vcpu->arch.exception.nr = nr;
220 vcpu->arch.exception.error_code = error_code;
221 }
222 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
223
224 /*
225 * Load the pae pdptrs. Return true is they are all valid.
226 */
227 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
228 {
229 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
230 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
231 int i;
232 int ret;
233 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
234
235 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
236 offset * sizeof(u64), sizeof(pdpte));
237 if (ret < 0) {
238 ret = 0;
239 goto out;
240 }
241 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
242 if (is_present_gpte(pdpte[i]) &&
243 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
244 ret = 0;
245 goto out;
246 }
247 }
248 ret = 1;
249
250 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
251 __set_bit(VCPU_EXREG_PDPTR,
252 (unsigned long *)&vcpu->arch.regs_avail);
253 __set_bit(VCPU_EXREG_PDPTR,
254 (unsigned long *)&vcpu->arch.regs_dirty);
255 out:
256
257 return ret;
258 }
259 EXPORT_SYMBOL_GPL(load_pdptrs);
260
261 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
262 {
263 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
264 bool changed = true;
265 int r;
266
267 if (is_long_mode(vcpu) || !is_pae(vcpu))
268 return false;
269
270 if (!test_bit(VCPU_EXREG_PDPTR,
271 (unsigned long *)&vcpu->arch.regs_avail))
272 return true;
273
274 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
275 if (r < 0)
276 goto out;
277 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
278 out:
279
280 return changed;
281 }
282
283 void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
284 {
285 if (cr0 & CR0_RESERVED_BITS) {
286 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
287 cr0, vcpu->arch.cr0);
288 kvm_inject_gp(vcpu, 0);
289 return;
290 }
291
292 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
293 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
294 kvm_inject_gp(vcpu, 0);
295 return;
296 }
297
298 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
299 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
300 "and a clear PE flag\n");
301 kvm_inject_gp(vcpu, 0);
302 return;
303 }
304
305 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
306 #ifdef CONFIG_X86_64
307 if ((vcpu->arch.shadow_efer & EFER_LME)) {
308 int cs_db, cs_l;
309
310 if (!is_pae(vcpu)) {
311 printk(KERN_DEBUG "set_cr0: #GP, start paging "
312 "in long mode while PAE is disabled\n");
313 kvm_inject_gp(vcpu, 0);
314 return;
315 }
316 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
317 if (cs_l) {
318 printk(KERN_DEBUG "set_cr0: #GP, start paging "
319 "in long mode while CS.L == 1\n");
320 kvm_inject_gp(vcpu, 0);
321 return;
322
323 }
324 } else
325 #endif
326 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
327 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
328 "reserved bits\n");
329 kvm_inject_gp(vcpu, 0);
330 return;
331 }
332
333 }
334
335 kvm_x86_ops->set_cr0(vcpu, cr0);
336 vcpu->arch.cr0 = cr0;
337
338 kvm_mmu_reset_context(vcpu);
339 return;
340 }
341 EXPORT_SYMBOL_GPL(kvm_set_cr0);
342
343 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
344 {
345 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
346 }
347 EXPORT_SYMBOL_GPL(kvm_lmsw);
348
349 void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
350 {
351 unsigned long old_cr4 = vcpu->arch.cr4;
352 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
353
354 if (cr4 & CR4_RESERVED_BITS) {
355 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
356 kvm_inject_gp(vcpu, 0);
357 return;
358 }
359
360 if (is_long_mode(vcpu)) {
361 if (!(cr4 & X86_CR4_PAE)) {
362 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
363 "in long mode\n");
364 kvm_inject_gp(vcpu, 0);
365 return;
366 }
367 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
368 && ((cr4 ^ old_cr4) & pdptr_bits)
369 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
370 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
371 kvm_inject_gp(vcpu, 0);
372 return;
373 }
374
375 if (cr4 & X86_CR4_VMXE) {
376 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
377 kvm_inject_gp(vcpu, 0);
378 return;
379 }
380 kvm_x86_ops->set_cr4(vcpu, cr4);
381 vcpu->arch.cr4 = cr4;
382 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
383 kvm_mmu_reset_context(vcpu);
384 }
385 EXPORT_SYMBOL_GPL(kvm_set_cr4);
386
387 void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
388 {
389 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
390 kvm_mmu_sync_roots(vcpu);
391 kvm_mmu_flush_tlb(vcpu);
392 return;
393 }
394
395 if (is_long_mode(vcpu)) {
396 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
397 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
398 kvm_inject_gp(vcpu, 0);
399 return;
400 }
401 } else {
402 if (is_pae(vcpu)) {
403 if (cr3 & CR3_PAE_RESERVED_BITS) {
404 printk(KERN_DEBUG
405 "set_cr3: #GP, reserved bits\n");
406 kvm_inject_gp(vcpu, 0);
407 return;
408 }
409 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
410 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
411 "reserved bits\n");
412 kvm_inject_gp(vcpu, 0);
413 return;
414 }
415 }
416 /*
417 * We don't check reserved bits in nonpae mode, because
418 * this isn't enforced, and VMware depends on this.
419 */
420 }
421
422 /*
423 * Does the new cr3 value map to physical memory? (Note, we
424 * catch an invalid cr3 even in real-mode, because it would
425 * cause trouble later on when we turn on paging anyway.)
426 *
427 * A real CPU would silently accept an invalid cr3 and would
428 * attempt to use it - with largely undefined (and often hard
429 * to debug) behavior on the guest side.
430 */
431 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
432 kvm_inject_gp(vcpu, 0);
433 else {
434 vcpu->arch.cr3 = cr3;
435 vcpu->arch.mmu.new_cr3(vcpu);
436 }
437 }
438 EXPORT_SYMBOL_GPL(kvm_set_cr3);
439
440 void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
441 {
442 if (cr8 & CR8_RESERVED_BITS) {
443 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
444 kvm_inject_gp(vcpu, 0);
445 return;
446 }
447 if (irqchip_in_kernel(vcpu->kvm))
448 kvm_lapic_set_tpr(vcpu, cr8);
449 else
450 vcpu->arch.cr8 = cr8;
451 }
452 EXPORT_SYMBOL_GPL(kvm_set_cr8);
453
454 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
455 {
456 if (irqchip_in_kernel(vcpu->kvm))
457 return kvm_lapic_get_cr8(vcpu);
458 else
459 return vcpu->arch.cr8;
460 }
461 EXPORT_SYMBOL_GPL(kvm_get_cr8);
462
463 static inline u32 bit(int bitno)
464 {
465 return 1 << (bitno & 31);
466 }
467
468 /*
469 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
470 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
471 *
472 * This list is modified at module load time to reflect the
473 * capabilities of the host cpu.
474 */
475 static u32 msrs_to_save[] = {
476 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
477 MSR_K6_STAR,
478 #ifdef CONFIG_X86_64
479 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
480 #endif
481 MSR_IA32_TSC, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
482 MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
483 };
484
485 static unsigned num_msrs_to_save;
486
487 static u32 emulated_msrs[] = {
488 MSR_IA32_MISC_ENABLE,
489 };
490
491 static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
492 {
493 if (efer & efer_reserved_bits) {
494 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
495 efer);
496 kvm_inject_gp(vcpu, 0);
497 return;
498 }
499
500 if (is_paging(vcpu)
501 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
502 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
503 kvm_inject_gp(vcpu, 0);
504 return;
505 }
506
507 if (efer & EFER_FFXSR) {
508 struct kvm_cpuid_entry2 *feat;
509
510 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
511 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
512 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
513 kvm_inject_gp(vcpu, 0);
514 return;
515 }
516 }
517
518 if (efer & EFER_SVME) {
519 struct kvm_cpuid_entry2 *feat;
520
521 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
522 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
523 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
524 kvm_inject_gp(vcpu, 0);
525 return;
526 }
527 }
528
529 kvm_x86_ops->set_efer(vcpu, efer);
530
531 efer &= ~EFER_LMA;
532 efer |= vcpu->arch.shadow_efer & EFER_LMA;
533
534 vcpu->arch.shadow_efer = efer;
535
536 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
537 kvm_mmu_reset_context(vcpu);
538 }
539
540 void kvm_enable_efer_bits(u64 mask)
541 {
542 efer_reserved_bits &= ~mask;
543 }
544 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
545
546
547 /*
548 * Writes msr value into into the appropriate "register".
549 * Returns 0 on success, non-0 otherwise.
550 * Assumes vcpu_load() was already called.
551 */
552 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
553 {
554 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
555 }
556
557 /*
558 * Adapt set_msr() to msr_io()'s calling convention
559 */
560 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
561 {
562 return kvm_set_msr(vcpu, index, *data);
563 }
564
565 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
566 {
567 static int version;
568 struct pvclock_wall_clock wc;
569 struct timespec now, sys, boot;
570
571 if (!wall_clock)
572 return;
573
574 version++;
575
576 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
577
578 /*
579 * The guest calculates current wall clock time by adding
580 * system time (updated by kvm_write_guest_time below) to the
581 * wall clock specified here. guest system time equals host
582 * system time for us, thus we must fill in host boot time here.
583 */
584 now = current_kernel_time();
585 ktime_get_ts(&sys);
586 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
587
588 wc.sec = boot.tv_sec;
589 wc.nsec = boot.tv_nsec;
590 wc.version = version;
591
592 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
593
594 version++;
595 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
596 }
597
598 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
599 {
600 uint32_t quotient, remainder;
601
602 /* Don't try to replace with do_div(), this one calculates
603 * "(dividend << 32) / divisor" */
604 __asm__ ( "divl %4"
605 : "=a" (quotient), "=d" (remainder)
606 : "0" (0), "1" (dividend), "r" (divisor) );
607 return quotient;
608 }
609
610 static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
611 {
612 uint64_t nsecs = 1000000000LL;
613 int32_t shift = 0;
614 uint64_t tps64;
615 uint32_t tps32;
616
617 tps64 = tsc_khz * 1000LL;
618 while (tps64 > nsecs*2) {
619 tps64 >>= 1;
620 shift--;
621 }
622
623 tps32 = (uint32_t)tps64;
624 while (tps32 <= (uint32_t)nsecs) {
625 tps32 <<= 1;
626 shift++;
627 }
628
629 hv_clock->tsc_shift = shift;
630 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
631
632 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
633 __func__, tsc_khz, hv_clock->tsc_shift,
634 hv_clock->tsc_to_system_mul);
635 }
636
637 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
638
639 static void kvm_write_guest_time(struct kvm_vcpu *v)
640 {
641 struct timespec ts;
642 unsigned long flags;
643 struct kvm_vcpu_arch *vcpu = &v->arch;
644 void *shared_kaddr;
645 unsigned long this_tsc_khz;
646
647 if ((!vcpu->time_page))
648 return;
649
650 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
651 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
652 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
653 vcpu->hv_clock_tsc_khz = this_tsc_khz;
654 }
655 put_cpu_var(cpu_tsc_khz);
656
657 /* Keep irq disabled to prevent changes to the clock */
658 local_irq_save(flags);
659 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
660 ktime_get_ts(&ts);
661 local_irq_restore(flags);
662
663 /* With all the info we got, fill in the values */
664
665 vcpu->hv_clock.system_time = ts.tv_nsec +
666 (NSEC_PER_SEC * (u64)ts.tv_sec);
667 /*
668 * The interface expects us to write an even number signaling that the
669 * update is finished. Since the guest won't see the intermediate
670 * state, we just increase by 2 at the end.
671 */
672 vcpu->hv_clock.version += 2;
673
674 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
675
676 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
677 sizeof(vcpu->hv_clock));
678
679 kunmap_atomic(shared_kaddr, KM_USER0);
680
681 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
682 }
683
684 static int kvm_request_guest_time_update(struct kvm_vcpu *v)
685 {
686 struct kvm_vcpu_arch *vcpu = &v->arch;
687
688 if (!vcpu->time_page)
689 return 0;
690 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
691 return 1;
692 }
693
694 static bool msr_mtrr_valid(unsigned msr)
695 {
696 switch (msr) {
697 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
698 case MSR_MTRRfix64K_00000:
699 case MSR_MTRRfix16K_80000:
700 case MSR_MTRRfix16K_A0000:
701 case MSR_MTRRfix4K_C0000:
702 case MSR_MTRRfix4K_C8000:
703 case MSR_MTRRfix4K_D0000:
704 case MSR_MTRRfix4K_D8000:
705 case MSR_MTRRfix4K_E0000:
706 case MSR_MTRRfix4K_E8000:
707 case MSR_MTRRfix4K_F0000:
708 case MSR_MTRRfix4K_F8000:
709 case MSR_MTRRdefType:
710 case MSR_IA32_CR_PAT:
711 return true;
712 case 0x2f8:
713 return true;
714 }
715 return false;
716 }
717
718 static bool valid_pat_type(unsigned t)
719 {
720 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
721 }
722
723 static bool valid_mtrr_type(unsigned t)
724 {
725 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
726 }
727
728 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
729 {
730 int i;
731
732 if (!msr_mtrr_valid(msr))
733 return false;
734
735 if (msr == MSR_IA32_CR_PAT) {
736 for (i = 0; i < 8; i++)
737 if (!valid_pat_type((data >> (i * 8)) & 0xff))
738 return false;
739 return true;
740 } else if (msr == MSR_MTRRdefType) {
741 if (data & ~0xcff)
742 return false;
743 return valid_mtrr_type(data & 0xff);
744 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
745 for (i = 0; i < 8 ; i++)
746 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
747 return false;
748 return true;
749 }
750
751 /* variable MTRRs */
752 return valid_mtrr_type(data & 0xff);
753 }
754
755 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
756 {
757 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
758
759 if (!mtrr_valid(vcpu, msr, data))
760 return 1;
761
762 if (msr == MSR_MTRRdefType) {
763 vcpu->arch.mtrr_state.def_type = data;
764 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
765 } else if (msr == MSR_MTRRfix64K_00000)
766 p[0] = data;
767 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
768 p[1 + msr - MSR_MTRRfix16K_80000] = data;
769 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
770 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
771 else if (msr == MSR_IA32_CR_PAT)
772 vcpu->arch.pat = data;
773 else { /* Variable MTRRs */
774 int idx, is_mtrr_mask;
775 u64 *pt;
776
777 idx = (msr - 0x200) / 2;
778 is_mtrr_mask = msr - 0x200 - 2 * idx;
779 if (!is_mtrr_mask)
780 pt =
781 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
782 else
783 pt =
784 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
785 *pt = data;
786 }
787
788 kvm_mmu_reset_context(vcpu);
789 return 0;
790 }
791
792 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
793 {
794 u64 mcg_cap = vcpu->arch.mcg_cap;
795 unsigned bank_num = mcg_cap & 0xff;
796
797 switch (msr) {
798 case MSR_IA32_MCG_STATUS:
799 vcpu->arch.mcg_status = data;
800 break;
801 case MSR_IA32_MCG_CTL:
802 if (!(mcg_cap & MCG_CTL_P))
803 return 1;
804 if (data != 0 && data != ~(u64)0)
805 return -1;
806 vcpu->arch.mcg_ctl = data;
807 break;
808 default:
809 if (msr >= MSR_IA32_MC0_CTL &&
810 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
811 u32 offset = msr - MSR_IA32_MC0_CTL;
812 /* only 0 or all 1s can be written to IA32_MCi_CTL */
813 if ((offset & 0x3) == 0 &&
814 data != 0 && data != ~(u64)0)
815 return -1;
816 vcpu->arch.mce_banks[offset] = data;
817 break;
818 }
819 return 1;
820 }
821 return 0;
822 }
823
824 int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
825 {
826 switch (msr) {
827 case MSR_EFER:
828 set_efer(vcpu, data);
829 break;
830 case MSR_K7_HWCR:
831 data &= ~(u64)0x40; /* ignore flush filter disable */
832 if (data != 0) {
833 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
834 data);
835 return 1;
836 }
837 break;
838 case MSR_FAM10H_MMIO_CONF_BASE:
839 if (data != 0) {
840 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
841 "0x%llx\n", data);
842 return 1;
843 }
844 break;
845 case MSR_AMD64_NB_CFG:
846 break;
847 case MSR_IA32_DEBUGCTLMSR:
848 if (!data) {
849 /* We support the non-activated case already */
850 break;
851 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
852 /* Values other than LBR and BTF are vendor-specific,
853 thus reserved and should throw a #GP */
854 return 1;
855 }
856 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
857 __func__, data);
858 break;
859 case MSR_IA32_UCODE_REV:
860 case MSR_IA32_UCODE_WRITE:
861 case MSR_VM_HSAVE_PA:
862 case MSR_AMD64_PATCH_LOADER:
863 break;
864 case 0x200 ... 0x2ff:
865 return set_msr_mtrr(vcpu, msr, data);
866 case MSR_IA32_APICBASE:
867 kvm_set_apic_base(vcpu, data);
868 break;
869 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
870 return kvm_x2apic_msr_write(vcpu, msr, data);
871 case MSR_IA32_MISC_ENABLE:
872 vcpu->arch.ia32_misc_enable_msr = data;
873 break;
874 case MSR_KVM_WALL_CLOCK:
875 vcpu->kvm->arch.wall_clock = data;
876 kvm_write_wall_clock(vcpu->kvm, data);
877 break;
878 case MSR_KVM_SYSTEM_TIME: {
879 if (vcpu->arch.time_page) {
880 kvm_release_page_dirty(vcpu->arch.time_page);
881 vcpu->arch.time_page = NULL;
882 }
883
884 vcpu->arch.time = data;
885
886 /* we verify if the enable bit is set... */
887 if (!(data & 1))
888 break;
889
890 /* ...but clean it before doing the actual write */
891 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
892
893 vcpu->arch.time_page =
894 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
895
896 if (is_error_page(vcpu->arch.time_page)) {
897 kvm_release_page_clean(vcpu->arch.time_page);
898 vcpu->arch.time_page = NULL;
899 }
900
901 kvm_request_guest_time_update(vcpu);
902 break;
903 }
904 case MSR_IA32_MCG_CTL:
905 case MSR_IA32_MCG_STATUS:
906 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
907 return set_msr_mce(vcpu, msr, data);
908
909 /* Performance counters are not protected by a CPUID bit,
910 * so we should check all of them in the generic path for the sake of
911 * cross vendor migration.
912 * Writing a zero into the event select MSRs disables them,
913 * which we perfectly emulate ;-). Any other value should be at least
914 * reported, some guests depend on them.
915 */
916 case MSR_P6_EVNTSEL0:
917 case MSR_P6_EVNTSEL1:
918 case MSR_K7_EVNTSEL0:
919 case MSR_K7_EVNTSEL1:
920 case MSR_K7_EVNTSEL2:
921 case MSR_K7_EVNTSEL3:
922 if (data != 0)
923 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
924 "0x%x data 0x%llx\n", msr, data);
925 break;
926 /* at least RHEL 4 unconditionally writes to the perfctr registers,
927 * so we ignore writes to make it happy.
928 */
929 case MSR_P6_PERFCTR0:
930 case MSR_P6_PERFCTR1:
931 case MSR_K7_PERFCTR0:
932 case MSR_K7_PERFCTR1:
933 case MSR_K7_PERFCTR2:
934 case MSR_K7_PERFCTR3:
935 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
936 "0x%x data 0x%llx\n", msr, data);
937 break;
938 default:
939 if (!ignore_msrs) {
940 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
941 msr, data);
942 return 1;
943 } else {
944 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
945 msr, data);
946 break;
947 }
948 }
949 return 0;
950 }
951 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
952
953
954 /*
955 * Reads an msr value (of 'msr_index') into 'pdata'.
956 * Returns 0 on success, non-0 otherwise.
957 * Assumes vcpu_load() was already called.
958 */
959 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
960 {
961 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
962 }
963
964 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
965 {
966 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
967
968 if (!msr_mtrr_valid(msr))
969 return 1;
970
971 if (msr == MSR_MTRRdefType)
972 *pdata = vcpu->arch.mtrr_state.def_type +
973 (vcpu->arch.mtrr_state.enabled << 10);
974 else if (msr == MSR_MTRRfix64K_00000)
975 *pdata = p[0];
976 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
977 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
978 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
979 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
980 else if (msr == MSR_IA32_CR_PAT)
981 *pdata = vcpu->arch.pat;
982 else { /* Variable MTRRs */
983 int idx, is_mtrr_mask;
984 u64 *pt;
985
986 idx = (msr - 0x200) / 2;
987 is_mtrr_mask = msr - 0x200 - 2 * idx;
988 if (!is_mtrr_mask)
989 pt =
990 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
991 else
992 pt =
993 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
994 *pdata = *pt;
995 }
996
997 return 0;
998 }
999
1000 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1001 {
1002 u64 data;
1003 u64 mcg_cap = vcpu->arch.mcg_cap;
1004 unsigned bank_num = mcg_cap & 0xff;
1005
1006 switch (msr) {
1007 case MSR_IA32_P5_MC_ADDR:
1008 case MSR_IA32_P5_MC_TYPE:
1009 data = 0;
1010 break;
1011 case MSR_IA32_MCG_CAP:
1012 data = vcpu->arch.mcg_cap;
1013 break;
1014 case MSR_IA32_MCG_CTL:
1015 if (!(mcg_cap & MCG_CTL_P))
1016 return 1;
1017 data = vcpu->arch.mcg_ctl;
1018 break;
1019 case MSR_IA32_MCG_STATUS:
1020 data = vcpu->arch.mcg_status;
1021 break;
1022 default:
1023 if (msr >= MSR_IA32_MC0_CTL &&
1024 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1025 u32 offset = msr - MSR_IA32_MC0_CTL;
1026 data = vcpu->arch.mce_banks[offset];
1027 break;
1028 }
1029 return 1;
1030 }
1031 *pdata = data;
1032 return 0;
1033 }
1034
1035 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1036 {
1037 u64 data;
1038
1039 switch (msr) {
1040 case MSR_IA32_PLATFORM_ID:
1041 case MSR_IA32_UCODE_REV:
1042 case MSR_IA32_EBL_CR_POWERON:
1043 case MSR_IA32_DEBUGCTLMSR:
1044 case MSR_IA32_LASTBRANCHFROMIP:
1045 case MSR_IA32_LASTBRANCHTOIP:
1046 case MSR_IA32_LASTINTFROMIP:
1047 case MSR_IA32_LASTINTTOIP:
1048 case MSR_K8_SYSCFG:
1049 case MSR_K7_HWCR:
1050 case MSR_VM_HSAVE_PA:
1051 case MSR_P6_PERFCTR0:
1052 case MSR_P6_PERFCTR1:
1053 case MSR_P6_EVNTSEL0:
1054 case MSR_P6_EVNTSEL1:
1055 case MSR_K7_EVNTSEL0:
1056 case MSR_K7_PERFCTR0:
1057 case MSR_K8_INT_PENDING_MSG:
1058 case MSR_AMD64_NB_CFG:
1059 case MSR_FAM10H_MMIO_CONF_BASE:
1060 data = 0;
1061 break;
1062 case MSR_MTRRcap:
1063 data = 0x500 | KVM_NR_VAR_MTRR;
1064 break;
1065 case 0x200 ... 0x2ff:
1066 return get_msr_mtrr(vcpu, msr, pdata);
1067 case 0xcd: /* fsb frequency */
1068 data = 3;
1069 break;
1070 case MSR_IA32_APICBASE:
1071 data = kvm_get_apic_base(vcpu);
1072 break;
1073 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1074 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1075 break;
1076 case MSR_IA32_MISC_ENABLE:
1077 data = vcpu->arch.ia32_misc_enable_msr;
1078 break;
1079 case MSR_IA32_PERF_STATUS:
1080 /* TSC increment by tick */
1081 data = 1000ULL;
1082 /* CPU multiplier */
1083 data |= (((uint64_t)4ULL) << 40);
1084 break;
1085 case MSR_EFER:
1086 data = vcpu->arch.shadow_efer;
1087 break;
1088 case MSR_KVM_WALL_CLOCK:
1089 data = vcpu->kvm->arch.wall_clock;
1090 break;
1091 case MSR_KVM_SYSTEM_TIME:
1092 data = vcpu->arch.time;
1093 break;
1094 case MSR_IA32_P5_MC_ADDR:
1095 case MSR_IA32_P5_MC_TYPE:
1096 case MSR_IA32_MCG_CAP:
1097 case MSR_IA32_MCG_CTL:
1098 case MSR_IA32_MCG_STATUS:
1099 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1100 return get_msr_mce(vcpu, msr, pdata);
1101 default:
1102 if (!ignore_msrs) {
1103 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1104 return 1;
1105 } else {
1106 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1107 data = 0;
1108 }
1109 break;
1110 }
1111 *pdata = data;
1112 return 0;
1113 }
1114 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1115
1116 /*
1117 * Read or write a bunch of msrs. All parameters are kernel addresses.
1118 *
1119 * @return number of msrs set successfully.
1120 */
1121 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1122 struct kvm_msr_entry *entries,
1123 int (*do_msr)(struct kvm_vcpu *vcpu,
1124 unsigned index, u64 *data))
1125 {
1126 int i;
1127
1128 vcpu_load(vcpu);
1129
1130 down_read(&vcpu->kvm->slots_lock);
1131 for (i = 0; i < msrs->nmsrs; ++i)
1132 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1133 break;
1134 up_read(&vcpu->kvm->slots_lock);
1135
1136 vcpu_put(vcpu);
1137
1138 return i;
1139 }
1140
1141 /*
1142 * Read or write a bunch of msrs. Parameters are user addresses.
1143 *
1144 * @return number of msrs set successfully.
1145 */
1146 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1147 int (*do_msr)(struct kvm_vcpu *vcpu,
1148 unsigned index, u64 *data),
1149 int writeback)
1150 {
1151 struct kvm_msrs msrs;
1152 struct kvm_msr_entry *entries;
1153 int r, n;
1154 unsigned size;
1155
1156 r = -EFAULT;
1157 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1158 goto out;
1159
1160 r = -E2BIG;
1161 if (msrs.nmsrs >= MAX_IO_MSRS)
1162 goto out;
1163
1164 r = -ENOMEM;
1165 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1166 entries = vmalloc(size);
1167 if (!entries)
1168 goto out;
1169
1170 r = -EFAULT;
1171 if (copy_from_user(entries, user_msrs->entries, size))
1172 goto out_free;
1173
1174 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1175 if (r < 0)
1176 goto out_free;
1177
1178 r = -EFAULT;
1179 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1180 goto out_free;
1181
1182 r = n;
1183
1184 out_free:
1185 vfree(entries);
1186 out:
1187 return r;
1188 }
1189
1190 int kvm_dev_ioctl_check_extension(long ext)
1191 {
1192 int r;
1193
1194 switch (ext) {
1195 case KVM_CAP_IRQCHIP:
1196 case KVM_CAP_HLT:
1197 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
1198 case KVM_CAP_SET_TSS_ADDR:
1199 case KVM_CAP_EXT_CPUID:
1200 case KVM_CAP_CLOCKSOURCE:
1201 case KVM_CAP_PIT:
1202 case KVM_CAP_NOP_IO_DELAY:
1203 case KVM_CAP_MP_STATE:
1204 case KVM_CAP_SYNC_MMU:
1205 case KVM_CAP_REINJECT_CONTROL:
1206 case KVM_CAP_IRQ_INJECT_STATUS:
1207 case KVM_CAP_ASSIGN_DEV_IRQ:
1208 case KVM_CAP_IRQFD:
1209 case KVM_CAP_IOEVENTFD:
1210 case KVM_CAP_PIT2:
1211 case KVM_CAP_PIT_STATE2:
1212 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
1213 r = 1;
1214 break;
1215 case KVM_CAP_COALESCED_MMIO:
1216 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1217 break;
1218 case KVM_CAP_VAPIC:
1219 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1220 break;
1221 case KVM_CAP_NR_VCPUS:
1222 r = KVM_MAX_VCPUS;
1223 break;
1224 case KVM_CAP_NR_MEMSLOTS:
1225 r = KVM_MEMORY_SLOTS;
1226 break;
1227 case KVM_CAP_PV_MMU:
1228 r = !tdp_enabled;
1229 break;
1230 case KVM_CAP_IOMMU:
1231 r = iommu_found();
1232 break;
1233 case KVM_CAP_MCE:
1234 r = KVM_MAX_MCE_BANKS;
1235 break;
1236 default:
1237 r = 0;
1238 break;
1239 }
1240 return r;
1241
1242 }
1243
1244 long kvm_arch_dev_ioctl(struct file *filp,
1245 unsigned int ioctl, unsigned long arg)
1246 {
1247 void __user *argp = (void __user *)arg;
1248 long r;
1249
1250 switch (ioctl) {
1251 case KVM_GET_MSR_INDEX_LIST: {
1252 struct kvm_msr_list __user *user_msr_list = argp;
1253 struct kvm_msr_list msr_list;
1254 unsigned n;
1255
1256 r = -EFAULT;
1257 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1258 goto out;
1259 n = msr_list.nmsrs;
1260 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1261 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1262 goto out;
1263 r = -E2BIG;
1264 if (n < msr_list.nmsrs)
1265 goto out;
1266 r = -EFAULT;
1267 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1268 num_msrs_to_save * sizeof(u32)))
1269 goto out;
1270 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
1271 &emulated_msrs,
1272 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1273 goto out;
1274 r = 0;
1275 break;
1276 }
1277 case KVM_GET_SUPPORTED_CPUID: {
1278 struct kvm_cpuid2 __user *cpuid_arg = argp;
1279 struct kvm_cpuid2 cpuid;
1280
1281 r = -EFAULT;
1282 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1283 goto out;
1284 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
1285 cpuid_arg->entries);
1286 if (r)
1287 goto out;
1288
1289 r = -EFAULT;
1290 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1291 goto out;
1292 r = 0;
1293 break;
1294 }
1295 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1296 u64 mce_cap;
1297
1298 mce_cap = KVM_MCE_CAP_SUPPORTED;
1299 r = -EFAULT;
1300 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1301 goto out;
1302 r = 0;
1303 break;
1304 }
1305 default:
1306 r = -EINVAL;
1307 }
1308 out:
1309 return r;
1310 }
1311
1312 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1313 {
1314 kvm_x86_ops->vcpu_load(vcpu, cpu);
1315 kvm_request_guest_time_update(vcpu);
1316 }
1317
1318 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1319 {
1320 kvm_x86_ops->vcpu_put(vcpu);
1321 kvm_put_guest_fpu(vcpu);
1322 }
1323
1324 static int is_efer_nx(void)
1325 {
1326 unsigned long long efer = 0;
1327
1328 rdmsrl_safe(MSR_EFER, &efer);
1329 return efer & EFER_NX;
1330 }
1331
1332 static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1333 {
1334 int i;
1335 struct kvm_cpuid_entry2 *e, *entry;
1336
1337 entry = NULL;
1338 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1339 e = &vcpu->arch.cpuid_entries[i];
1340 if (e->function == 0x80000001) {
1341 entry = e;
1342 break;
1343 }
1344 }
1345 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
1346 entry->edx &= ~(1 << 20);
1347 printk(KERN_INFO "kvm: guest NX capability removed\n");
1348 }
1349 }
1350
1351 /* when an old userspace process fills a new kernel module */
1352 static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1353 struct kvm_cpuid *cpuid,
1354 struct kvm_cpuid_entry __user *entries)
1355 {
1356 int r, i;
1357 struct kvm_cpuid_entry *cpuid_entries;
1358
1359 r = -E2BIG;
1360 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1361 goto out;
1362 r = -ENOMEM;
1363 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1364 if (!cpuid_entries)
1365 goto out;
1366 r = -EFAULT;
1367 if (copy_from_user(cpuid_entries, entries,
1368 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1369 goto out_free;
1370 for (i = 0; i < cpuid->nent; i++) {
1371 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1372 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1373 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1374 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1375 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1376 vcpu->arch.cpuid_entries[i].index = 0;
1377 vcpu->arch.cpuid_entries[i].flags = 0;
1378 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1379 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1380 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1381 }
1382 vcpu->arch.cpuid_nent = cpuid->nent;
1383 cpuid_fix_nx_cap(vcpu);
1384 r = 0;
1385 kvm_apic_set_version(vcpu);
1386
1387 out_free:
1388 vfree(cpuid_entries);
1389 out:
1390 return r;
1391 }
1392
1393 static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
1394 struct kvm_cpuid2 *cpuid,
1395 struct kvm_cpuid_entry2 __user *entries)
1396 {
1397 int r;
1398
1399 r = -E2BIG;
1400 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1401 goto out;
1402 r = -EFAULT;
1403 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
1404 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
1405 goto out;
1406 vcpu->arch.cpuid_nent = cpuid->nent;
1407 kvm_apic_set_version(vcpu);
1408 return 0;
1409
1410 out:
1411 return r;
1412 }
1413
1414 static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
1415 struct kvm_cpuid2 *cpuid,
1416 struct kvm_cpuid_entry2 __user *entries)
1417 {
1418 int r;
1419
1420 r = -E2BIG;
1421 if (cpuid->nent < vcpu->arch.cpuid_nent)
1422 goto out;
1423 r = -EFAULT;
1424 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
1425 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
1426 goto out;
1427 return 0;
1428
1429 out:
1430 cpuid->nent = vcpu->arch.cpuid_nent;
1431 return r;
1432 }
1433
1434 static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1435 u32 index)
1436 {
1437 entry->function = function;
1438 entry->index = index;
1439 cpuid_count(entry->function, entry->index,
1440 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
1441 entry->flags = 0;
1442 }
1443
1444 #define F(x) bit(X86_FEATURE_##x)
1445
1446 static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1447 u32 index, int *nent, int maxnent)
1448 {
1449 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
1450 unsigned f_gbpages = kvm_x86_ops->gb_page_enable() ? F(GBPAGES) : 0;
1451 #ifdef CONFIG_X86_64
1452 unsigned f_lm = F(LM);
1453 #else
1454 unsigned f_lm = 0;
1455 #endif
1456
1457 /* cpuid 1.edx */
1458 const u32 kvm_supported_word0_x86_features =
1459 F(FPU) | F(VME) | F(DE) | F(PSE) |
1460 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1461 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1462 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1463 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1464 0 /* Reserved, DS, ACPI */ | F(MMX) |
1465 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1466 0 /* HTT, TM, Reserved, PBE */;
1467 /* cpuid 0x80000001.edx */
1468 const u32 kvm_supported_word1_x86_features =
1469 F(FPU) | F(VME) | F(DE) | F(PSE) |
1470 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1471 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1472 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1473 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1474 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
1475 F(FXSR) | F(FXSR_OPT) | f_gbpages | 0 /* RDTSCP */ |
1476 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1477 /* cpuid 1.ecx */
1478 const u32 kvm_supported_word4_x86_features =
1479 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1480 0 /* DS-CPL, VMX, SMX, EST */ |
1481 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1482 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1483 0 /* Reserved, DCA */ | F(XMM4_1) |
1484 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
1485 0 /* Reserved, XSAVE, OSXSAVE */;
1486 /* cpuid 0x80000001.ecx */
1487 const u32 kvm_supported_word6_x86_features =
1488 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1489 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1490 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1491 0 /* SKINIT */ | 0 /* WDT */;
1492
1493 /* all calls to cpuid_count() should be made on the same cpu */
1494 get_cpu();
1495 do_cpuid_1_ent(entry, function, index);
1496 ++*nent;
1497
1498 switch (function) {
1499 case 0:
1500 entry->eax = min(entry->eax, (u32)0xb);
1501 break;
1502 case 1:
1503 entry->edx &= kvm_supported_word0_x86_features;
1504 entry->ecx &= kvm_supported_word4_x86_features;
1505 /* we support x2apic emulation even if host does not support
1506 * it since we emulate x2apic in software */
1507 entry->ecx |= F(X2APIC);
1508 break;
1509 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1510 * may return different values. This forces us to get_cpu() before
1511 * issuing the first command, and also to emulate this annoying behavior
1512 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1513 case 2: {
1514 int t, times = entry->eax & 0xff;
1515
1516 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1517 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
1518 for (t = 1; t < times && *nent < maxnent; ++t) {
1519 do_cpuid_1_ent(&entry[t], function, 0);
1520 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1521 ++*nent;
1522 }
1523 break;
1524 }
1525 /* function 4 and 0xb have additional index. */
1526 case 4: {
1527 int i, cache_type;
1528
1529 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1530 /* read more entries until cache_type is zero */
1531 for (i = 1; *nent < maxnent; ++i) {
1532 cache_type = entry[i - 1].eax & 0x1f;
1533 if (!cache_type)
1534 break;
1535 do_cpuid_1_ent(&entry[i], function, i);
1536 entry[i].flags |=
1537 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1538 ++*nent;
1539 }
1540 break;
1541 }
1542 case 0xb: {
1543 int i, level_type;
1544
1545 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1546 /* read more entries until level_type is zero */
1547 for (i = 1; *nent < maxnent; ++i) {
1548 level_type = entry[i - 1].ecx & 0xff00;
1549 if (!level_type)
1550 break;
1551 do_cpuid_1_ent(&entry[i], function, i);
1552 entry[i].flags |=
1553 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1554 ++*nent;
1555 }
1556 break;
1557 }
1558 case 0x80000000:
1559 entry->eax = min(entry->eax, 0x8000001a);
1560 break;
1561 case 0x80000001:
1562 entry->edx &= kvm_supported_word1_x86_features;
1563 entry->ecx &= kvm_supported_word6_x86_features;
1564 break;
1565 }
1566 put_cpu();
1567 }
1568
1569 #undef F
1570
1571 static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
1572 struct kvm_cpuid_entry2 __user *entries)
1573 {
1574 struct kvm_cpuid_entry2 *cpuid_entries;
1575 int limit, nent = 0, r = -E2BIG;
1576 u32 func;
1577
1578 if (cpuid->nent < 1)
1579 goto out;
1580 r = -ENOMEM;
1581 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1582 if (!cpuid_entries)
1583 goto out;
1584
1585 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1586 limit = cpuid_entries[0].eax;
1587 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1588 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1589 &nent, cpuid->nent);
1590 r = -E2BIG;
1591 if (nent >= cpuid->nent)
1592 goto out_free;
1593
1594 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1595 limit = cpuid_entries[nent - 1].eax;
1596 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1597 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1598 &nent, cpuid->nent);
1599 r = -E2BIG;
1600 if (nent >= cpuid->nent)
1601 goto out_free;
1602
1603 r = -EFAULT;
1604 if (copy_to_user(entries, cpuid_entries,
1605 nent * sizeof(struct kvm_cpuid_entry2)))
1606 goto out_free;
1607 cpuid->nent = nent;
1608 r = 0;
1609
1610 out_free:
1611 vfree(cpuid_entries);
1612 out:
1613 return r;
1614 }
1615
1616 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1617 struct kvm_lapic_state *s)
1618 {
1619 vcpu_load(vcpu);
1620 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
1621 vcpu_put(vcpu);
1622
1623 return 0;
1624 }
1625
1626 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1627 struct kvm_lapic_state *s)
1628 {
1629 vcpu_load(vcpu);
1630 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1631 kvm_apic_post_state_restore(vcpu);
1632 vcpu_put(vcpu);
1633
1634 return 0;
1635 }
1636
1637 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1638 struct kvm_interrupt *irq)
1639 {
1640 if (irq->irq < 0 || irq->irq >= 256)
1641 return -EINVAL;
1642 if (irqchip_in_kernel(vcpu->kvm))
1643 return -ENXIO;
1644 vcpu_load(vcpu);
1645
1646 kvm_queue_interrupt(vcpu, irq->irq, false);
1647
1648 vcpu_put(vcpu);
1649
1650 return 0;
1651 }
1652
1653 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1654 {
1655 vcpu_load(vcpu);
1656 kvm_inject_nmi(vcpu);
1657 vcpu_put(vcpu);
1658
1659 return 0;
1660 }
1661
1662 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1663 struct kvm_tpr_access_ctl *tac)
1664 {
1665 if (tac->flags)
1666 return -EINVAL;
1667 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1668 return 0;
1669 }
1670
1671 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
1672 u64 mcg_cap)
1673 {
1674 int r;
1675 unsigned bank_num = mcg_cap & 0xff, bank;
1676
1677 r = -EINVAL;
1678 if (!bank_num)
1679 goto out;
1680 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
1681 goto out;
1682 r = 0;
1683 vcpu->arch.mcg_cap = mcg_cap;
1684 /* Init IA32_MCG_CTL to all 1s */
1685 if (mcg_cap & MCG_CTL_P)
1686 vcpu->arch.mcg_ctl = ~(u64)0;
1687 /* Init IA32_MCi_CTL to all 1s */
1688 for (bank = 0; bank < bank_num; bank++)
1689 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
1690 out:
1691 return r;
1692 }
1693
1694 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
1695 struct kvm_x86_mce *mce)
1696 {
1697 u64 mcg_cap = vcpu->arch.mcg_cap;
1698 unsigned bank_num = mcg_cap & 0xff;
1699 u64 *banks = vcpu->arch.mce_banks;
1700
1701 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
1702 return -EINVAL;
1703 /*
1704 * if IA32_MCG_CTL is not all 1s, the uncorrected error
1705 * reporting is disabled
1706 */
1707 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
1708 vcpu->arch.mcg_ctl != ~(u64)0)
1709 return 0;
1710 banks += 4 * mce->bank;
1711 /*
1712 * if IA32_MCi_CTL is not all 1s, the uncorrected error
1713 * reporting is disabled for the bank
1714 */
1715 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
1716 return 0;
1717 if (mce->status & MCI_STATUS_UC) {
1718 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
1719 !(vcpu->arch.cr4 & X86_CR4_MCE)) {
1720 printk(KERN_DEBUG "kvm: set_mce: "
1721 "injects mce exception while "
1722 "previous one is in progress!\n");
1723 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1724 return 0;
1725 }
1726 if (banks[1] & MCI_STATUS_VAL)
1727 mce->status |= MCI_STATUS_OVER;
1728 banks[2] = mce->addr;
1729 banks[3] = mce->misc;
1730 vcpu->arch.mcg_status = mce->mcg_status;
1731 banks[1] = mce->status;
1732 kvm_queue_exception(vcpu, MC_VECTOR);
1733 } else if (!(banks[1] & MCI_STATUS_VAL)
1734 || !(banks[1] & MCI_STATUS_UC)) {
1735 if (banks[1] & MCI_STATUS_VAL)
1736 mce->status |= MCI_STATUS_OVER;
1737 banks[2] = mce->addr;
1738 banks[3] = mce->misc;
1739 banks[1] = mce->status;
1740 } else
1741 banks[1] |= MCI_STATUS_OVER;
1742 return 0;
1743 }
1744
1745 long kvm_arch_vcpu_ioctl(struct file *filp,
1746 unsigned int ioctl, unsigned long arg)
1747 {
1748 struct kvm_vcpu *vcpu = filp->private_data;
1749 void __user *argp = (void __user *)arg;
1750 int r;
1751 struct kvm_lapic_state *lapic = NULL;
1752
1753 switch (ioctl) {
1754 case KVM_GET_LAPIC: {
1755 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1756
1757 r = -ENOMEM;
1758 if (!lapic)
1759 goto out;
1760 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
1761 if (r)
1762 goto out;
1763 r = -EFAULT;
1764 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
1765 goto out;
1766 r = 0;
1767 break;
1768 }
1769 case KVM_SET_LAPIC: {
1770 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1771 r = -ENOMEM;
1772 if (!lapic)
1773 goto out;
1774 r = -EFAULT;
1775 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
1776 goto out;
1777 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
1778 if (r)
1779 goto out;
1780 r = 0;
1781 break;
1782 }
1783 case KVM_INTERRUPT: {
1784 struct kvm_interrupt irq;
1785
1786 r = -EFAULT;
1787 if (copy_from_user(&irq, argp, sizeof irq))
1788 goto out;
1789 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1790 if (r)
1791 goto out;
1792 r = 0;
1793 break;
1794 }
1795 case KVM_NMI: {
1796 r = kvm_vcpu_ioctl_nmi(vcpu);
1797 if (r)
1798 goto out;
1799 r = 0;
1800 break;
1801 }
1802 case KVM_SET_CPUID: {
1803 struct kvm_cpuid __user *cpuid_arg = argp;
1804 struct kvm_cpuid cpuid;
1805
1806 r = -EFAULT;
1807 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1808 goto out;
1809 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1810 if (r)
1811 goto out;
1812 break;
1813 }
1814 case KVM_SET_CPUID2: {
1815 struct kvm_cpuid2 __user *cpuid_arg = argp;
1816 struct kvm_cpuid2 cpuid;
1817
1818 r = -EFAULT;
1819 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1820 goto out;
1821 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
1822 cpuid_arg->entries);
1823 if (r)
1824 goto out;
1825 break;
1826 }
1827 case KVM_GET_CPUID2: {
1828 struct kvm_cpuid2 __user *cpuid_arg = argp;
1829 struct kvm_cpuid2 cpuid;
1830
1831 r = -EFAULT;
1832 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1833 goto out;
1834 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
1835 cpuid_arg->entries);
1836 if (r)
1837 goto out;
1838 r = -EFAULT;
1839 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1840 goto out;
1841 r = 0;
1842 break;
1843 }
1844 case KVM_GET_MSRS:
1845 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1846 break;
1847 case KVM_SET_MSRS:
1848 r = msr_io(vcpu, argp, do_set_msr, 0);
1849 break;
1850 case KVM_TPR_ACCESS_REPORTING: {
1851 struct kvm_tpr_access_ctl tac;
1852
1853 r = -EFAULT;
1854 if (copy_from_user(&tac, argp, sizeof tac))
1855 goto out;
1856 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1857 if (r)
1858 goto out;
1859 r = -EFAULT;
1860 if (copy_to_user(argp, &tac, sizeof tac))
1861 goto out;
1862 r = 0;
1863 break;
1864 };
1865 case KVM_SET_VAPIC_ADDR: {
1866 struct kvm_vapic_addr va;
1867
1868 r = -EINVAL;
1869 if (!irqchip_in_kernel(vcpu->kvm))
1870 goto out;
1871 r = -EFAULT;
1872 if (copy_from_user(&va, argp, sizeof va))
1873 goto out;
1874 r = 0;
1875 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1876 break;
1877 }
1878 case KVM_X86_SETUP_MCE: {
1879 u64 mcg_cap;
1880
1881 r = -EFAULT;
1882 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
1883 goto out;
1884 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
1885 break;
1886 }
1887 case KVM_X86_SET_MCE: {
1888 struct kvm_x86_mce mce;
1889
1890 r = -EFAULT;
1891 if (copy_from_user(&mce, argp, sizeof mce))
1892 goto out;
1893 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
1894 break;
1895 }
1896 default:
1897 r = -EINVAL;
1898 }
1899 out:
1900 kfree(lapic);
1901 return r;
1902 }
1903
1904 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1905 {
1906 int ret;
1907
1908 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1909 return -1;
1910 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1911 return ret;
1912 }
1913
1914 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
1915 u64 ident_addr)
1916 {
1917 kvm->arch.ept_identity_map_addr = ident_addr;
1918 return 0;
1919 }
1920
1921 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1922 u32 kvm_nr_mmu_pages)
1923 {
1924 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1925 return -EINVAL;
1926
1927 down_write(&kvm->slots_lock);
1928 spin_lock(&kvm->mmu_lock);
1929
1930 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
1931 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1932
1933 spin_unlock(&kvm->mmu_lock);
1934 up_write(&kvm->slots_lock);
1935 return 0;
1936 }
1937
1938 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1939 {
1940 return kvm->arch.n_alloc_mmu_pages;
1941 }
1942
1943 gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1944 {
1945 int i;
1946 struct kvm_mem_alias *alias;
1947
1948 for (i = 0; i < kvm->arch.naliases; ++i) {
1949 alias = &kvm->arch.aliases[i];
1950 if (gfn >= alias->base_gfn
1951 && gfn < alias->base_gfn + alias->npages)
1952 return alias->target_gfn + gfn - alias->base_gfn;
1953 }
1954 return gfn;
1955 }
1956
1957 /*
1958 * Set a new alias region. Aliases map a portion of physical memory into
1959 * another portion. This is useful for memory windows, for example the PC
1960 * VGA region.
1961 */
1962 static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1963 struct kvm_memory_alias *alias)
1964 {
1965 int r, n;
1966 struct kvm_mem_alias *p;
1967
1968 r = -EINVAL;
1969 /* General sanity checks */
1970 if (alias->memory_size & (PAGE_SIZE - 1))
1971 goto out;
1972 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1973 goto out;
1974 if (alias->slot >= KVM_ALIAS_SLOTS)
1975 goto out;
1976 if (alias->guest_phys_addr + alias->memory_size
1977 < alias->guest_phys_addr)
1978 goto out;
1979 if (alias->target_phys_addr + alias->memory_size
1980 < alias->target_phys_addr)
1981 goto out;
1982
1983 down_write(&kvm->slots_lock);
1984 spin_lock(&kvm->mmu_lock);
1985
1986 p = &kvm->arch.aliases[alias->slot];
1987 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1988 p->npages = alias->memory_size >> PAGE_SHIFT;
1989 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1990
1991 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
1992 if (kvm->arch.aliases[n - 1].npages)
1993 break;
1994 kvm->arch.naliases = n;
1995
1996 spin_unlock(&kvm->mmu_lock);
1997 kvm_mmu_zap_all(kvm);
1998
1999 up_write(&kvm->slots_lock);
2000
2001 return 0;
2002
2003 out:
2004 return r;
2005 }
2006
2007 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2008 {
2009 int r;
2010
2011 r = 0;
2012 switch (chip->chip_id) {
2013 case KVM_IRQCHIP_PIC_MASTER:
2014 memcpy(&chip->chip.pic,
2015 &pic_irqchip(kvm)->pics[0],
2016 sizeof(struct kvm_pic_state));
2017 break;
2018 case KVM_IRQCHIP_PIC_SLAVE:
2019 memcpy(&chip->chip.pic,
2020 &pic_irqchip(kvm)->pics[1],
2021 sizeof(struct kvm_pic_state));
2022 break;
2023 case KVM_IRQCHIP_IOAPIC:
2024 memcpy(&chip->chip.ioapic,
2025 ioapic_irqchip(kvm),
2026 sizeof(struct kvm_ioapic_state));
2027 break;
2028 default:
2029 r = -EINVAL;
2030 break;
2031 }
2032 return r;
2033 }
2034
2035 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2036 {
2037 int r;
2038
2039 r = 0;
2040 switch (chip->chip_id) {
2041 case KVM_IRQCHIP_PIC_MASTER:
2042 spin_lock(&pic_irqchip(kvm)->lock);
2043 memcpy(&pic_irqchip(kvm)->pics[0],
2044 &chip->chip.pic,
2045 sizeof(struct kvm_pic_state));
2046 spin_unlock(&pic_irqchip(kvm)->lock);
2047 break;
2048 case KVM_IRQCHIP_PIC_SLAVE:
2049 spin_lock(&pic_irqchip(kvm)->lock);
2050 memcpy(&pic_irqchip(kvm)->pics[1],
2051 &chip->chip.pic,
2052 sizeof(struct kvm_pic_state));
2053 spin_unlock(&pic_irqchip(kvm)->lock);
2054 break;
2055 case KVM_IRQCHIP_IOAPIC:
2056 mutex_lock(&kvm->irq_lock);
2057 memcpy(ioapic_irqchip(kvm),
2058 &chip->chip.ioapic,
2059 sizeof(struct kvm_ioapic_state));
2060 mutex_unlock(&kvm->irq_lock);
2061 break;
2062 default:
2063 r = -EINVAL;
2064 break;
2065 }
2066 kvm_pic_update_irq(pic_irqchip(kvm));
2067 return r;
2068 }
2069
2070 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2071 {
2072 int r = 0;
2073
2074 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2075 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
2076 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2077 return r;
2078 }
2079
2080 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2081 {
2082 int r = 0;
2083
2084 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2085 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
2086 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2087 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2088 return r;
2089 }
2090
2091 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2092 {
2093 int r = 0;
2094
2095 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2096 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2097 sizeof(ps->channels));
2098 ps->flags = kvm->arch.vpit->pit_state.flags;
2099 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2100 return r;
2101 }
2102
2103 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2104 {
2105 int r = 0, start = 0;
2106 u32 prev_legacy, cur_legacy;
2107 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2108 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2109 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2110 if (!prev_legacy && cur_legacy)
2111 start = 1;
2112 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2113 sizeof(kvm->arch.vpit->pit_state.channels));
2114 kvm->arch.vpit->pit_state.flags = ps->flags;
2115 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
2116 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2117 return r;
2118 }
2119
2120 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2121 struct kvm_reinject_control *control)
2122 {
2123 if (!kvm->arch.vpit)
2124 return -ENXIO;
2125 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2126 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
2127 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2128 return 0;
2129 }
2130
2131 /*
2132 * Get (and clear) the dirty memory log for a memory slot.
2133 */
2134 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2135 struct kvm_dirty_log *log)
2136 {
2137 int r;
2138 int n;
2139 struct kvm_memory_slot *memslot;
2140 int is_dirty = 0;
2141
2142 down_write(&kvm->slots_lock);
2143
2144 r = kvm_get_dirty_log(kvm, log, &is_dirty);
2145 if (r)
2146 goto out;
2147
2148 /* If nothing is dirty, don't bother messing with page tables. */
2149 if (is_dirty) {
2150 spin_lock(&kvm->mmu_lock);
2151 kvm_mmu_slot_remove_write_access(kvm, log->slot);
2152 spin_unlock(&kvm->mmu_lock);
2153 kvm_flush_remote_tlbs(kvm);
2154 memslot = &kvm->memslots[log->slot];
2155 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2156 memset(memslot->dirty_bitmap, 0, n);
2157 }
2158 r = 0;
2159 out:
2160 up_write(&kvm->slots_lock);
2161 return r;
2162 }
2163
2164 long kvm_arch_vm_ioctl(struct file *filp,
2165 unsigned int ioctl, unsigned long arg)
2166 {
2167 struct kvm *kvm = filp->private_data;
2168 void __user *argp = (void __user *)arg;
2169 int r = -EINVAL;
2170 /*
2171 * This union makes it completely explicit to gcc-3.x
2172 * that these two variables' stack usage should be
2173 * combined, not added together.
2174 */
2175 union {
2176 struct kvm_pit_state ps;
2177 struct kvm_pit_state2 ps2;
2178 struct kvm_memory_alias alias;
2179 struct kvm_pit_config pit_config;
2180 } u;
2181
2182 switch (ioctl) {
2183 case KVM_SET_TSS_ADDR:
2184 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2185 if (r < 0)
2186 goto out;
2187 break;
2188 case KVM_SET_IDENTITY_MAP_ADDR: {
2189 u64 ident_addr;
2190
2191 r = -EFAULT;
2192 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2193 goto out;
2194 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2195 if (r < 0)
2196 goto out;
2197 break;
2198 }
2199 case KVM_SET_MEMORY_REGION: {
2200 struct kvm_memory_region kvm_mem;
2201 struct kvm_userspace_memory_region kvm_userspace_mem;
2202
2203 r = -EFAULT;
2204 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2205 goto out;
2206 kvm_userspace_mem.slot = kvm_mem.slot;
2207 kvm_userspace_mem.flags = kvm_mem.flags;
2208 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2209 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2210 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2211 if (r)
2212 goto out;
2213 break;
2214 }
2215 case KVM_SET_NR_MMU_PAGES:
2216 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2217 if (r)
2218 goto out;
2219 break;
2220 case KVM_GET_NR_MMU_PAGES:
2221 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2222 break;
2223 case KVM_SET_MEMORY_ALIAS:
2224 r = -EFAULT;
2225 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
2226 goto out;
2227 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
2228 if (r)
2229 goto out;
2230 break;
2231 case KVM_CREATE_IRQCHIP:
2232 r = -ENOMEM;
2233 kvm->arch.vpic = kvm_create_pic(kvm);
2234 if (kvm->arch.vpic) {
2235 r = kvm_ioapic_init(kvm);
2236 if (r) {
2237 kfree(kvm->arch.vpic);
2238 kvm->arch.vpic = NULL;
2239 goto out;
2240 }
2241 } else
2242 goto out;
2243 r = kvm_setup_default_irq_routing(kvm);
2244 if (r) {
2245 kfree(kvm->arch.vpic);
2246 kfree(kvm->arch.vioapic);
2247 goto out;
2248 }
2249 break;
2250 case KVM_CREATE_PIT:
2251 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2252 goto create_pit;
2253 case KVM_CREATE_PIT2:
2254 r = -EFAULT;
2255 if (copy_from_user(&u.pit_config, argp,
2256 sizeof(struct kvm_pit_config)))
2257 goto out;
2258 create_pit:
2259 down_write(&kvm->slots_lock);
2260 r = -EEXIST;
2261 if (kvm->arch.vpit)
2262 goto create_pit_unlock;
2263 r = -ENOMEM;
2264 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
2265 if (kvm->arch.vpit)
2266 r = 0;
2267 create_pit_unlock:
2268 up_write(&kvm->slots_lock);
2269 break;
2270 case KVM_IRQ_LINE_STATUS:
2271 case KVM_IRQ_LINE: {
2272 struct kvm_irq_level irq_event;
2273
2274 r = -EFAULT;
2275 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2276 goto out;
2277 if (irqchip_in_kernel(kvm)) {
2278 __s32 status;
2279 mutex_lock(&kvm->irq_lock);
2280 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2281 irq_event.irq, irq_event.level);
2282 mutex_unlock(&kvm->irq_lock);
2283 if (ioctl == KVM_IRQ_LINE_STATUS) {
2284 irq_event.status = status;
2285 if (copy_to_user(argp, &irq_event,
2286 sizeof irq_event))
2287 goto out;
2288 }
2289 r = 0;
2290 }
2291 break;
2292 }
2293 case KVM_GET_IRQCHIP: {
2294 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
2295 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
2296
2297 r = -ENOMEM;
2298 if (!chip)
2299 goto out;
2300 r = -EFAULT;
2301 if (copy_from_user(chip, argp, sizeof *chip))
2302 goto get_irqchip_out;
2303 r = -ENXIO;
2304 if (!irqchip_in_kernel(kvm))
2305 goto get_irqchip_out;
2306 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
2307 if (r)
2308 goto get_irqchip_out;
2309 r = -EFAULT;
2310 if (copy_to_user(argp, chip, sizeof *chip))
2311 goto get_irqchip_out;
2312 r = 0;
2313 get_irqchip_out:
2314 kfree(chip);
2315 if (r)
2316 goto out;
2317 break;
2318 }
2319 case KVM_SET_IRQCHIP: {
2320 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
2321 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
2322
2323 r = -ENOMEM;
2324 if (!chip)
2325 goto out;
2326 r = -EFAULT;
2327 if (copy_from_user(chip, argp, sizeof *chip))
2328 goto set_irqchip_out;
2329 r = -ENXIO;
2330 if (!irqchip_in_kernel(kvm))
2331 goto set_irqchip_out;
2332 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
2333 if (r)
2334 goto set_irqchip_out;
2335 r = 0;
2336 set_irqchip_out:
2337 kfree(chip);
2338 if (r)
2339 goto out;
2340 break;
2341 }
2342 case KVM_GET_PIT: {
2343 r = -EFAULT;
2344 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
2345 goto out;
2346 r = -ENXIO;
2347 if (!kvm->arch.vpit)
2348 goto out;
2349 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
2350 if (r)
2351 goto out;
2352 r = -EFAULT;
2353 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
2354 goto out;
2355 r = 0;
2356 break;
2357 }
2358 case KVM_SET_PIT: {
2359 r = -EFAULT;
2360 if (copy_from_user(&u.ps, argp, sizeof u.ps))
2361 goto out;
2362 r = -ENXIO;
2363 if (!kvm->arch.vpit)
2364 goto out;
2365 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
2366 if (r)
2367 goto out;
2368 r = 0;
2369 break;
2370 }
2371 case KVM_GET_PIT2: {
2372 r = -ENXIO;
2373 if (!kvm->arch.vpit)
2374 goto out;
2375 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
2376 if (r)
2377 goto out;
2378 r = -EFAULT;
2379 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
2380 goto out;
2381 r = 0;
2382 break;
2383 }
2384 case KVM_SET_PIT2: {
2385 r = -EFAULT;
2386 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
2387 goto out;
2388 r = -ENXIO;
2389 if (!kvm->arch.vpit)
2390 goto out;
2391 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
2392 if (r)
2393 goto out;
2394 r = 0;
2395 break;
2396 }
2397 case KVM_REINJECT_CONTROL: {
2398 struct kvm_reinject_control control;
2399 r = -EFAULT;
2400 if (copy_from_user(&control, argp, sizeof(control)))
2401 goto out;
2402 r = kvm_vm_ioctl_reinject(kvm, &control);
2403 if (r)
2404 goto out;
2405 r = 0;
2406 break;
2407 }
2408 default:
2409 ;
2410 }
2411 out:
2412 return r;
2413 }
2414
2415 static void kvm_init_msr_list(void)
2416 {
2417 u32 dummy[2];
2418 unsigned i, j;
2419
2420 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
2421 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2422 continue;
2423 if (j < i)
2424 msrs_to_save[j] = msrs_to_save[i];
2425 j++;
2426 }
2427 num_msrs_to_save = j;
2428 }
2429
2430 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
2431 const void *v)
2432 {
2433 if (vcpu->arch.apic &&
2434 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
2435 return 0;
2436
2437 return kvm_io_bus_write(&vcpu->kvm->mmio_bus, addr, len, v);
2438 }
2439
2440 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
2441 {
2442 if (vcpu->arch.apic &&
2443 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
2444 return 0;
2445
2446 return kvm_io_bus_read(&vcpu->kvm->mmio_bus, addr, len, v);
2447 }
2448
2449 static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2450 struct kvm_vcpu *vcpu)
2451 {
2452 void *data = val;
2453 int r = X86EMUL_CONTINUE;
2454
2455 while (bytes) {
2456 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2457 unsigned offset = addr & (PAGE_SIZE-1);
2458 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
2459 int ret;
2460
2461 if (gpa == UNMAPPED_GVA) {
2462 r = X86EMUL_PROPAGATE_FAULT;
2463 goto out;
2464 }
2465 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
2466 if (ret < 0) {
2467 r = X86EMUL_UNHANDLEABLE;
2468 goto out;
2469 }
2470
2471 bytes -= toread;
2472 data += toread;
2473 addr += toread;
2474 }
2475 out:
2476 return r;
2477 }
2478
2479 static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2480 struct kvm_vcpu *vcpu)
2481 {
2482 void *data = val;
2483 int r = X86EMUL_CONTINUE;
2484
2485 while (bytes) {
2486 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2487 unsigned offset = addr & (PAGE_SIZE-1);
2488 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2489 int ret;
2490
2491 if (gpa == UNMAPPED_GVA) {
2492 r = X86EMUL_PROPAGATE_FAULT;
2493 goto out;
2494 }
2495 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2496 if (ret < 0) {
2497 r = X86EMUL_UNHANDLEABLE;
2498 goto out;
2499 }
2500
2501 bytes -= towrite;
2502 data += towrite;
2503 addr += towrite;
2504 }
2505 out:
2506 return r;
2507 }
2508
2509
2510 static int emulator_read_emulated(unsigned long addr,
2511 void *val,
2512 unsigned int bytes,
2513 struct kvm_vcpu *vcpu)
2514 {
2515 gpa_t gpa;
2516
2517 if (vcpu->mmio_read_completed) {
2518 memcpy(val, vcpu->mmio_data, bytes);
2519 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
2520 vcpu->mmio_phys_addr, *(u64 *)val);
2521 vcpu->mmio_read_completed = 0;
2522 return X86EMUL_CONTINUE;
2523 }
2524
2525 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2526
2527 /* For APIC access vmexit */
2528 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2529 goto mmio;
2530
2531 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2532 == X86EMUL_CONTINUE)
2533 return X86EMUL_CONTINUE;
2534 if (gpa == UNMAPPED_GVA)
2535 return X86EMUL_PROPAGATE_FAULT;
2536
2537 mmio:
2538 /*
2539 * Is this MMIO handled locally?
2540 */
2541 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
2542 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
2543 return X86EMUL_CONTINUE;
2544 }
2545
2546 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
2547
2548 vcpu->mmio_needed = 1;
2549 vcpu->mmio_phys_addr = gpa;
2550 vcpu->mmio_size = bytes;
2551 vcpu->mmio_is_write = 0;
2552
2553 return X86EMUL_UNHANDLEABLE;
2554 }
2555
2556 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
2557 const void *val, int bytes)
2558 {
2559 int ret;
2560
2561 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
2562 if (ret < 0)
2563 return 0;
2564 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
2565 return 1;
2566 }
2567
2568 static int emulator_write_emulated_onepage(unsigned long addr,
2569 const void *val,
2570 unsigned int bytes,
2571 struct kvm_vcpu *vcpu)
2572 {
2573 gpa_t gpa;
2574
2575 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2576
2577 if (gpa == UNMAPPED_GVA) {
2578 kvm_inject_page_fault(vcpu, addr, 2);
2579 return X86EMUL_PROPAGATE_FAULT;
2580 }
2581
2582 /* For APIC access vmexit */
2583 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2584 goto mmio;
2585
2586 if (emulator_write_phys(vcpu, gpa, val, bytes))
2587 return X86EMUL_CONTINUE;
2588
2589 mmio:
2590 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
2591 /*
2592 * Is this MMIO handled locally?
2593 */
2594 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
2595 return X86EMUL_CONTINUE;
2596
2597 vcpu->mmio_needed = 1;
2598 vcpu->mmio_phys_addr = gpa;
2599 vcpu->mmio_size = bytes;
2600 vcpu->mmio_is_write = 1;
2601 memcpy(vcpu->mmio_data, val, bytes);
2602
2603 return X86EMUL_CONTINUE;
2604 }
2605
2606 int emulator_write_emulated(unsigned long addr,
2607 const void *val,
2608 unsigned int bytes,
2609 struct kvm_vcpu *vcpu)
2610 {
2611 /* Crossing a page boundary? */
2612 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2613 int rc, now;
2614
2615 now = -addr & ~PAGE_MASK;
2616 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2617 if (rc != X86EMUL_CONTINUE)
2618 return rc;
2619 addr += now;
2620 val += now;
2621 bytes -= now;
2622 }
2623 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2624 }
2625 EXPORT_SYMBOL_GPL(emulator_write_emulated);
2626
2627 static int emulator_cmpxchg_emulated(unsigned long addr,
2628 const void *old,
2629 const void *new,
2630 unsigned int bytes,
2631 struct kvm_vcpu *vcpu)
2632 {
2633 static int reported;
2634
2635 if (!reported) {
2636 reported = 1;
2637 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2638 }
2639 #ifndef CONFIG_X86_64
2640 /* guests cmpxchg8b have to be emulated atomically */
2641 if (bytes == 8) {
2642 gpa_t gpa;
2643 struct page *page;
2644 char *kaddr;
2645 u64 val;
2646
2647 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2648
2649 if (gpa == UNMAPPED_GVA ||
2650 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2651 goto emul_write;
2652
2653 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2654 goto emul_write;
2655
2656 val = *(u64 *)new;
2657
2658 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
2659
2660 kaddr = kmap_atomic(page, KM_USER0);
2661 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2662 kunmap_atomic(kaddr, KM_USER0);
2663 kvm_release_page_dirty(page);
2664 }
2665 emul_write:
2666 #endif
2667
2668 return emulator_write_emulated(addr, new, bytes, vcpu);
2669 }
2670
2671 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2672 {
2673 return kvm_x86_ops->get_segment_base(vcpu, seg);
2674 }
2675
2676 int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2677 {
2678 kvm_mmu_invlpg(vcpu, address);
2679 return X86EMUL_CONTINUE;
2680 }
2681
2682 int emulate_clts(struct kvm_vcpu *vcpu)
2683 {
2684 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
2685 return X86EMUL_CONTINUE;
2686 }
2687
2688 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2689 {
2690 struct kvm_vcpu *vcpu = ctxt->vcpu;
2691
2692 switch (dr) {
2693 case 0 ... 3:
2694 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2695 return X86EMUL_CONTINUE;
2696 default:
2697 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
2698 return X86EMUL_UNHANDLEABLE;
2699 }
2700 }
2701
2702 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2703 {
2704 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2705 int exception;
2706
2707 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2708 if (exception) {
2709 /* FIXME: better handling */
2710 return X86EMUL_UNHANDLEABLE;
2711 }
2712 return X86EMUL_CONTINUE;
2713 }
2714
2715 void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2716 {
2717 u8 opcodes[4];
2718 unsigned long rip = kvm_rip_read(vcpu);
2719 unsigned long rip_linear;
2720
2721 if (!printk_ratelimit())
2722 return;
2723
2724 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2725
2726 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
2727
2728 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2729 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
2730 }
2731 EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2732
2733 static struct x86_emulate_ops emulate_ops = {
2734 .read_std = kvm_read_guest_virt,
2735 .read_emulated = emulator_read_emulated,
2736 .write_emulated = emulator_write_emulated,
2737 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2738 };
2739
2740 static void cache_all_regs(struct kvm_vcpu *vcpu)
2741 {
2742 kvm_register_read(vcpu, VCPU_REGS_RAX);
2743 kvm_register_read(vcpu, VCPU_REGS_RSP);
2744 kvm_register_read(vcpu, VCPU_REGS_RIP);
2745 vcpu->arch.regs_dirty = ~0;
2746 }
2747
2748 int emulate_instruction(struct kvm_vcpu *vcpu,
2749 struct kvm_run *run,
2750 unsigned long cr2,
2751 u16 error_code,
2752 int emulation_type)
2753 {
2754 int r, shadow_mask;
2755 struct decode_cache *c;
2756
2757 kvm_clear_exception_queue(vcpu);
2758 vcpu->arch.mmio_fault_cr2 = cr2;
2759 /*
2760 * TODO: fix x86_emulate.c to use guest_read/write_register
2761 * instead of direct ->regs accesses, can save hundred cycles
2762 * on Intel for instructions that don't read/change RSP, for
2763 * for example.
2764 */
2765 cache_all_regs(vcpu);
2766
2767 vcpu->mmio_is_write = 0;
2768 vcpu->arch.pio.string = 0;
2769
2770 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
2771 int cs_db, cs_l;
2772 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2773
2774 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2775 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2776 vcpu->arch.emulate_ctxt.mode =
2777 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
2778 ? X86EMUL_MODE_REAL : cs_l
2779 ? X86EMUL_MODE_PROT64 : cs_db
2780 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2781
2782 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
2783
2784 /* Only allow emulation of specific instructions on #UD
2785 * (namely VMMCALL, sysenter, sysexit, syscall)*/
2786 c = &vcpu->arch.emulate_ctxt.decode;
2787 if (emulation_type & EMULTYPE_TRAP_UD) {
2788 if (!c->twobyte)
2789 return EMULATE_FAIL;
2790 switch (c->b) {
2791 case 0x01: /* VMMCALL */
2792 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2793 return EMULATE_FAIL;
2794 break;
2795 case 0x34: /* sysenter */
2796 case 0x35: /* sysexit */
2797 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2798 return EMULATE_FAIL;
2799 break;
2800 case 0x05: /* syscall */
2801 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2802 return EMULATE_FAIL;
2803 break;
2804 default:
2805 return EMULATE_FAIL;
2806 }
2807
2808 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
2809 return EMULATE_FAIL;
2810 }
2811
2812 ++vcpu->stat.insn_emulation;
2813 if (r) {
2814 ++vcpu->stat.insn_emulation_fail;
2815 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2816 return EMULATE_DONE;
2817 return EMULATE_FAIL;
2818 }
2819 }
2820
2821 if (emulation_type & EMULTYPE_SKIP) {
2822 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
2823 return EMULATE_DONE;
2824 }
2825
2826 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
2827 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
2828
2829 if (r == 0)
2830 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
2831
2832 if (vcpu->arch.pio.string)
2833 return EMULATE_DO_MMIO;
2834
2835 if ((r || vcpu->mmio_is_write) && run) {
2836 run->exit_reason = KVM_EXIT_MMIO;
2837 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2838 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2839 run->mmio.len = vcpu->mmio_size;
2840 run->mmio.is_write = vcpu->mmio_is_write;
2841 }
2842
2843 if (r) {
2844 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2845 return EMULATE_DONE;
2846 if (!vcpu->mmio_needed) {
2847 kvm_report_emulation_failure(vcpu, "mmio");
2848 return EMULATE_FAIL;
2849 }
2850 return EMULATE_DO_MMIO;
2851 }
2852
2853 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
2854
2855 if (vcpu->mmio_is_write) {
2856 vcpu->mmio_needed = 0;
2857 return EMULATE_DO_MMIO;
2858 }
2859
2860 return EMULATE_DONE;
2861 }
2862 EXPORT_SYMBOL_GPL(emulate_instruction);
2863
2864 static int pio_copy_data(struct kvm_vcpu *vcpu)
2865 {
2866 void *p = vcpu->arch.pio_data;
2867 gva_t q = vcpu->arch.pio.guest_gva;
2868 unsigned bytes;
2869 int ret;
2870
2871 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2872 if (vcpu->arch.pio.in)
2873 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
2874 else
2875 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
2876 return ret;
2877 }
2878
2879 int complete_pio(struct kvm_vcpu *vcpu)
2880 {
2881 struct kvm_pio_request *io = &vcpu->arch.pio;
2882 long delta;
2883 int r;
2884 unsigned long val;
2885
2886 if (!io->string) {
2887 if (io->in) {
2888 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2889 memcpy(&val, vcpu->arch.pio_data, io->size);
2890 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2891 }
2892 } else {
2893 if (io->in) {
2894 r = pio_copy_data(vcpu);
2895 if (r)
2896 return r;
2897 }
2898
2899 delta = 1;
2900 if (io->rep) {
2901 delta *= io->cur_count;
2902 /*
2903 * The size of the register should really depend on
2904 * current address size.
2905 */
2906 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2907 val -= delta;
2908 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
2909 }
2910 if (io->down)
2911 delta = -delta;
2912 delta *= io->size;
2913 if (io->in) {
2914 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2915 val += delta;
2916 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2917 } else {
2918 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2919 val += delta;
2920 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2921 }
2922 }
2923
2924 io->count -= io->cur_count;
2925 io->cur_count = 0;
2926
2927 return 0;
2928 }
2929
2930 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
2931 {
2932 /* TODO: String I/O for in kernel device */
2933 int r;
2934
2935 if (vcpu->arch.pio.in)
2936 r = kvm_io_bus_read(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2937 vcpu->arch.pio.size, pd);
2938 else
2939 r = kvm_io_bus_write(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2940 vcpu->arch.pio.size, pd);
2941 return r;
2942 }
2943
2944 static int pio_string_write(struct kvm_vcpu *vcpu)
2945 {
2946 struct kvm_pio_request *io = &vcpu->arch.pio;
2947 void *pd = vcpu->arch.pio_data;
2948 int i, r = 0;
2949
2950 for (i = 0; i < io->cur_count; i++) {
2951 if (kvm_io_bus_write(&vcpu->kvm->pio_bus,
2952 io->port, io->size, pd)) {
2953 r = -EOPNOTSUPP;
2954 break;
2955 }
2956 pd += io->size;
2957 }
2958 return r;
2959 }
2960
2961 int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2962 int size, unsigned port)
2963 {
2964 unsigned long val;
2965
2966 vcpu->run->exit_reason = KVM_EXIT_IO;
2967 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
2968 vcpu->run->io.size = vcpu->arch.pio.size = size;
2969 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
2970 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2971 vcpu->run->io.port = vcpu->arch.pio.port = port;
2972 vcpu->arch.pio.in = in;
2973 vcpu->arch.pio.string = 0;
2974 vcpu->arch.pio.down = 0;
2975 vcpu->arch.pio.rep = 0;
2976
2977 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
2978 size, 1);
2979
2980 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2981 memcpy(vcpu->arch.pio_data, &val, 4);
2982
2983 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
2984 complete_pio(vcpu);
2985 return 1;
2986 }
2987 return 0;
2988 }
2989 EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2990
2991 int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2992 int size, unsigned long count, int down,
2993 gva_t address, int rep, unsigned port)
2994 {
2995 unsigned now, in_page;
2996 int ret = 0;
2997
2998 vcpu->run->exit_reason = KVM_EXIT_IO;
2999 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
3000 vcpu->run->io.size = vcpu->arch.pio.size = size;
3001 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3002 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
3003 vcpu->run->io.port = vcpu->arch.pio.port = port;
3004 vcpu->arch.pio.in = in;
3005 vcpu->arch.pio.string = 1;
3006 vcpu->arch.pio.down = down;
3007 vcpu->arch.pio.rep = rep;
3008
3009 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
3010 size, count);
3011
3012 if (!count) {
3013 kvm_x86_ops->skip_emulated_instruction(vcpu);
3014 return 1;
3015 }
3016
3017 if (!down)
3018 in_page = PAGE_SIZE - offset_in_page(address);
3019 else
3020 in_page = offset_in_page(address) + size;
3021 now = min(count, (unsigned long)in_page / size);
3022 if (!now)
3023 now = 1;
3024 if (down) {
3025 /*
3026 * String I/O in reverse. Yuck. Kill the guest, fix later.
3027 */
3028 pr_unimpl(vcpu, "guest string pio down\n");
3029 kvm_inject_gp(vcpu, 0);
3030 return 1;
3031 }
3032 vcpu->run->io.count = now;
3033 vcpu->arch.pio.cur_count = now;
3034
3035 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
3036 kvm_x86_ops->skip_emulated_instruction(vcpu);
3037
3038 vcpu->arch.pio.guest_gva = address;
3039
3040 if (!vcpu->arch.pio.in) {
3041 /* string PIO write */
3042 ret = pio_copy_data(vcpu);
3043 if (ret == X86EMUL_PROPAGATE_FAULT) {
3044 kvm_inject_gp(vcpu, 0);
3045 return 1;
3046 }
3047 if (ret == 0 && !pio_string_write(vcpu)) {
3048 complete_pio(vcpu);
3049 if (vcpu->arch.pio.count == 0)
3050 ret = 1;
3051 }
3052 }
3053 /* no string PIO read support yet */
3054
3055 return ret;
3056 }
3057 EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
3058
3059 static void bounce_off(void *info)
3060 {
3061 /* nothing */
3062 }
3063
3064 static unsigned int ref_freq;
3065 static unsigned long tsc_khz_ref;
3066
3067 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3068 void *data)
3069 {
3070 struct cpufreq_freqs *freq = data;
3071 struct kvm *kvm;
3072 struct kvm_vcpu *vcpu;
3073 int i, send_ipi = 0;
3074
3075 if (!ref_freq)
3076 ref_freq = freq->old;
3077
3078 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3079 return 0;
3080 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3081 return 0;
3082 per_cpu(cpu_tsc_khz, freq->cpu) = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
3083
3084 spin_lock(&kvm_lock);
3085 list_for_each_entry(kvm, &vm_list, vm_list) {
3086 kvm_for_each_vcpu(i, vcpu, kvm) {
3087 if (vcpu->cpu != freq->cpu)
3088 continue;
3089 if (!kvm_request_guest_time_update(vcpu))
3090 continue;
3091 if (vcpu->cpu != smp_processor_id())
3092 send_ipi++;
3093 }
3094 }
3095 spin_unlock(&kvm_lock);
3096
3097 if (freq->old < freq->new && send_ipi) {
3098 /*
3099 * We upscale the frequency. Must make the guest
3100 * doesn't see old kvmclock values while running with
3101 * the new frequency, otherwise we risk the guest sees
3102 * time go backwards.
3103 *
3104 * In case we update the frequency for another cpu
3105 * (which might be in guest context) send an interrupt
3106 * to kick the cpu out of guest context. Next time
3107 * guest context is entered kvmclock will be updated,
3108 * so the guest will not see stale values.
3109 */
3110 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3111 }
3112 return 0;
3113 }
3114
3115 static struct notifier_block kvmclock_cpufreq_notifier_block = {
3116 .notifier_call = kvmclock_cpufreq_notifier
3117 };
3118
3119 int kvm_arch_init(void *opaque)
3120 {
3121 int r, cpu;
3122 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3123
3124 if (kvm_x86_ops) {
3125 printk(KERN_ERR "kvm: already loaded the other module\n");
3126 r = -EEXIST;
3127 goto out;
3128 }
3129
3130 if (!ops->cpu_has_kvm_support()) {
3131 printk(KERN_ERR "kvm: no hardware support\n");
3132 r = -EOPNOTSUPP;
3133 goto out;
3134 }
3135 if (ops->disabled_by_bios()) {
3136 printk(KERN_ERR "kvm: disabled by bios\n");
3137 r = -EOPNOTSUPP;
3138 goto out;
3139 }
3140
3141 r = kvm_mmu_module_init();
3142 if (r)
3143 goto out;
3144
3145 kvm_init_msr_list();
3146
3147 kvm_x86_ops = ops;
3148 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
3149 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3150 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
3151 PT_DIRTY_MASK, PT64_NX_MASK, 0);
3152
3153 for_each_possible_cpu(cpu)
3154 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
3155 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
3156 tsc_khz_ref = tsc_khz;
3157 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3158 CPUFREQ_TRANSITION_NOTIFIER);
3159 }
3160
3161 return 0;
3162
3163 out:
3164 return r;
3165 }
3166
3167 void kvm_arch_exit(void)
3168 {
3169 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3170 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3171 CPUFREQ_TRANSITION_NOTIFIER);
3172 kvm_x86_ops = NULL;
3173 kvm_mmu_module_exit();
3174 }
3175
3176 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3177 {
3178 ++vcpu->stat.halt_exits;
3179 if (irqchip_in_kernel(vcpu->kvm)) {
3180 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
3181 return 1;
3182 } else {
3183 vcpu->run->exit_reason = KVM_EXIT_HLT;
3184 return 0;
3185 }
3186 }
3187 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3188
3189 static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3190 unsigned long a1)
3191 {
3192 if (is_long_mode(vcpu))
3193 return a0;
3194 else
3195 return a0 | ((gpa_t)a1 << 32);
3196 }
3197
3198 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3199 {
3200 unsigned long nr, a0, a1, a2, a3, ret;
3201 int r = 1;
3202
3203 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3204 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3205 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3206 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3207 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
3208
3209 trace_kvm_hypercall(nr, a0, a1, a2, a3);
3210
3211 if (!is_long_mode(vcpu)) {
3212 nr &= 0xFFFFFFFF;
3213 a0 &= 0xFFFFFFFF;
3214 a1 &= 0xFFFFFFFF;
3215 a2 &= 0xFFFFFFFF;
3216 a3 &= 0xFFFFFFFF;
3217 }
3218
3219 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
3220 ret = -KVM_EPERM;
3221 goto out;
3222 }
3223
3224 switch (nr) {
3225 case KVM_HC_VAPIC_POLL_IRQ:
3226 ret = 0;
3227 break;
3228 case KVM_HC_MMU_OP:
3229 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3230 break;
3231 default:
3232 ret = -KVM_ENOSYS;
3233 break;
3234 }
3235 out:
3236 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
3237 ++vcpu->stat.hypercalls;
3238 return r;
3239 }
3240 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3241
3242 int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3243 {
3244 char instruction[3];
3245 int ret = 0;
3246 unsigned long rip = kvm_rip_read(vcpu);
3247
3248
3249 /*
3250 * Blow out the MMU to ensure that no other VCPU has an active mapping
3251 * to ensure that the updated hypercall appears atomically across all
3252 * VCPUs.
3253 */
3254 kvm_mmu_zap_all(vcpu->kvm);
3255
3256 kvm_x86_ops->patch_hypercall(vcpu, instruction);
3257 if (emulator_write_emulated(rip, instruction, 3, vcpu)
3258 != X86EMUL_CONTINUE)
3259 ret = -EFAULT;
3260
3261 return ret;
3262 }
3263
3264 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3265 {
3266 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3267 }
3268
3269 void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3270 {
3271 struct descriptor_table dt = { limit, base };
3272
3273 kvm_x86_ops->set_gdt(vcpu, &dt);
3274 }
3275
3276 void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3277 {
3278 struct descriptor_table dt = { limit, base };
3279
3280 kvm_x86_ops->set_idt(vcpu, &dt);
3281 }
3282
3283 void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3284 unsigned long *rflags)
3285 {
3286 kvm_lmsw(vcpu, msw);
3287 *rflags = kvm_x86_ops->get_rflags(vcpu);
3288 }
3289
3290 unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3291 {
3292 unsigned long value;
3293
3294 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3295 switch (cr) {
3296 case 0:
3297 value = vcpu->arch.cr0;
3298 break;
3299 case 2:
3300 value = vcpu->arch.cr2;
3301 break;
3302 case 3:
3303 value = vcpu->arch.cr3;
3304 break;
3305 case 4:
3306 value = vcpu->arch.cr4;
3307 break;
3308 case 8:
3309 value = kvm_get_cr8(vcpu);
3310 break;
3311 default:
3312 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3313 return 0;
3314 }
3315
3316 return value;
3317 }
3318
3319 void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
3320 unsigned long *rflags)
3321 {
3322 switch (cr) {
3323 case 0:
3324 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
3325 *rflags = kvm_x86_ops->get_rflags(vcpu);
3326 break;
3327 case 2:
3328 vcpu->arch.cr2 = val;
3329 break;
3330 case 3:
3331 kvm_set_cr3(vcpu, val);
3332 break;
3333 case 4:
3334 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
3335 break;
3336 case 8:
3337 kvm_set_cr8(vcpu, val & 0xfUL);
3338 break;
3339 default:
3340 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3341 }
3342 }
3343
3344 static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
3345 {
3346 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
3347 int j, nent = vcpu->arch.cpuid_nent;
3348
3349 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
3350 /* when no next entry is found, the current entry[i] is reselected */
3351 for (j = i + 1; ; j = (j + 1) % nent) {
3352 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
3353 if (ej->function == e->function) {
3354 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
3355 return j;
3356 }
3357 }
3358 return 0; /* silence gcc, even though control never reaches here */
3359 }
3360
3361 /* find an entry with matching function, matching index (if needed), and that
3362 * should be read next (if it's stateful) */
3363 static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
3364 u32 function, u32 index)
3365 {
3366 if (e->function != function)
3367 return 0;
3368 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3369 return 0;
3370 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
3371 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
3372 return 0;
3373 return 1;
3374 }
3375
3376 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
3377 u32 function, u32 index)
3378 {
3379 int i;
3380 struct kvm_cpuid_entry2 *best = NULL;
3381
3382 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
3383 struct kvm_cpuid_entry2 *e;
3384
3385 e = &vcpu->arch.cpuid_entries[i];
3386 if (is_matching_cpuid_entry(e, function, index)) {
3387 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3388 move_to_next_stateful_cpuid_entry(vcpu, i);
3389 best = e;
3390 break;
3391 }
3392 /*
3393 * Both basic or both extended?
3394 */
3395 if (((e->function ^ function) & 0x80000000) == 0)
3396 if (!best || e->function > best->function)
3397 best = e;
3398 }
3399 return best;
3400 }
3401
3402 int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
3403 {
3404 struct kvm_cpuid_entry2 *best;
3405
3406 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
3407 if (best)
3408 return best->eax & 0xff;
3409 return 36;
3410 }
3411
3412 void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3413 {
3414 u32 function, index;
3415 struct kvm_cpuid_entry2 *best;
3416
3417 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3418 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3419 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3420 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3421 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3422 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3423 best = kvm_find_cpuid_entry(vcpu, function, index);
3424 if (best) {
3425 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3426 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3427 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3428 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
3429 }
3430 kvm_x86_ops->skip_emulated_instruction(vcpu);
3431 trace_kvm_cpuid(function,
3432 kvm_register_read(vcpu, VCPU_REGS_RAX),
3433 kvm_register_read(vcpu, VCPU_REGS_RBX),
3434 kvm_register_read(vcpu, VCPU_REGS_RCX),
3435 kvm_register_read(vcpu, VCPU_REGS_RDX));
3436 }
3437 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
3438
3439 /*
3440 * Check if userspace requested an interrupt window, and that the
3441 * interrupt window is open.
3442 *
3443 * No need to exit to userspace if we already have an interrupt queued.
3444 */
3445 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
3446 struct kvm_run *kvm_run)
3447 {
3448 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
3449 kvm_run->request_interrupt_window &&
3450 kvm_arch_interrupt_allowed(vcpu));
3451 }
3452
3453 static void post_kvm_run_save(struct kvm_vcpu *vcpu,
3454 struct kvm_run *kvm_run)
3455 {
3456 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
3457 kvm_run->cr8 = kvm_get_cr8(vcpu);
3458 kvm_run->apic_base = kvm_get_apic_base(vcpu);
3459 if (irqchip_in_kernel(vcpu->kvm))
3460 kvm_run->ready_for_interrupt_injection = 1;
3461 else
3462 kvm_run->ready_for_interrupt_injection =
3463 kvm_arch_interrupt_allowed(vcpu) &&
3464 !kvm_cpu_has_interrupt(vcpu) &&
3465 !kvm_event_needs_reinjection(vcpu);
3466 }
3467
3468 static void vapic_enter(struct kvm_vcpu *vcpu)
3469 {
3470 struct kvm_lapic *apic = vcpu->arch.apic;
3471 struct page *page;
3472
3473 if (!apic || !apic->vapic_addr)
3474 return;
3475
3476 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
3477
3478 vcpu->arch.apic->vapic_page = page;
3479 }
3480
3481 static void vapic_exit(struct kvm_vcpu *vcpu)
3482 {
3483 struct kvm_lapic *apic = vcpu->arch.apic;
3484
3485 if (!apic || !apic->vapic_addr)
3486 return;
3487
3488 down_read(&vcpu->kvm->slots_lock);
3489 kvm_release_page_dirty(apic->vapic_page);
3490 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
3491 up_read(&vcpu->kvm->slots_lock);
3492 }
3493
3494 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
3495 {
3496 int max_irr, tpr;
3497
3498 if (!kvm_x86_ops->update_cr8_intercept)
3499 return;
3500
3501 if (!vcpu->arch.apic->vapic_addr)
3502 max_irr = kvm_lapic_find_highest_irr(vcpu);
3503 else
3504 max_irr = -1;
3505
3506 if (max_irr != -1)
3507 max_irr >>= 4;
3508
3509 tpr = kvm_lapic_get_cr8(vcpu);
3510
3511 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
3512 }
3513
3514 static void inject_pending_event(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3515 {
3516 /* try to reinject previous events if any */
3517 if (vcpu->arch.exception.pending) {
3518 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
3519 vcpu->arch.exception.has_error_code,
3520 vcpu->arch.exception.error_code);
3521 return;
3522 }
3523
3524 if (vcpu->arch.nmi_injected) {
3525 kvm_x86_ops->set_nmi(vcpu);
3526 return;
3527 }
3528
3529 if (vcpu->arch.interrupt.pending) {
3530 kvm_x86_ops->set_irq(vcpu);
3531 return;
3532 }
3533
3534 /* try to inject new event if pending */
3535 if (vcpu->arch.nmi_pending) {
3536 if (kvm_x86_ops->nmi_allowed(vcpu)) {
3537 vcpu->arch.nmi_pending = false;
3538 vcpu->arch.nmi_injected = true;
3539 kvm_x86_ops->set_nmi(vcpu);
3540 }
3541 } else if (kvm_cpu_has_interrupt(vcpu)) {
3542 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
3543 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
3544 false);
3545 kvm_x86_ops->set_irq(vcpu);
3546 }
3547 }
3548 }
3549
3550 static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3551 {
3552 int r;
3553 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
3554 kvm_run->request_interrupt_window;
3555
3556 if (vcpu->requests)
3557 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3558 kvm_mmu_unload(vcpu);
3559
3560 r = kvm_mmu_reload(vcpu);
3561 if (unlikely(r))
3562 goto out;
3563
3564 if (vcpu->requests) {
3565 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
3566 __kvm_migrate_timers(vcpu);
3567 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3568 kvm_write_guest_time(vcpu);
3569 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3570 kvm_mmu_sync_roots(vcpu);
3571 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3572 kvm_x86_ops->tlb_flush(vcpu);
3573 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3574 &vcpu->requests)) {
3575 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
3576 r = 0;
3577 goto out;
3578 }
3579 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
3580 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
3581 r = 0;
3582 goto out;
3583 }
3584 }
3585
3586 preempt_disable();
3587
3588 kvm_x86_ops->prepare_guest_switch(vcpu);
3589 kvm_load_guest_fpu(vcpu);
3590
3591 local_irq_disable();
3592
3593 clear_bit(KVM_REQ_KICK, &vcpu->requests);
3594 smp_mb__after_clear_bit();
3595
3596 if (vcpu->requests || need_resched() || signal_pending(current)) {
3597 set_bit(KVM_REQ_KICK, &vcpu->requests);
3598 local_irq_enable();
3599 preempt_enable();
3600 r = 1;
3601 goto out;
3602 }
3603
3604 inject_pending_event(vcpu, kvm_run);
3605
3606 /* enable NMI/IRQ window open exits if needed */
3607 if (vcpu->arch.nmi_pending)
3608 kvm_x86_ops->enable_nmi_window(vcpu);
3609 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
3610 kvm_x86_ops->enable_irq_window(vcpu);
3611
3612 if (kvm_lapic_enabled(vcpu)) {
3613 update_cr8_intercept(vcpu);
3614 kvm_lapic_sync_to_vapic(vcpu);
3615 }
3616
3617 up_read(&vcpu->kvm->slots_lock);
3618
3619 kvm_guest_enter();
3620
3621 get_debugreg(vcpu->arch.host_dr6, 6);
3622 get_debugreg(vcpu->arch.host_dr7, 7);
3623 if (unlikely(vcpu->arch.switch_db_regs)) {
3624 get_debugreg(vcpu->arch.host_db[0], 0);
3625 get_debugreg(vcpu->arch.host_db[1], 1);
3626 get_debugreg(vcpu->arch.host_db[2], 2);
3627 get_debugreg(vcpu->arch.host_db[3], 3);
3628
3629 set_debugreg(0, 7);
3630 set_debugreg(vcpu->arch.eff_db[0], 0);
3631 set_debugreg(vcpu->arch.eff_db[1], 1);
3632 set_debugreg(vcpu->arch.eff_db[2], 2);
3633 set_debugreg(vcpu->arch.eff_db[3], 3);
3634 }
3635
3636 trace_kvm_entry(vcpu->vcpu_id);
3637 kvm_x86_ops->run(vcpu, kvm_run);
3638
3639 if (unlikely(vcpu->arch.switch_db_regs)) {
3640 set_debugreg(0, 7);
3641 set_debugreg(vcpu->arch.host_db[0], 0);
3642 set_debugreg(vcpu->arch.host_db[1], 1);
3643 set_debugreg(vcpu->arch.host_db[2], 2);
3644 set_debugreg(vcpu->arch.host_db[3], 3);
3645 }
3646 set_debugreg(vcpu->arch.host_dr6, 6);
3647 set_debugreg(vcpu->arch.host_dr7, 7);
3648
3649 set_bit(KVM_REQ_KICK, &vcpu->requests);
3650 local_irq_enable();
3651
3652 ++vcpu->stat.exits;
3653
3654 /*
3655 * We must have an instruction between local_irq_enable() and
3656 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3657 * the interrupt shadow. The stat.exits increment will do nicely.
3658 * But we need to prevent reordering, hence this barrier():
3659 */
3660 barrier();
3661
3662 kvm_guest_exit();
3663
3664 preempt_enable();
3665
3666 down_read(&vcpu->kvm->slots_lock);
3667
3668 /*
3669 * Profile KVM exit RIPs:
3670 */
3671 if (unlikely(prof_on == KVM_PROFILING)) {
3672 unsigned long rip = kvm_rip_read(vcpu);
3673 profile_hit(KVM_PROFILING, (void *)rip);
3674 }
3675
3676
3677 kvm_lapic_sync_from_vapic(vcpu);
3678
3679 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
3680 out:
3681 return r;
3682 }
3683
3684
3685 static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3686 {
3687 int r;
3688
3689 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
3690 pr_debug("vcpu %d received sipi with vector # %x\n",
3691 vcpu->vcpu_id, vcpu->arch.sipi_vector);
3692 kvm_lapic_reset(vcpu);
3693 r = kvm_arch_vcpu_reset(vcpu);
3694 if (r)
3695 return r;
3696 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
3697 }
3698
3699 down_read(&vcpu->kvm->slots_lock);
3700 vapic_enter(vcpu);
3701
3702 r = 1;
3703 while (r > 0) {
3704 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
3705 r = vcpu_enter_guest(vcpu, kvm_run);
3706 else {
3707 up_read(&vcpu->kvm->slots_lock);
3708 kvm_vcpu_block(vcpu);
3709 down_read(&vcpu->kvm->slots_lock);
3710 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
3711 {
3712 switch(vcpu->arch.mp_state) {
3713 case KVM_MP_STATE_HALTED:
3714 vcpu->arch.mp_state =
3715 KVM_MP_STATE_RUNNABLE;
3716 case KVM_MP_STATE_RUNNABLE:
3717 break;
3718 case KVM_MP_STATE_SIPI_RECEIVED:
3719 default:
3720 r = -EINTR;
3721 break;
3722 }
3723 }
3724 }
3725
3726 if (r <= 0)
3727 break;
3728
3729 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
3730 if (kvm_cpu_has_pending_timer(vcpu))
3731 kvm_inject_pending_timer_irqs(vcpu);
3732
3733 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3734 r = -EINTR;
3735 kvm_run->exit_reason = KVM_EXIT_INTR;
3736 ++vcpu->stat.request_irq_exits;
3737 }
3738 if (signal_pending(current)) {
3739 r = -EINTR;
3740 kvm_run->exit_reason = KVM_EXIT_INTR;
3741 ++vcpu->stat.signal_exits;
3742 }
3743 if (need_resched()) {
3744 up_read(&vcpu->kvm->slots_lock);
3745 kvm_resched(vcpu);
3746 down_read(&vcpu->kvm->slots_lock);
3747 }
3748 }
3749
3750 up_read(&vcpu->kvm->slots_lock);
3751 post_kvm_run_save(vcpu, kvm_run);
3752
3753 vapic_exit(vcpu);
3754
3755 return r;
3756 }
3757
3758 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3759 {
3760 int r;
3761 sigset_t sigsaved;
3762
3763 vcpu_load(vcpu);
3764
3765 if (vcpu->sigset_active)
3766 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3767
3768 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
3769 kvm_vcpu_block(vcpu);
3770 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
3771 r = -EAGAIN;
3772 goto out;
3773 }
3774
3775 /* re-sync apic's tpr */
3776 if (!irqchip_in_kernel(vcpu->kvm))
3777 kvm_set_cr8(vcpu, kvm_run->cr8);
3778
3779 if (vcpu->arch.pio.cur_count) {
3780 r = complete_pio(vcpu);
3781 if (r)
3782 goto out;
3783 }
3784 #if CONFIG_HAS_IOMEM
3785 if (vcpu->mmio_needed) {
3786 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3787 vcpu->mmio_read_completed = 1;
3788 vcpu->mmio_needed = 0;
3789
3790 down_read(&vcpu->kvm->slots_lock);
3791 r = emulate_instruction(vcpu, kvm_run,
3792 vcpu->arch.mmio_fault_cr2, 0,
3793 EMULTYPE_NO_DECODE);
3794 up_read(&vcpu->kvm->slots_lock);
3795 if (r == EMULATE_DO_MMIO) {
3796 /*
3797 * Read-modify-write. Back to userspace.
3798 */
3799 r = 0;
3800 goto out;
3801 }
3802 }
3803 #endif
3804 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3805 kvm_register_write(vcpu, VCPU_REGS_RAX,
3806 kvm_run->hypercall.ret);
3807
3808 r = __vcpu_run(vcpu, kvm_run);
3809
3810 out:
3811 if (vcpu->sigset_active)
3812 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3813
3814 vcpu_put(vcpu);
3815 return r;
3816 }
3817
3818 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3819 {
3820 vcpu_load(vcpu);
3821
3822 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3823 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3824 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3825 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3826 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3827 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3828 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3829 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3830 #ifdef CONFIG_X86_64
3831 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3832 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3833 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3834 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3835 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3836 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3837 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3838 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
3839 #endif
3840
3841 regs->rip = kvm_rip_read(vcpu);
3842 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3843
3844 /*
3845 * Don't leak debug flags in case they were set for guest debugging
3846 */
3847 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3848 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3849
3850 vcpu_put(vcpu);
3851
3852 return 0;
3853 }
3854
3855 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3856 {
3857 vcpu_load(vcpu);
3858
3859 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3860 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3861 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3862 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3863 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3864 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3865 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3866 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
3867 #ifdef CONFIG_X86_64
3868 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3869 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3870 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3871 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3872 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3873 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3874 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3875 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3876
3877 #endif
3878
3879 kvm_rip_write(vcpu, regs->rip);
3880 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3881
3882
3883 vcpu->arch.exception.pending = false;
3884
3885 vcpu_put(vcpu);
3886
3887 return 0;
3888 }
3889
3890 void kvm_get_segment(struct kvm_vcpu *vcpu,
3891 struct kvm_segment *var, int seg)
3892 {
3893 kvm_x86_ops->get_segment(vcpu, var, seg);
3894 }
3895
3896 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3897 {
3898 struct kvm_segment cs;
3899
3900 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
3901 *db = cs.db;
3902 *l = cs.l;
3903 }
3904 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3905
3906 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3907 struct kvm_sregs *sregs)
3908 {
3909 struct descriptor_table dt;
3910
3911 vcpu_load(vcpu);
3912
3913 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3914 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3915 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3916 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3917 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3918 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
3919
3920 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3921 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
3922
3923 kvm_x86_ops->get_idt(vcpu, &dt);
3924 sregs->idt.limit = dt.limit;
3925 sregs->idt.base = dt.base;
3926 kvm_x86_ops->get_gdt(vcpu, &dt);
3927 sregs->gdt.limit = dt.limit;
3928 sregs->gdt.base = dt.base;
3929
3930 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3931 sregs->cr0 = vcpu->arch.cr0;
3932 sregs->cr2 = vcpu->arch.cr2;
3933 sregs->cr3 = vcpu->arch.cr3;
3934 sregs->cr4 = vcpu->arch.cr4;
3935 sregs->cr8 = kvm_get_cr8(vcpu);
3936 sregs->efer = vcpu->arch.shadow_efer;
3937 sregs->apic_base = kvm_get_apic_base(vcpu);
3938
3939 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
3940
3941 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
3942 set_bit(vcpu->arch.interrupt.nr,
3943 (unsigned long *)sregs->interrupt_bitmap);
3944
3945 vcpu_put(vcpu);
3946
3947 return 0;
3948 }
3949
3950 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3951 struct kvm_mp_state *mp_state)
3952 {
3953 vcpu_load(vcpu);
3954 mp_state->mp_state = vcpu->arch.mp_state;
3955 vcpu_put(vcpu);
3956 return 0;
3957 }
3958
3959 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3960 struct kvm_mp_state *mp_state)
3961 {
3962 vcpu_load(vcpu);
3963 vcpu->arch.mp_state = mp_state->mp_state;
3964 vcpu_put(vcpu);
3965 return 0;
3966 }
3967
3968 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3969 struct kvm_segment *var, int seg)
3970 {
3971 kvm_x86_ops->set_segment(vcpu, var, seg);
3972 }
3973
3974 static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3975 struct kvm_segment *kvm_desct)
3976 {
3977 kvm_desct->base = get_desc_base(seg_desc);
3978 kvm_desct->limit = get_desc_limit(seg_desc);
3979 if (seg_desc->g) {
3980 kvm_desct->limit <<= 12;
3981 kvm_desct->limit |= 0xfff;
3982 }
3983 kvm_desct->selector = selector;
3984 kvm_desct->type = seg_desc->type;
3985 kvm_desct->present = seg_desc->p;
3986 kvm_desct->dpl = seg_desc->dpl;
3987 kvm_desct->db = seg_desc->d;
3988 kvm_desct->s = seg_desc->s;
3989 kvm_desct->l = seg_desc->l;
3990 kvm_desct->g = seg_desc->g;
3991 kvm_desct->avl = seg_desc->avl;
3992 if (!selector)
3993 kvm_desct->unusable = 1;
3994 else
3995 kvm_desct->unusable = 0;
3996 kvm_desct->padding = 0;
3997 }
3998
3999 static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
4000 u16 selector,
4001 struct descriptor_table *dtable)
4002 {
4003 if (selector & 1 << 2) {
4004 struct kvm_segment kvm_seg;
4005
4006 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
4007
4008 if (kvm_seg.unusable)
4009 dtable->limit = 0;
4010 else
4011 dtable->limit = kvm_seg.limit;
4012 dtable->base = kvm_seg.base;
4013 }
4014 else
4015 kvm_x86_ops->get_gdt(vcpu, dtable);
4016 }
4017
4018 /* allowed just for 8 bytes segments */
4019 static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4020 struct desc_struct *seg_desc)
4021 {
4022 gpa_t gpa;
4023 struct descriptor_table dtable;
4024 u16 index = selector >> 3;
4025
4026 get_segment_descriptor_dtable(vcpu, selector, &dtable);
4027
4028 if (dtable.limit < index * 8 + 7) {
4029 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
4030 return 1;
4031 }
4032 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
4033 gpa += index * 8;
4034 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
4035 }
4036
4037 /* allowed just for 8 bytes segments */
4038 static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4039 struct desc_struct *seg_desc)
4040 {
4041 gpa_t gpa;
4042 struct descriptor_table dtable;
4043 u16 index = selector >> 3;
4044
4045 get_segment_descriptor_dtable(vcpu, selector, &dtable);
4046
4047 if (dtable.limit < index * 8 + 7)
4048 return 1;
4049 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
4050 gpa += index * 8;
4051 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
4052 }
4053
4054 static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
4055 struct desc_struct *seg_desc)
4056 {
4057 u32 base_addr = get_desc_base(seg_desc);
4058
4059 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
4060 }
4061
4062 static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
4063 {
4064 struct kvm_segment kvm_seg;
4065
4066 kvm_get_segment(vcpu, &kvm_seg, seg);
4067 return kvm_seg.selector;
4068 }
4069
4070 static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
4071 u16 selector,
4072 struct kvm_segment *kvm_seg)
4073 {
4074 struct desc_struct seg_desc;
4075
4076 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
4077 return 1;
4078 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
4079 return 0;
4080 }
4081
4082 static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
4083 {
4084 struct kvm_segment segvar = {
4085 .base = selector << 4,
4086 .limit = 0xffff,
4087 .selector = selector,
4088 .type = 3,
4089 .present = 1,
4090 .dpl = 3,
4091 .db = 0,
4092 .s = 1,
4093 .l = 0,
4094 .g = 0,
4095 .avl = 0,
4096 .unusable = 0,
4097 };
4098 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
4099 return 0;
4100 }
4101
4102 int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4103 int type_bits, int seg)
4104 {
4105 struct kvm_segment kvm_seg;
4106
4107 if (!(vcpu->arch.cr0 & X86_CR0_PE))
4108 return kvm_load_realmode_segment(vcpu, selector, seg);
4109 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
4110 return 1;
4111 kvm_seg.type |= type_bits;
4112
4113 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
4114 seg != VCPU_SREG_LDTR)
4115 if (!kvm_seg.s)
4116 kvm_seg.unusable = 1;
4117
4118 kvm_set_segment(vcpu, &kvm_seg, seg);
4119 return 0;
4120 }
4121
4122 static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4123 struct tss_segment_32 *tss)
4124 {
4125 tss->cr3 = vcpu->arch.cr3;
4126 tss->eip = kvm_rip_read(vcpu);
4127 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
4128 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4129 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4130 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4131 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4132 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4133 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4134 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4135 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4136 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4137 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4138 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4139 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4140 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4141 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4142 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
4143 }
4144
4145 static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4146 struct tss_segment_32 *tss)
4147 {
4148 kvm_set_cr3(vcpu, tss->cr3);
4149
4150 kvm_rip_write(vcpu, tss->eip);
4151 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
4152
4153 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4154 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4155 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4156 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4157 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4158 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4159 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4160 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
4161
4162 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
4163 return 1;
4164
4165 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
4166 return 1;
4167
4168 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
4169 return 1;
4170
4171 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
4172 return 1;
4173
4174 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
4175 return 1;
4176
4177 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
4178 return 1;
4179
4180 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
4181 return 1;
4182 return 0;
4183 }
4184
4185 static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4186 struct tss_segment_16 *tss)
4187 {
4188 tss->ip = kvm_rip_read(vcpu);
4189 tss->flag = kvm_x86_ops->get_rflags(vcpu);
4190 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4191 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4192 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4193 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4194 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4195 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4196 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4197 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
4198
4199 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4200 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4201 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4202 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4203 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
4204 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
4205 }
4206
4207 static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4208 struct tss_segment_16 *tss)
4209 {
4210 kvm_rip_write(vcpu, tss->ip);
4211 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
4212 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
4213 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
4214 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
4215 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
4216 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
4217 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
4218 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
4219 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
4220
4221 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
4222 return 1;
4223
4224 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
4225 return 1;
4226
4227 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
4228 return 1;
4229
4230 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
4231 return 1;
4232
4233 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
4234 return 1;
4235 return 0;
4236 }
4237
4238 static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
4239 u16 old_tss_sel, u32 old_tss_base,
4240 struct desc_struct *nseg_desc)
4241 {
4242 struct tss_segment_16 tss_segment_16;
4243 int ret = 0;
4244
4245 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4246 sizeof tss_segment_16))
4247 goto out;
4248
4249 save_state_to_tss16(vcpu, &tss_segment_16);
4250
4251 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4252 sizeof tss_segment_16))
4253 goto out;
4254
4255 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4256 &tss_segment_16, sizeof tss_segment_16))
4257 goto out;
4258
4259 if (old_tss_sel != 0xffff) {
4260 tss_segment_16.prev_task_link = old_tss_sel;
4261
4262 if (kvm_write_guest(vcpu->kvm,
4263 get_tss_base_addr(vcpu, nseg_desc),
4264 &tss_segment_16.prev_task_link,
4265 sizeof tss_segment_16.prev_task_link))
4266 goto out;
4267 }
4268
4269 if (load_state_from_tss16(vcpu, &tss_segment_16))
4270 goto out;
4271
4272 ret = 1;
4273 out:
4274 return ret;
4275 }
4276
4277 static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
4278 u16 old_tss_sel, u32 old_tss_base,
4279 struct desc_struct *nseg_desc)
4280 {
4281 struct tss_segment_32 tss_segment_32;
4282 int ret = 0;
4283
4284 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4285 sizeof tss_segment_32))
4286 goto out;
4287
4288 save_state_to_tss32(vcpu, &tss_segment_32);
4289
4290 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4291 sizeof tss_segment_32))
4292 goto out;
4293
4294 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4295 &tss_segment_32, sizeof tss_segment_32))
4296 goto out;
4297
4298 if (old_tss_sel != 0xffff) {
4299 tss_segment_32.prev_task_link = old_tss_sel;
4300
4301 if (kvm_write_guest(vcpu->kvm,
4302 get_tss_base_addr(vcpu, nseg_desc),
4303 &tss_segment_32.prev_task_link,
4304 sizeof tss_segment_32.prev_task_link))
4305 goto out;
4306 }
4307
4308 if (load_state_from_tss32(vcpu, &tss_segment_32))
4309 goto out;
4310
4311 ret = 1;
4312 out:
4313 return ret;
4314 }
4315
4316 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
4317 {
4318 struct kvm_segment tr_seg;
4319 struct desc_struct cseg_desc;
4320 struct desc_struct nseg_desc;
4321 int ret = 0;
4322 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
4323 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
4324
4325 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
4326
4327 /* FIXME: Handle errors. Failure to read either TSS or their
4328 * descriptors should generate a pagefault.
4329 */
4330 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
4331 goto out;
4332
4333 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
4334 goto out;
4335
4336 if (reason != TASK_SWITCH_IRET) {
4337 int cpl;
4338
4339 cpl = kvm_x86_ops->get_cpl(vcpu);
4340 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
4341 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4342 return 1;
4343 }
4344 }
4345
4346 if (!nseg_desc.p || get_desc_limit(&nseg_desc) < 0x67) {
4347 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
4348 return 1;
4349 }
4350
4351 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
4352 cseg_desc.type &= ~(1 << 1); //clear the B flag
4353 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
4354 }
4355
4356 if (reason == TASK_SWITCH_IRET) {
4357 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4358 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
4359 }
4360
4361 /* set back link to prev task only if NT bit is set in eflags
4362 note that old_tss_sel is not used afetr this point */
4363 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4364 old_tss_sel = 0xffff;
4365
4366 /* set back link to prev task only if NT bit is set in eflags
4367 note that old_tss_sel is not used afetr this point */
4368 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4369 old_tss_sel = 0xffff;
4370
4371 if (nseg_desc.type & 8)
4372 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
4373 old_tss_base, &nseg_desc);
4374 else
4375 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
4376 old_tss_base, &nseg_desc);
4377
4378 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
4379 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4380 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
4381 }
4382
4383 if (reason != TASK_SWITCH_IRET) {
4384 nseg_desc.type |= (1 << 1);
4385 save_guest_segment_descriptor(vcpu, tss_selector,
4386 &nseg_desc);
4387 }
4388
4389 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
4390 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
4391 tr_seg.type = 11;
4392 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
4393 out:
4394 return ret;
4395 }
4396 EXPORT_SYMBOL_GPL(kvm_task_switch);
4397
4398 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4399 struct kvm_sregs *sregs)
4400 {
4401 int mmu_reset_needed = 0;
4402 int pending_vec, max_bits;
4403 struct descriptor_table dt;
4404
4405 vcpu_load(vcpu);
4406
4407 dt.limit = sregs->idt.limit;
4408 dt.base = sregs->idt.base;
4409 kvm_x86_ops->set_idt(vcpu, &dt);
4410 dt.limit = sregs->gdt.limit;
4411 dt.base = sregs->gdt.base;
4412 kvm_x86_ops->set_gdt(vcpu, &dt);
4413
4414 vcpu->arch.cr2 = sregs->cr2;
4415 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
4416 vcpu->arch.cr3 = sregs->cr3;
4417
4418 kvm_set_cr8(vcpu, sregs->cr8);
4419
4420 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
4421 kvm_x86_ops->set_efer(vcpu, sregs->efer);
4422 kvm_set_apic_base(vcpu, sregs->apic_base);
4423
4424 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
4425
4426 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
4427 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
4428 vcpu->arch.cr0 = sregs->cr0;
4429
4430 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
4431 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
4432 if (!is_long_mode(vcpu) && is_pae(vcpu))
4433 load_pdptrs(vcpu, vcpu->arch.cr3);
4434
4435 if (mmu_reset_needed)
4436 kvm_mmu_reset_context(vcpu);
4437
4438 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4439 pending_vec = find_first_bit(
4440 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4441 if (pending_vec < max_bits) {
4442 kvm_queue_interrupt(vcpu, pending_vec, false);
4443 pr_debug("Set back pending irq %d\n", pending_vec);
4444 if (irqchip_in_kernel(vcpu->kvm))
4445 kvm_pic_clear_isr_ack(vcpu->kvm);
4446 }
4447
4448 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4449 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4450 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4451 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4452 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4453 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
4454
4455 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4456 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
4457
4458 update_cr8_intercept(vcpu);
4459
4460 /* Older userspace won't unhalt the vcpu on reset. */
4461 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
4462 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4463 !(vcpu->arch.cr0 & X86_CR0_PE))
4464 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4465
4466 vcpu_put(vcpu);
4467
4468 return 0;
4469 }
4470
4471 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4472 struct kvm_guest_debug *dbg)
4473 {
4474 int i, r;
4475
4476 vcpu_load(vcpu);
4477
4478 if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) ==
4479 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) {
4480 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4481 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4482 vcpu->arch.switch_db_regs =
4483 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4484 } else {
4485 for (i = 0; i < KVM_NR_DB_REGS; i++)
4486 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4487 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4488 }
4489
4490 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
4491
4492 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4493 kvm_queue_exception(vcpu, DB_VECTOR);
4494 else if (dbg->control & KVM_GUESTDBG_INJECT_BP)
4495 kvm_queue_exception(vcpu, BP_VECTOR);
4496
4497 vcpu_put(vcpu);
4498
4499 return r;
4500 }
4501
4502 /*
4503 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4504 * we have asm/x86/processor.h
4505 */
4506 struct fxsave {
4507 u16 cwd;
4508 u16 swd;
4509 u16 twd;
4510 u16 fop;
4511 u64 rip;
4512 u64 rdp;
4513 u32 mxcsr;
4514 u32 mxcsr_mask;
4515 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4516 #ifdef CONFIG_X86_64
4517 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4518 #else
4519 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4520 #endif
4521 };
4522
4523 /*
4524 * Translate a guest virtual address to a guest physical address.
4525 */
4526 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4527 struct kvm_translation *tr)
4528 {
4529 unsigned long vaddr = tr->linear_address;
4530 gpa_t gpa;
4531
4532 vcpu_load(vcpu);
4533 down_read(&vcpu->kvm->slots_lock);
4534 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
4535 up_read(&vcpu->kvm->slots_lock);
4536 tr->physical_address = gpa;
4537 tr->valid = gpa != UNMAPPED_GVA;
4538 tr->writeable = 1;
4539 tr->usermode = 0;
4540 vcpu_put(vcpu);
4541
4542 return 0;
4543 }
4544
4545 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4546 {
4547 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
4548
4549 vcpu_load(vcpu);
4550
4551 memcpy(fpu->fpr, fxsave->st_space, 128);
4552 fpu->fcw = fxsave->cwd;
4553 fpu->fsw = fxsave->swd;
4554 fpu->ftwx = fxsave->twd;
4555 fpu->last_opcode = fxsave->fop;
4556 fpu->last_ip = fxsave->rip;
4557 fpu->last_dp = fxsave->rdp;
4558 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4559
4560 vcpu_put(vcpu);
4561
4562 return 0;
4563 }
4564
4565 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4566 {
4567 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
4568
4569 vcpu_load(vcpu);
4570
4571 memcpy(fxsave->st_space, fpu->fpr, 128);
4572 fxsave->cwd = fpu->fcw;
4573 fxsave->swd = fpu->fsw;
4574 fxsave->twd = fpu->ftwx;
4575 fxsave->fop = fpu->last_opcode;
4576 fxsave->rip = fpu->last_ip;
4577 fxsave->rdp = fpu->last_dp;
4578 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4579
4580 vcpu_put(vcpu);
4581
4582 return 0;
4583 }
4584
4585 void fx_init(struct kvm_vcpu *vcpu)
4586 {
4587 unsigned after_mxcsr_mask;
4588
4589 /*
4590 * Touch the fpu the first time in non atomic context as if
4591 * this is the first fpu instruction the exception handler
4592 * will fire before the instruction returns and it'll have to
4593 * allocate ram with GFP_KERNEL.
4594 */
4595 if (!used_math())
4596 kvm_fx_save(&vcpu->arch.host_fx_image);
4597
4598 /* Initialize guest FPU by resetting ours and saving into guest's */
4599 preempt_disable();
4600 kvm_fx_save(&vcpu->arch.host_fx_image);
4601 kvm_fx_finit();
4602 kvm_fx_save(&vcpu->arch.guest_fx_image);
4603 kvm_fx_restore(&vcpu->arch.host_fx_image);
4604 preempt_enable();
4605
4606 vcpu->arch.cr0 |= X86_CR0_ET;
4607 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
4608 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4609 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
4610 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4611 }
4612 EXPORT_SYMBOL_GPL(fx_init);
4613
4614 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4615 {
4616 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4617 return;
4618
4619 vcpu->guest_fpu_loaded = 1;
4620 kvm_fx_save(&vcpu->arch.host_fx_image);
4621 kvm_fx_restore(&vcpu->arch.guest_fx_image);
4622 }
4623 EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4624
4625 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4626 {
4627 if (!vcpu->guest_fpu_loaded)
4628 return;
4629
4630 vcpu->guest_fpu_loaded = 0;
4631 kvm_fx_save(&vcpu->arch.guest_fx_image);
4632 kvm_fx_restore(&vcpu->arch.host_fx_image);
4633 ++vcpu->stat.fpu_reload;
4634 }
4635 EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
4636
4637 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4638 {
4639 if (vcpu->arch.time_page) {
4640 kvm_release_page_dirty(vcpu->arch.time_page);
4641 vcpu->arch.time_page = NULL;
4642 }
4643
4644 kvm_x86_ops->vcpu_free(vcpu);
4645 }
4646
4647 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4648 unsigned int id)
4649 {
4650 return kvm_x86_ops->vcpu_create(kvm, id);
4651 }
4652
4653 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4654 {
4655 int r;
4656
4657 /* We do fxsave: this must be aligned. */
4658 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
4659
4660 vcpu->arch.mtrr_state.have_fixed = 1;
4661 vcpu_load(vcpu);
4662 r = kvm_arch_vcpu_reset(vcpu);
4663 if (r == 0)
4664 r = kvm_mmu_setup(vcpu);
4665 vcpu_put(vcpu);
4666 if (r < 0)
4667 goto free_vcpu;
4668
4669 return 0;
4670 free_vcpu:
4671 kvm_x86_ops->vcpu_free(vcpu);
4672 return r;
4673 }
4674
4675 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
4676 {
4677 vcpu_load(vcpu);
4678 kvm_mmu_unload(vcpu);
4679 vcpu_put(vcpu);
4680
4681 kvm_x86_ops->vcpu_free(vcpu);
4682 }
4683
4684 int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4685 {
4686 vcpu->arch.nmi_pending = false;
4687 vcpu->arch.nmi_injected = false;
4688
4689 vcpu->arch.switch_db_regs = 0;
4690 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4691 vcpu->arch.dr6 = DR6_FIXED_1;
4692 vcpu->arch.dr7 = DR7_FIXED_1;
4693
4694 return kvm_x86_ops->vcpu_reset(vcpu);
4695 }
4696
4697 void kvm_arch_hardware_enable(void *garbage)
4698 {
4699 kvm_x86_ops->hardware_enable(garbage);
4700 }
4701
4702 void kvm_arch_hardware_disable(void *garbage)
4703 {
4704 kvm_x86_ops->hardware_disable(garbage);
4705 }
4706
4707 int kvm_arch_hardware_setup(void)
4708 {
4709 return kvm_x86_ops->hardware_setup();
4710 }
4711
4712 void kvm_arch_hardware_unsetup(void)
4713 {
4714 kvm_x86_ops->hardware_unsetup();
4715 }
4716
4717 void kvm_arch_check_processor_compat(void *rtn)
4718 {
4719 kvm_x86_ops->check_processor_compatibility(rtn);
4720 }
4721
4722 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4723 {
4724 struct page *page;
4725 struct kvm *kvm;
4726 int r;
4727
4728 BUG_ON(vcpu->kvm == NULL);
4729 kvm = vcpu->kvm;
4730
4731 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4732 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
4733 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4734 else
4735 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
4736
4737 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4738 if (!page) {
4739 r = -ENOMEM;
4740 goto fail;
4741 }
4742 vcpu->arch.pio_data = page_address(page);
4743
4744 r = kvm_mmu_create(vcpu);
4745 if (r < 0)
4746 goto fail_free_pio_data;
4747
4748 if (irqchip_in_kernel(kvm)) {
4749 r = kvm_create_lapic(vcpu);
4750 if (r < 0)
4751 goto fail_mmu_destroy;
4752 }
4753
4754 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
4755 GFP_KERNEL);
4756 if (!vcpu->arch.mce_banks) {
4757 r = -ENOMEM;
4758 goto fail_mmu_destroy;
4759 }
4760 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
4761
4762 return 0;
4763
4764 fail_mmu_destroy:
4765 kvm_mmu_destroy(vcpu);
4766 fail_free_pio_data:
4767 free_page((unsigned long)vcpu->arch.pio_data);
4768 fail:
4769 return r;
4770 }
4771
4772 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4773 {
4774 kvm_free_lapic(vcpu);
4775 down_read(&vcpu->kvm->slots_lock);
4776 kvm_mmu_destroy(vcpu);
4777 up_read(&vcpu->kvm->slots_lock);
4778 free_page((unsigned long)vcpu->arch.pio_data);
4779 }
4780
4781 struct kvm *kvm_arch_create_vm(void)
4782 {
4783 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4784
4785 if (!kvm)
4786 return ERR_PTR(-ENOMEM);
4787
4788 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4789 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
4790
4791 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4792 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4793
4794 rdtscll(kvm->arch.vm_init_tsc);
4795
4796 return kvm;
4797 }
4798
4799 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4800 {
4801 vcpu_load(vcpu);
4802 kvm_mmu_unload(vcpu);
4803 vcpu_put(vcpu);
4804 }
4805
4806 static void kvm_free_vcpus(struct kvm *kvm)
4807 {
4808 unsigned int i;
4809 struct kvm_vcpu *vcpu;
4810
4811 /*
4812 * Unpin any mmu pages first.
4813 */
4814 kvm_for_each_vcpu(i, vcpu, kvm)
4815 kvm_unload_vcpu_mmu(vcpu);
4816 kvm_for_each_vcpu(i, vcpu, kvm)
4817 kvm_arch_vcpu_free(vcpu);
4818
4819 mutex_lock(&kvm->lock);
4820 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
4821 kvm->vcpus[i] = NULL;
4822
4823 atomic_set(&kvm->online_vcpus, 0);
4824 mutex_unlock(&kvm->lock);
4825 }
4826
4827 void kvm_arch_sync_events(struct kvm *kvm)
4828 {
4829 kvm_free_all_assigned_devices(kvm);
4830 }
4831
4832 void kvm_arch_destroy_vm(struct kvm *kvm)
4833 {
4834 kvm_iommu_unmap_guest(kvm);
4835 kvm_free_pit(kvm);
4836 kfree(kvm->arch.vpic);
4837 kfree(kvm->arch.vioapic);
4838 kvm_free_vcpus(kvm);
4839 kvm_free_physmem(kvm);
4840 if (kvm->arch.apic_access_page)
4841 put_page(kvm->arch.apic_access_page);
4842 if (kvm->arch.ept_identity_pagetable)
4843 put_page(kvm->arch.ept_identity_pagetable);
4844 kfree(kvm);
4845 }
4846
4847 int kvm_arch_set_memory_region(struct kvm *kvm,
4848 struct kvm_userspace_memory_region *mem,
4849 struct kvm_memory_slot old,
4850 int user_alloc)
4851 {
4852 int npages = mem->memory_size >> PAGE_SHIFT;
4853 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4854
4855 /*To keep backward compatibility with older userspace,
4856 *x86 needs to hanlde !user_alloc case.
4857 */
4858 if (!user_alloc) {
4859 if (npages && !old.rmap) {
4860 unsigned long userspace_addr;
4861
4862 down_write(&current->mm->mmap_sem);
4863 userspace_addr = do_mmap(NULL, 0,
4864 npages * PAGE_SIZE,
4865 PROT_READ | PROT_WRITE,
4866 MAP_PRIVATE | MAP_ANONYMOUS,
4867 0);
4868 up_write(&current->mm->mmap_sem);
4869
4870 if (IS_ERR((void *)userspace_addr))
4871 return PTR_ERR((void *)userspace_addr);
4872
4873 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4874 spin_lock(&kvm->mmu_lock);
4875 memslot->userspace_addr = userspace_addr;
4876 spin_unlock(&kvm->mmu_lock);
4877 } else {
4878 if (!old.user_alloc && old.rmap) {
4879 int ret;
4880
4881 down_write(&current->mm->mmap_sem);
4882 ret = do_munmap(current->mm, old.userspace_addr,
4883 old.npages * PAGE_SIZE);
4884 up_write(&current->mm->mmap_sem);
4885 if (ret < 0)
4886 printk(KERN_WARNING
4887 "kvm_vm_ioctl_set_memory_region: "
4888 "failed to munmap memory\n");
4889 }
4890 }
4891 }
4892
4893 spin_lock(&kvm->mmu_lock);
4894 if (!kvm->arch.n_requested_mmu_pages) {
4895 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4896 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4897 }
4898
4899 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
4900 spin_unlock(&kvm->mmu_lock);
4901 kvm_flush_remote_tlbs(kvm);
4902
4903 return 0;
4904 }
4905
4906 void kvm_arch_flush_shadow(struct kvm *kvm)
4907 {
4908 kvm_mmu_zap_all(kvm);
4909 kvm_reload_remote_mmus(kvm);
4910 }
4911
4912 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4913 {
4914 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
4915 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4916 || vcpu->arch.nmi_pending ||
4917 (kvm_arch_interrupt_allowed(vcpu) &&
4918 kvm_cpu_has_interrupt(vcpu));
4919 }
4920
4921 void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4922 {
4923 int me;
4924 int cpu = vcpu->cpu;
4925
4926 if (waitqueue_active(&vcpu->wq)) {
4927 wake_up_interruptible(&vcpu->wq);
4928 ++vcpu->stat.halt_wakeup;
4929 }
4930
4931 me = get_cpu();
4932 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
4933 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
4934 smp_send_reschedule(cpu);
4935 put_cpu();
4936 }
4937
4938 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
4939 {
4940 return kvm_x86_ops->interrupt_allowed(vcpu);
4941 }
4942
4943 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
4944 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
4945 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
4946 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
4947 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
Linus' kernel tree