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be2net: account for skb allocation failures
[linux-2.6.git] / sound / pci / ens1370.c
blob863eafea691f24cc2efe984292f509851f1e8491
1 /*
2 * Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
4 * Thomas Sailer <sailer@ife.ee.ethz.ch>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22 /* Power-Management-Code ( CONFIG_PM )
23 * for ens1371 only ( FIXME )
24 * derived from cs4281.c, atiixp.c and via82xx.c
25 * using http://www.alsa-project.org/~tiwai/writing-an-alsa-driver/
26 * by Kurt J. Bosch
27 */
28
29 #include <asm/io.h>
30 #include <linux/delay.h>
31 #include <linux/interrupt.h>
32 #include <linux/init.h>
33 #include <linux/pci.h>
34 #include <linux/slab.h>
35 #include <linux/gameport.h>
36 #include <linux/moduleparam.h>
37 #include <linux/mutex.h>
38
39 #include <sound/core.h>
40 #include <sound/control.h>
41 #include <sound/pcm.h>
42 #include <sound/rawmidi.h>
43 #ifdef CHIP1371
44 #include <sound/ac97_codec.h>
45 #else
46 #include <sound/ak4531_codec.h>
47 #endif
48 #include <sound/initval.h>
49 #include <sound/asoundef.h>
50
51 #ifndef CHIP1371
52 #undef CHIP1370
53 #define CHIP1370
54 #endif
55
56 #ifdef CHIP1370
57 #define DRIVER_NAME "ENS1370"
58 #else
59 #define DRIVER_NAME "ENS1371"
60 #endif
61
62
63 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>");
64 MODULE_LICENSE("GPL");
65 #ifdef CHIP1370
66 MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
67 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370},"
68 "{Creative Labs,SB PCI64/128 (ES1370)}}");
69 #endif
70 #ifdef CHIP1371
71 MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
72 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73},"
73 "{Ensoniq,AudioPCI ES1373},"
74 "{Creative Labs,Ectiva EV1938},"
75 "{Creative Labs,SB PCI64/128 (ES1371/73)},"
76 "{Creative Labs,Vibra PCI128},"
77 "{Ectiva,EV1938}}");
78 #endif
79
80 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
81 #define SUPPORT_JOYSTICK
82 #endif
83
84 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
85 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
86 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
87 #ifdef SUPPORT_JOYSTICK
88 #ifdef CHIP1371
89 static int joystick_port[SNDRV_CARDS];
90 #else
91 static int joystick[SNDRV_CARDS];
92 #endif
93 #endif
94 #ifdef CHIP1371
95 static int spdif[SNDRV_CARDS];
96 static int lineio[SNDRV_CARDS];
97 #endif
98
99 module_param_array(index, int, NULL, 0444);
100 MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
101 module_param_array(id, charp, NULL, 0444);
102 MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
103 module_param_array(enable, bool, NULL, 0444);
104 MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
105 #ifdef SUPPORT_JOYSTICK
106 #ifdef CHIP1371
107 module_param_array(joystick_port, int, NULL, 0444);
108 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
109 #else
110 module_param_array(joystick, bool, NULL, 0444);
111 MODULE_PARM_DESC(joystick, "Enable joystick.");
112 #endif
113 #endif /* SUPPORT_JOYSTICK */
114 #ifdef CHIP1371
115 module_param_array(spdif, int, NULL, 0444);
116 MODULE_PARM_DESC(spdif, "S/PDIF output (-1 = none, 0 = auto, 1 = force).");
117 module_param_array(lineio, int, NULL, 0444);
118 MODULE_PARM_DESC(lineio, "Line In to Rear Out (0 = auto, 1 = force).");
119 #endif
120
121 /* ES1371 chip ID */
122 /* This is a little confusing because all ES1371 compatible chips have the
123 same DEVICE_ID, the only thing differentiating them is the REV_ID field.
124 This is only significant if you want to enable features on the later parts.
125 Yes, I know it's stupid and why didn't we use the sub IDs?
126 */
127 #define ES1371REV_ES1373_A 0x04
128 #define ES1371REV_ES1373_B 0x06
129 #define ES1371REV_CT5880_A 0x07
130 #define CT5880REV_CT5880_C 0x02
131 #define CT5880REV_CT5880_D 0x03 /* ??? -jk */
132 #define CT5880REV_CT5880_E 0x04 /* mw */
133 #define ES1371REV_ES1371_B 0x09
134 #define EV1938REV_EV1938_A 0x00
135 #define ES1371REV_ES1373_8 0x08
136
137 /*
138 * Direct registers
139 */
140
141 #define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
142
143 #define ES_REG_CONTROL 0x00 /* R/W: Interrupt/Chip select control register */
144 #define ES_1370_ADC_STOP (1<<31) /* disable capture buffer transfers */
145 #define ES_1370_XCTL1 (1<<30) /* general purpose output bit */
146 #define ES_1373_BYPASS_P1 (1<<31) /* bypass SRC for PB1 */
147 #define ES_1373_BYPASS_P2 (1<<30) /* bypass SRC for PB2 */
148 #define ES_1373_BYPASS_R (1<<29) /* bypass SRC for REC */
149 #define ES_1373_TEST_BIT (1<<28) /* should be set to 0 for normal operation */
150 #define ES_1373_RECEN_B (1<<27) /* mix record with playback for I2S/SPDIF out */
151 #define ES_1373_SPDIF_THRU (1<<26) /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
152 #define ES_1371_JOY_ASEL(o) (((o)&0x03)<<24)/* joystick port mapping */
153 #define ES_1371_JOY_ASELM (0x03<<24) /* mask for above */
154 #define ES_1371_JOY_ASELI(i) (((i)>>24)&0x03)
155 #define ES_1371_GPIO_IN(i) (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
156 #define ES_1370_PCLKDIVO(o) (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
157 #define ES_1370_PCLKDIVM ((0x1fff)<<16) /* mask for above */
158 #define ES_1370_PCLKDIVI(i) (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
159 #define ES_1371_GPIO_OUT(o) (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
160 #define ES_1371_GPIO_OUTM (0x0f<<16) /* mask for above */
161 #define ES_MSFMTSEL (1<<15) /* MPEG serial data format; 0 = SONY, 1 = I2S */
162 #define ES_1370_M_SBB (1<<14) /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
163 #define ES_1371_SYNC_RES (1<<14) /* Warm AC97 reset */
164 #define ES_1370_WTSRSEL(o) (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
165 #define ES_1370_WTSRSELM (0x03<<12) /* mask for above */
166 #define ES_1371_ADC_STOP (1<<13) /* disable CCB transfer capture information */
167 #define ES_1371_PWR_INTRM (1<<12) /* power level change interrupts enable */
168 #define ES_1370_DAC_SYNC (1<<11) /* DAC's are synchronous */
169 #define ES_1371_M_CB (1<<11) /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
170 #define ES_CCB_INTRM (1<<10) /* CCB voice interrupts enable */
171 #define ES_1370_M_CB (1<<9) /* capture clock source; 0 = ADC; 1 = MPEG */
172 #define ES_1370_XCTL0 (1<<8) /* generap purpose output bit */
173 #define ES_1371_PDLEV(o) (((o)&0x03)<<8) /* current power down level */
174 #define ES_1371_PDLEVM (0x03<<8) /* mask for above */
175 #define ES_BREQ (1<<7) /* memory bus request enable */
176 #define ES_DAC1_EN (1<<6) /* DAC1 playback channel enable */
177 #define ES_DAC2_EN (1<<5) /* DAC2 playback channel enable */
178 #define ES_ADC_EN (1<<4) /* ADC capture channel enable */
179 #define ES_UART_EN (1<<3) /* UART enable */
180 #define ES_JYSTK_EN (1<<2) /* Joystick module enable */
181 #define ES_1370_CDC_EN (1<<1) /* Codec interface enable */
182 #define ES_1371_XTALCKDIS (1<<1) /* Xtal clock disable */
183 #define ES_1370_SERR_DISABLE (1<<0) /* PCI serr signal disable */
184 #define ES_1371_PCICLKDIS (1<<0) /* PCI clock disable */
185 #define ES_REG_STATUS 0x04 /* R/O: Interrupt/Chip select status register */
186 #define ES_INTR (1<<31) /* Interrupt is pending */
187 #define ES_1371_ST_AC97_RST (1<<29) /* CT5880 AC'97 Reset bit */
188 #define ES_1373_REAR_BIT27 (1<<27) /* rear bits: 000 - front, 010 - mirror, 101 - separate */
189 #define ES_1373_REAR_BIT26 (1<<26)
190 #define ES_1373_REAR_BIT24 (1<<24)
191 #define ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
192 #define ES_1373_SPDIF_EN (1<<18) /* SPDIF enable */
193 #define ES_1373_SPDIF_TEST (1<<17) /* SPDIF test */
194 #define ES_1371_TEST (1<<16) /* test ASIC */
195 #define ES_1373_GPIO_INT(i) (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
196 #define ES_1370_CSTAT (1<<10) /* CODEC is busy or register write in progress */
197 #define ES_1370_CBUSY (1<<9) /* CODEC is busy */
198 #define ES_1370_CWRIP (1<<8) /* CODEC register write in progress */
199 #define ES_1371_SYNC_ERR (1<<8) /* CODEC synchronization error occurred */
200 #define ES_1371_VC(i) (((i)>>6)&0x03) /* voice code from CCB module */
201 #define ES_1370_VC(i) (((i)>>5)&0x03) /* voice code from CCB module */
202 #define ES_1371_MPWR (1<<5) /* power level interrupt pending */
203 #define ES_MCCB (1<<4) /* CCB interrupt pending */
204 #define ES_UART (1<<3) /* UART interrupt pending */
205 #define ES_DAC1 (1<<2) /* DAC1 channel interrupt pending */
206 #define ES_DAC2 (1<<1) /* DAC2 channel interrupt pending */
207 #define ES_ADC (1<<0) /* ADC channel interrupt pending */
208 #define ES_REG_UART_DATA 0x08 /* R/W: UART data register */
209 #define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
210 #define ES_RXINT (1<<7) /* RX interrupt occurred */
211 #define ES_TXINT (1<<2) /* TX interrupt occurred */
212 #define ES_TXRDY (1<<1) /* transmitter ready */
213 #define ES_RXRDY (1<<0) /* receiver ready */
214 #define ES_REG_UART_CONTROL 0x09 /* W/O: UART control register */
215 #define ES_RXINTEN (1<<7) /* RX interrupt enable */
216 #define ES_TXINTENO(o) (((o)&0x03)<<5) /* TX interrupt enable */
217 #define ES_TXINTENM (0x03<<5) /* mask for above */
218 #define ES_TXINTENI(i) (((i)>>5)&0x03)
219 #define ES_CNTRL(o) (((o)&0x03)<<0) /* control */
220 #define ES_CNTRLM (0x03<<0) /* mask for above */
221 #define ES_REG_UART_RES 0x0a /* R/W: UART reserver register */
222 #define ES_TEST_MODE (1<<0) /* test mode enabled */
223 #define ES_REG_MEM_PAGE 0x0c /* R/W: Memory page register */
224 #define ES_MEM_PAGEO(o) (((o)&0x0f)<<0) /* memory page select - out */
225 #define ES_MEM_PAGEM (0x0f<<0) /* mask for above */
226 #define ES_MEM_PAGEI(i) (((i)>>0)&0x0f) /* memory page select - in */
227 #define ES_REG_1370_CODEC 0x10 /* W/O: Codec write register address */
228 #define ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
229 #define ES_REG_1371_CODEC 0x14 /* W/R: Codec Read/Write register address */
230 #define ES_1371_CODEC_RDY (1<<31) /* codec ready */
231 #define ES_1371_CODEC_WIP (1<<30) /* codec register access in progress */
232 #define EV_1938_CODEC_MAGIC (1<<26)
233 #define ES_1371_CODEC_PIRD (1<<23) /* codec read/write select register */
234 #define ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
235 #define ES_1371_CODEC_READS(a) ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
236 #define ES_1371_CODEC_READ(i) (((i)>>0)&0xffff)
237
238 #define ES_REG_1371_SMPRATE 0x10 /* W/R: Codec rate converter interface register */
239 #define ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
240 #define ES_1371_SRC_RAM_ADDRM (0x7f<<25) /* mask for above */
241 #define ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
242 #define ES_1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */
243 #define ES_1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */
244 #define ES_1371_SRC_DISABLE (1<<22) /* sample rate converter disable */
245 #define ES_1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */
246 #define ES_1371_DIS_P2 (1<<20) /* playback channel 1 accumulator update disable */
247 #define ES_1371_DIS_R1 (1<<19) /* capture channel accumulator update disable */
248 #define ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
249 #define ES_1371_SRC_RAM_DATAM (0xffff<<0) /* mask for above */
250 #define ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
251
252 #define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
253 #define ES_1371_JFAST (1<<31) /* fast joystick timing */
254 #define ES_1371_HIB (1<<30) /* host interrupt blocking enable */
255 #define ES_1371_VSB (1<<29) /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
256 #define ES_1371_VMPUO(o) (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
257 #define ES_1371_VMPUM (0x03<<27) /* mask for above */
258 #define ES_1371_VMPUI(i) (((i)>>27)&0x03)/* base register address */
259 #define ES_1371_VCDCO(o) (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
260 #define ES_1371_VCDCM (0x03<<25) /* mask for above */
261 #define ES_1371_VCDCI(i) (((i)>>25)&0x03)/* CODEC address */
262 #define ES_1371_FIRQ (1<<24) /* force an interrupt */
263 #define ES_1371_SDMACAP (1<<23) /* enable event capture for slave DMA controller */
264 #define ES_1371_SPICAP (1<<22) /* enable event capture for slave IRQ controller */
265 #define ES_1371_MDMACAP (1<<21) /* enable event capture for master DMA controller */
266 #define ES_1371_MPICAP (1<<20) /* enable event capture for master IRQ controller */
267 #define ES_1371_ADCAP (1<<19) /* enable event capture for ADLIB register; 0x388xH */
268 #define ES_1371_SVCAP (1<<18) /* enable event capture for SB registers */
269 #define ES_1371_CDCCAP (1<<17) /* enable event capture for CODEC registers */
270 #define ES_1371_BACAP (1<<16) /* enable event capture for SoundScape base address */
271 #define ES_1371_EXI(i) (((i)>>8)&0x07) /* event number */
272 #define ES_1371_AI(i) (((i)>>3)&0x1f) /* event significant I/O address */
273 #define ES_1371_WR (1<<2) /* event capture; 0 = read; 1 = write */
274 #define ES_1371_LEGINT (1<<0) /* interrupt for legacy events; 0 = interrupt did occur */
275
276 #define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
277
278 #define ES_REG_SERIAL 0x20 /* R/W: Serial interface control register */
279 #define ES_1371_DAC_TEST (1<<22) /* DAC test mode enable */
280 #define ES_P2_END_INCO(o) (((o)&0x07)<<19)/* binary offset value to increment / loop end */
281 #define ES_P2_END_INCM (0x07<<19) /* mask for above */
282 #define ES_P2_END_INCI(i) (((i)>>16)&0x07)/* binary offset value to increment / loop end */
283 #define ES_P2_ST_INCO(o) (((o)&0x07)<<16)/* binary offset value to increment / start */
284 #define ES_P2_ST_INCM (0x07<<16) /* mask for above */
285 #define ES_P2_ST_INCI(i) (((i)<<16)&0x07)/* binary offset value to increment / start */
286 #define ES_R1_LOOP_SEL (1<<15) /* ADC; 0 - loop mode; 1 = stop mode */
287 #define ES_P2_LOOP_SEL (1<<14) /* DAC2; 0 - loop mode; 1 = stop mode */
288 #define ES_P1_LOOP_SEL (1<<13) /* DAC1; 0 - loop mode; 1 = stop mode */
289 #define ES_P2_PAUSE (1<<12) /* DAC2; 0 - play mode; 1 = pause mode */
290 #define ES_P1_PAUSE (1<<11) /* DAC1; 0 - play mode; 1 = pause mode */
291 #define ES_R1_INT_EN (1<<10) /* ADC interrupt enable */
292 #define ES_P2_INT_EN (1<<9) /* DAC2 interrupt enable */
293 #define ES_P1_INT_EN (1<<8) /* DAC1 interrupt enable */
294 #define ES_P1_SCT_RLD (1<<7) /* force sample counter reload for DAC1 */
295 #define ES_P2_DAC_SEN (1<<6) /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
296 #define ES_R1_MODEO(o) (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
297 #define ES_R1_MODEM (0x03<<4) /* mask for above */
298 #define ES_R1_MODEI(i) (((i)>>4)&0x03)
299 #define ES_P2_MODEO(o) (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
300 #define ES_P2_MODEM (0x03<<2) /* mask for above */
301 #define ES_P2_MODEI(i) (((i)>>2)&0x03)
302 #define ES_P1_MODEO(o) (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
303 #define ES_P1_MODEM (0x03<<0) /* mask for above */
304 #define ES_P1_MODEI(i) (((i)>>0)&0x03)
305
306 #define ES_REG_DAC1_COUNT 0x24 /* R/W: DAC1 sample count register */
307 #define ES_REG_DAC2_COUNT 0x28 /* R/W: DAC2 sample count register */
308 #define ES_REG_ADC_COUNT 0x2c /* R/W: ADC sample count register */
309 #define ES_REG_CURR_COUNT(i) (((i)>>16)&0xffff)
310 #define ES_REG_COUNTO(o) (((o)&0xffff)<<0)
311 #define ES_REG_COUNTM (0xffff<<0)
312 #define ES_REG_COUNTI(i) (((i)>>0)&0xffff)
313
314 #define ES_REG_DAC1_FRAME 0x30 /* R/W: PAGE 0x0c; DAC1 frame address */
315 #define ES_REG_DAC1_SIZE 0x34 /* R/W: PAGE 0x0c; DAC1 frame size */
316 #define ES_REG_DAC2_FRAME 0x38 /* R/W: PAGE 0x0c; DAC2 frame address */
317 #define ES_REG_DAC2_SIZE 0x3c /* R/W: PAGE 0x0c; DAC2 frame size */
318 #define ES_REG_ADC_FRAME 0x30 /* R/W: PAGE 0x0d; ADC frame address */
319 #define ES_REG_ADC_SIZE 0x34 /* R/W: PAGE 0x0d; ADC frame size */
320 #define ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
321 #define ES_REG_FCURR_COUNTM (0xffff<<16)
322 #define ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
323 #define ES_REG_FSIZEO(o) (((o)&0xffff)<<0)
324 #define ES_REG_FSIZEM (0xffff<<0)
325 #define ES_REG_FSIZEI(i) (((i)>>0)&0xffff)
326 #define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
327 #define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
328
329 #define ES_REG_UART_FIFO 0x30 /* R/W: PAGE 0x0e; UART FIFO register */
330 #define ES_REG_UF_VALID (1<<8)
331 #define ES_REG_UF_BYTEO(o) (((o)&0xff)<<0)
332 #define ES_REG_UF_BYTEM (0xff<<0)
333 #define ES_REG_UF_BYTEI(i) (((i)>>0)&0xff)
334
335
336 /*
337 * Pages
338 */
339
340 #define ES_PAGE_DAC 0x0c
341 #define ES_PAGE_ADC 0x0d
342 #define ES_PAGE_UART 0x0e
343 #define ES_PAGE_UART1 0x0f
344
345 /*
346 * Sample rate converter addresses
347 */
348
349 #define ES_SMPREG_DAC1 0x70
350 #define ES_SMPREG_DAC2 0x74
351 #define ES_SMPREG_ADC 0x78
352 #define ES_SMPREG_VOL_ADC 0x6c
353 #define ES_SMPREG_VOL_DAC1 0x7c
354 #define ES_SMPREG_VOL_DAC2 0x7e
355 #define ES_SMPREG_TRUNC_N 0x00
356 #define ES_SMPREG_INT_REGS 0x01
357 #define ES_SMPREG_ACCUM_FRAC 0x02
358 #define ES_SMPREG_VFREQ_FRAC 0x03
359
360 /*
361 * Some contants
362 */
363
364 #define ES_1370_SRCLOCK 1411200
365 #define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
366
367 /*
368 * Open modes
369 */
370
371 #define ES_MODE_PLAY1 0x0001
372 #define ES_MODE_PLAY2 0x0002
373 #define ES_MODE_CAPTURE 0x0004
374
375 #define ES_MODE_OUTPUT 0x0001 /* for MIDI */
376 #define ES_MODE_INPUT 0x0002 /* for MIDI */
377
378 /*
379
380 */
381
382 struct ensoniq {
383 spinlock_t reg_lock;
384 struct mutex src_mutex;
385
386 int irq;
387
388 unsigned long playback1size;
389 unsigned long playback2size;
390 unsigned long capture3size;
391
392 unsigned long port;
393 unsigned int mode;
394 unsigned int uartm; /* UART mode */
395
396 unsigned int ctrl; /* control register */
397 unsigned int sctrl; /* serial control register */
398 unsigned int cssr; /* control status register */
399 unsigned int uartc; /* uart control register */
400 unsigned int rev; /* chip revision */
401
402 union {
403 #ifdef CHIP1371
404 struct {
405 struct snd_ac97 *ac97;
406 } es1371;
407 #else
408 struct {
409 int pclkdiv_lock;
410 struct snd_ak4531 *ak4531;
411 } es1370;
412 #endif
413 } u;
414
415 struct pci_dev *pci;
416 struct snd_card *card;
417 struct snd_pcm *pcm1; /* DAC1/ADC PCM */
418 struct snd_pcm *pcm2; /* DAC2 PCM */
419 struct snd_pcm_substream *playback1_substream;
420 struct snd_pcm_substream *playback2_substream;
421 struct snd_pcm_substream *capture_substream;
422 unsigned int p1_dma_size;
423 unsigned int p2_dma_size;
424 unsigned int c_dma_size;
425 unsigned int p1_period_size;
426 unsigned int p2_period_size;
427 unsigned int c_period_size;
428 struct snd_rawmidi *rmidi;
429 struct snd_rawmidi_substream *midi_input;
430 struct snd_rawmidi_substream *midi_output;
431
432 unsigned int spdif;
433 unsigned int spdif_default;
434 unsigned int spdif_stream;
435
436 #ifdef CHIP1370
437 struct snd_dma_buffer dma_bug;
438 #endif
439
440 #ifdef SUPPORT_JOYSTICK
441 struct gameport *gameport;
442 #endif
443 };
444
445 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id);
446
447 static DEFINE_PCI_DEVICE_TABLE(snd_audiopci_ids) = {
448 #ifdef CHIP1370
449 { PCI_VDEVICE(ENSONIQ, 0x5000), 0, }, /* ES1370 */
450 #endif
451 #ifdef CHIP1371
452 { PCI_VDEVICE(ENSONIQ, 0x1371), 0, }, /* ES1371 */
453 { PCI_VDEVICE(ENSONIQ, 0x5880), 0, }, /* ES1373 - CT5880 */
454 { PCI_VDEVICE(ECTIVA, 0x8938), 0, }, /* Ectiva EV1938 */
455 #endif
456 { 0, }
457 };
458
459 MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
460
461 /*
462 * constants
463 */
464
465 #define POLL_COUNT 0xa000
466
467 #ifdef CHIP1370
468 static unsigned int snd_es1370_fixed_rates[] =
469 {5512, 11025, 22050, 44100};
470 static struct snd_pcm_hw_constraint_list snd_es1370_hw_constraints_rates = {
471 .count = 4,
472 .list = snd_es1370_fixed_rates,
473 .mask = 0,
474 };
475 static struct snd_ratnum es1370_clock = {
476 .num = ES_1370_SRCLOCK,
477 .den_min = 29,
478 .den_max = 353,
479 .den_step = 1,
480 };
481 static struct snd_pcm_hw_constraint_ratnums snd_es1370_hw_constraints_clock = {
482 .nrats = 1,
483 .rats = &es1370_clock,
484 };
485 #else
486 static struct snd_ratden es1371_dac_clock = {
487 .num_min = 3000 * (1 << 15),
488 .num_max = 48000 * (1 << 15),
489 .num_step = 3000,
490 .den = 1 << 15,
491 };
492 static struct snd_pcm_hw_constraint_ratdens snd_es1371_hw_constraints_dac_clock = {
493 .nrats = 1,
494 .rats = &es1371_dac_clock,
495 };
496 static struct snd_ratnum es1371_adc_clock = {
497 .num = 48000 << 15,
498 .den_min = 32768,
499 .den_max = 393216,
500 .den_step = 1,
501 };
502 static struct snd_pcm_hw_constraint_ratnums snd_es1371_hw_constraints_adc_clock = {
503 .nrats = 1,
504 .rats = &es1371_adc_clock,
505 };
506 #endif
507 static const unsigned int snd_ensoniq_sample_shift[] =
508 {0, 1, 1, 2};
509
510 /*
511 * common I/O routines
512 */
513
514 #ifdef CHIP1371
515
516 static unsigned int snd_es1371_wait_src_ready(struct ensoniq * ensoniq)
517 {
518 unsigned int t, r = 0;
519
520 for (t = 0; t < POLL_COUNT; t++) {
521 r = inl(ES_REG(ensoniq, 1371_SMPRATE));
522 if ((r & ES_1371_SRC_RAM_BUSY) == 0)
523 return r;
524 cond_resched();
525 }
526 snd_printk(KERN_ERR "wait src ready timeout 0x%lx [0x%x]\n",
527 ES_REG(ensoniq, 1371_SMPRATE), r);
528 return 0;
529 }
530
531 static unsigned int snd_es1371_src_read(struct ensoniq * ensoniq, unsigned short reg)
532 {
533 unsigned int temp, i, orig, r;
534
535 /* wait for ready */
536 temp = orig = snd_es1371_wait_src_ready(ensoniq);
537
538 /* expose the SRC state bits */
539 r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
540 ES_1371_DIS_P2 | ES_1371_DIS_R1);
541 r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
542 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
543
544 /* now, wait for busy and the correct time to read */
545 temp = snd_es1371_wait_src_ready(ensoniq);
546
547 if ((temp & 0x00870000) != 0x00010000) {
548 /* wait for the right state */
549 for (i = 0; i < POLL_COUNT; i++) {
550 temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
551 if ((temp & 0x00870000) == 0x00010000)
552 break;
553 }
554 }
555
556 /* hide the state bits */
557 r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
558 ES_1371_DIS_P2 | ES_1371_DIS_R1);
559 r |= ES_1371_SRC_RAM_ADDRO(reg);
560 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
561
562 return temp;
563 }
564
565 static void snd_es1371_src_write(struct ensoniq * ensoniq,
566 unsigned short reg, unsigned short data)
567 {
568 unsigned int r;
569
570 r = snd_es1371_wait_src_ready(ensoniq) &
571 (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
572 ES_1371_DIS_P2 | ES_1371_DIS_R1);
573 r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
574 outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
575 }
576
577 #endif /* CHIP1371 */
578
579 #ifdef CHIP1370
580
581 static void snd_es1370_codec_write(struct snd_ak4531 *ak4531,
582 unsigned short reg, unsigned short val)
583 {
584 struct ensoniq *ensoniq = ak4531->private_data;
585 unsigned long end_time = jiffies + HZ / 10;
586
587 #if 0
588 printk(KERN_DEBUG
589 "CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n",
590 reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
591 #endif
592 do {
593 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
594 outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
595 return;
596 }
597 schedule_timeout_uninterruptible(1);
598 } while (time_after(end_time, jiffies));
599 snd_printk(KERN_ERR "codec write timeout, status = 0x%x\n",
600 inl(ES_REG(ensoniq, STATUS)));
601 }
602
603 #endif /* CHIP1370 */
604
605 #ifdef CHIP1371
606
607 static inline bool is_ev1938(struct ensoniq *ensoniq)
608 {
609 return ensoniq->pci->device == 0x8938;
610 }
611
612 static void snd_es1371_codec_write(struct snd_ac97 *ac97,
613 unsigned short reg, unsigned short val)
614 {
615 struct ensoniq *ensoniq = ac97->private_data;
616 unsigned int t, x, flag;
617
618 flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0;
619 mutex_lock(&ensoniq->src_mutex);
620 for (t = 0; t < POLL_COUNT; t++) {
621 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
622 /* save the current state for latter */
623 x = snd_es1371_wait_src_ready(ensoniq);
624 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
625 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
626 ES_REG(ensoniq, 1371_SMPRATE));
627 /* wait for not busy (state 0) first to avoid
628 transition states */
629 for (t = 0; t < POLL_COUNT; t++) {
630 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
631 0x00000000)
632 break;
633 }
634 /* wait for a SAFE time to write addr/data and then do it, dammit */
635 for (t = 0; t < POLL_COUNT; t++) {
636 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
637 0x00010000)
638 break;
639 }
640 outl(ES_1371_CODEC_WRITE(reg, val) | flag,
641 ES_REG(ensoniq, 1371_CODEC));
642 /* restore SRC reg */
643 snd_es1371_wait_src_ready(ensoniq);
644 outl(x, ES_REG(ensoniq, 1371_SMPRATE));
645 mutex_unlock(&ensoniq->src_mutex);
646 return;
647 }
648 }
649 mutex_unlock(&ensoniq->src_mutex);
650 snd_printk(KERN_ERR "codec write timeout at 0x%lx [0x%x]\n",
651 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
652 }
653
654 static unsigned short snd_es1371_codec_read(struct snd_ac97 *ac97,
655 unsigned short reg)
656 {
657 struct ensoniq *ensoniq = ac97->private_data;
658 unsigned int t, x, flag, fail = 0;
659
660 flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0;
661 __again:
662 mutex_lock(&ensoniq->src_mutex);
663 for (t = 0; t < POLL_COUNT; t++) {
664 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
665 /* save the current state for latter */
666 x = snd_es1371_wait_src_ready(ensoniq);
667 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
668 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
669 ES_REG(ensoniq, 1371_SMPRATE));
670 /* wait for not busy (state 0) first to avoid
671 transition states */
672 for (t = 0; t < POLL_COUNT; t++) {
673 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
674 0x00000000)
675 break;
676 }
677 /* wait for a SAFE time to write addr/data and then do it, dammit */
678 for (t = 0; t < POLL_COUNT; t++) {
679 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
680 0x00010000)
681 break;
682 }
683 outl(ES_1371_CODEC_READS(reg) | flag,
684 ES_REG(ensoniq, 1371_CODEC));
685 /* restore SRC reg */
686 snd_es1371_wait_src_ready(ensoniq);
687 outl(x, ES_REG(ensoniq, 1371_SMPRATE));
688 /* wait for WIP again */
689 for (t = 0; t < POLL_COUNT; t++) {
690 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
691 break;
692 }
693 /* now wait for the stinkin' data (RDY) */
694 for (t = 0; t < POLL_COUNT; t++) {
695 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) {
696 if (is_ev1938(ensoniq)) {
697 for (t = 0; t < 100; t++)
698 inl(ES_REG(ensoniq, CONTROL));
699 x = inl(ES_REG(ensoniq, 1371_CODEC));
700 }
701 mutex_unlock(&ensoniq->src_mutex);
702 return ES_1371_CODEC_READ(x);
703 }
704 }
705 mutex_unlock(&ensoniq->src_mutex);
706 if (++fail > 10) {
707 snd_printk(KERN_ERR "codec read timeout (final) "
708 "at 0x%lx, reg = 0x%x [0x%x]\n",
709 ES_REG(ensoniq, 1371_CODEC), reg,
710 inl(ES_REG(ensoniq, 1371_CODEC)));
711 return 0;
712 }
713 goto __again;
714 }
715 }
716 mutex_unlock(&ensoniq->src_mutex);
717 snd_printk(KERN_ERR "es1371: codec read timeout at 0x%lx [0x%x]\n",
718 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
719 return 0;
720 }
721
722 static void snd_es1371_codec_wait(struct snd_ac97 *ac97)
723 {
724 msleep(750);
725 snd_es1371_codec_read(ac97, AC97_RESET);
726 snd_es1371_codec_read(ac97, AC97_VENDOR_ID1);
727 snd_es1371_codec_read(ac97, AC97_VENDOR_ID2);
728 msleep(50);
729 }
730
731 static void snd_es1371_adc_rate(struct ensoniq * ensoniq, unsigned int rate)
732 {
733 unsigned int n, truncm, freq, result;
734
735 mutex_lock(&ensoniq->src_mutex);
736 n = rate / 3000;
737 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
738 n--;
739 truncm = (21 * n - 1) | 1;
740 freq = ((48000UL << 15) / rate) * n;
741 result = (48000UL << 15) / (freq / n);
742 if (rate >= 24000) {
743 if (truncm > 239)
744 truncm = 239;
745 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
746 (((239 - truncm) >> 1) << 9) | (n << 4));
747 } else {
748 if (truncm > 119)
749 truncm = 119;
750 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
751 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
752 }
753 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
754 (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC +
755 ES_SMPREG_INT_REGS) & 0x00ff) |
756 ((freq >> 5) & 0xfc00));
757 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
758 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
759 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
760 mutex_unlock(&ensoniq->src_mutex);
761 }
762
763 static void snd_es1371_dac1_rate(struct ensoniq * ensoniq, unsigned int rate)
764 {
765 unsigned int freq, r;
766
767 mutex_lock(&ensoniq->src_mutex);
768 freq = ((rate << 15) + 1500) / 3000;
769 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
770 ES_1371_DIS_P2 | ES_1371_DIS_R1)) |
771 ES_1371_DIS_P1;
772 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
773 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
774 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 +
775 ES_SMPREG_INT_REGS) & 0x00ff) |
776 ((freq >> 5) & 0xfc00));
777 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
778 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
779 ES_1371_DIS_P2 | ES_1371_DIS_R1));
780 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
781 mutex_unlock(&ensoniq->src_mutex);
782 }
783
784 static void snd_es1371_dac2_rate(struct ensoniq * ensoniq, unsigned int rate)
785 {
786 unsigned int freq, r;
787
788 mutex_lock(&ensoniq->src_mutex);
789 freq = ((rate << 15) + 1500) / 3000;
790 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
791 ES_1371_DIS_P1 | ES_1371_DIS_R1)) |
792 ES_1371_DIS_P2;
793 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
794 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
795 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 +
796 ES_SMPREG_INT_REGS) & 0x00ff) |
797 ((freq >> 5) & 0xfc00));
798 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC,
799 freq & 0x7fff);
800 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
801 ES_1371_DIS_P1 | ES_1371_DIS_R1));
802 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
803 mutex_unlock(&ensoniq->src_mutex);
804 }
805
806 #endif /* CHIP1371 */
807
808 static int snd_ensoniq_trigger(struct snd_pcm_substream *substream, int cmd)
809 {
810 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
811 switch (cmd) {
812 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
813 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
814 {
815 unsigned int what = 0;
816 struct snd_pcm_substream *s;
817 snd_pcm_group_for_each_entry(s, substream) {
818 if (s == ensoniq->playback1_substream) {
819 what |= ES_P1_PAUSE;
820 snd_pcm_trigger_done(s, substream);
821 } else if (s == ensoniq->playback2_substream) {
822 what |= ES_P2_PAUSE;
823 snd_pcm_trigger_done(s, substream);
824 } else if (s == ensoniq->capture_substream)
825 return -EINVAL;
826 }
827 spin_lock(&ensoniq->reg_lock);
828 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
829 ensoniq->sctrl |= what;
830 else
831 ensoniq->sctrl &= ~what;
832 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
833 spin_unlock(&ensoniq->reg_lock);
834 break;
835 }
836 case SNDRV_PCM_TRIGGER_START:
837 case SNDRV_PCM_TRIGGER_STOP:
838 {
839 unsigned int what = 0;
840 struct snd_pcm_substream *s;
841 snd_pcm_group_for_each_entry(s, substream) {
842 if (s == ensoniq->playback1_substream) {
843 what |= ES_DAC1_EN;
844 snd_pcm_trigger_done(s, substream);
845 } else if (s == ensoniq->playback2_substream) {
846 what |= ES_DAC2_EN;
847 snd_pcm_trigger_done(s, substream);
848 } else if (s == ensoniq->capture_substream) {
849 what |= ES_ADC_EN;
850 snd_pcm_trigger_done(s, substream);
851 }
852 }
853 spin_lock(&ensoniq->reg_lock);
854 if (cmd == SNDRV_PCM_TRIGGER_START)
855 ensoniq->ctrl |= what;
856 else
857 ensoniq->ctrl &= ~what;
858 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
859 spin_unlock(&ensoniq->reg_lock);
860 break;
861 }
862 default:
863 return -EINVAL;
864 }
865 return 0;
866 }
867
868 /*
869 * PCM part
870 */
871
872 static int snd_ensoniq_hw_params(struct snd_pcm_substream *substream,
873 struct snd_pcm_hw_params *hw_params)
874 {
875 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
876 }
877
878 static int snd_ensoniq_hw_free(struct snd_pcm_substream *substream)
879 {
880 return snd_pcm_lib_free_pages(substream);
881 }
882
883 static int snd_ensoniq_playback1_prepare(struct snd_pcm_substream *substream)
884 {
885 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
886 struct snd_pcm_runtime *runtime = substream->runtime;
887 unsigned int mode = 0;
888
889 ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
890 ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
891 if (snd_pcm_format_width(runtime->format) == 16)
892 mode |= 0x02;
893 if (runtime->channels > 1)
894 mode |= 0x01;
895 spin_lock_irq(&ensoniq->reg_lock);
896 ensoniq->ctrl &= ~ES_DAC1_EN;
897 #ifdef CHIP1371
898 /* 48k doesn't need SRC (it breaks AC3-passthru) */
899 if (runtime->rate == 48000)
900 ensoniq->ctrl |= ES_1373_BYPASS_P1;
901 else
902 ensoniq->ctrl &= ~ES_1373_BYPASS_P1;
903 #endif
904 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
905 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
906 outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
907 outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
908 ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM);
909 ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
910 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
911 outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
912 ES_REG(ensoniq, DAC1_COUNT));
913 #ifdef CHIP1370
914 ensoniq->ctrl &= ~ES_1370_WTSRSELM;
915 switch (runtime->rate) {
916 case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
917 case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
918 case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
919 case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
920 default: snd_BUG();
921 }
922 #endif
923 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
924 spin_unlock_irq(&ensoniq->reg_lock);
925 #ifndef CHIP1370
926 snd_es1371_dac1_rate(ensoniq, runtime->rate);
927 #endif
928 return 0;
929 }
930
931 static int snd_ensoniq_playback2_prepare(struct snd_pcm_substream *substream)
932 {
933 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
934 struct snd_pcm_runtime *runtime = substream->runtime;
935 unsigned int mode = 0;
936
937 ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
938 ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
939 if (snd_pcm_format_width(runtime->format) == 16)
940 mode |= 0x02;
941 if (runtime->channels > 1)
942 mode |= 0x01;
943 spin_lock_irq(&ensoniq->reg_lock);
944 ensoniq->ctrl &= ~ES_DAC2_EN;
945 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
946 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
947 outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
948 outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
949 ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
950 ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM);
951 ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
952 ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
953 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
954 outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
955 ES_REG(ensoniq, DAC2_COUNT));
956 #ifdef CHIP1370
957 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
958 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
959 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
960 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
961 }
962 #endif
963 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
964 spin_unlock_irq(&ensoniq->reg_lock);
965 #ifndef CHIP1370
966 snd_es1371_dac2_rate(ensoniq, runtime->rate);
967 #endif
968 return 0;
969 }
970
971 static int snd_ensoniq_capture_prepare(struct snd_pcm_substream *substream)
972 {
973 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
974 struct snd_pcm_runtime *runtime = substream->runtime;
975 unsigned int mode = 0;
976
977 ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
978 ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
979 if (snd_pcm_format_width(runtime->format) == 16)
980 mode |= 0x02;
981 if (runtime->channels > 1)
982 mode |= 0x01;
983 spin_lock_irq(&ensoniq->reg_lock);
984 ensoniq->ctrl &= ~ES_ADC_EN;
985 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
986 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
987 outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
988 outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
989 ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
990 ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
991 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
992 outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
993 ES_REG(ensoniq, ADC_COUNT));
994 #ifdef CHIP1370
995 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
996 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
997 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
998 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
999 }
1000 #endif
1001 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1002 spin_unlock_irq(&ensoniq->reg_lock);
1003 #ifndef CHIP1370
1004 snd_es1371_adc_rate(ensoniq, runtime->rate);
1005 #endif
1006 return 0;
1007 }
1008
1009 static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(struct snd_pcm_substream *substream)
1010 {
1011 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1012 size_t ptr;
1013
1014 spin_lock(&ensoniq->reg_lock);
1015 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
1016 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1017 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
1018 ptr = bytes_to_frames(substream->runtime, ptr);
1019 } else {
1020 ptr = 0;
1021 }
1022 spin_unlock(&ensoniq->reg_lock);
1023 return ptr;
1024 }
1025
1026 static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(struct snd_pcm_substream *substream)
1027 {
1028 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1029 size_t ptr;
1030
1031 spin_lock(&ensoniq->reg_lock);
1032 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
1033 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1034 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
1035 ptr = bytes_to_frames(substream->runtime, ptr);
1036 } else {
1037 ptr = 0;
1038 }
1039 spin_unlock(&ensoniq->reg_lock);
1040 return ptr;
1041 }
1042
1043 static snd_pcm_uframes_t snd_ensoniq_capture_pointer(struct snd_pcm_substream *substream)
1044 {
1045 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1046 size_t ptr;
1047
1048 spin_lock(&ensoniq->reg_lock);
1049 if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
1050 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1051 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
1052 ptr = bytes_to_frames(substream->runtime, ptr);
1053 } else {
1054 ptr = 0;
1055 }
1056 spin_unlock(&ensoniq->reg_lock);
1057 return ptr;
1058 }
1059
1060 static struct snd_pcm_hardware snd_ensoniq_playback1 =
1061 {
1062 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1063 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1064 SNDRV_PCM_INFO_MMAP_VALID |
1065 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1066 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1067 .rates =
1068 #ifndef CHIP1370
1069 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1070 #else
1071 (SNDRV_PCM_RATE_KNOT | /* 5512Hz rate */
1072 SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 |
1073 SNDRV_PCM_RATE_44100),
1074 #endif
1075 .rate_min = 4000,
1076 .rate_max = 48000,
1077 .channels_min = 1,
1078 .channels_max = 2,
1079 .buffer_bytes_max = (128*1024),
1080 .period_bytes_min = 64,
1081 .period_bytes_max = (128*1024),
1082 .periods_min = 1,
1083 .periods_max = 1024,
1084 .fifo_size = 0,
1085 };
1086
1087 static struct snd_pcm_hardware snd_ensoniq_playback2 =
1088 {
1089 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1090 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1091 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE |
1092 SNDRV_PCM_INFO_SYNC_START),
1093 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1094 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1095 .rate_min = 4000,
1096 .rate_max = 48000,
1097 .channels_min = 1,
1098 .channels_max = 2,
1099 .buffer_bytes_max = (128*1024),
1100 .period_bytes_min = 64,
1101 .period_bytes_max = (128*1024),
1102 .periods_min = 1,
1103 .periods_max = 1024,
1104 .fifo_size = 0,
1105 };
1106
1107 static struct snd_pcm_hardware snd_ensoniq_capture =
1108 {
1109 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1110 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1111 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1112 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1113 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1114 .rate_min = 4000,
1115 .rate_max = 48000,
1116 .channels_min = 1,
1117 .channels_max = 2,
1118 .buffer_bytes_max = (128*1024),
1119 .period_bytes_min = 64,
1120 .period_bytes_max = (128*1024),
1121 .periods_min = 1,
1122 .periods_max = 1024,
1123 .fifo_size = 0,
1124 };
1125
1126 static int snd_ensoniq_playback1_open(struct snd_pcm_substream *substream)
1127 {
1128 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1129 struct snd_pcm_runtime *runtime = substream->runtime;
1130
1131 ensoniq->mode |= ES_MODE_PLAY1;
1132 ensoniq->playback1_substream = substream;
1133 runtime->hw = snd_ensoniq_playback1;
1134 snd_pcm_set_sync(substream);
1135 spin_lock_irq(&ensoniq->reg_lock);
1136 if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
1137 ensoniq->spdif_stream = ensoniq->spdif_default;
1138 spin_unlock_irq(&ensoniq->reg_lock);
1139 #ifdef CHIP1370
1140 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1141 &snd_es1370_hw_constraints_rates);
1142 #else
1143 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1144 &snd_es1371_hw_constraints_dac_clock);
1145 #endif
1146 return 0;
1147 }
1148
1149 static int snd_ensoniq_playback2_open(struct snd_pcm_substream *substream)
1150 {
1151 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1152 struct snd_pcm_runtime *runtime = substream->runtime;
1153
1154 ensoniq->mode |= ES_MODE_PLAY2;
1155 ensoniq->playback2_substream = substream;
1156 runtime->hw = snd_ensoniq_playback2;
1157 snd_pcm_set_sync(substream);
1158 spin_lock_irq(&ensoniq->reg_lock);
1159 if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
1160 ensoniq->spdif_stream = ensoniq->spdif_default;
1161 spin_unlock_irq(&ensoniq->reg_lock);
1162 #ifdef CHIP1370
1163 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1164 &snd_es1370_hw_constraints_clock);
1165 #else
1166 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1167 &snd_es1371_hw_constraints_dac_clock);
1168 #endif
1169 return 0;
1170 }
1171
1172 static int snd_ensoniq_capture_open(struct snd_pcm_substream *substream)
1173 {
1174 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1175 struct snd_pcm_runtime *runtime = substream->runtime;
1176
1177 ensoniq->mode |= ES_MODE_CAPTURE;
1178 ensoniq->capture_substream = substream;
1179 runtime->hw = snd_ensoniq_capture;
1180 snd_pcm_set_sync(substream);
1181 #ifdef CHIP1370
1182 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1183 &snd_es1370_hw_constraints_clock);
1184 #else
1185 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1186 &snd_es1371_hw_constraints_adc_clock);
1187 #endif
1188 return 0;
1189 }
1190
1191 static int snd_ensoniq_playback1_close(struct snd_pcm_substream *substream)
1192 {
1193 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1194
1195 ensoniq->playback1_substream = NULL;
1196 ensoniq->mode &= ~ES_MODE_PLAY1;
1197 return 0;
1198 }
1199
1200 static int snd_ensoniq_playback2_close(struct snd_pcm_substream *substream)
1201 {
1202 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1203
1204 ensoniq->playback2_substream = NULL;
1205 spin_lock_irq(&ensoniq->reg_lock);
1206 #ifdef CHIP1370
1207 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
1208 #endif
1209 ensoniq->mode &= ~ES_MODE_PLAY2;
1210 spin_unlock_irq(&ensoniq->reg_lock);
1211 return 0;
1212 }
1213
1214 static int snd_ensoniq_capture_close(struct snd_pcm_substream *substream)
1215 {
1216 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1217
1218 ensoniq->capture_substream = NULL;
1219 spin_lock_irq(&ensoniq->reg_lock);
1220 #ifdef CHIP1370
1221 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
1222 #endif
1223 ensoniq->mode &= ~ES_MODE_CAPTURE;
1224 spin_unlock_irq(&ensoniq->reg_lock);
1225 return 0;
1226 }
1227
1228 static struct snd_pcm_ops snd_ensoniq_playback1_ops = {
1229 .open = snd_ensoniq_playback1_open,
1230 .close = snd_ensoniq_playback1_close,
1231 .ioctl = snd_pcm_lib_ioctl,
1232 .hw_params = snd_ensoniq_hw_params,
1233 .hw_free = snd_ensoniq_hw_free,
1234 .prepare = snd_ensoniq_playback1_prepare,
1235 .trigger = snd_ensoniq_trigger,
1236 .pointer = snd_ensoniq_playback1_pointer,
1237 };
1238
1239 static struct snd_pcm_ops snd_ensoniq_playback2_ops = {
1240 .open = snd_ensoniq_playback2_open,
1241 .close = snd_ensoniq_playback2_close,
1242 .ioctl = snd_pcm_lib_ioctl,
1243 .hw_params = snd_ensoniq_hw_params,
1244 .hw_free = snd_ensoniq_hw_free,
1245 .prepare = snd_ensoniq_playback2_prepare,
1246 .trigger = snd_ensoniq_trigger,
1247 .pointer = snd_ensoniq_playback2_pointer,
1248 };
1249
1250 static struct snd_pcm_ops snd_ensoniq_capture_ops = {
1251 .open = snd_ensoniq_capture_open,
1252 .close = snd_ensoniq_capture_close,
1253 .ioctl = snd_pcm_lib_ioctl,
1254 .hw_params = snd_ensoniq_hw_params,
1255 .hw_free = snd_ensoniq_hw_free,
1256 .prepare = snd_ensoniq_capture_prepare,
1257 .trigger = snd_ensoniq_trigger,
1258 .pointer = snd_ensoniq_capture_pointer,
1259 };
1260
1261 static int __devinit snd_ensoniq_pcm(struct ensoniq * ensoniq, int device,
1262 struct snd_pcm ** rpcm)
1263 {
1264 struct snd_pcm *pcm;
1265 int err;
1266
1267 if (rpcm)
1268 *rpcm = NULL;
1269 #ifdef CHIP1370
1270 err = snd_pcm_new(ensoniq->card, "ES1370/1", device, 1, 1, &pcm);
1271 #else
1272 err = snd_pcm_new(ensoniq->card, "ES1371/1", device, 1, 1, &pcm);
1273 #endif
1274 if (err < 0)
1275 return err;
1276
1277 #ifdef CHIP1370
1278 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1279 #else
1280 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1281 #endif
1282 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
1283
1284 pcm->private_data = ensoniq;
1285 pcm->info_flags = 0;
1286 #ifdef CHIP1370
1287 strcpy(pcm->name, "ES1370 DAC2/ADC");
1288 #else
1289 strcpy(pcm->name, "ES1371 DAC2/ADC");
1290 #endif
1291 ensoniq->pcm1 = pcm;
1292
1293 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1294 snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1295
1296 if (rpcm)
1297 *rpcm = pcm;
1298 return 0;
1299 }
1300
1301 static int __devinit snd_ensoniq_pcm2(struct ensoniq * ensoniq, int device,
1302 struct snd_pcm ** rpcm)
1303 {
1304 struct snd_pcm *pcm;
1305 int err;
1306
1307 if (rpcm)
1308 *rpcm = NULL;
1309 #ifdef CHIP1370
1310 err = snd_pcm_new(ensoniq->card, "ES1370/2", device, 1, 0, &pcm);
1311 #else
1312 err = snd_pcm_new(ensoniq->card, "ES1371/2", device, 1, 0, &pcm);
1313 #endif
1314 if (err < 0)
1315 return err;
1316
1317 #ifdef CHIP1370
1318 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1319 #else
1320 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1321 #endif
1322 pcm->private_data = ensoniq;
1323 pcm->info_flags = 0;
1324 #ifdef CHIP1370
1325 strcpy(pcm->name, "ES1370 DAC1");
1326 #else
1327 strcpy(pcm->name, "ES1371 DAC1");
1328 #endif
1329 ensoniq->pcm2 = pcm;
1330
1331 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1332 snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1333
1334 if (rpcm)
1335 *rpcm = pcm;
1336 return 0;
1337 }
1338
1339 /*
1340 * Mixer section
1341 */
1342
1343 /*
1344 * ENS1371 mixer (including SPDIF interface)
1345 */
1346 #ifdef CHIP1371
1347 static int snd_ens1373_spdif_info(struct snd_kcontrol *kcontrol,
1348 struct snd_ctl_elem_info *uinfo)
1349 {
1350 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1351 uinfo->count = 1;
1352 return 0;
1353 }
1354
1355 static int snd_ens1373_spdif_default_get(struct snd_kcontrol *kcontrol,
1356 struct snd_ctl_elem_value *ucontrol)
1357 {
1358 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1359 spin_lock_irq(&ensoniq->reg_lock);
1360 ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
1361 ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
1362 ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
1363 ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
1364 spin_unlock_irq(&ensoniq->reg_lock);
1365 return 0;
1366 }
1367
1368 static int snd_ens1373_spdif_default_put(struct snd_kcontrol *kcontrol,
1369 struct snd_ctl_elem_value *ucontrol)
1370 {
1371 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1372 unsigned int val;
1373 int change;
1374
1375 val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1376 ((u32)ucontrol->value.iec958.status[1] << 8) |
1377 ((u32)ucontrol->value.iec958.status[2] << 16) |
1378 ((u32)ucontrol->value.iec958.status[3] << 24);
1379 spin_lock_irq(&ensoniq->reg_lock);
1380 change = ensoniq->spdif_default != val;
1381 ensoniq->spdif_default = val;
1382 if (change && ensoniq->playback1_substream == NULL &&
1383 ensoniq->playback2_substream == NULL)
1384 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1385 spin_unlock_irq(&ensoniq->reg_lock);
1386 return change;
1387 }
1388
1389 static int snd_ens1373_spdif_mask_get(struct snd_kcontrol *kcontrol,
1390 struct snd_ctl_elem_value *ucontrol)
1391 {
1392 ucontrol->value.iec958.status[0] = 0xff;
1393 ucontrol->value.iec958.status[1] = 0xff;
1394 ucontrol->value.iec958.status[2] = 0xff;
1395 ucontrol->value.iec958.status[3] = 0xff;
1396 return 0;
1397 }
1398
1399 static int snd_ens1373_spdif_stream_get(struct snd_kcontrol *kcontrol,
1400 struct snd_ctl_elem_value *ucontrol)
1401 {
1402 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1403 spin_lock_irq(&ensoniq->reg_lock);
1404 ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
1405 ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
1406 ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
1407 ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
1408 spin_unlock_irq(&ensoniq->reg_lock);
1409 return 0;
1410 }
1411
1412 static int snd_ens1373_spdif_stream_put(struct snd_kcontrol *kcontrol,
1413 struct snd_ctl_elem_value *ucontrol)
1414 {
1415 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1416 unsigned int val;
1417 int change;
1418
1419 val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1420 ((u32)ucontrol->value.iec958.status[1] << 8) |
1421 ((u32)ucontrol->value.iec958.status[2] << 16) |
1422 ((u32)ucontrol->value.iec958.status[3] << 24);
1423 spin_lock_irq(&ensoniq->reg_lock);
1424 change = ensoniq->spdif_stream != val;
1425 ensoniq->spdif_stream = val;
1426 if (change && (ensoniq->playback1_substream != NULL ||
1427 ensoniq->playback2_substream != NULL))
1428 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1429 spin_unlock_irq(&ensoniq->reg_lock);
1430 return change;
1431 }
1432
1433 #define ES1371_SPDIF(xname) \
1434 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
1435 .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
1436
1437 #define snd_es1371_spdif_info snd_ctl_boolean_mono_info
1438
1439 static int snd_es1371_spdif_get(struct snd_kcontrol *kcontrol,
1440 struct snd_ctl_elem_value *ucontrol)
1441 {
1442 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1443
1444 spin_lock_irq(&ensoniq->reg_lock);
1445 ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
1446 spin_unlock_irq(&ensoniq->reg_lock);
1447 return 0;
1448 }
1449
1450 static int snd_es1371_spdif_put(struct snd_kcontrol *kcontrol,
1451 struct snd_ctl_elem_value *ucontrol)
1452 {
1453 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1454 unsigned int nval1, nval2;
1455 int change;
1456
1457 nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
1458 nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
1459 spin_lock_irq(&ensoniq->reg_lock);
1460 change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
1461 ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
1462 ensoniq->ctrl |= nval1;
1463 ensoniq->cssr &= ~ES_1373_SPDIF_EN;
1464 ensoniq->cssr |= nval2;
1465 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1466 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1467 spin_unlock_irq(&ensoniq->reg_lock);
1468 return change;
1469 }
1470
1471
1472 /* spdif controls */
1473 static struct snd_kcontrol_new snd_es1371_mixer_spdif[] __devinitdata = {
1474 ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)),
1475 {
1476 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1477 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1478 .info = snd_ens1373_spdif_info,
1479 .get = snd_ens1373_spdif_default_get,
1480 .put = snd_ens1373_spdif_default_put,
1481 },
1482 {
1483 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1484 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1485 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1486 .info = snd_ens1373_spdif_info,
1487 .get = snd_ens1373_spdif_mask_get
1488 },
1489 {
1490 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1491 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1492 .info = snd_ens1373_spdif_info,
1493 .get = snd_ens1373_spdif_stream_get,
1494 .put = snd_ens1373_spdif_stream_put
1495 },
1496 };
1497
1498
1499 #define snd_es1373_rear_info snd_ctl_boolean_mono_info
1500
1501 static int snd_es1373_rear_get(struct snd_kcontrol *kcontrol,
1502 struct snd_ctl_elem_value *ucontrol)
1503 {
1504 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1505 int val = 0;
1506
1507 spin_lock_irq(&ensoniq->reg_lock);
1508 if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|
1509 ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26)
1510 val = 1;
1511 ucontrol->value.integer.value[0] = val;
1512 spin_unlock_irq(&ensoniq->reg_lock);
1513 return 0;
1514 }
1515
1516 static int snd_es1373_rear_put(struct snd_kcontrol *kcontrol,
1517 struct snd_ctl_elem_value *ucontrol)
1518 {
1519 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1520 unsigned int nval1;
1521 int change;
1522
1523 nval1 = ucontrol->value.integer.value[0] ?
1524 ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1525 spin_lock_irq(&ensoniq->reg_lock);
1526 change = (ensoniq->cssr & (ES_1373_REAR_BIT27|
1527 ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1;
1528 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24);
1529 ensoniq->cssr |= nval1;
1530 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1531 spin_unlock_irq(&ensoniq->reg_lock);
1532 return change;
1533 }
1534
1535 static struct snd_kcontrol_new snd_ens1373_rear __devinitdata =
1536 {
1537 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1538 .name = "AC97 2ch->4ch Copy Switch",
1539 .info = snd_es1373_rear_info,
1540 .get = snd_es1373_rear_get,
1541 .put = snd_es1373_rear_put,
1542 };
1543
1544 #define snd_es1373_line_info snd_ctl_boolean_mono_info
1545
1546 static int snd_es1373_line_get(struct snd_kcontrol *kcontrol,
1547 struct snd_ctl_elem_value *ucontrol)
1548 {
1549 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1550 int val = 0;
1551
1552 spin_lock_irq(&ensoniq->reg_lock);
1553 if ((ensoniq->ctrl & ES_1371_GPIO_OUTM) >= 4)
1554 val = 1;
1555 ucontrol->value.integer.value[0] = val;
1556 spin_unlock_irq(&ensoniq->reg_lock);
1557 return 0;
1558 }
1559
1560 static int snd_es1373_line_put(struct snd_kcontrol *kcontrol,
1561 struct snd_ctl_elem_value *ucontrol)
1562 {
1563 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1564 int changed;
1565 unsigned int ctrl;
1566
1567 spin_lock_irq(&ensoniq->reg_lock);
1568 ctrl = ensoniq->ctrl;
1569 if (ucontrol->value.integer.value[0])
1570 ensoniq->ctrl |= ES_1371_GPIO_OUT(4); /* switch line-in -> rear out */
1571 else
1572 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4);
1573 changed = (ctrl != ensoniq->ctrl);
1574 if (changed)
1575 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1576 spin_unlock_irq(&ensoniq->reg_lock);
1577 return changed;
1578 }
1579
1580 static struct snd_kcontrol_new snd_ens1373_line __devinitdata =
1581 {
1582 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1583 .name = "Line In->Rear Out Switch",
1584 .info = snd_es1373_line_info,
1585 .get = snd_es1373_line_get,
1586 .put = snd_es1373_line_put,
1587 };
1588
1589 static void snd_ensoniq_mixer_free_ac97(struct snd_ac97 *ac97)
1590 {
1591 struct ensoniq *ensoniq = ac97->private_data;
1592 ensoniq->u.es1371.ac97 = NULL;
1593 }
1594
1595 struct es1371_quirk {
1596 unsigned short vid; /* vendor ID */
1597 unsigned short did; /* device ID */
1598 unsigned char rev; /* revision */
1599 };
1600
1601 static int es1371_quirk_lookup(struct ensoniq *ensoniq,
1602 struct es1371_quirk *list)
1603 {
1604 while (list->vid != (unsigned short)PCI_ANY_ID) {
1605 if (ensoniq->pci->vendor == list->vid &&
1606 ensoniq->pci->device == list->did &&
1607 ensoniq->rev == list->rev)
1608 return 1;
1609 list++;
1610 }
1611 return 0;
1612 }
1613
1614 static struct es1371_quirk es1371_spdif_present[] __devinitdata = {
1615 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1616 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1617 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1618 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1619 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1620 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1621 };
1622
1623 static struct snd_pci_quirk ens1373_line_quirk[] __devinitdata = {
1624 SND_PCI_QUIRK_ID(0x1274, 0x2000), /* GA-7DXR */
1625 SND_PCI_QUIRK_ID(0x1458, 0xa000), /* GA-8IEXP */
1626 { } /* end */
1627 };
1628
1629 static int __devinit snd_ensoniq_1371_mixer(struct ensoniq *ensoniq,
1630 int has_spdif, int has_line)
1631 {
1632 struct snd_card *card = ensoniq->card;
1633 struct snd_ac97_bus *pbus;
1634 struct snd_ac97_template ac97;
1635 int err;
1636 static struct snd_ac97_bus_ops ops = {
1637 .write = snd_es1371_codec_write,
1638 .read = snd_es1371_codec_read,
1639 .wait = snd_es1371_codec_wait,
1640 };
1641
1642 if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0)
1643 return err;
1644
1645 memset(&ac97, 0, sizeof(ac97));
1646 ac97.private_data = ensoniq;
1647 ac97.private_free = snd_ensoniq_mixer_free_ac97;
1648 ac97.pci = ensoniq->pci;
1649 ac97.scaps = AC97_SCAP_AUDIO;
1650 if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0)
1651 return err;
1652 if (has_spdif > 0 ||
1653 (!has_spdif && es1371_quirk_lookup(ensoniq, es1371_spdif_present))) {
1654 struct snd_kcontrol *kctl;
1655 int i, is_spdif = 0;
1656
1657 ensoniq->spdif_default = ensoniq->spdif_stream =
1658 SNDRV_PCM_DEFAULT_CON_SPDIF;
1659 outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
1660
1661 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
1662 is_spdif++;
1663
1664 for (i = 0; i < ARRAY_SIZE(snd_es1371_mixer_spdif); i++) {
1665 kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq);
1666 if (!kctl)
1667 return -ENOMEM;
1668 kctl->id.index = is_spdif;
1669 err = snd_ctl_add(card, kctl);
1670 if (err < 0)
1671 return err;
1672 }
1673 }
1674 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
1675 /* mirror rear to front speakers */
1676 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1677 ensoniq->cssr |= ES_1373_REAR_BIT26;
1678 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
1679 if (err < 0)
1680 return err;
1681 }
1682 if (has_line > 0 ||
1683 snd_pci_quirk_lookup(ensoniq->pci, ens1373_line_quirk)) {
1684 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line,
1685 ensoniq));
1686 if (err < 0)
1687 return err;
1688 }
1689
1690 return 0;
1691 }
1692
1693 #endif /* CHIP1371 */
1694
1695 /* generic control callbacks for ens1370 */
1696 #ifdef CHIP1370
1697 #define ENSONIQ_CONTROL(xname, mask) \
1698 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
1699 .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
1700 .private_value = mask }
1701
1702 #define snd_ensoniq_control_info snd_ctl_boolean_mono_info
1703
1704 static int snd_ensoniq_control_get(struct snd_kcontrol *kcontrol,
1705 struct snd_ctl_elem_value *ucontrol)
1706 {
1707 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1708 int mask = kcontrol->private_value;
1709
1710 spin_lock_irq(&ensoniq->reg_lock);
1711 ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
1712 spin_unlock_irq(&ensoniq->reg_lock);
1713 return 0;
1714 }
1715
1716 static int snd_ensoniq_control_put(struct snd_kcontrol *kcontrol,
1717 struct snd_ctl_elem_value *ucontrol)
1718 {
1719 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1720 int mask = kcontrol->private_value;
1721 unsigned int nval;
1722 int change;
1723
1724 nval = ucontrol->value.integer.value[0] ? mask : 0;
1725 spin_lock_irq(&ensoniq->reg_lock);
1726 change = (ensoniq->ctrl & mask) != nval;
1727 ensoniq->ctrl &= ~mask;
1728 ensoniq->ctrl |= nval;
1729 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1730 spin_unlock_irq(&ensoniq->reg_lock);
1731 return change;
1732 }
1733
1734 /*
1735 * ENS1370 mixer
1736 */
1737
1738 static struct snd_kcontrol_new snd_es1370_controls[2] __devinitdata = {
1739 ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
1740 ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
1741 };
1742
1743 #define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
1744
1745 static void snd_ensoniq_mixer_free_ak4531(struct snd_ak4531 *ak4531)
1746 {
1747 struct ensoniq *ensoniq = ak4531->private_data;
1748 ensoniq->u.es1370.ak4531 = NULL;
1749 }
1750
1751 static int __devinit snd_ensoniq_1370_mixer(struct ensoniq * ensoniq)
1752 {
1753 struct snd_card *card = ensoniq->card;
1754 struct snd_ak4531 ak4531;
1755 unsigned int idx;
1756 int err;
1757
1758 /* try reset AK4531 */
1759 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1760 inw(ES_REG(ensoniq, 1370_CODEC));
1761 udelay(100);
1762 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1763 inw(ES_REG(ensoniq, 1370_CODEC));
1764 udelay(100);
1765
1766 memset(&ak4531, 0, sizeof(ak4531));
1767 ak4531.write = snd_es1370_codec_write;
1768 ak4531.private_data = ensoniq;
1769 ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
1770 if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0)
1771 return err;
1772 for (idx = 0; idx < ES1370_CONTROLS; idx++) {
1773 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
1774 if (err < 0)
1775 return err;
1776 }
1777 return 0;
1778 }
1779
1780 #endif /* CHIP1370 */
1781
1782 #ifdef SUPPORT_JOYSTICK
1783
1784 #ifdef CHIP1371
1785 static int __devinit snd_ensoniq_get_joystick_port(int dev)
1786 {
1787 switch (joystick_port[dev]) {
1788 case 0: /* disabled */
1789 case 1: /* auto-detect */
1790 case 0x200:
1791 case 0x208:
1792 case 0x210:
1793 case 0x218:
1794 return joystick_port[dev];
1795
1796 default:
1797 printk(KERN_ERR "ens1371: invalid joystick port %#x", joystick_port[dev]);
1798 return 0;
1799 }
1800 }
1801 #else
1802 static inline int snd_ensoniq_get_joystick_port(int dev)
1803 {
1804 return joystick[dev] ? 0x200 : 0;
1805 }
1806 #endif
1807
1808 static int __devinit snd_ensoniq_create_gameport(struct ensoniq *ensoniq, int dev)
1809 {
1810 struct gameport *gp;
1811 int io_port;
1812
1813 io_port = snd_ensoniq_get_joystick_port(dev);
1814
1815 switch (io_port) {
1816 case 0:
1817 return -ENOSYS;
1818
1819 case 1: /* auto_detect */
1820 for (io_port = 0x200; io_port <= 0x218; io_port += 8)
1821 if (request_region(io_port, 8, "ens137x: gameport"))
1822 break;
1823 if (io_port > 0x218) {
1824 printk(KERN_WARNING "ens137x: no gameport ports available\n");
1825 return -EBUSY;
1826 }
1827 break;
1828
1829 default:
1830 if (!request_region(io_port, 8, "ens137x: gameport")) {
1831 printk(KERN_WARNING "ens137x: gameport io port 0x%#x in use\n",
1832 io_port);
1833 return -EBUSY;
1834 }
1835 break;
1836 }
1837
1838 ensoniq->gameport = gp = gameport_allocate_port();
1839 if (!gp) {
1840 printk(KERN_ERR "ens137x: cannot allocate memory for gameport\n");
1841 release_region(io_port, 8);
1842 return -ENOMEM;
1843 }
1844
1845 gameport_set_name(gp, "ES137x");
1846 gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci));
1847 gameport_set_dev_parent(gp, &ensoniq->pci->dev);
1848 gp->io = io_port;
1849
1850 ensoniq->ctrl |= ES_JYSTK_EN;
1851 #ifdef CHIP1371
1852 ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
1853 ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8);
1854 #endif
1855 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1856
1857 gameport_register_port(ensoniq->gameport);
1858
1859 return 0;
1860 }
1861
1862 static void snd_ensoniq_free_gameport(struct ensoniq *ensoniq)
1863 {
1864 if (ensoniq->gameport) {
1865 int port = ensoniq->gameport->io;
1866
1867 gameport_unregister_port(ensoniq->gameport);
1868 ensoniq->gameport = NULL;
1869 ensoniq->ctrl &= ~ES_JYSTK_EN;
1870 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1871 release_region(port, 8);
1872 }
1873 }
1874 #else
1875 static inline int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, long port) { return -ENOSYS; }
1876 static inline void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) { }
1877 #endif /* SUPPORT_JOYSTICK */
1878
1879 /*
1880
1881 */
1882
1883 static void snd_ensoniq_proc_read(struct snd_info_entry *entry,
1884 struct snd_info_buffer *buffer)
1885 {
1886 struct ensoniq *ensoniq = entry->private_data;
1887
1888 #ifdef CHIP1370
1889 snd_iprintf(buffer, "Ensoniq AudioPCI ES1370\n\n");
1890 #else
1891 snd_iprintf(buffer, "Ensoniq AudioPCI ES1371\n\n");
1892 #endif
1893 snd_iprintf(buffer, "Joystick enable : %s\n",
1894 ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off");
1895 #ifdef CHIP1370
1896 snd_iprintf(buffer, "MIC +5V bias : %s\n",
1897 ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off");
1898 snd_iprintf(buffer, "Line In to AOUT : %s\n",
1899 ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off");
1900 #else
1901 snd_iprintf(buffer, "Joystick port : 0x%x\n",
1902 (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
1903 #endif
1904 }
1905
1906 static void __devinit snd_ensoniq_proc_init(struct ensoniq * ensoniq)
1907 {
1908 struct snd_info_entry *entry;
1909
1910 if (! snd_card_proc_new(ensoniq->card, "audiopci", &entry))
1911 snd_info_set_text_ops(entry, ensoniq, snd_ensoniq_proc_read);
1912 }
1913
1914 /*
1915
1916 */
1917
1918 static int snd_ensoniq_free(struct ensoniq *ensoniq)
1919 {
1920 snd_ensoniq_free_gameport(ensoniq);
1921 if (ensoniq->irq < 0)
1922 goto __hw_end;
1923 #ifdef CHIP1370
1924 outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL)); /* switch everything off */
1925 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
1926 #else
1927 outl(0, ES_REG(ensoniq, CONTROL)); /* switch everything off */
1928 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
1929 #endif
1930 if (ensoniq->irq >= 0)
1931 synchronize_irq(ensoniq->irq);
1932 pci_set_power_state(ensoniq->pci, 3);
1933 __hw_end:
1934 #ifdef CHIP1370
1935 if (ensoniq->dma_bug.area)
1936 snd_dma_free_pages(&ensoniq->dma_bug);
1937 #endif
1938 if (ensoniq->irq >= 0)
1939 free_irq(ensoniq->irq, ensoniq);
1940 pci_release_regions(ensoniq->pci);
1941 pci_disable_device(ensoniq->pci);
1942 kfree(ensoniq);
1943 return 0;
1944 }
1945
1946 static int snd_ensoniq_dev_free(struct snd_device *device)
1947 {
1948 struct ensoniq *ensoniq = device->device_data;
1949 return snd_ensoniq_free(ensoniq);
1950 }
1951
1952 #ifdef CHIP1371
1953 static struct snd_pci_quirk es1371_amplifier_hack[] __devinitdata = {
1954 SND_PCI_QUIRK_ID(0x107b, 0x2150), /* Gateway Solo 2150 */
1955 SND_PCI_QUIRK_ID(0x13bd, 0x100c), /* EV1938 on Mebius PC-MJ100V */
1956 SND_PCI_QUIRK_ID(0x1102, 0x5938), /* Targa Xtender300 */
1957 SND_PCI_QUIRK_ID(0x1102, 0x8938), /* IPC Topnote G notebook */
1958 { } /* end */
1959 };
1960
1961 static struct es1371_quirk es1371_ac97_reset_hack[] = {
1962 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1963 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1964 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1965 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1966 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1967 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1968 };
1969 #endif
1970
1971 static void snd_ensoniq_chip_init(struct ensoniq *ensoniq)
1972 {
1973 #ifdef CHIP1371
1974 int idx;
1975 #endif
1976 /* this code was part of snd_ensoniq_create before intruduction
1977 * of suspend/resume
1978 */
1979 #ifdef CHIP1370
1980 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1981 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1982 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1983 outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME));
1984 outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
1985 #else
1986 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1987 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1988 outl(0, ES_REG(ensoniq, 1371_LEGACY));
1989 if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) {
1990 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1991 /* need to delay around 20ms(bleech) to give
1992 some CODECs enough time to wakeup */
1993 msleep(20);
1994 }
1995 /* AC'97 warm reset to start the bitclk */
1996 outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
1997 inl(ES_REG(ensoniq, CONTROL));
1998 udelay(20);
1999 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
2000 /* Init the sample rate converter */
2001 snd_es1371_wait_src_ready(ensoniq);
2002 outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
2003 for (idx = 0; idx < 0x80; idx++)
2004 snd_es1371_src_write(ensoniq, idx, 0);
2005 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
2006 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
2007 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
2008 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
2009 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
2010 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
2011 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
2012 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
2013 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
2014 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
2015 snd_es1371_adc_rate(ensoniq, 22050);
2016 snd_es1371_dac1_rate(ensoniq, 22050);
2017 snd_es1371_dac2_rate(ensoniq, 22050);
2018 /* WARNING:
2019 * enabling the sample rate converter without properly programming
2020 * its parameters causes the chip to lock up (the SRC busy bit will
2021 * be stuck high, and I've found no way to rectify this other than
2022 * power cycle) - Thomas Sailer
2023 */
2024 snd_es1371_wait_src_ready(ensoniq);
2025 outl(0, ES_REG(ensoniq, 1371_SMPRATE));
2026 /* try reset codec directly */
2027 outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
2028 #endif
2029 outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
2030 outb(0x00, ES_REG(ensoniq, UART_RES));
2031 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2032 synchronize_irq(ensoniq->irq);
2033 }
2034
2035 #ifdef CONFIG_PM
2036 static int snd_ensoniq_suspend(struct pci_dev *pci, pm_message_t state)
2037 {
2038 struct snd_card *card = pci_get_drvdata(pci);
2039 struct ensoniq *ensoniq = card->private_data;
2040
2041 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2042
2043 snd_pcm_suspend_all(ensoniq->pcm1);
2044 snd_pcm_suspend_all(ensoniq->pcm2);
2045
2046 #ifdef CHIP1371
2047 snd_ac97_suspend(ensoniq->u.es1371.ac97);
2048 #else
2049 /* try to reset AK4531 */
2050 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
2051 inw(ES_REG(ensoniq, 1370_CODEC));
2052 udelay(100);
2053 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
2054 inw(ES_REG(ensoniq, 1370_CODEC));
2055 udelay(100);
2056 snd_ak4531_suspend(ensoniq->u.es1370.ak4531);
2057 #endif
2058
2059 pci_disable_device(pci);
2060 pci_save_state(pci);
2061 pci_set_power_state(pci, pci_choose_state(pci, state));
2062 return 0;
2063 }
2064
2065 static int snd_ensoniq_resume(struct pci_dev *pci)
2066 {
2067 struct snd_card *card = pci_get_drvdata(pci);
2068 struct ensoniq *ensoniq = card->private_data;
2069
2070 pci_set_power_state(pci, PCI_D0);
2071 pci_restore_state(pci);
2072 if (pci_enable_device(pci) < 0) {
2073 printk(KERN_ERR DRIVER_NAME ": pci_enable_device failed, "
2074 "disabling device\n");
2075 snd_card_disconnect(card);
2076 return -EIO;
2077 }
2078 pci_set_master(pci);
2079
2080 snd_ensoniq_chip_init(ensoniq);
2081
2082 #ifdef CHIP1371
2083 snd_ac97_resume(ensoniq->u.es1371.ac97);
2084 #else
2085 snd_ak4531_resume(ensoniq->u.es1370.ak4531);
2086 #endif
2087 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2088 return 0;
2089 }
2090 #endif /* CONFIG_PM */
2091
2092
2093 static int __devinit snd_ensoniq_create(struct snd_card *card,
2094 struct pci_dev *pci,
2095 struct ensoniq ** rensoniq)
2096 {
2097 struct ensoniq *ensoniq;
2098 int err;
2099 static struct snd_device_ops ops = {
2100 .dev_free = snd_ensoniq_dev_free,
2101 };
2102
2103 *rensoniq = NULL;
2104 if ((err = pci_enable_device(pci)) < 0)
2105 return err;
2106 ensoniq = kzalloc(sizeof(*ensoniq), GFP_KERNEL);
2107 if (ensoniq == NULL) {
2108 pci_disable_device(pci);
2109 return -ENOMEM;
2110 }
2111 spin_lock_init(&ensoniq->reg_lock);
2112 mutex_init(&ensoniq->src_mutex);
2113 ensoniq->card = card;
2114 ensoniq->pci = pci;
2115 ensoniq->irq = -1;
2116 if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) {
2117 kfree(ensoniq);
2118 pci_disable_device(pci);
2119 return err;
2120 }
2121 ensoniq->port = pci_resource_start(pci, 0);
2122 if (request_irq(pci->irq, snd_audiopci_interrupt, IRQF_SHARED,
2123 "Ensoniq AudioPCI", ensoniq)) {
2124 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2125 snd_ensoniq_free(ensoniq);
2126 return -EBUSY;
2127 }
2128 ensoniq->irq = pci->irq;
2129 #ifdef CHIP1370
2130 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2131 16, &ensoniq->dma_bug) < 0) {
2132 snd_printk(KERN_ERR "unable to allocate space for phantom area - dma_bug\n");
2133 snd_ensoniq_free(ensoniq);
2134 return -EBUSY;
2135 }
2136 #endif
2137 pci_set_master(pci);
2138 ensoniq->rev = pci->revision;
2139 #ifdef CHIP1370
2140 #if 0
2141 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE |
2142 ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2143 #else /* get microphone working */
2144 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2145 #endif
2146 ensoniq->sctrl = 0;
2147 #else
2148 ensoniq->ctrl = 0;
2149 ensoniq->sctrl = 0;
2150 ensoniq->cssr = 0;
2151 if (snd_pci_quirk_lookup(pci, es1371_amplifier_hack))
2152 ensoniq->ctrl |= ES_1371_GPIO_OUT(1); /* turn amplifier on */
2153
2154 if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack))
2155 ensoniq->cssr |= ES_1371_ST_AC97_RST;
2156 #endif
2157
2158 snd_ensoniq_chip_init(ensoniq);
2159
2160 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) {
2161 snd_ensoniq_free(ensoniq);
2162 return err;
2163 }
2164
2165 snd_ensoniq_proc_init(ensoniq);
2166
2167 snd_card_set_dev(card, &pci->dev);
2168
2169 *rensoniq = ensoniq;
2170 return 0;
2171 }
2172
2173 /*
2174 * MIDI section
2175 */
2176
2177 static void snd_ensoniq_midi_interrupt(struct ensoniq * ensoniq)
2178 {
2179 struct snd_rawmidi *rmidi = ensoniq->rmidi;
2180 unsigned char status, mask, byte;
2181
2182 if (rmidi == NULL)
2183 return;
2184 /* do Rx at first */
2185 spin_lock(&ensoniq->reg_lock);
2186 mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
2187 while (mask) {
2188 status = inb(ES_REG(ensoniq, UART_STATUS));
2189 if ((status & mask) == 0)
2190 break;
2191 byte = inb(ES_REG(ensoniq, UART_DATA));
2192 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
2193 }
2194 spin_unlock(&ensoniq->reg_lock);
2195
2196 /* do Tx at second */
2197 spin_lock(&ensoniq->reg_lock);
2198 mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
2199 while (mask) {
2200 status = inb(ES_REG(ensoniq, UART_STATUS));
2201 if ((status & mask) == 0)
2202 break;
2203 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
2204 ensoniq->uartc &= ~ES_TXINTENM;
2205 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2206 mask &= ~ES_TXRDY;
2207 } else {
2208 outb(byte, ES_REG(ensoniq, UART_DATA));
2209 }
2210 }
2211 spin_unlock(&ensoniq->reg_lock);
2212 }
2213
2214 static int snd_ensoniq_midi_input_open(struct snd_rawmidi_substream *substream)
2215 {
2216 struct ensoniq *ensoniq = substream->rmidi->private_data;
2217
2218 spin_lock_irq(&ensoniq->reg_lock);
2219 ensoniq->uartm |= ES_MODE_INPUT;
2220 ensoniq->midi_input = substream;
2221 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2222 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2223 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2224 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2225 }
2226 spin_unlock_irq(&ensoniq->reg_lock);
2227 return 0;
2228 }
2229
2230 static int snd_ensoniq_midi_input_close(struct snd_rawmidi_substream *substream)
2231 {
2232 struct ensoniq *ensoniq = substream->rmidi->private_data;
2233
2234 spin_lock_irq(&ensoniq->reg_lock);
2235 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2236 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2237 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2238 } else {
2239 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
2240 }
2241 ensoniq->midi_input = NULL;
2242 ensoniq->uartm &= ~ES_MODE_INPUT;
2243 spin_unlock_irq(&ensoniq->reg_lock);
2244 return 0;
2245 }
2246
2247 static int snd_ensoniq_midi_output_open(struct snd_rawmidi_substream *substream)
2248 {
2249 struct ensoniq *ensoniq = substream->rmidi->private_data;
2250
2251 spin_lock_irq(&ensoniq->reg_lock);
2252 ensoniq->uartm |= ES_MODE_OUTPUT;
2253 ensoniq->midi_output = substream;
2254 if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2255 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2256 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2257 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2258 }
2259 spin_unlock_irq(&ensoniq->reg_lock);
2260 return 0;
2261 }
2262
2263 static int snd_ensoniq_midi_output_close(struct snd_rawmidi_substream *substream)
2264 {
2265 struct ensoniq *ensoniq = substream->rmidi->private_data;
2266
2267 spin_lock_irq(&ensoniq->reg_lock);
2268 if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2269 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2270 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2271 } else {
2272 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
2273 }
2274 ensoniq->midi_output = NULL;
2275 ensoniq->uartm &= ~ES_MODE_OUTPUT;
2276 spin_unlock_irq(&ensoniq->reg_lock);
2277 return 0;
2278 }
2279
2280 static void snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2281 {
2282 unsigned long flags;
2283 struct ensoniq *ensoniq = substream->rmidi->private_data;
2284 int idx;
2285
2286 spin_lock_irqsave(&ensoniq->reg_lock, flags);
2287 if (up) {
2288 if ((ensoniq->uartc & ES_RXINTEN) == 0) {
2289 /* empty input FIFO */
2290 for (idx = 0; idx < 32; idx++)
2291 inb(ES_REG(ensoniq, UART_DATA));
2292 ensoniq->uartc |= ES_RXINTEN;
2293 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2294 }
2295 } else {
2296 if (ensoniq->uartc & ES_RXINTEN) {
2297 ensoniq->uartc &= ~ES_RXINTEN;
2298 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2299 }
2300 }
2301 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2302 }
2303
2304 static void snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2305 {
2306 unsigned long flags;
2307 struct ensoniq *ensoniq = substream->rmidi->private_data;
2308 unsigned char byte;
2309
2310 spin_lock_irqsave(&ensoniq->reg_lock, flags);
2311 if (up) {
2312 if (ES_TXINTENI(ensoniq->uartc) == 0) {
2313 ensoniq->uartc |= ES_TXINTENO(1);
2314 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2315 while (ES_TXINTENI(ensoniq->uartc) == 1 &&
2316 (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
2317 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2318 ensoniq->uartc &= ~ES_TXINTENM;
2319 } else {
2320 outb(byte, ES_REG(ensoniq, UART_DATA));
2321 }
2322 }
2323 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2324 }
2325 } else {
2326 if (ES_TXINTENI(ensoniq->uartc) == 1) {
2327 ensoniq->uartc &= ~ES_TXINTENM;
2328 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2329 }
2330 }
2331 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2332 }
2333
2334 static struct snd_rawmidi_ops snd_ensoniq_midi_output =
2335 {
2336 .open = snd_ensoniq_midi_output_open,
2337 .close = snd_ensoniq_midi_output_close,
2338 .trigger = snd_ensoniq_midi_output_trigger,
2339 };
2340
2341 static struct snd_rawmidi_ops snd_ensoniq_midi_input =
2342 {
2343 .open = snd_ensoniq_midi_input_open,
2344 .close = snd_ensoniq_midi_input_close,
2345 .trigger = snd_ensoniq_midi_input_trigger,
2346 };
2347
2348 static int __devinit snd_ensoniq_midi(struct ensoniq * ensoniq, int device,
2349 struct snd_rawmidi **rrawmidi)
2350 {
2351 struct snd_rawmidi *rmidi;
2352 int err;
2353
2354 if (rrawmidi)
2355 *rrawmidi = NULL;
2356 if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0)
2357 return err;
2358 #ifdef CHIP1370
2359 strcpy(rmidi->name, "ES1370");
2360 #else
2361 strcpy(rmidi->name, "ES1371");
2362 #endif
2363 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
2364 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
2365 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT |
2366 SNDRV_RAWMIDI_INFO_DUPLEX;
2367 rmidi->private_data = ensoniq;
2368 ensoniq->rmidi = rmidi;
2369 if (rrawmidi)
2370 *rrawmidi = rmidi;
2371 return 0;
2372 }
2373
2374 /*
2375 * Interrupt handler
2376 */
2377
2378 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id)
2379 {
2380 struct ensoniq *ensoniq = dev_id;
2381 unsigned int status, sctrl;
2382
2383 if (ensoniq == NULL)
2384 return IRQ_NONE;
2385
2386 status = inl(ES_REG(ensoniq, STATUS));
2387 if (!(status & ES_INTR))
2388 return IRQ_NONE;
2389
2390 spin_lock(&ensoniq->reg_lock);
2391 sctrl = ensoniq->sctrl;
2392 if (status & ES_DAC1)
2393 sctrl &= ~ES_P1_INT_EN;
2394 if (status & ES_DAC2)
2395 sctrl &= ~ES_P2_INT_EN;
2396 if (status & ES_ADC)
2397 sctrl &= ~ES_R1_INT_EN;
2398 outl(sctrl, ES_REG(ensoniq, SERIAL));
2399 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2400 spin_unlock(&ensoniq->reg_lock);
2401
2402 if (status & ES_UART)
2403 snd_ensoniq_midi_interrupt(ensoniq);
2404 if ((status & ES_DAC2) && ensoniq->playback2_substream)
2405 snd_pcm_period_elapsed(ensoniq->playback2_substream);
2406 if ((status & ES_ADC) && ensoniq->capture_substream)
2407 snd_pcm_period_elapsed(ensoniq->capture_substream);
2408 if ((status & ES_DAC1) && ensoniq->playback1_substream)
2409 snd_pcm_period_elapsed(ensoniq->playback1_substream);
2410 return IRQ_HANDLED;
2411 }
2412
2413 static int __devinit snd_audiopci_probe(struct pci_dev *pci,
2414 const struct pci_device_id *pci_id)
2415 {
2416 static int dev;
2417 struct snd_card *card;
2418 struct ensoniq *ensoniq;
2419 int err, pcm_devs[2];
2420
2421 if (dev >= SNDRV_CARDS)
2422 return -ENODEV;
2423 if (!enable[dev]) {
2424 dev++;
2425 return -ENOENT;
2426 }
2427
2428 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2429 if (err < 0)
2430 return err;
2431
2432 if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) {
2433 snd_card_free(card);
2434 return err;
2435 }
2436 card->private_data = ensoniq;
2437
2438 pcm_devs[0] = 0; pcm_devs[1] = 1;
2439 #ifdef CHIP1370
2440 if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) {
2441 snd_card_free(card);
2442 return err;
2443 }
2444 #endif
2445 #ifdef CHIP1371
2446 if ((err = snd_ensoniq_1371_mixer(ensoniq, spdif[dev], lineio[dev])) < 0) {
2447 snd_card_free(card);
2448 return err;
2449 }
2450 #endif
2451 if ((err = snd_ensoniq_pcm(ensoniq, 0, NULL)) < 0) {
2452 snd_card_free(card);
2453 return err;
2454 }
2455 if ((err = snd_ensoniq_pcm2(ensoniq, 1, NULL)) < 0) {
2456 snd_card_free(card);
2457 return err;
2458 }
2459 if ((err = snd_ensoniq_midi(ensoniq, 0, NULL)) < 0) {
2460 snd_card_free(card);
2461 return err;
2462 }
2463
2464 snd_ensoniq_create_gameport(ensoniq, dev);
2465
2466 strcpy(card->driver, DRIVER_NAME);
2467
2468 strcpy(card->shortname, "Ensoniq AudioPCI");
2469 sprintf(card->longname, "%s %s at 0x%lx, irq %i",
2470 card->shortname,
2471 card->driver,
2472 ensoniq->port,
2473 ensoniq->irq);
2474
2475 if ((err = snd_card_register(card)) < 0) {
2476 snd_card_free(card);
2477 return err;
2478 }
2479
2480 pci_set_drvdata(pci, card);
2481 dev++;
2482 return 0;
2483 }
2484
2485 static void __devexit snd_audiopci_remove(struct pci_dev *pci)
2486 {
2487 snd_card_free(pci_get_drvdata(pci));
2488 pci_set_drvdata(pci, NULL);
2489 }
2490
2491 static struct pci_driver driver = {
2492 .name = DRIVER_NAME,
2493 .id_table = snd_audiopci_ids,
2494 .probe = snd_audiopci_probe,
2495 .remove = __devexit_p(snd_audiopci_remove),
2496 #ifdef CONFIG_PM
2497 .suspend = snd_ensoniq_suspend,
2498 .resume = snd_ensoniq_resume,
2499 #endif
2500 };
2501
2502 static int __init alsa_card_ens137x_init(void)
2503 {
2504 return pci_register_driver(&driver);
2505 }
2506
2507 static void __exit alsa_card_ens137x_exit(void)
2508 {
2509 pci_unregister_driver(&driver);
2510 }
2511
2512 module_init(alsa_card_ens137x_init)
2513 module_exit(alsa_card_ens137x_exit)
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