2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
31 #include <asm/atomic.h>
34 #include <asm/mpspec.h>
36 #include <asm/pgalloc.h>
37 #include <asm/mach_apic.h>
40 #include <asm/proto.h>
41 #include <asm/timex.h>
44 int disable_apic_timer __cpuinitdata
;
45 static int apic_calibrate_pmtmr __initdata
;
48 /* Local APIC timer works in C2 */
49 int local_apic_timer_c2_ok
;
50 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
53 * Debug level, exported for io_apic.c
57 static struct resource lapic_resource
= {
59 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
62 static unsigned int calibration_result
;
64 static int lapic_next_event(unsigned long delta
,
65 struct clock_event_device
*evt
);
66 static void lapic_timer_setup(enum clock_event_mode mode
,
67 struct clock_event_device
*evt
);
68 static void lapic_timer_broadcast(cpumask_t mask
);
69 static void apic_pm_activate(void);
71 static struct clock_event_device lapic_clockevent
= {
73 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
74 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
76 .set_mode
= lapic_timer_setup
,
77 .set_next_event
= lapic_next_event
,
78 .broadcast
= lapic_timer_broadcast
,
82 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
84 static unsigned long apic_phys
;
87 * Get the LAPIC version
89 static inline int lapic_get_version(void)
91 return GET_APIC_VERSION(apic_read(APIC_LVR
));
95 * Check, if the APIC is integrated or a seperate chip
97 static inline int lapic_is_integrated(void)
103 * Check, whether this is a modern or a first generation APIC
105 static int modern_apic(void)
107 /* AMD systems use old APIC versions, so check the CPU */
108 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
109 boot_cpu_data
.x86
>= 0xf)
111 return lapic_get_version() >= 0x14;
114 void apic_wait_icr_idle(void)
116 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
120 u32
safe_apic_wait_icr_idle(void)
127 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
131 } while (timeout
++ < 1000);
137 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
139 void __cpuinit
enable_NMI_through_LVT0(void)
143 /* unmask and set to NMI */
145 apic_write(APIC_LVT0
, v
);
149 * lapic_get_maxlvt - get the maximum number of local vector table entries
151 int lapic_get_maxlvt(void)
153 unsigned int v
, maxlvt
;
155 v
= apic_read(APIC_LVR
);
156 maxlvt
= GET_APIC_MAXLVT(v
);
161 * This function sets up the local APIC timer, with a timeout of
162 * 'clocks' APIC bus clock. During calibration we actually call
163 * this function twice on the boot CPU, once with a bogus timeout
164 * value, second time for real. The other (noncalibrating) CPUs
165 * call this function only once, with the real, calibrated value.
167 * We do reads before writes even if unnecessary, to get around the
168 * P5 APIC double write bug.
171 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
173 unsigned int lvtt_value
, tmp_value
;
175 lvtt_value
= LOCAL_TIMER_VECTOR
;
177 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
179 lvtt_value
|= APIC_LVT_MASKED
;
181 apic_write(APIC_LVTT
, lvtt_value
);
186 tmp_value
= apic_read(APIC_TDCR
);
187 apic_write(APIC_TDCR
, (tmp_value
188 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
192 apic_write(APIC_TMICT
, clocks
);
196 * Setup extended LVT, AMD specific (K8, family 10h)
198 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
199 * MCE interrupts are supported. Thus MCE offset must be set to 0.
202 #define APIC_EILVT_LVTOFF_MCE 0
203 #define APIC_EILVT_LVTOFF_IBS 1
205 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
207 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
208 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
213 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
215 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
216 return APIC_EILVT_LVTOFF_MCE
;
219 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
221 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
222 return APIC_EILVT_LVTOFF_IBS
;
226 * Program the next event, relative to now
228 static int lapic_next_event(unsigned long delta
,
229 struct clock_event_device
*evt
)
231 apic_write(APIC_TMICT
, delta
);
236 * Setup the lapic timer in periodic or oneshot mode
238 static void lapic_timer_setup(enum clock_event_mode mode
,
239 struct clock_event_device
*evt
)
244 /* Lapic used as dummy for broadcast ? */
245 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
248 local_irq_save(flags
);
251 case CLOCK_EVT_MODE_PERIODIC
:
252 case CLOCK_EVT_MODE_ONESHOT
:
253 __setup_APIC_LVTT(calibration_result
,
254 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
256 case CLOCK_EVT_MODE_UNUSED
:
257 case CLOCK_EVT_MODE_SHUTDOWN
:
258 v
= apic_read(APIC_LVTT
);
259 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
260 apic_write(APIC_LVTT
, v
);
262 case CLOCK_EVT_MODE_RESUME
:
263 /* Nothing to do here */
267 local_irq_restore(flags
);
271 * Local APIC timer broadcast function
273 static void lapic_timer_broadcast(cpumask_t mask
)
276 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
281 * Setup the local APIC timer for this CPU. Copy the initilized values
282 * of the boot CPU and register the clock event in the framework.
284 static void setup_APIC_timer(void)
286 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
288 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
289 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
291 clockevents_register_device(levt
);
295 * In this function we calibrate APIC bus clocks to the external
296 * timer. Unfortunately we cannot use jiffies and the timer irq
297 * to calibrate, since some later bootup code depends on getting
298 * the first irq? Ugh.
300 * We want to do the calibration only once since we
301 * want to have local timer irqs syncron. CPUs connected
302 * by the same APIC bus have the very same bus frequency.
303 * And we want to have irqs off anyways, no accidental
307 #define TICK_COUNT 100000000
309 static void __init
calibrate_APIC_clock(void)
311 unsigned apic
, apic_start
;
312 unsigned long tsc
, tsc_start
;
318 * Put whatever arbitrary (but long enough) timeout
319 * value into the APIC clock, we just want to get the
320 * counter running for calibration.
322 * No interrupt enable !
324 __setup_APIC_LVTT(250000000, 0, 0);
326 apic_start
= apic_read(APIC_TMCCT
);
327 #ifdef CONFIG_X86_PM_TIMER
328 if (apic_calibrate_pmtmr
&& pmtmr_ioport
) {
329 pmtimer_wait(5000); /* 5ms wait */
330 apic
= apic_read(APIC_TMCCT
);
331 result
= (apic_start
- apic
) * 1000L / 5;
338 apic
= apic_read(APIC_TMCCT
);
340 } while ((tsc
- tsc_start
) < TICK_COUNT
&&
341 (apic_start
- apic
) < TICK_COUNT
);
343 result
= (apic_start
- apic
) * 1000L * tsc_khz
/
349 printk(KERN_DEBUG
"APIC timer calibration result %d\n", result
);
351 printk(KERN_INFO
"Detected %d.%03d MHz APIC timer.\n",
352 result
/ 1000 / 1000, result
/ 1000 % 1000);
354 /* Calculate the scaled math multiplication factor */
355 lapic_clockevent
.mult
= div_sc(result
, NSEC_PER_SEC
, 32);
356 lapic_clockevent
.max_delta_ns
=
357 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
358 lapic_clockevent
.min_delta_ns
=
359 clockevent_delta2ns(0xF, &lapic_clockevent
);
361 calibration_result
= result
/ HZ
;
365 * Setup the boot APIC
367 * Calibrate and verify the result.
369 void __init
setup_boot_APIC_clock(void)
372 * The local apic timer can be disabled via the kernel commandline.
373 * Register the lapic timer as a dummy clock event source on SMP
374 * systems, so the broadcast mechanism is used. On UP systems simply
377 if (disable_apic_timer
) {
378 printk(KERN_INFO
"Disabling APIC timer\n");
379 /* No broadcast on UP ! */
380 if (num_possible_cpus() > 1) {
381 lapic_clockevent
.mult
= 1;
387 printk(KERN_INFO
"Using local APIC timer interrupts.\n");
388 calibrate_APIC_clock();
391 * Do a sanity check on the APIC calibration result
393 if (calibration_result
< (1000000 / HZ
)) {
395 "APIC frequency too slow, disabling apic timer\n");
396 /* No broadcast on UP ! */
397 if (num_possible_cpus() > 1)
403 * If nmi_watchdog is set to IO_APIC, we need the
404 * PIT/HPET going. Otherwise register lapic as a dummy
407 if (nmi_watchdog
!= NMI_IO_APIC
)
408 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
410 printk(KERN_WARNING
"APIC timer registered as dummy,"
411 " due to nmi_watchdog=1!\n");
417 * AMD C1E enabled CPUs have a real nasty problem: Some BIOSes set the
418 * C1E flag only in the secondary CPU, so when we detect the wreckage
419 * we already have enabled the boot CPU local apic timer. Check, if
420 * disable_apic_timer is set and the DUMMY flag is cleared. If yes,
421 * set the DUMMY flag again and force the broadcast mode in the
424 void __cpuinit
check_boot_apic_timer_broadcast(void)
426 if (!disable_apic_timer
||
427 (lapic_clockevent
.features
& CLOCK_EVT_FEAT_DUMMY
))
430 printk(KERN_INFO
"AMD C1E detected late. Force timer broadcast.\n");
431 lapic_clockevent
.features
|= CLOCK_EVT_FEAT_DUMMY
;
434 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE
,
435 &boot_cpu_physical_apicid
);
439 void __cpuinit
setup_secondary_APIC_clock(void)
441 check_boot_apic_timer_broadcast();
446 * The guts of the apic timer interrupt
448 static void local_apic_timer_interrupt(void)
450 int cpu
= smp_processor_id();
451 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
454 * Normally we should not be here till LAPIC has been initialized but
455 * in some cases like kdump, its possible that there is a pending LAPIC
456 * timer interrupt from previous kernel's context and is delivered in
457 * new kernel the moment interrupts are enabled.
459 * Interrupts are enabled early and LAPIC is setup much later, hence
460 * its possible that when we get here evt->event_handler is NULL.
461 * Check for event_handler being NULL and discard the interrupt as
464 if (!evt
->event_handler
) {
466 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
468 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
473 * the NMI deadlock-detector uses this.
475 add_pda(apic_timer_irqs
, 1);
477 evt
->event_handler(evt
);
481 * Local APIC timer interrupt. This is the most natural way for doing
482 * local interrupts, but local timer interrupts can be emulated by
483 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
485 * [ if a single-CPU system runs an SMP kernel then we call the local
486 * interrupt as well. Thus we cannot inline the local irq ... ]
488 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
490 struct pt_regs
*old_regs
= set_irq_regs(regs
);
493 * NOTE! We'd better ACK the irq immediately,
494 * because timer handling can be slow.
498 * update_process_times() expects us to have done irq_enter().
499 * Besides, if we don't timer interrupts ignore the global
500 * interrupt lock, which is the WrongThing (tm) to do.
504 local_apic_timer_interrupt();
506 set_irq_regs(old_regs
);
509 int setup_profiling_timer(unsigned int multiplier
)
516 * Local APIC start and shutdown
520 * clear_local_APIC - shutdown the local APIC
522 * This is called, when a CPU is disabled and before rebooting, so the state of
523 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
524 * leftovers during boot.
526 void clear_local_APIC(void)
528 int maxlvt
= lapic_get_maxlvt();
531 /* APIC hasn't been mapped yet */
535 maxlvt
= lapic_get_maxlvt();
537 * Masking an LVT entry can trigger a local APIC error
538 * if the vector is zero. Mask LVTERR first to prevent this.
541 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
542 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
545 * Careful: we have to set masks only first to deassert
546 * any level-triggered sources.
548 v
= apic_read(APIC_LVTT
);
549 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
550 v
= apic_read(APIC_LVT0
);
551 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
552 v
= apic_read(APIC_LVT1
);
553 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
555 v
= apic_read(APIC_LVTPC
);
556 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
560 * Clean APIC state for other OSs:
562 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
563 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
564 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
566 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
568 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
569 apic_write(APIC_ESR
, 0);
574 * disable_local_APIC - clear and disable the local APIC
576 void disable_local_APIC(void)
583 * Disable APIC (implies clearing of registers
586 value
= apic_read(APIC_SPIV
);
587 value
&= ~APIC_SPIV_APIC_ENABLED
;
588 apic_write(APIC_SPIV
, value
);
591 void lapic_shutdown(void)
598 local_irq_save(flags
);
600 disable_local_APIC();
602 local_irq_restore(flags
);
606 * This is to verify that we're looking at a real local APIC.
607 * Check these against your board if the CPUs aren't getting
608 * started for no apparent reason.
610 int __init
verify_local_APIC(void)
612 unsigned int reg0
, reg1
;
615 * The version register is read-only in a real APIC.
617 reg0
= apic_read(APIC_LVR
);
618 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
619 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
620 reg1
= apic_read(APIC_LVR
);
621 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
624 * The two version reads above should print the same
625 * numbers. If the second one is different, then we
626 * poke at a non-APIC.
632 * Check if the version looks reasonably.
634 reg1
= GET_APIC_VERSION(reg0
);
635 if (reg1
== 0x00 || reg1
== 0xff)
637 reg1
= lapic_get_maxlvt();
638 if (reg1
< 0x02 || reg1
== 0xff)
642 * The ID register is read/write in a real APIC.
644 reg0
= apic_read(APIC_ID
);
645 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
646 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
647 reg1
= apic_read(APIC_ID
);
648 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
649 apic_write(APIC_ID
, reg0
);
650 if (reg1
!= (reg0
^ APIC_ID_MASK
))
654 * The next two are just to see if we have sane values.
655 * They're only really relevant if we're in Virtual Wire
656 * compatibility mode, but most boxes are anymore.
658 reg0
= apic_read(APIC_LVT0
);
659 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
660 reg1
= apic_read(APIC_LVT1
);
661 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
667 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
669 void __init
sync_Arb_IDs(void)
671 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
678 apic_wait_icr_idle();
680 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
681 apic_write(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
686 * An initial setup of the virtual wire mode.
688 void __init
init_bsp_APIC(void)
693 * Don't do the setup now if we have a SMP BIOS as the
694 * through-I/O-APIC virtual wire mode might be active.
696 if (smp_found_config
|| !cpu_has_apic
)
699 value
= apic_read(APIC_LVR
);
702 * Do not trust the local APIC being empty at bootup.
709 value
= apic_read(APIC_SPIV
);
710 value
&= ~APIC_VECTOR_MASK
;
711 value
|= APIC_SPIV_APIC_ENABLED
;
712 value
|= APIC_SPIV_FOCUS_DISABLED
;
713 value
|= SPURIOUS_APIC_VECTOR
;
714 apic_write(APIC_SPIV
, value
);
717 * Set up the virtual wire mode.
719 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
721 apic_write(APIC_LVT1
, value
);
725 * setup_local_APIC - setup the local APIC
727 void __cpuinit
setup_local_APIC(void)
732 value
= apic_read(APIC_LVR
);
734 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f);
737 * Double-check whether this APIC is really registered.
738 * This is meaningless in clustered apic mode, so we skip it.
740 if (!apic_id_registered())
744 * Intel recommends to set DFR, LDR and TPR before enabling
745 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
746 * document number 292116). So here it goes...
751 * Set Task Priority to 'accept all'. We never change this
754 value
= apic_read(APIC_TASKPRI
);
755 value
&= ~APIC_TPRI_MASK
;
756 apic_write(APIC_TASKPRI
, value
);
759 * After a crash, we no longer service the interrupts and a pending
760 * interrupt from previous kernel might still have ISR bit set.
762 * Most probably by now CPU has serviced that pending interrupt and
763 * it might not have done the ack_APIC_irq() because it thought,
764 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
765 * does not clear the ISR bit and cpu thinks it has already serivced
766 * the interrupt. Hence a vector might get locked. It was noticed
767 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
769 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
770 value
= apic_read(APIC_ISR
+ i
*0x10);
771 for (j
= 31; j
>= 0; j
--) {
778 * Now that we are all set up, enable the APIC
780 value
= apic_read(APIC_SPIV
);
781 value
&= ~APIC_VECTOR_MASK
;
785 value
|= APIC_SPIV_APIC_ENABLED
;
787 /* We always use processor focus */
790 * Set spurious IRQ vector
792 value
|= SPURIOUS_APIC_VECTOR
;
793 apic_write(APIC_SPIV
, value
);
798 * set up through-local-APIC on the BP's LINT0. This is not
799 * strictly necessary in pure symmetric-IO mode, but sometimes
800 * we delegate interrupts to the 8259A.
803 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
805 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
806 if (!smp_processor_id() && !value
) {
807 value
= APIC_DM_EXTINT
;
808 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
811 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
812 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
815 apic_write(APIC_LVT0
, value
);
818 * only the BP should see the LINT1 NMI signal, obviously.
820 if (!smp_processor_id())
823 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
824 apic_write(APIC_LVT1
, value
);
827 void __cpuinit
lapic_setup_esr(void)
829 unsigned maxlvt
= lapic_get_maxlvt();
831 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
);
833 * spec says clear errors after enabling vector.
836 apic_write(APIC_ESR
, 0);
839 void __cpuinit
end_local_APIC_setup(void)
842 nmi_watchdog_default();
843 setup_apic_nmi_watchdog(NULL
);
848 * Detect and enable local APICs on non-SMP boards.
849 * Original code written by Keir Fraser.
850 * On AMD64 we trust the BIOS - if it says no APIC it is likely
851 * not correctly set up (usually the APIC timer won't work etc.)
853 static int __init
detect_init_APIC(void)
856 printk(KERN_INFO
"No local APIC present\n");
860 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
861 boot_cpu_physical_apicid
= 0;
865 void __init
early_init_lapic_mapping(void)
867 unsigned long apic_phys
;
870 * If no local APIC can be found then go out
871 * : it means there is no mpatable and MADT
873 if (!smp_found_config
)
876 apic_phys
= mp_lapic_addr
;
878 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
879 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
880 APIC_BASE
, apic_phys
);
883 * Fetch the APIC ID of the BSP in case we have a
884 * default configuration (or the MP table is broken).
886 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
890 * init_apic_mappings - initialize APIC mappings
892 void __init
init_apic_mappings(void)
895 * If no local APIC can be found then set up a fake all
896 * zeroes page to simulate the local APIC and another
897 * one for the IO-APIC.
899 if (!smp_found_config
&& detect_init_APIC()) {
900 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
901 apic_phys
= __pa(apic_phys
);
903 apic_phys
= mp_lapic_addr
;
905 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
906 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
907 APIC_BASE
, apic_phys
);
910 * Fetch the APIC ID of the BSP in case we have a
911 * default configuration (or the MP table is broken).
913 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
917 * This initializes the IO-APIC and APIC hardware if this is
920 int __init
APIC_init_uniprocessor(void)
923 printk(KERN_INFO
"Apic disabled\n");
928 printk(KERN_INFO
"Apic disabled by BIOS\n");
934 phys_cpu_present_map
= physid_mask_of_physid(boot_cpu_physical_apicid
);
935 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
940 * Now enable IO-APICs, actually call clear_IO_APIC
941 * We need clear_IO_APIC before enabling vector on BP
943 if (!skip_ioapic_setup
&& nr_ioapics
)
946 end_local_APIC_setup();
948 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
952 setup_boot_APIC_clock();
953 check_nmi_watchdog();
958 * Local APIC interrupts
962 * This interrupt should _never_ happen with our APIC/SMP architecture
964 asmlinkage
void smp_spurious_interrupt(void)
970 * Check if this really is a spurious interrupt and ACK it
971 * if it is a vectored one. Just in case...
972 * Spurious interrupts should not be ACKed.
974 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
975 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
978 add_pda(irq_spurious_count
, 1);
983 * This interrupt should never happen with our APIC/SMP architecture
985 asmlinkage
void smp_error_interrupt(void)
991 /* First tickle the hardware, only then report what went on. -- REW */
992 v
= apic_read(APIC_ESR
);
993 apic_write(APIC_ESR
, 0);
994 v1
= apic_read(APIC_ESR
);
996 atomic_inc(&irq_err_count
);
998 /* Here is what the APIC error bits mean:
1001 2: Send accept error
1002 3: Receive accept error
1004 5: Send illegal vector
1005 6: Received illegal vector
1006 7: Illegal register address
1008 printk(KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)\n",
1009 smp_processor_id(), v
, v1
);
1013 void disconnect_bsp_APIC(int virt_wire_setup
)
1015 /* Go back to Virtual Wire compatibility mode */
1016 unsigned long value
;
1018 /* For the spurious interrupt use vector F, and enable it */
1019 value
= apic_read(APIC_SPIV
);
1020 value
&= ~APIC_VECTOR_MASK
;
1021 value
|= APIC_SPIV_APIC_ENABLED
;
1023 apic_write(APIC_SPIV
, value
);
1025 if (!virt_wire_setup
) {
1027 * For LVT0 make it edge triggered, active high,
1028 * external and enabled
1030 value
= apic_read(APIC_LVT0
);
1031 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1032 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1033 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1034 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1035 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1036 apic_write(APIC_LVT0
, value
);
1039 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1042 /* For LVT1 make it edge triggered, active high, nmi and enabled */
1043 value
= apic_read(APIC_LVT1
);
1044 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1045 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1046 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1047 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1048 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1049 apic_write(APIC_LVT1
, value
);
1058 /* 'active' is true if the local APIC was enabled by us and
1059 not the BIOS; this signifies that we are also responsible
1060 for disabling it before entering apm/acpi suspend */
1062 /* r/w apic fields */
1063 unsigned int apic_id
;
1064 unsigned int apic_taskpri
;
1065 unsigned int apic_ldr
;
1066 unsigned int apic_dfr
;
1067 unsigned int apic_spiv
;
1068 unsigned int apic_lvtt
;
1069 unsigned int apic_lvtpc
;
1070 unsigned int apic_lvt0
;
1071 unsigned int apic_lvt1
;
1072 unsigned int apic_lvterr
;
1073 unsigned int apic_tmict
;
1074 unsigned int apic_tdcr
;
1075 unsigned int apic_thmr
;
1078 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1080 unsigned long flags
;
1083 if (!apic_pm_state
.active
)
1086 maxlvt
= lapic_get_maxlvt();
1088 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1089 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1090 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1091 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1092 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1093 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1095 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1096 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1097 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1098 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1099 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1100 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1101 #ifdef CONFIG_X86_MCE_INTEL
1103 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1105 local_irq_save(flags
);
1106 disable_local_APIC();
1107 local_irq_restore(flags
);
1111 static int lapic_resume(struct sys_device
*dev
)
1114 unsigned long flags
;
1117 if (!apic_pm_state
.active
)
1120 maxlvt
= lapic_get_maxlvt();
1122 local_irq_save(flags
);
1123 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1124 l
&= ~MSR_IA32_APICBASE_BASE
;
1125 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1126 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1127 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1128 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1129 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1130 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1131 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1132 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1133 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1134 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1135 #ifdef CONFIG_X86_MCE_INTEL
1137 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1140 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1141 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1142 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1143 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1144 apic_write(APIC_ESR
, 0);
1145 apic_read(APIC_ESR
);
1146 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1147 apic_write(APIC_ESR
, 0);
1148 apic_read(APIC_ESR
);
1149 local_irq_restore(flags
);
1153 static struct sysdev_class lapic_sysclass
= {
1155 .resume
= lapic_resume
,
1156 .suspend
= lapic_suspend
,
1159 static struct sys_device device_lapic
= {
1161 .cls
= &lapic_sysclass
,
1164 static void __cpuinit
apic_pm_activate(void)
1166 apic_pm_state
.active
= 1;
1169 static int __init
init_lapic_sysfs(void)
1175 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1177 error
= sysdev_class_register(&lapic_sysclass
);
1179 error
= sysdev_register(&device_lapic
);
1182 device_initcall(init_lapic_sysfs
);
1184 #else /* CONFIG_PM */
1186 static void apic_pm_activate(void) { }
1188 #endif /* CONFIG_PM */
1191 * apic_is_clustered_box() -- Check if we can expect good TSC
1193 * Thus far, the major user of this is IBM's Summit2 series:
1195 * Clustered boxes may have unsynced TSC problems if they are
1196 * multi-chassis. Use available data to take a good guess.
1197 * If in doubt, go HPET.
1199 __cpuinit
int apic_is_clustered_box(void)
1201 int i
, clusters
, zeros
;
1203 u16
*bios_cpu_apicid
;
1204 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
1207 * there is not this kind of box with AMD CPU yet.
1208 * Some AMD box with quadcore cpu and 8 sockets apicid
1209 * will be [4, 0x23] or [8, 0x27] could be thought to
1210 * vsmp box still need checking...
1212 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
1215 bios_cpu_apicid
= x86_bios_cpu_apicid_early_ptr
;
1216 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
1218 for (i
= 0; i
< NR_CPUS
; i
++) {
1219 /* are we being called early in kernel startup? */
1220 if (bios_cpu_apicid
) {
1221 id
= bios_cpu_apicid
[i
];
1223 else if (i
< nr_cpu_ids
) {
1225 id
= per_cpu(x86_bios_cpu_apicid
, i
);
1232 if (id
!= BAD_APICID
)
1233 __set_bit(APIC_CLUSTERID(id
), clustermap
);
1236 /* Problem: Partially populated chassis may not have CPUs in some of
1237 * the APIC clusters they have been allocated. Only present CPUs have
1238 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1239 * Since clusters are allocated sequentially, count zeros only if
1240 * they are bounded by ones.
1244 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
1245 if (test_bit(i
, clustermap
)) {
1246 clusters
+= 1 + zeros
;
1252 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1253 * not guaranteed to be synced between boards
1255 if (is_vsmp_box() && clusters
> 1)
1259 * If clusters > 2, then should be multi-chassis.
1260 * May have to revisit this when multi-core + hyperthreaded CPUs come
1261 * out, but AFAIK this will work even for them.
1263 return (clusters
> 2);
1267 * APIC command line parameters
1269 static int __init
apic_set_verbosity(char *str
)
1272 skip_ioapic_setup
= 0;
1276 if (strcmp("debug", str
) == 0)
1277 apic_verbosity
= APIC_DEBUG
;
1278 else if (strcmp("verbose", str
) == 0)
1279 apic_verbosity
= APIC_VERBOSE
;
1281 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
1282 " use apic=verbose or apic=debug\n", str
);
1288 early_param("apic", apic_set_verbosity
);
1290 static __init
int setup_disableapic(char *str
)
1293 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1296 early_param("disableapic", setup_disableapic
);
1298 /* same as disableapic, for compatibility */
1299 static __init
int setup_nolapic(char *str
)
1301 return setup_disableapic(str
);
1303 early_param("nolapic", setup_nolapic
);
1305 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1307 local_apic_timer_c2_ok
= 1;
1310 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1312 static __init
int setup_noapictimer(char *str
)
1314 if (str
[0] != ' ' && str
[0] != 0)
1316 disable_apic_timer
= 1;
1319 __setup("noapictimer", setup_noapictimer
);
1321 static __init
int setup_apicpmtimer(char *s
)
1323 apic_calibrate_pmtmr
= 1;
1327 __setup("apicpmtimer", setup_apicpmtimer
);
1329 static int __init
lapic_insert_resource(void)
1334 /* Put local APIC into the resource map. */
1335 lapic_resource
.start
= apic_phys
;
1336 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
1337 insert_resource(&iomem_resource
, &lapic_resource
);
1343 * need call insert after e820_reserve_resources()
1344 * that is using request_resource
1346 late_initcall(lapic_insert_resource
);