arch/arm/mach-at91/at91rm9200_time.c

   1 /*
   2  * linux/arch/arm/mach-at91/at91rm9200_time.c
   3  *
   4  *  Copyright (C) 2003 SAN People
   5  *  Copyright (C) 2003 ATMEL
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/clockchips.h>
  26 #include <linux/export.h>
  27 #include <linux/of.h>
  28 #include <linux/of_address.h>
  29 #include <linux/of_irq.h>
  30
  31 #include <asm/mach/time.h>
  32
  33 #include <mach/at91_st.h>
  34
  35 static unsigned long last_crtr;
  36 static u32 irqmask;
  37 static struct clock_event_device clkevt;
  38
  39 #define RM9200_TIMER_LATCH      ((AT91_SLOW_CLOCK + HZ/2) / HZ)
  40
  41 /*
  42  * The ST_CRTR is updated asynchronously to the master clock ... but
  43  * the updates as seen by the CPU don't seem to be strictly monotonic.
  44  * Waiting until we read the same value twice avoids glitching.
  45  */
  46 static inline unsigned long read_CRTR(void)
  47 {
  48         unsigned long x1, x2;
  49
  50         x1 = at91_st_read(AT91_ST_CRTR);
  51         do {
  52                 x2 = at91_st_read(AT91_ST_CRTR);
  53                 if (x1 == x2)
  54                         break;
  55                 x1 = x2;
  56         } while (1);
  57         return x1;
  58 }
  59
  60 /*
  61  * IRQ handler for the timer.
  62  */
  63 static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
  64 {
  65         u32     sr = at91_st_read(AT91_ST_SR) & irqmask;
  66
  67         /*
  68          * irqs should be disabled here, but as the irq is shared they are only
  69          * guaranteed to be off if the timer irq is registered first.
  70          */
  71         WARN_ON_ONCE(!irqs_disabled());
  72
  73         /* simulate "oneshot" timer with alarm */
  74         if (sr & AT91_ST_ALMS) {
  75                 clkevt.event_handler(&clkevt);
  76                 return IRQ_HANDLED;
  77         }
  78
  79         /* periodic mode should handle delayed ticks */
  80         if (sr & AT91_ST_PITS) {
  81                 u32     crtr = read_CRTR();
  82
  83                 while (((crtr - last_crtr) & AT91_ST_CRTV) >= RM9200_TIMER_LATCH) {
  84                         last_crtr += RM9200_TIMER_LATCH;
  85                         clkevt.event_handler(&clkevt);
  86                 }
  87                 return IRQ_HANDLED;
  88         }
  89
  90         /* this irq is shared ... */
  91         return IRQ_NONE;
  92 }
  93
  94 static struct irqaction at91rm9200_timer_irq = {
  95         .name           = "at91_tick",
  96         .flags          = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
  97         .handler        = at91rm9200_timer_interrupt,
  98         .irq            = NR_IRQS_LEGACY + AT91_ID_SYS,
  99 };
 100
 101 static cycle_t read_clk32k(struct clocksource *cs)
 102 {
 103         return read_CRTR();
 104 }
 105
 106 static struct clocksource clk32k = {
 107         .name           = "32k_counter",
 108         .rating         = 150,
 109         .read           = read_clk32k,
 110         .mask           = CLOCKSOURCE_MASK(20),
 111         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 112 };
 113
 114 static void
 115 clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
 116 {
 117         /* Disable and flush pending timer interrupts */
 118         at91_st_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
 119         at91_st_read(AT91_ST_SR);
 120
 121         last_crtr = read_CRTR();
 122         switch (mode) {
 123         case CLOCK_EVT_MODE_PERIODIC:
 124                 /* PIT for periodic irqs; fixed rate of 1/HZ */
 125                 irqmask = AT91_ST_PITS;
 126                 at91_st_write(AT91_ST_PIMR, RM9200_TIMER_LATCH);
 127                 break;
 128         case CLOCK_EVT_MODE_ONESHOT:
 129                 /* ALM for oneshot irqs, set by next_event()
 130                  * before 32 seconds have passed
 131                  */
 132                 irqmask = AT91_ST_ALMS;
 133                 at91_st_write(AT91_ST_RTAR, last_crtr);
 134                 break;
 135         case CLOCK_EVT_MODE_SHUTDOWN:
 136         case CLOCK_EVT_MODE_UNUSED:
 137         case CLOCK_EVT_MODE_RESUME:
 138                 irqmask = 0;
 139                 break;
 140         }
 141         at91_st_write(AT91_ST_IER, irqmask);
 142 }
 143
 144 static int
 145 clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
 146 {
 147         u32             alm;
 148         int             status = 0;
 149
 150         BUG_ON(delta < 2);
 151
 152         /* The alarm IRQ uses absolute time (now+delta), not the relative
 153          * time (delta) in our calling convention.  Like all clockevents
 154          * using such "match" hardware, we have a race to defend against.
 155          *
 156          * Our defense here is to have set up the clockevent device so the
 157          * delta is at least two.  That way we never end up writing RTAR
 158          * with the value then held in CRTR ... which would mean the match
 159          * wouldn't trigger until 32 seconds later, after CRTR wraps.
 160          */
 161         alm = read_CRTR();
 162
 163         /* Cancel any pending alarm; flush any pending IRQ */
 164         at91_st_write(AT91_ST_RTAR, alm);
 165         at91_st_read(AT91_ST_SR);
 166
 167         /* Schedule alarm by writing RTAR. */
 168         alm += delta;
 169         at91_st_write(AT91_ST_RTAR, alm);
 170
 171         return status;
 172 }
 173
 174 static struct clock_event_device clkevt = {
 175         .name           = "at91_tick",
 176         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 177         .shift          = 32,
 178         .rating         = 150,
 179         .set_next_event = clkevt32k_next_event,
 180         .set_mode       = clkevt32k_mode,
 181 };
 182
 183 void __iomem *at91_st_base;
 184 EXPORT_SYMBOL_GPL(at91_st_base);
 185
 186 #ifdef CONFIG_OF
 187 static struct of_device_id at91rm9200_st_timer_ids[] = {
 188         { .compatible = "atmel,at91rm9200-st" },
 189         { /* sentinel */ }
 190 };
 191
 192 static int __init of_at91rm9200_st_init(void)
 193 {
 194         struct device_node *np;
 195         int ret;
 196
 197         np = of_find_matching_node(NULL, at91rm9200_st_timer_ids);
 198         if (!np)
 199                 goto err;
 200
 201         at91_st_base = of_iomap(np, 0);
 202         if (!at91_st_base)
 203                 goto node_err;
 204
 205         /* Get the interrupts property */
 206         ret = irq_of_parse_and_map(np, 0);
 207         if (!ret)
 208                 goto ioremap_err;
 209         at91rm9200_timer_irq.irq = ret;
 210
 211         of_node_put(np);
 212
 213         return 0;
 214
 215 ioremap_err:
 216         iounmap(at91_st_base);
 217 node_err:
 218         of_node_put(np);
 219 err:
 220         return -EINVAL;
 221 }
 222 #else
 223 static int __init of_at91rm9200_st_init(void)
 224 {
 225         return -EINVAL;
 226 }
 227 #endif
 228
 229 void __init at91rm9200_ioremap_st(u32 addr)
 230 {
 231 #ifdef CONFIG_OF
 232         struct device_node *np;
 233
 234         np = of_find_matching_node(NULL, at91rm9200_st_timer_ids);
 235         if (np) {
 236                 of_node_put(np);
 237                 return;
 238         }
 239 #endif
 240         at91_st_base = ioremap(addr, 256);
 241         if (!at91_st_base)
 242                 panic("Impossible to ioremap ST\n");
 243 }
 244
 245 /*
 246  * ST (system timer) module supports both clockevents and clocksource.
 247  */
 248 void __init at91rm9200_timer_init(void)
 249 {
 250         /* For device tree enabled device: initialize here */
 251         of_at91rm9200_st_init();
 252
 253         /* Disable all timer interrupts, and clear any pending ones */
 254         at91_st_write(AT91_ST_IDR,
 255                 AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
 256         at91_st_read(AT91_ST_SR);
 257
 258         /* Make IRQs happen for the system timer */
 259         setup_irq(at91rm9200_timer_irq.irq, &at91rm9200_timer_irq);
 260
 261         /* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
 262          * directly for the clocksource and all clockevents, after adjusting
 263          * its prescaler from the 1 Hz default.
 264          */
 265         at91_st_write(AT91_ST_RTMR, 1);
 266
 267         /* Setup timer clockevent, with minimum of two ticks (important!!) */
 268         clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
 269         clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt);
 270         clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1;
 271         clkevt.cpumask = cpumask_of(0);
 272         clockevents_register_device(&clkevt);
 273
 274         /* register clocksource */
 275         clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);
 276 }