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[PATCH] atyfb: Fix section warnings
[linux-2.6.git] / drivers / video / aty / atyfb_base.c
blob22e720611bf674b31702260ca858b684c889084f
1 /*
2 * ATI Frame Buffer Device Driver Core
3 *
4 * Copyright (C) 2004 Alex Kern <alex.kern@gmx.de>
5 * Copyright (C) 1997-2001 Geert Uytterhoeven
6 * Copyright (C) 1998 Bernd Harries
7 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
8 *
9 * This driver supports the following ATI graphics chips:
10 * - ATI Mach64
11 *
12 * To do: add support for
13 * - ATI Rage128 (from aty128fb.c)
14 * - ATI Radeon (from radeonfb.c)
15 *
16 * This driver is partly based on the PowerMac console driver:
17 *
18 * Copyright (C) 1996 Paul Mackerras
19 *
20 * and on the PowerMac ATI/mach64 display driver:
21 *
22 * Copyright (C) 1997 Michael AK Tesch
23 *
24 * with work by Jon Howell
25 * Harry AC Eaton
26 * Anthony Tong <atong@uiuc.edu>
27 *
28 * Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
29 * Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
30 *
31 * This file is subject to the terms and conditions of the GNU General Public
32 * License. See the file COPYING in the main directory of this archive for
33 * more details.
34 *
35 * Many thanks to Nitya from ATI devrel for support and patience !
36 */
37
38 /******************************************************************************
39
40 TODO:
41
42 - cursor support on all cards and all ramdacs.
43 - cursor parameters controlable via ioctl()s.
44 - guess PLL and MCLK based on the original PLL register values initialized
45 by Open Firmware (if they are initialized). BIOS is done
46
47 (Anyone with Mac to help with this?)
48
49 ******************************************************************************/
50
51
52 #include <linux/config.h>
53 #include <linux/module.h>
54 #include <linux/moduleparam.h>
55 #include <linux/kernel.h>
56 #include <linux/errno.h>
57 #include <linux/string.h>
58 #include <linux/mm.h>
59 #include <linux/slab.h>
60 #include <linux/vmalloc.h>
61 #include <linux/delay.h>
62 #include <linux/console.h>
63 #include <linux/fb.h>
64 #include <linux/init.h>
65 #include <linux/pci.h>
66 #include <linux/interrupt.h>
67 #include <linux/spinlock.h>
68 #include <linux/wait.h>
69 #include <linux/backlight.h>
70
71 #include <asm/io.h>
72 #include <asm/uaccess.h>
73
74 #include <video/mach64.h>
75 #include "atyfb.h"
76 #include "ati_ids.h"
77
78 #ifdef __powerpc__
79 #include <asm/machdep.h>
80 #include <asm/prom.h>
81 #include "../macmodes.h"
82 #endif
83 #ifdef __sparc__
84 #include <asm/pbm.h>
85 #include <asm/fbio.h>
86 #endif
87
88 #ifdef CONFIG_ADB_PMU
89 #include <linux/adb.h>
90 #include <linux/pmu.h>
91 #endif
92 #ifdef CONFIG_BOOTX_TEXT
93 #include <asm/btext.h>
94 #endif
95 #ifdef CONFIG_PMAC_BACKLIGHT
96 #include <asm/backlight.h>
97 #endif
98 #ifdef CONFIG_MTRR
99 #include <asm/mtrr.h>
100 #endif
101
102 /*
103 * Debug flags.
104 */
105 #undef DEBUG
106 /*#define DEBUG*/
107
108 /* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
109 /* - must be large enough to catch all GUI-Regs */
110 /* - must be aligned to a PAGE boundary */
111 #define GUI_RESERVE (1 * PAGE_SIZE)
112
113 /* FIXME: remove the FAIL definition */
114 #define FAIL(msg) do { \
115 if (!(var->activate & FB_ACTIVATE_TEST)) \
116 printk(KERN_CRIT "atyfb: " msg "\n"); \
117 return -EINVAL; \
118 } while (0)
119 #define FAIL_MAX(msg, x, _max_) do { \
120 if (x > _max_) { \
121 if (!(var->activate & FB_ACTIVATE_TEST)) \
122 printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); \
123 return -EINVAL; \
124 } \
125 } while (0)
126 #ifdef DEBUG
127 #define DPRINTK(fmt, args...) printk(KERN_DEBUG "atyfb: " fmt, ## args)
128 #else
129 #define DPRINTK(fmt, args...)
130 #endif
131
132 #define PRINTKI(fmt, args...) printk(KERN_INFO "atyfb: " fmt, ## args)
133 #define PRINTKE(fmt, args...) printk(KERN_ERR "atyfb: " fmt, ## args)
134
135 #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD)
136 static const u32 lt_lcd_regs[] = {
137 CONFIG_PANEL_LG,
138 LCD_GEN_CNTL_LG,
139 DSTN_CONTROL_LG,
140 HFB_PITCH_ADDR_LG,
141 HORZ_STRETCHING_LG,
142 VERT_STRETCHING_LG,
143 0, /* EXT_VERT_STRETCH */
144 LT_GIO_LG,
145 POWER_MANAGEMENT_LG
146 };
147
148 void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
149 {
150 if (M64_HAS(LT_LCD_REGS)) {
151 aty_st_le32(lt_lcd_regs[index], val, par);
152 } else {
153 unsigned long temp;
154
155 /* write addr byte */
156 temp = aty_ld_le32(LCD_INDEX, par);
157 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
158 /* write the register value */
159 aty_st_le32(LCD_DATA, val, par);
160 }
161 }
162
163 u32 aty_ld_lcd(int index, const struct atyfb_par *par)
164 {
165 if (M64_HAS(LT_LCD_REGS)) {
166 return aty_ld_le32(lt_lcd_regs[index], par);
167 } else {
168 unsigned long temp;
169
170 /* write addr byte */
171 temp = aty_ld_le32(LCD_INDEX, par);
172 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
173 /* read the register value */
174 return aty_ld_le32(LCD_DATA, par);
175 }
176 }
177 #endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */
178
179 #ifdef CONFIG_FB_ATY_GENERIC_LCD
180 /*
181 * ATIReduceRatio --
182 *
183 * Reduce a fraction by factoring out the largest common divider of the
184 * fraction's numerator and denominator.
185 */
186 static void ATIReduceRatio(int *Numerator, int *Denominator)
187 {
188 int Multiplier, Divider, Remainder;
189
190 Multiplier = *Numerator;
191 Divider = *Denominator;
192
193 while ((Remainder = Multiplier % Divider))
194 {
195 Multiplier = Divider;
196 Divider = Remainder;
197 }
198
199 *Numerator /= Divider;
200 *Denominator /= Divider;
201 }
202 #endif
203 /*
204 * The Hardware parameters for each card
205 */
206
207 struct aty_cmap_regs {
208 u8 windex;
209 u8 lut;
210 u8 mask;
211 u8 rindex;
212 u8 cntl;
213 };
214
215 struct pci_mmap_map {
216 unsigned long voff;
217 unsigned long poff;
218 unsigned long size;
219 unsigned long prot_flag;
220 unsigned long prot_mask;
221 };
222
223 static struct fb_fix_screeninfo atyfb_fix __devinitdata = {
224 .id = "ATY Mach64",
225 .type = FB_TYPE_PACKED_PIXELS,
226 .visual = FB_VISUAL_PSEUDOCOLOR,
227 .xpanstep = 8,
228 .ypanstep = 1,
229 };
230
231 /*
232 * Frame buffer device API
233 */
234
235 static int atyfb_open(struct fb_info *info, int user);
236 static int atyfb_release(struct fb_info *info, int user);
237 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
238 static int atyfb_set_par(struct fb_info *info);
239 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
240 u_int transp, struct fb_info *info);
241 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
242 static int atyfb_blank(int blank, struct fb_info *info);
243 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg);
244 extern void atyfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
245 extern void atyfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
246 extern void atyfb_imageblit(struct fb_info *info, const struct fb_image *image);
247 #ifdef __sparc__
248 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma);
249 #endif
250 static int atyfb_sync(struct fb_info *info);
251
252 /*
253 * Internal routines
254 */
255
256 static int aty_init(struct fb_info *info, const char *name);
257 #ifdef CONFIG_ATARI
258 static int store_video_par(char *videopar, unsigned char m64_num);
259 #endif
260
261 static struct crtc saved_crtc;
262 static union aty_pll saved_pll;
263 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
264
265 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
266 static int aty_var_to_crtc(const struct fb_info *info, const struct fb_var_screeninfo *var, struct crtc *crtc);
267 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var);
268 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
269 #ifdef CONFIG_PPC
270 static int read_aty_sense(const struct atyfb_par *par);
271 #endif
272
273
274 /*
275 * Interface used by the world
276 */
277
278 static struct fb_var_screeninfo default_var = {
279 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
280 640, 480, 640, 480, 0, 0, 8, 0,
281 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
282 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
283 0, FB_VMODE_NONINTERLACED
284 };
285
286 static struct fb_videomode defmode = {
287 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
288 NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
289 0, FB_VMODE_NONINTERLACED
290 };
291
292 static struct fb_ops atyfb_ops = {
293 .owner = THIS_MODULE,
294 .fb_open = atyfb_open,
295 .fb_release = atyfb_release,
296 .fb_check_var = atyfb_check_var,
297 .fb_set_par = atyfb_set_par,
298 .fb_setcolreg = atyfb_setcolreg,
299 .fb_pan_display = atyfb_pan_display,
300 .fb_blank = atyfb_blank,
301 .fb_ioctl = atyfb_ioctl,
302 .fb_fillrect = atyfb_fillrect,
303 .fb_copyarea = atyfb_copyarea,
304 .fb_imageblit = atyfb_imageblit,
305 #ifdef __sparc__
306 .fb_mmap = atyfb_mmap,
307 #endif
308 .fb_sync = atyfb_sync,
309 };
310
311 static int noaccel;
312 #ifdef CONFIG_MTRR
313 static int nomtrr;
314 #endif
315 static int vram;
316 static int pll;
317 static int mclk;
318 static int xclk;
319 static int comp_sync __devinitdata = -1;
320 static char *mode;
321
322 #ifdef CONFIG_PPC
323 static int default_vmode __devinitdata = VMODE_CHOOSE;
324 static int default_cmode __devinitdata = CMODE_CHOOSE;
325
326 module_param_named(vmode, default_vmode, int, 0);
327 MODULE_PARM_DESC(vmode, "int: video mode for mac");
328 module_param_named(cmode, default_cmode, int, 0);
329 MODULE_PARM_DESC(cmode, "int: color mode for mac");
330 #endif
331
332 #ifdef CONFIG_ATARI
333 static unsigned int mach64_count __devinitdata = 0;
334 static unsigned long phys_vmembase[FB_MAX] __devinitdata = { 0, };
335 static unsigned long phys_size[FB_MAX] __devinitdata = { 0, };
336 static unsigned long phys_guiregbase[FB_MAX] __devinitdata = { 0, };
337 #endif
338
339 /* top -> down is an evolution of mach64 chipset, any corrections? */
340 #define ATI_CHIP_88800GX (M64F_GX)
341 #define ATI_CHIP_88800CX (M64F_GX)
342
343 #define ATI_CHIP_264CT (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
344 #define ATI_CHIP_264ET (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
345
346 #define ATI_CHIP_264VT (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
347 #define ATI_CHIP_264GT (M64F_GT | M64F_INTEGRATED | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
348
349 #define ATI_CHIP_264VTB (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
350 #define ATI_CHIP_264VT3 (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
351 #define ATI_CHIP_264VT4 (M64F_VT | M64F_INTEGRATED | M64F_GTB_DSP)
352
353 /* FIXME what is this chip? */
354 #define ATI_CHIP_264LT (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP)
355
356 /* make sets shorter */
357 #define ATI_MODERN_SET (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
358
359 #define ATI_CHIP_264GTB (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
360 /*#define ATI_CHIP_264GTDVD ?*/
361 #define ATI_CHIP_264LTG (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
362
363 #define ATI_CHIP_264GT2C (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
364 #define ATI_CHIP_264GTPRO (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
365 #define ATI_CHIP_264LTPRO (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
366
367 #define ATI_CHIP_264XL (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4)
368 #define ATI_CHIP_MOBILITY (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_MOBIL_BUS)
369
370 static struct {
371 u16 pci_id;
372 const char *name;
373 int pll, mclk, xclk, ecp_max;
374 u32 features;
375 } aty_chips[] __devinitdata = {
376 #ifdef CONFIG_FB_ATY_GX
377 /* Mach64 GX */
378 { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, 0, ATI_CHIP_88800GX },
379 { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, 0, ATI_CHIP_88800CX },
380 #endif /* CONFIG_FB_ATY_GX */
381
382 #ifdef CONFIG_FB_ATY_CT
383 { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, 0, ATI_CHIP_264CT },
384 { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, 0, ATI_CHIP_264ET },
385
386 /* FIXME what is this chip? */
387 { PCI_CHIP_MACH64LT, "ATI264LT (Mach64 LT)", 135, 63, 63, 0, ATI_CHIP_264LT },
388
389 { PCI_CHIP_MACH64VT, "ATI264VT (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT },
390 { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, 80, ATI_CHIP_264GT },
391
392 { PCI_CHIP_MACH64VU, "ATI264VT3 (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3 },
393 { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GU)", 200, 67, 67, 100, ATI_CHIP_264GTB },
394
395 { PCI_CHIP_MACH64LG, "3D RAGE LT (Mach64 LG)", 230, 63, 63, 100, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
396
397 { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, 100, ATI_CHIP_264VT4 },
398
399 { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
400 { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
401 { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
402 { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
403
404 { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
405 { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
406 { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
407 { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
408 { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
409
410 { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, 135, ATI_CHIP_264LTPRO },
411 { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
412 { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
413 { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
414 { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
415
416 { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
417 { PCI_CHIP_MACH64GN, "3D RAGE XC (Mach64 GN, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
418 { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
419 { PCI_CHIP_MACH64GL, "3D RAGE XC (Mach64 GL, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
420 { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL | M64F_SDRAM_MAGIC_PLL },
421 { PCI_CHIP_MACH64GS, "3D RAGE XC (Mach64 GS, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL },
422
423 { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
424 { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
425 { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
426 { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
427 #endif /* CONFIG_FB_ATY_CT */
428 };
429
430 /* can not fail */
431 static int __devinit correct_chipset(struct atyfb_par *par)
432 {
433 u8 rev;
434 u16 type;
435 u32 chip_id;
436 const char *name;
437 int i;
438
439 for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
440 if (par->pci_id == aty_chips[i].pci_id)
441 break;
442
443 name = aty_chips[i].name;
444 par->pll_limits.pll_max = aty_chips[i].pll;
445 par->pll_limits.mclk = aty_chips[i].mclk;
446 par->pll_limits.xclk = aty_chips[i].xclk;
447 par->pll_limits.ecp_max = aty_chips[i].ecp_max;
448 par->features = aty_chips[i].features;
449
450 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
451 type = chip_id & CFG_CHIP_TYPE;
452 rev = (chip_id & CFG_CHIP_REV) >> 24;
453
454 switch(par->pci_id) {
455 #ifdef CONFIG_FB_ATY_GX
456 case PCI_CHIP_MACH64GX:
457 if(type != 0x00d7)
458 return -ENODEV;
459 break;
460 case PCI_CHIP_MACH64CX:
461 if(type != 0x0057)
462 return -ENODEV;
463 break;
464 #endif
465 #ifdef CONFIG_FB_ATY_CT
466 case PCI_CHIP_MACH64VT:
467 switch (rev & 0x07) {
468 case 0x00:
469 switch (rev & 0xc0) {
470 case 0x00:
471 name = "ATI264VT (A3) (Mach64 VT)";
472 par->pll_limits.pll_max = 170;
473 par->pll_limits.mclk = 67;
474 par->pll_limits.xclk = 67;
475 par->pll_limits.ecp_max = 80;
476 par->features = ATI_CHIP_264VT;
477 break;
478 case 0x40:
479 name = "ATI264VT2 (A4) (Mach64 VT)";
480 par->pll_limits.pll_max = 200;
481 par->pll_limits.mclk = 67;
482 par->pll_limits.xclk = 67;
483 par->pll_limits.ecp_max = 80;
484 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
485 break;
486 }
487 break;
488 case 0x01:
489 name = "ATI264VT3 (B1) (Mach64 VT)";
490 par->pll_limits.pll_max = 200;
491 par->pll_limits.mclk = 67;
492 par->pll_limits.xclk = 67;
493 par->pll_limits.ecp_max = 80;
494 par->features = ATI_CHIP_264VTB;
495 break;
496 case 0x02:
497 name = "ATI264VT3 (B2) (Mach64 VT)";
498 par->pll_limits.pll_max = 200;
499 par->pll_limits.mclk = 67;
500 par->pll_limits.xclk = 67;
501 par->pll_limits.ecp_max = 80;
502 par->features = ATI_CHIP_264VT3;
503 break;
504 }
505 break;
506 case PCI_CHIP_MACH64GT:
507 switch (rev & 0x07) {
508 case 0x01:
509 name = "3D RAGE II (Mach64 GT)";
510 par->pll_limits.pll_max = 170;
511 par->pll_limits.mclk = 67;
512 par->pll_limits.xclk = 67;
513 par->pll_limits.ecp_max = 80;
514 par->features = ATI_CHIP_264GTB;
515 break;
516 case 0x02:
517 name = "3D RAGE II+ (Mach64 GT)";
518 par->pll_limits.pll_max = 200;
519 par->pll_limits.mclk = 67;
520 par->pll_limits.xclk = 67;
521 par->pll_limits.ecp_max = 100;
522 par->features = ATI_CHIP_264GTB;
523 break;
524 }
525 break;
526 #endif
527 }
528
529 PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev);
530 return 0;
531 }
532
533 static char ram_dram[] __devinitdata = "DRAM";
534 static char ram_resv[] __devinitdata = "RESV";
535 #ifdef CONFIG_FB_ATY_GX
536 static char ram_vram[] __devinitdata = "VRAM";
537 #endif /* CONFIG_FB_ATY_GX */
538 #ifdef CONFIG_FB_ATY_CT
539 static char ram_edo[] __devinitdata = "EDO";
540 static char ram_sdram[] __devinitdata = "SDRAM (1:1)";
541 static char ram_sgram[] __devinitdata = "SGRAM (1:1)";
542 static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)";
543 static char ram_off[] __devinitdata = "OFF";
544 #endif /* CONFIG_FB_ATY_CT */
545
546
547 static u32 pseudo_palette[17];
548
549 #ifdef CONFIG_FB_ATY_GX
550 static char *aty_gx_ram[8] __devinitdata = {
551 ram_dram, ram_vram, ram_vram, ram_dram,
552 ram_dram, ram_vram, ram_vram, ram_resv
553 };
554 #endif /* CONFIG_FB_ATY_GX */
555
556 #ifdef CONFIG_FB_ATY_CT
557 static char *aty_ct_ram[8] __devinitdata = {
558 ram_off, ram_dram, ram_edo, ram_edo,
559 ram_sdram, ram_sgram, ram_sdram32, ram_resv
560 };
561 #endif /* CONFIG_FB_ATY_CT */
562
563 static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var, struct atyfb_par *par)
564 {
565 u32 pixclock = var->pixclock;
566 #ifdef CONFIG_FB_ATY_GENERIC_LCD
567 u32 lcd_on_off;
568 par->pll.ct.xres = 0;
569 if (par->lcd_table != 0) {
570 lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
571 if(lcd_on_off & LCD_ON) {
572 par->pll.ct.xres = var->xres;
573 pixclock = par->lcd_pixclock;
574 }
575 }
576 #endif
577 return pixclock;
578 }
579
580 #if defined(CONFIG_PPC)
581
582 /*
583 * Apple monitor sense
584 */
585
586 static int __devinit read_aty_sense(const struct atyfb_par *par)
587 {
588 int sense, i;
589
590 aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
591 __delay(200);
592 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
593 __delay(2000);
594 i = aty_ld_le32(GP_IO, par); /* get primary sense value */
595 sense = ((i & 0x3000) >> 3) | (i & 0x100);
596
597 /* drive each sense line low in turn and collect the other 2 */
598 aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
599 __delay(2000);
600 i = aty_ld_le32(GP_IO, par);
601 sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
602 aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
603 __delay(200);
604
605 aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
606 __delay(2000);
607 i = aty_ld_le32(GP_IO, par);
608 sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
609 aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
610 __delay(200);
611
612 aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
613 __delay(2000);
614 sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
615 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
616 return sense;
617 }
618
619 #endif /* defined(CONFIG_PPC) */
620
621 /* ------------------------------------------------------------------------- */
622
623 /*
624 * CRTC programming
625 */
626
627 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
628 {
629 #ifdef CONFIG_FB_ATY_GENERIC_LCD
630 if (par->lcd_table != 0) {
631 if(!M64_HAS(LT_LCD_REGS)) {
632 crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
633 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
634 }
635 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par);
636 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
637
638
639 /* switch to non shadow registers */
640 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
641 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
642
643 /* save stretching */
644 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
645 crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
646 if (!M64_HAS(LT_LCD_REGS))
647 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
648 }
649 #endif
650 crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
651 crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
652 crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
653 crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
654 crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
655 crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
656 crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
657
658 #ifdef CONFIG_FB_ATY_GENERIC_LCD
659 if (par->lcd_table != 0) {
660 /* switch to shadow registers */
661 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
662 SHADOW_EN | SHADOW_RW_EN, par);
663
664 crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
665 crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
666 crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
667 crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
668
669 aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
670 }
671 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
672 }
673
674 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
675 {
676 #ifdef CONFIG_FB_ATY_GENERIC_LCD
677 if (par->lcd_table != 0) {
678 /* stop CRTC */
679 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
680
681 /* update non-shadow registers first */
682 aty_st_lcd(CONFIG_PANEL, crtc->lcd_config_panel, par);
683 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
684 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
685
686 /* temporarily disable stretching */
687 aty_st_lcd(HORZ_STRETCHING,
688 crtc->horz_stretching &
689 ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
690 aty_st_lcd(VERT_STRETCHING,
691 crtc->vert_stretching &
692 ~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 |
693 VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
694 }
695 #endif
696 /* turn off CRT */
697 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
698
699 DPRINTK("setting up CRTC\n");
700 DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
701 ((((crtc->h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->v_tot_disp>>16) & 0x7ff) + 1),
702 (crtc->h_sync_strt_wid & 0x200000)?'N':'P', (crtc->v_sync_strt_wid & 0x200000)?'N':'P',
703 (crtc->gen_cntl & CRTC_CSYNC_EN)?'P':'N');
704
705 DPRINTK("CRTC_H_TOTAL_DISP: %x\n",crtc->h_tot_disp);
706 DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n",crtc->h_sync_strt_wid);
707 DPRINTK("CRTC_V_TOTAL_DISP: %x\n",crtc->v_tot_disp);
708 DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n",crtc->v_sync_strt_wid);
709 DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch);
710 DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline);
711 DPRINTK("CRTC_GEN_CNTL: %x\n",crtc->gen_cntl);
712
713 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
714 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
715 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
716 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
717 aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
718 aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
719
720 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
721 #if 0
722 FIXME
723 if (par->accel_flags & FB_ACCELF_TEXT)
724 aty_init_engine(par, info);
725 #endif
726 #ifdef CONFIG_FB_ATY_GENERIC_LCD
727 /* after setting the CRTC registers we should set the LCD registers. */
728 if (par->lcd_table != 0) {
729 /* switch to shadow registers */
730 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
731 (SHADOW_EN | SHADOW_RW_EN), par);
732
733 DPRINTK("set shadow CRT to %ix%i %c%c\n",
734 ((((crtc->shadow_h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->shadow_v_tot_disp>>16) & 0x7ff) + 1),
735 (crtc->shadow_h_sync_strt_wid & 0x200000)?'N':'P', (crtc->shadow_v_sync_strt_wid & 0x200000)?'N':'P');
736
737 DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n", crtc->shadow_h_tot_disp);
738 DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n", crtc->shadow_h_sync_strt_wid);
739 DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n", crtc->shadow_v_tot_disp);
740 DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n", crtc->shadow_v_sync_strt_wid);
741
742 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
743 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
744 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
745 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
746
747 /* restore CRTC selection & shadow state and enable stretching */
748 DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl);
749 DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching);
750 DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching);
751 if(!M64_HAS(LT_LCD_REGS))
752 DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch);
753
754 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
755 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
756 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
757 if(!M64_HAS(LT_LCD_REGS)) {
758 aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
759 aty_ld_le32(LCD_INDEX, par);
760 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
761 }
762 }
763 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
764 }
765
766 static int aty_var_to_crtc(const struct fb_info *info,
767 const struct fb_var_screeninfo *var, struct crtc *crtc)
768 {
769 struct atyfb_par *par = (struct atyfb_par *) info->par;
770 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
771 u32 sync, vmode, vdisplay;
772 u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol;
773 u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync;
774 u32 pix_width, dp_pix_width, dp_chain_mask;
775
776 /* input */
777 xres = var->xres;
778 yres = var->yres;
779 vxres = var->xres_virtual;
780 vyres = var->yres_virtual;
781 xoffset = var->xoffset;
782 yoffset = var->yoffset;
783 bpp = var->bits_per_pixel;
784 if (bpp == 16)
785 bpp = (var->green.length == 5) ? 15 : 16;
786 sync = var->sync;
787 vmode = var->vmode;
788
789 /* convert (and round up) and validate */
790 if (vxres < xres + xoffset)
791 vxres = xres + xoffset;
792 h_disp = xres;
793
794 if (vyres < yres + yoffset)
795 vyres = yres + yoffset;
796 v_disp = yres;
797
798 if (bpp <= 8) {
799 bpp = 8;
800 pix_width = CRTC_PIX_WIDTH_8BPP;
801 dp_pix_width =
802 HOST_8BPP | SRC_8BPP | DST_8BPP |
803 BYTE_ORDER_LSB_TO_MSB;
804 dp_chain_mask = DP_CHAIN_8BPP;
805 } else if (bpp <= 15) {
806 bpp = 16;
807 pix_width = CRTC_PIX_WIDTH_15BPP;
808 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
809 BYTE_ORDER_LSB_TO_MSB;
810 dp_chain_mask = DP_CHAIN_15BPP;
811 } else if (bpp <= 16) {
812 bpp = 16;
813 pix_width = CRTC_PIX_WIDTH_16BPP;
814 dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP |
815 BYTE_ORDER_LSB_TO_MSB;
816 dp_chain_mask = DP_CHAIN_16BPP;
817 } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
818 bpp = 24;
819 pix_width = CRTC_PIX_WIDTH_24BPP;
820 dp_pix_width =
821 HOST_8BPP | SRC_8BPP | DST_8BPP |
822 BYTE_ORDER_LSB_TO_MSB;
823 dp_chain_mask = DP_CHAIN_24BPP;
824 } else if (bpp <= 32) {
825 bpp = 32;
826 pix_width = CRTC_PIX_WIDTH_32BPP;
827 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
828 BYTE_ORDER_LSB_TO_MSB;
829 dp_chain_mask = DP_CHAIN_32BPP;
830 } else
831 FAIL("invalid bpp");
832
833 if (vxres * vyres * bpp / 8 > info->fix.smem_len)
834 FAIL("not enough video RAM");
835
836 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
837 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
838
839 if((xres > 1600) || (yres > 1200)) {
840 FAIL("MACH64 chips are designed for max 1600x1200\n"
841 "select anoter resolution.");
842 }
843 h_sync_strt = h_disp + var->right_margin;
844 h_sync_end = h_sync_strt + var->hsync_len;
845 h_sync_dly = var->right_margin & 7;
846 h_total = h_sync_end + h_sync_dly + var->left_margin;
847
848 v_sync_strt = v_disp + var->lower_margin;
849 v_sync_end = v_sync_strt + var->vsync_len;
850 v_total = v_sync_end + var->upper_margin;
851
852 #ifdef CONFIG_FB_ATY_GENERIC_LCD
853 if (par->lcd_table != 0) {
854 if(!M64_HAS(LT_LCD_REGS)) {
855 u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
856 crtc->lcd_index = lcd_index &
857 ~(LCD_INDEX_MASK | LCD_DISPLAY_DIS | LCD_SRC_SEL | CRTC2_DISPLAY_DIS);
858 aty_st_le32(LCD_INDEX, lcd_index, par);
859 }
860
861 if (!M64_HAS(MOBIL_BUS))
862 crtc->lcd_index |= CRTC2_DISPLAY_DIS;
863
864 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par) | 0x4000;
865 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
866
867 crtc->lcd_gen_cntl &=
868 ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN |
869 /*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
870 USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
871 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT;
872
873 if((crtc->lcd_gen_cntl & LCD_ON) &&
874 ((xres > par->lcd_width) || (yres > par->lcd_height))) {
875 /* We cannot display the mode on the LCD. If the CRT is enabled
876 we can turn off the LCD.
877 If the CRT is off, it isn't a good idea to switch it on; we don't
878 know if one is connected. So it's better to fail then.
879 */
880 if (crtc->lcd_gen_cntl & CRT_ON) {
881 if (!(var->activate & FB_ACTIVATE_TEST))
882 PRINTKI("Disable LCD panel, because video mode does not fit.\n");
883 crtc->lcd_gen_cntl &= ~LCD_ON;
884 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
885 } else {
886 if (!(var->activate & FB_ACTIVATE_TEST))
887 PRINTKE("Video mode exceeds size of LCD panel.\nConnect this computer to a conventional monitor if you really need this mode.\n");
888 return -EINVAL;
889 }
890 }
891 }
892
893 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
894 int VScan = 1;
895 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
896 const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
897 const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 }; */
898
899 vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED);
900
901 /* This is horror! When we simulate, say 640x480 on an 800x600
902 LCD monitor, the CRTC should be programmed 800x600 values for
903 the non visible part, but 640x480 for the visible part.
904 This code has been tested on a laptop with it's 1400x1050 LCD
905 monitor and a conventional monitor both switched on.
906 Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
907 works with little glitches also with DOUBLESCAN modes
908 */
909 if (yres < par->lcd_height) {
910 VScan = par->lcd_height / yres;
911 if(VScan > 1) {
912 VScan = 2;
913 vmode |= FB_VMODE_DOUBLE;
914 }
915 }
916
917 h_sync_strt = h_disp + par->lcd_right_margin;
918 h_sync_end = h_sync_strt + par->lcd_hsync_len;
919 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
920 h_total = h_disp + par->lcd_hblank_len;
921
922 v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
923 v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
924 v_total = v_disp + par->lcd_vblank_len / VScan;
925 }
926 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
927
928 h_disp = (h_disp >> 3) - 1;
929 h_sync_strt = (h_sync_strt >> 3) - 1;
930 h_sync_end = (h_sync_end >> 3) - 1;
931 h_total = (h_total >> 3) - 1;
932 h_sync_wid = h_sync_end - h_sync_strt;
933
934 FAIL_MAX("h_disp too large", h_disp, 0xff);
935 FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff);
936 /*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
937 if(h_sync_wid > 0x1f)
938 h_sync_wid = 0x1f;
939 FAIL_MAX("h_total too large", h_total, 0x1ff);
940
941 if (vmode & FB_VMODE_DOUBLE) {
942 v_disp <<= 1;
943 v_sync_strt <<= 1;
944 v_sync_end <<= 1;
945 v_total <<= 1;
946 }
947
948 vdisplay = yres;
949 #ifdef CONFIG_FB_ATY_GENERIC_LCD
950 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON))
951 vdisplay = par->lcd_height;
952 #endif
953
954 v_disp--;
955 v_sync_strt--;
956 v_sync_end--;
957 v_total--;
958 v_sync_wid = v_sync_end - v_sync_strt;
959
960 FAIL_MAX("v_disp too large", v_disp, 0x7ff);
961 FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff);
962 /*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
963 if(v_sync_wid > 0x1f)
964 v_sync_wid = 0x1f;
965 FAIL_MAX("v_total too large", v_total, 0x7ff);
966
967 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
968
969 /* output */
970 crtc->vxres = vxres;
971 crtc->vyres = vyres;
972 crtc->xoffset = xoffset;
973 crtc->yoffset = yoffset;
974 crtc->bpp = bpp;
975 crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
976 crtc->vline_crnt_vline = 0;
977
978 crtc->h_tot_disp = h_total | (h_disp<<16);
979 crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
980 ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) | (h_sync_pol<<21);
981 crtc->v_tot_disp = v_total | (v_disp<<16);
982 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
983
984 /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
985 crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync;
986 crtc->gen_cntl |= CRTC_VGA_LINEAR;
987
988 /* Enable doublescan mode if requested */
989 if (vmode & FB_VMODE_DOUBLE)
990 crtc->gen_cntl |= CRTC_DBL_SCAN_EN;
991 /* Enable interlaced mode if requested */
992 if (vmode & FB_VMODE_INTERLACED)
993 crtc->gen_cntl |= CRTC_INTERLACE_EN;
994 #ifdef CONFIG_FB_ATY_GENERIC_LCD
995 if (par->lcd_table != 0) {
996 vdisplay = yres;
997 if(vmode & FB_VMODE_DOUBLE)
998 vdisplay <<= 1;
999 crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH);
1000 crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 |
1001 /*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
1002 USE_SHADOWED_VEND | USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
1003 crtc->lcd_gen_cntl |= (DONT_SHADOW_VPAR/* | LOCK_8DOT*/);
1004
1005 /* MOBILITY M1 tested, FIXME: LT */
1006 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
1007 if (!M64_HAS(LT_LCD_REGS))
1008 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
1009 ~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3);
1010
1011 crtc->horz_stretching &=
1012 ~(HORZ_STRETCH_RATIO | HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO |
1013 HORZ_STRETCH_MODE | HORZ_STRETCH_EN);
1014 if (xres < par->lcd_width && crtc->lcd_gen_cntl & LCD_ON) {
1015 do {
1016 /*
1017 * The horizontal blender misbehaves when HDisplay is less than a
1018 * a certain threshold (440 for a 1024-wide panel). It doesn't
1019 * stretch such modes enough. Use pixel replication instead of
1020 * blending to stretch modes that can be made to exactly fit the
1021 * panel width. The undocumented "NoLCDBlend" option allows the
1022 * pixel-replicated mode to be slightly wider or narrower than the
1023 * panel width. It also causes a mode that is exactly half as wide
1024 * as the panel to be pixel-replicated, rather than blended.
1025 */
1026 int HDisplay = xres & ~7;
1027 int nStretch = par->lcd_width / HDisplay;
1028 int Remainder = par->lcd_width % HDisplay;
1029
1030 if ((!Remainder && ((nStretch > 2))) ||
1031 (((HDisplay * 16) / par->lcd_width) < 7)) {
1032 static const char StretchLoops[] = {10, 12, 13, 15, 16};
1033 int horz_stretch_loop = -1, BestRemainder;
1034 int Numerator = HDisplay, Denominator = par->lcd_width;
1035 int Index = 5;
1036 ATIReduceRatio(&Numerator, &Denominator);
1037
1038 BestRemainder = (Numerator * 16) / Denominator;
1039 while (--Index >= 0) {
1040 Remainder = ((Denominator - Numerator) * StretchLoops[Index]) %
1041 Denominator;
1042 if (Remainder < BestRemainder) {
1043 horz_stretch_loop = Index;
1044 if (!(BestRemainder = Remainder))
1045 break;
1046 }
1047 }
1048
1049 if ((horz_stretch_loop >= 0) && !BestRemainder) {
1050 int horz_stretch_ratio = 0, Accumulator = 0;
1051 int reuse_previous = 1;
1052
1053 Index = StretchLoops[horz_stretch_loop];
1054
1055 while (--Index >= 0) {
1056 if (Accumulator > 0)
1057 horz_stretch_ratio |= reuse_previous;
1058 else
1059 Accumulator += Denominator;
1060 Accumulator -= Numerator;
1061 reuse_previous <<= 1;
1062 }
1063
1064 crtc->horz_stretching |= (HORZ_STRETCH_EN |
1065 ((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) |
1066 (horz_stretch_ratio & HORZ_STRETCH_RATIO));
1067 break; /* Out of the do { ... } while (0) */
1068 }
1069 }
1070
1071 crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN |
1072 (((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
1073 } while (0);
1074 }
1075
1076 if (vdisplay < par->lcd_height && crtc->lcd_gen_cntl & LCD_ON) {
1077 crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN |
1078 (((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
1079
1080 if (!M64_HAS(LT_LCD_REGS) &&
1081 xres <= (M64_HAS(MOBIL_BUS)?1024:800))
1082 crtc->ext_vert_stretch |= VERT_STRETCH_MODE;
1083 } else {
1084 /*
1085 * Don't use vertical blending if the mode is too wide or not
1086 * vertically stretched.
1087 */
1088 crtc->vert_stretching = 0;
1089 }
1090 /* copy to shadow crtc */
1091 crtc->shadow_h_tot_disp = crtc->h_tot_disp;
1092 crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid;
1093 crtc->shadow_v_tot_disp = crtc->v_tot_disp;
1094 crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid;
1095 }
1096 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1097
1098 if (M64_HAS(MAGIC_FIFO)) {
1099 /* FIXME: display FIFO low watermark values */
1100 crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_FIFO_LWM);
1101 }
1102 crtc->dp_pix_width = dp_pix_width;
1103 crtc->dp_chain_mask = dp_chain_mask;
1104
1105 return 0;
1106 }
1107
1108 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var)
1109 {
1110 u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
1111 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid,
1112 h_sync_pol;
1113 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1114 u32 pix_width;
1115 u32 double_scan, interlace;
1116
1117 /* input */
1118 h_total = crtc->h_tot_disp & 0x1ff;
1119 h_disp = (crtc->h_tot_disp >> 16) & 0xff;
1120 h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100);
1121 h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
1122 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
1123 h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
1124 v_total = crtc->v_tot_disp & 0x7ff;
1125 v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
1126 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1127 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1128 v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
1129 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1130 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1131 double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN;
1132 interlace = crtc->gen_cntl & CRTC_INTERLACE_EN;
1133
1134 /* convert */
1135 xres = (h_disp + 1) * 8;
1136 yres = v_disp + 1;
1137 left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
1138 right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
1139 hslen = h_sync_wid * 8;
1140 upper = v_total - v_sync_strt - v_sync_wid;
1141 lower = v_sync_strt - v_disp;
1142 vslen = v_sync_wid;
1143 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1144 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1145 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1146
1147 switch (pix_width) {
1148 #if 0
1149 case CRTC_PIX_WIDTH_4BPP:
1150 bpp = 4;
1151 var->red.offset = 0;
1152 var->red.length = 8;
1153 var->green.offset = 0;
1154 var->green.length = 8;
1155 var->blue.offset = 0;
1156 var->blue.length = 8;
1157 var->transp.offset = 0;
1158 var->transp.length = 0;
1159 break;
1160 #endif
1161 case CRTC_PIX_WIDTH_8BPP:
1162 bpp = 8;
1163 var->red.offset = 0;
1164 var->red.length = 8;
1165 var->green.offset = 0;
1166 var->green.length = 8;
1167 var->blue.offset = 0;
1168 var->blue.length = 8;
1169 var->transp.offset = 0;
1170 var->transp.length = 0;
1171 break;
1172 case CRTC_PIX_WIDTH_15BPP: /* RGB 555 */
1173 bpp = 16;
1174 var->red.offset = 10;
1175 var->red.length = 5;
1176 var->green.offset = 5;
1177 var->green.length = 5;
1178 var->blue.offset = 0;
1179 var->blue.length = 5;
1180 var->transp.offset = 0;
1181 var->transp.length = 0;
1182 break;
1183 case CRTC_PIX_WIDTH_16BPP: /* RGB 565 */
1184 bpp = 16;
1185 var->red.offset = 11;
1186 var->red.length = 5;
1187 var->green.offset = 5;
1188 var->green.length = 6;
1189 var->blue.offset = 0;
1190 var->blue.length = 5;
1191 var->transp.offset = 0;
1192 var->transp.length = 0;
1193 break;
1194 case CRTC_PIX_WIDTH_24BPP: /* RGB 888 */
1195 bpp = 24;
1196 var->red.offset = 16;
1197 var->red.length = 8;
1198 var->green.offset = 8;
1199 var->green.length = 8;
1200 var->blue.offset = 0;
1201 var->blue.length = 8;
1202 var->transp.offset = 0;
1203 var->transp.length = 0;
1204 break;
1205 case CRTC_PIX_WIDTH_32BPP: /* ARGB 8888 */
1206 bpp = 32;
1207 var->red.offset = 16;
1208 var->red.length = 8;
1209 var->green.offset = 8;
1210 var->green.length = 8;
1211 var->blue.offset = 0;
1212 var->blue.length = 8;
1213 var->transp.offset = 24;
1214 var->transp.length = 8;
1215 break;
1216 default:
1217 PRINTKE("Invalid pixel width\n");
1218 return -EINVAL;
1219 }
1220
1221 /* output */
1222 var->xres = xres;
1223 var->yres = yres;
1224 var->xres_virtual = crtc->vxres;
1225 var->yres_virtual = crtc->vyres;
1226 var->bits_per_pixel = bpp;
1227 var->left_margin = left;
1228 var->right_margin = right;
1229 var->upper_margin = upper;
1230 var->lower_margin = lower;
1231 var->hsync_len = hslen;
1232 var->vsync_len = vslen;
1233 var->sync = sync;
1234 var->vmode = FB_VMODE_NONINTERLACED;
1235 /* In double scan mode, the vertical parameters are doubled, so we need to
1236 half them to get the right values.
1237 In interlaced mode the values are already correct, so no correction is
1238 necessary.
1239 */
1240 if (interlace)
1241 var->vmode = FB_VMODE_INTERLACED;
1242
1243 if (double_scan) {
1244 var->vmode = FB_VMODE_DOUBLE;
1245 var->yres>>=1;
1246 var->upper_margin>>=1;
1247 var->lower_margin>>=1;
1248 var->vsync_len>>=1;
1249 }
1250
1251 return 0;
1252 }
1253
1254 /* ------------------------------------------------------------------------- */
1255
1256 static int atyfb_set_par(struct fb_info *info)
1257 {
1258 struct atyfb_par *par = (struct atyfb_par *) info->par;
1259 struct fb_var_screeninfo *var = &info->var;
1260 u32 tmp, pixclock;
1261 int err;
1262 #ifdef DEBUG
1263 struct fb_var_screeninfo debug;
1264 u32 pixclock_in_ps;
1265 #endif
1266 if (par->asleep)
1267 return 0;
1268
1269 if ((err = aty_var_to_crtc(info, var, &par->crtc)))
1270 return err;
1271
1272 pixclock = atyfb_get_pixclock(var, par);
1273
1274 if (pixclock == 0) {
1275 PRINTKE("Invalid pixclock\n");
1276 return -EINVAL;
1277 } else {
1278 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &par->pll)))
1279 return err;
1280 }
1281
1282 par->accel_flags = var->accel_flags; /* hack */
1283
1284 if (var->accel_flags) {
1285 info->fbops->fb_sync = atyfb_sync;
1286 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1287 } else {
1288 info->fbops->fb_sync = NULL;
1289 info->flags |= FBINFO_HWACCEL_DISABLED;
1290 }
1291
1292 if (par->blitter_may_be_busy)
1293 wait_for_idle(par);
1294
1295 aty_set_crtc(par, &par->crtc);
1296 par->dac_ops->set_dac(info, &par->pll, var->bits_per_pixel, par->accel_flags);
1297 par->pll_ops->set_pll(info, &par->pll);
1298
1299 #ifdef DEBUG
1300 if(par->pll_ops && par->pll_ops->pll_to_var)
1301 pixclock_in_ps = par->pll_ops->pll_to_var(info, &(par->pll));
1302 else
1303 pixclock_in_ps = 0;
1304
1305 if(0 == pixclock_in_ps) {
1306 PRINTKE("ALERT ops->pll_to_var get 0\n");
1307 pixclock_in_ps = pixclock;
1308 }
1309
1310 memset(&debug, 0, sizeof(debug));
1311 if(!aty_crtc_to_var(&(par->crtc), &debug)) {
1312 u32 hSync, vRefresh;
1313 u32 h_disp, h_sync_strt, h_sync_end, h_total;
1314 u32 v_disp, v_sync_strt, v_sync_end, v_total;
1315
1316 h_disp = debug.xres;
1317 h_sync_strt = h_disp + debug.right_margin;
1318 h_sync_end = h_sync_strt + debug.hsync_len;
1319 h_total = h_sync_end + debug.left_margin;
1320 v_disp = debug.yres;
1321 v_sync_strt = v_disp + debug.lower_margin;
1322 v_sync_end = v_sync_strt + debug.vsync_len;
1323 v_total = v_sync_end + debug.upper_margin;
1324
1325 hSync = 1000000000 / (pixclock_in_ps * h_total);
1326 vRefresh = (hSync * 1000) / v_total;
1327 if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
1328 vRefresh *= 2;
1329 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1330 vRefresh /= 2;
1331
1332 DPRINTK("atyfb_set_par\n");
1333 DPRINTK(" Set Visible Mode to %ix%i-%i\n", var->xres, var->yres, var->bits_per_pixel);
1334 DPRINTK(" Virtual resolution %ix%i, pixclock_in_ps %i (calculated %i)\n",
1335 var->xres_virtual, var->yres_virtual, pixclock, pixclock_in_ps);
1336 DPRINTK(" Dot clock: %i MHz\n", 1000000 / pixclock_in_ps);
1337 DPRINTK(" Horizontal sync: %i kHz\n", hSync);
1338 DPRINTK(" Vertical refresh: %i Hz\n", vRefresh);
1339 DPRINTK(" x style: %i.%03i %i %i %i %i %i %i %i %i\n",
1340 1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps,
1341 h_disp, h_sync_strt, h_sync_end, h_total,
1342 v_disp, v_sync_strt, v_sync_end, v_total);
1343 DPRINTK(" fb style: %i %i %i %i %i %i %i %i %i\n",
1344 pixclock_in_ps,
1345 debug.left_margin, h_disp, debug.right_margin, debug.hsync_len,
1346 debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len);
1347 }
1348 #endif /* DEBUG */
1349
1350 if (!M64_HAS(INTEGRATED)) {
1351 /* Don't forget MEM_CNTL */
1352 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
1353 switch (var->bits_per_pixel) {
1354 case 8:
1355 tmp |= 0x02000000;
1356 break;
1357 case 16:
1358 tmp |= 0x03000000;
1359 break;
1360 case 32:
1361 tmp |= 0x06000000;
1362 break;
1363 }
1364 aty_st_le32(MEM_CNTL, tmp, par);
1365 } else {
1366 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
1367 if (!M64_HAS(MAGIC_POSTDIV))
1368 tmp |= par->mem_refresh_rate << 20;
1369 switch (var->bits_per_pixel) {
1370 case 8:
1371 case 24:
1372 tmp |= 0x00000000;
1373 break;
1374 case 16:
1375 tmp |= 0x04000000;
1376 break;
1377 case 32:
1378 tmp |= 0x08000000;
1379 break;
1380 }
1381 if (M64_HAS(CT_BUS)) {
1382 aty_st_le32(DAC_CNTL, 0x87010184, par);
1383 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1384 } else if (M64_HAS(VT_BUS)) {
1385 aty_st_le32(DAC_CNTL, 0x87010184, par);
1386 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1387 } else if (M64_HAS(MOBIL_BUS)) {
1388 aty_st_le32(DAC_CNTL, 0x80010102, par);
1389 aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1390 } else {
1391 /* GT */
1392 aty_st_le32(DAC_CNTL, 0x86010102, par);
1393 aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1394 aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
1395 }
1396 aty_st_le32(MEM_CNTL, tmp, par);
1397 }
1398 aty_st_8(DAC_MASK, 0xff, par);
1399
1400 info->fix.line_length = var->xres_virtual * var->bits_per_pixel/8;
1401 info->fix.visual = var->bits_per_pixel <= 8 ?
1402 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1403
1404 /* Initialize the graphics engine */
1405 if (par->accel_flags & FB_ACCELF_TEXT)
1406 aty_init_engine(par, info);
1407
1408 #ifdef CONFIG_BOOTX_TEXT
1409 btext_update_display(info->fix.smem_start,
1410 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
1411 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
1412 var->bits_per_pixel,
1413 par->crtc.vxres * var->bits_per_pixel / 8);
1414 #endif /* CONFIG_BOOTX_TEXT */
1415 #if 0
1416 /* switch to accelerator mode */
1417 if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN))
1418 aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par);
1419 #endif
1420 #ifdef DEBUG
1421 {
1422 /* dump non shadow CRTC, pll, LCD registers */
1423 int i; u32 base;
1424
1425 /* CRTC registers */
1426 base = 0x2000;
1427 printk("debug atyfb: Mach64 non-shadow register values:");
1428 for (i = 0; i < 256; i = i+4) {
1429 if(i%16 == 0) printk("\ndebug atyfb: 0x%04X: ", base + i);
1430 printk(" %08X", aty_ld_le32(i, par));
1431 }
1432 printk("\n\n");
1433
1434 #ifdef CONFIG_FB_ATY_CT
1435 /* PLL registers */
1436 base = 0x00;
1437 printk("debug atyfb: Mach64 PLL register values:");
1438 for (i = 0; i < 64; i++) {
1439 if(i%16 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1440 if(i%4 == 0) printk(" ");
1441 printk("%02X", aty_ld_pll_ct(i, par));
1442 }
1443 printk("\n\n");
1444 #endif /* CONFIG_FB_ATY_CT */
1445
1446 #ifdef CONFIG_FB_ATY_GENERIC_LCD
1447 if (par->lcd_table != 0) {
1448 /* LCD registers */
1449 base = 0x00;
1450 printk("debug atyfb: LCD register values:");
1451 if(M64_HAS(LT_LCD_REGS)) {
1452 for(i = 0; i <= POWER_MANAGEMENT; i++) {
1453 if(i == EXT_VERT_STRETCH)
1454 continue;
1455 printk("\ndebug atyfb: 0x%04X: ", lt_lcd_regs[i]);
1456 printk(" %08X", aty_ld_lcd(i, par));
1457 }
1458
1459 } else {
1460 for (i = 0; i < 64; i++) {
1461 if(i%4 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1462 printk(" %08X", aty_ld_lcd(i, par));
1463 }
1464 }
1465 printk("\n\n");
1466 }
1467 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1468 }
1469 #endif /* DEBUG */
1470 return 0;
1471 }
1472
1473 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1474 {
1475 struct atyfb_par *par = (struct atyfb_par *) info->par;
1476 int err;
1477 struct crtc crtc;
1478 union aty_pll pll;
1479 u32 pixclock;
1480
1481 memcpy(&pll, &(par->pll), sizeof(pll));
1482
1483 if((err = aty_var_to_crtc(info, var, &crtc)))
1484 return err;
1485
1486 pixclock = atyfb_get_pixclock(var, par);
1487
1488 if (pixclock == 0) {
1489 if (!(var->activate & FB_ACTIVATE_TEST))
1490 PRINTKE("Invalid pixclock\n");
1491 return -EINVAL;
1492 } else {
1493 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &pll)))
1494 return err;
1495 }
1496
1497 if (var->accel_flags & FB_ACCELF_TEXT)
1498 info->var.accel_flags = FB_ACCELF_TEXT;
1499 else
1500 info->var.accel_flags = 0;
1501
1502 #if 0 /* fbmon is not done. uncomment for 2.5.x -brad */
1503 if (!fbmon_valid_timings(pixclock, htotal, vtotal, info))
1504 return -EINVAL;
1505 #endif
1506 aty_crtc_to_var(&crtc, var);
1507 var->pixclock = par->pll_ops->pll_to_var(info, &pll);
1508 return 0;
1509 }
1510
1511 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
1512 {
1513 u32 xoffset = info->var.xoffset;
1514 u32 yoffset = info->var.yoffset;
1515 u32 vxres = par->crtc.vxres;
1516 u32 bpp = info->var.bits_per_pixel;
1517
1518 par->crtc.off_pitch = ((yoffset * vxres + xoffset) * bpp / 64) | (vxres << 19);
1519 }
1520
1521
1522 /*
1523 * Open/Release the frame buffer device
1524 */
1525
1526 static int atyfb_open(struct fb_info *info, int user)
1527 {
1528 struct atyfb_par *par = (struct atyfb_par *) info->par;
1529
1530 if (user) {
1531 par->open++;
1532 #ifdef __sparc__
1533 par->mmaped = 0;
1534 #endif
1535 }
1536 return (0);
1537 }
1538
1539 static irqreturn_t aty_irq(int irq, void *dev_id, struct pt_regs *fp)
1540 {
1541 struct atyfb_par *par = dev_id;
1542 int handled = 0;
1543 u32 int_cntl;
1544
1545 spin_lock(&par->int_lock);
1546
1547 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
1548
1549 if (int_cntl & CRTC_VBLANK_INT) {
1550 /* clear interrupt */
1551 aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) | CRTC_VBLANK_INT_AK, par);
1552 par->vblank.count++;
1553 if (par->vblank.pan_display) {
1554 par->vblank.pan_display = 0;
1555 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1556 }
1557 wake_up_interruptible(&par->vblank.wait);
1558 handled = 1;
1559 }
1560
1561 spin_unlock(&par->int_lock);
1562
1563 return IRQ_RETVAL(handled);
1564 }
1565
1566 static int aty_enable_irq(struct atyfb_par *par, int reenable)
1567 {
1568 u32 int_cntl;
1569
1570 if (!test_and_set_bit(0, &par->irq_flags)) {
1571 if (request_irq(par->irq, aty_irq, SA_SHIRQ, "atyfb", par)) {
1572 clear_bit(0, &par->irq_flags);
1573 return -EINVAL;
1574 }
1575 spin_lock_irq(&par->int_lock);
1576 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1577 /* clear interrupt */
1578 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par);
1579 /* enable interrupt */
1580 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par);
1581 spin_unlock_irq(&par->int_lock);
1582 } else if (reenable) {
1583 spin_lock_irq(&par->int_lock);
1584 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1585 if (!(int_cntl & CRTC_VBLANK_INT_EN)) {
1586 printk("atyfb: someone disabled IRQ [%08x]\n", int_cntl);
1587 /* re-enable interrupt */
1588 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par );
1589 }
1590 spin_unlock_irq(&par->int_lock);
1591 }
1592
1593 return 0;
1594 }
1595
1596 static int aty_disable_irq(struct atyfb_par *par)
1597 {
1598 u32 int_cntl;
1599
1600 if (test_and_clear_bit(0, &par->irq_flags)) {
1601 if (par->vblank.pan_display) {
1602 par->vblank.pan_display = 0;
1603 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1604 }
1605 spin_lock_irq(&par->int_lock);
1606 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1607 /* disable interrupt */
1608 aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par );
1609 spin_unlock_irq(&par->int_lock);
1610 free_irq(par->irq, par);
1611 }
1612
1613 return 0;
1614 }
1615
1616 static int atyfb_release(struct fb_info *info, int user)
1617 {
1618 struct atyfb_par *par = (struct atyfb_par *) info->par;
1619 if (user) {
1620 par->open--;
1621 mdelay(1);
1622 wait_for_idle(par);
1623 if (!par->open) {
1624 #ifdef __sparc__
1625 int was_mmaped = par->mmaped;
1626
1627 par->mmaped = 0;
1628
1629 if (was_mmaped) {
1630 struct fb_var_screeninfo var;
1631
1632 /* Now reset the default display config, we have no
1633 * idea what the program(s) which mmap'd the chip did
1634 * to the configuration, nor whether it restored it
1635 * correctly.
1636 */
1637 var = default_var;
1638 if (noaccel)
1639 var.accel_flags &= ~FB_ACCELF_TEXT;
1640 else
1641 var.accel_flags |= FB_ACCELF_TEXT;
1642 if (var.yres == var.yres_virtual) {
1643 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
1644 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
1645 if (var.yres_virtual < var.yres)
1646 var.yres_virtual = var.yres;
1647 }
1648 }
1649 #endif
1650 aty_disable_irq(par);
1651 }
1652 }
1653 return (0);
1654 }
1655
1656 /*
1657 * Pan or Wrap the Display
1658 *
1659 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1660 */
1661
1662 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1663 {
1664 struct atyfb_par *par = (struct atyfb_par *) info->par;
1665 u32 xres, yres, xoffset, yoffset;
1666
1667 xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
1668 yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
1669 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1670 yres >>= 1;
1671 xoffset = (var->xoffset + 7) & ~7;
1672 yoffset = var->yoffset;
1673 if (xoffset + xres > par->crtc.vxres || yoffset + yres > par->crtc.vyres)
1674 return -EINVAL;
1675 info->var.xoffset = xoffset;
1676 info->var.yoffset = yoffset;
1677 if (par->asleep)
1678 return 0;
1679
1680 set_off_pitch(par, info);
1681 if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) {
1682 par->vblank.pan_display = 1;
1683 } else {
1684 par->vblank.pan_display = 0;
1685 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1686 }
1687
1688 return 0;
1689 }
1690
1691 static int aty_waitforvblank(struct atyfb_par *par, u32 crtc)
1692 {
1693 struct aty_interrupt *vbl;
1694 unsigned int count;
1695 int ret;
1696
1697 switch (crtc) {
1698 case 0:
1699 vbl = &par->vblank;
1700 break;
1701 default:
1702 return -ENODEV;
1703 }
1704
1705 ret = aty_enable_irq(par, 0);
1706 if (ret)
1707 return ret;
1708
1709 count = vbl->count;
1710 ret = wait_event_interruptible_timeout(vbl->wait, count != vbl->count, HZ/10);
1711 if (ret < 0) {
1712 return ret;
1713 }
1714 if (ret == 0) {
1715 aty_enable_irq(par, 1);
1716 return -ETIMEDOUT;
1717 }
1718
1719 return 0;
1720 }
1721
1722
1723 #ifdef DEBUG
1724 #define ATYIO_CLKR 0x41545900 /* ATY\00 */
1725 #define ATYIO_CLKW 0x41545901 /* ATY\01 */
1726
1727 struct atyclk {
1728 u32 ref_clk_per;
1729 u8 pll_ref_div;
1730 u8 mclk_fb_div;
1731 u8 mclk_post_div; /* 1,2,3,4,8 */
1732 u8 mclk_fb_mult; /* 2 or 4 */
1733 u8 xclk_post_div; /* 1,2,3,4,8 */
1734 u8 vclk_fb_div;
1735 u8 vclk_post_div; /* 1,2,3,4,6,8,12 */
1736 u32 dsp_xclks_per_row; /* 0-16383 */
1737 u32 dsp_loop_latency; /* 0-15 */
1738 u32 dsp_precision; /* 0-7 */
1739 u32 dsp_on; /* 0-2047 */
1740 u32 dsp_off; /* 0-2047 */
1741 };
1742
1743 #define ATYIO_FEATR 0x41545902 /* ATY\02 */
1744 #define ATYIO_FEATW 0x41545903 /* ATY\03 */
1745 #endif
1746
1747 #ifndef FBIO_WAITFORVSYNC
1748 #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
1749 #endif
1750
1751 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
1752 {
1753 struct atyfb_par *par = (struct atyfb_par *) info->par;
1754 #ifdef __sparc__
1755 struct fbtype fbtyp;
1756 #endif
1757
1758 switch (cmd) {
1759 #ifdef __sparc__
1760 case FBIOGTYPE:
1761 fbtyp.fb_type = FBTYPE_PCI_GENERIC;
1762 fbtyp.fb_width = par->crtc.vxres;
1763 fbtyp.fb_height = par->crtc.vyres;
1764 fbtyp.fb_depth = info->var.bits_per_pixel;
1765 fbtyp.fb_cmsize = info->cmap.len;
1766 fbtyp.fb_size = info->fix.smem_len;
1767 if (copy_to_user((struct fbtype __user *) arg, &fbtyp, sizeof(fbtyp)))
1768 return -EFAULT;
1769 break;
1770 #endif /* __sparc__ */
1771
1772 case FBIO_WAITFORVSYNC:
1773 {
1774 u32 crtc;
1775
1776 if (get_user(crtc, (__u32 __user *) arg))
1777 return -EFAULT;
1778
1779 return aty_waitforvblank(par, crtc);
1780 }
1781 break;
1782
1783 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
1784 case ATYIO_CLKR:
1785 if (M64_HAS(INTEGRATED)) {
1786 struct atyclk clk;
1787 union aty_pll *pll = &(par->pll);
1788 u32 dsp_config = pll->ct.dsp_config;
1789 u32 dsp_on_off = pll->ct.dsp_on_off;
1790 clk.ref_clk_per = par->ref_clk_per;
1791 clk.pll_ref_div = pll->ct.pll_ref_div;
1792 clk.mclk_fb_div = pll->ct.mclk_fb_div;
1793 clk.mclk_post_div = pll->ct.mclk_post_div_real;
1794 clk.mclk_fb_mult = pll->ct.mclk_fb_mult;
1795 clk.xclk_post_div = pll->ct.xclk_post_div_real;
1796 clk.vclk_fb_div = pll->ct.vclk_fb_div;
1797 clk.vclk_post_div = pll->ct.vclk_post_div_real;
1798 clk.dsp_xclks_per_row = dsp_config & 0x3fff;
1799 clk.dsp_loop_latency = (dsp_config >> 16) & 0xf;
1800 clk.dsp_precision = (dsp_config >> 20) & 7;
1801 clk.dsp_off = dsp_on_off & 0x7ff;
1802 clk.dsp_on = (dsp_on_off >> 16) & 0x7ff;
1803 if (copy_to_user((struct atyclk __user *) arg, &clk,
1804 sizeof(clk)))
1805 return -EFAULT;
1806 } else
1807 return -EINVAL;
1808 break;
1809 case ATYIO_CLKW:
1810 if (M64_HAS(INTEGRATED)) {
1811 struct atyclk clk;
1812 union aty_pll *pll = &(par->pll);
1813 if (copy_from_user(&clk, (struct atyclk __user *) arg, sizeof(clk)))
1814 return -EFAULT;
1815 par->ref_clk_per = clk.ref_clk_per;
1816 pll->ct.pll_ref_div = clk.pll_ref_div;
1817 pll->ct.mclk_fb_div = clk.mclk_fb_div;
1818 pll->ct.mclk_post_div_real = clk.mclk_post_div;
1819 pll->ct.mclk_fb_mult = clk.mclk_fb_mult;
1820 pll->ct.xclk_post_div_real = clk.xclk_post_div;
1821 pll->ct.vclk_fb_div = clk.vclk_fb_div;
1822 pll->ct.vclk_post_div_real = clk.vclk_post_div;
1823 pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) |
1824 ((clk.dsp_loop_latency & 0xf)<<16)| ((clk.dsp_precision & 7)<<20);
1825 pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) | ((clk.dsp_on & 0x7ff)<<16);
1826 /*aty_calc_pll_ct(info, &pll->ct);*/
1827 aty_set_pll_ct(info, pll);
1828 } else
1829 return -EINVAL;
1830 break;
1831 case ATYIO_FEATR:
1832 if (get_user(par->features, (u32 __user *) arg))
1833 return -EFAULT;
1834 break;
1835 case ATYIO_FEATW:
1836 if (put_user(par->features, (u32 __user *) arg))
1837 return -EFAULT;
1838 break;
1839 #endif /* DEBUG && CONFIG_FB_ATY_CT */
1840 default:
1841 return -EINVAL;
1842 }
1843 return 0;
1844 }
1845
1846 static int atyfb_sync(struct fb_info *info)
1847 {
1848 struct atyfb_par *par = (struct atyfb_par *) info->par;
1849
1850 if (par->blitter_may_be_busy)
1851 wait_for_idle(par);
1852 return 0;
1853 }
1854
1855 #ifdef __sparc__
1856 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
1857 {
1858 struct atyfb_par *par = (struct atyfb_par *) info->par;
1859 unsigned int size, page, map_size = 0;
1860 unsigned long map_offset = 0;
1861 unsigned long off;
1862 int i;
1863
1864 if (!par->mmap_map)
1865 return -ENXIO;
1866
1867 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1868 return -EINVAL;
1869
1870 off = vma->vm_pgoff << PAGE_SHIFT;
1871 size = vma->vm_end - vma->vm_start;
1872
1873 /* To stop the swapper from even considering these pages. */
1874 vma->vm_flags |= (VM_IO | VM_RESERVED);
1875
1876 if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) ||
1877 ((off == info->fix.smem_len) && (size == PAGE_SIZE)))
1878 off += 0x8000000000000000UL;
1879
1880 vma->vm_pgoff = off >> PAGE_SHIFT; /* propagate off changes */
1881
1882 /* Each page, see which map applies */
1883 for (page = 0; page < size;) {
1884 map_size = 0;
1885 for (i = 0; par->mmap_map[i].size; i++) {
1886 unsigned long start = par->mmap_map[i].voff;
1887 unsigned long end = start + par->mmap_map[i].size;
1888 unsigned long offset = off + page;
1889
1890 if (start > offset)
1891 continue;
1892 if (offset >= end)
1893 continue;
1894
1895 map_size = par->mmap_map[i].size - (offset - start);
1896 map_offset =
1897 par->mmap_map[i].poff + (offset - start);
1898 break;
1899 }
1900 if (!map_size) {
1901 page += PAGE_SIZE;
1902 continue;
1903 }
1904 if (page + map_size > size)
1905 map_size = size - page;
1906
1907 pgprot_val(vma->vm_page_prot) &=
1908 ~(par->mmap_map[i].prot_mask);
1909 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
1910
1911 if (remap_pfn_range(vma, vma->vm_start + page,
1912 map_offset >> PAGE_SHIFT, map_size, vma->vm_page_prot))
1913 return -EAGAIN;
1914
1915 page += map_size;
1916 }
1917
1918 if (!map_size)
1919 return -EINVAL;
1920
1921 if (!par->mmaped)
1922 par->mmaped = 1;
1923 return 0;
1924 }
1925
1926 static struct {
1927 u32 yoffset;
1928 u8 r[2][256];
1929 u8 g[2][256];
1930 u8 b[2][256];
1931 } atyfb_save;
1932
1933 static void atyfb_save_palette(struct atyfb_par *par, int enter)
1934 {
1935 int i, tmp;
1936
1937 for (i = 0; i < 256; i++) {
1938 tmp = aty_ld_8(DAC_CNTL, par) & 0xfc;
1939 if (M64_HAS(EXTRA_BRIGHT))
1940 tmp |= 0x2;
1941 aty_st_8(DAC_CNTL, tmp, par);
1942 aty_st_8(DAC_MASK, 0xff, par);
1943
1944 writeb(i, &par->aty_cmap_regs->rindex);
1945 atyfb_save.r[enter][i] = readb(&par->aty_cmap_regs->lut);
1946 atyfb_save.g[enter][i] = readb(&par->aty_cmap_regs->lut);
1947 atyfb_save.b[enter][i] = readb(&par->aty_cmap_regs->lut);
1948 writeb(i, &par->aty_cmap_regs->windex);
1949 writeb(atyfb_save.r[1 - enter][i],
1950 &par->aty_cmap_regs->lut);
1951 writeb(atyfb_save.g[1 - enter][i],
1952 &par->aty_cmap_regs->lut);
1953 writeb(atyfb_save.b[1 - enter][i],
1954 &par->aty_cmap_regs->lut);
1955 }
1956 }
1957
1958 static void atyfb_palette(int enter)
1959 {
1960 struct atyfb_par *par;
1961 struct fb_info *info;
1962 int i;
1963
1964 for (i = 0; i < FB_MAX; i++) {
1965 info = registered_fb[i];
1966 if (info && info->fbops == &atyfb_ops) {
1967 par = (struct atyfb_par *) info->par;
1968
1969 atyfb_save_palette(par, enter);
1970 if (enter) {
1971 atyfb_save.yoffset = info->var.yoffset;
1972 info->var.yoffset = 0;
1973 set_off_pitch(par, info);
1974 } else {
1975 info->var.yoffset = atyfb_save.yoffset;
1976 set_off_pitch(par, info);
1977 }
1978 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1979 break;
1980 }
1981 }
1982 }
1983 #endif /* __sparc__ */
1984
1985
1986
1987 #if defined(CONFIG_PM) && defined(CONFIG_PCI)
1988
1989 /* Power management routines. Those are used for PowerBook sleep.
1990 */
1991 static int aty_power_mgmt(int sleep, struct atyfb_par *par)
1992 {
1993 u32 pm;
1994 int timeout;
1995
1996 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1997 pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
1998 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1999 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2000
2001 timeout = 2000;
2002 if (sleep) {
2003 /* Sleep */
2004 pm &= ~PWR_MGT_ON;
2005 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2006 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2007 udelay(10);
2008 pm &= ~(PWR_BLON | AUTO_PWR_UP);
2009 pm |= SUSPEND_NOW;
2010 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2011 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2012 udelay(10);
2013 pm |= PWR_MGT_ON;
2014 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2015 do {
2016 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2017 mdelay(1);
2018 if ((--timeout) == 0)
2019 break;
2020 } while ((pm & PWR_MGT_STATUS_MASK) != PWR_MGT_STATUS_SUSPEND);
2021 } else {
2022 /* Wakeup */
2023 pm &= ~PWR_MGT_ON;
2024 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2025 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2026 udelay(10);
2027 pm &= ~SUSPEND_NOW;
2028 pm |= (PWR_BLON | AUTO_PWR_UP);
2029 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2030 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2031 udelay(10);
2032 pm |= PWR_MGT_ON;
2033 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2034 do {
2035 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2036 mdelay(1);
2037 if ((--timeout) == 0)
2038 break;
2039 } while ((pm & PWR_MGT_STATUS_MASK) != 0);
2040 }
2041 mdelay(500);
2042
2043 return timeout ? 0 : -EIO;
2044 }
2045
2046 static int atyfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2047 {
2048 struct fb_info *info = pci_get_drvdata(pdev);
2049 struct atyfb_par *par = (struct atyfb_par *) info->par;
2050
2051 #ifndef CONFIG_PPC_PMAC
2052 /* HACK ALERT ! Once I find a proper way to say to each driver
2053 * individually what will happen with it's PCI slot, I'll change
2054 * that. On laptops, the AGP slot is just unclocked, so D2 is
2055 * expected, while on desktops, the card is powered off
2056 */
2057 return 0;
2058 #endif /* CONFIG_PPC_PMAC */
2059
2060 if (state.event == pdev->dev.power.power_state.event)
2061 return 0;
2062
2063 acquire_console_sem();
2064
2065 fb_set_suspend(info, 1);
2066
2067 /* Idle & reset engine */
2068 wait_for_idle(par);
2069 aty_reset_engine(par);
2070
2071 /* Blank display and LCD */
2072 atyfb_blank(FB_BLANK_POWERDOWN, info);
2073
2074 par->asleep = 1;
2075 par->lock_blank = 1;
2076
2077 /* Set chip to "suspend" mode */
2078 if (aty_power_mgmt(1, par)) {
2079 par->asleep = 0;
2080 par->lock_blank = 0;
2081 atyfb_blank(FB_BLANK_UNBLANK, info);
2082 fb_set_suspend(info, 0);
2083 release_console_sem();
2084 return -EIO;
2085 }
2086
2087 release_console_sem();
2088
2089 pdev->dev.power.power_state = state;
2090
2091 return 0;
2092 }
2093
2094 static int atyfb_pci_resume(struct pci_dev *pdev)
2095 {
2096 struct fb_info *info = pci_get_drvdata(pdev);
2097 struct atyfb_par *par = (struct atyfb_par *) info->par;
2098
2099 if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2100 return 0;
2101
2102 acquire_console_sem();
2103
2104 if (pdev->dev.power.power_state.event == 2)
2105 aty_power_mgmt(0, par);
2106 par->asleep = 0;
2107
2108 /* Restore display */
2109 atyfb_set_par(info);
2110
2111 /* Refresh */
2112 fb_set_suspend(info, 0);
2113
2114 /* Unblank */
2115 par->lock_blank = 0;
2116 atyfb_blank(FB_BLANK_UNBLANK, info);
2117
2118 release_console_sem();
2119
2120 pdev->dev.power.power_state = PMSG_ON;
2121
2122 return 0;
2123 }
2124
2125 #endif /* defined(CONFIG_PM) && defined(CONFIG_PCI) */
2126
2127 /* Backlight */
2128 #ifdef CONFIG_FB_ATY_BACKLIGHT
2129 #define MAX_LEVEL 0xFF
2130
2131 static struct backlight_properties aty_bl_data;
2132
2133 static int aty_bl_get_level_brightness(struct atyfb_par *par, int level)
2134 {
2135 struct fb_info *info = pci_get_drvdata(par->pdev);
2136 int atylevel;
2137
2138 /* Get and convert the value */
2139 mutex_lock(&info->bl_mutex);
2140 atylevel = info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL;
2141 mutex_unlock(&info->bl_mutex);
2142
2143 if (atylevel < 0)
2144 atylevel = 0;
2145 else if (atylevel > MAX_LEVEL)
2146 atylevel = MAX_LEVEL;
2147
2148 return atylevel;
2149 }
2150
2151 static int aty_bl_update_status(struct backlight_device *bd)
2152 {
2153 struct atyfb_par *par = class_get_devdata(&bd->class_dev);
2154 unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
2155 int level;
2156
2157 if (bd->props->power != FB_BLANK_UNBLANK ||
2158 bd->props->fb_blank != FB_BLANK_UNBLANK)
2159 level = 0;
2160 else
2161 level = bd->props->brightness;
2162
2163 reg |= (BLMOD_EN | BIASMOD_EN);
2164 if (level > 0) {
2165 reg &= ~BIAS_MOD_LEVEL_MASK;
2166 reg |= (aty_bl_get_level_brightness(par, level) << BIAS_MOD_LEVEL_SHIFT);
2167 } else {
2168 reg &= ~BIAS_MOD_LEVEL_MASK;
2169 reg |= (aty_bl_get_level_brightness(par, 0) << BIAS_MOD_LEVEL_SHIFT);
2170 }
2171 aty_st_lcd(LCD_MISC_CNTL, reg, par);
2172
2173 return 0;
2174 }
2175
2176 static int aty_bl_get_brightness(struct backlight_device *bd)
2177 {
2178 return bd->props->brightness;
2179 }
2180
2181 static struct backlight_properties aty_bl_data = {
2182 .owner = THIS_MODULE,
2183 .get_brightness = aty_bl_get_brightness,
2184 .update_status = aty_bl_update_status,
2185 .max_brightness = (FB_BACKLIGHT_LEVELS - 1),
2186 };
2187
2188 static void aty_bl_init(struct atyfb_par *par)
2189 {
2190 struct fb_info *info = pci_get_drvdata(par->pdev);
2191 struct backlight_device *bd;
2192 char name[12];
2193
2194 #ifdef CONFIG_PMAC_BACKLIGHT
2195 if (!pmac_has_backlight_type("ati"))
2196 return;
2197 #endif
2198
2199 snprintf(name, sizeof(name), "atybl%d", info->node);
2200
2201 bd = backlight_device_register(name, par, &aty_bl_data);
2202 if (IS_ERR(bd)) {
2203 info->bl_dev = NULL;
2204 printk("aty: Backlight registration failed\n");
2205 goto error;
2206 }
2207
2208 mutex_lock(&info->bl_mutex);
2209 info->bl_dev = bd;
2210 fb_bl_default_curve(info, 0,
2211 0x3F * FB_BACKLIGHT_MAX / MAX_LEVEL,
2212 0xFF * FB_BACKLIGHT_MAX / MAX_LEVEL);
2213 mutex_unlock(&info->bl_mutex);
2214
2215 up(&bd->sem);
2216 bd->props->brightness = aty_bl_data.max_brightness;
2217 bd->props->power = FB_BLANK_UNBLANK;
2218 bd->props->update_status(bd);
2219 down(&bd->sem);
2220
2221 #ifdef CONFIG_PMAC_BACKLIGHT
2222 mutex_lock(&pmac_backlight_mutex);
2223 if (!pmac_backlight)
2224 pmac_backlight = bd;
2225 mutex_unlock(&pmac_backlight_mutex);
2226 #endif
2227
2228 printk("aty: Backlight initialized (%s)\n", name);
2229
2230 return;
2231
2232 error:
2233 return;
2234 }
2235
2236 static void aty_bl_exit(struct atyfb_par *par)
2237 {
2238 struct fb_info *info = pci_get_drvdata(par->pdev);
2239
2240 #ifdef CONFIG_PMAC_BACKLIGHT
2241 mutex_lock(&pmac_backlight_mutex);
2242 #endif
2243
2244 mutex_lock(&info->bl_mutex);
2245 if (info->bl_dev) {
2246 #ifdef CONFIG_PMAC_BACKLIGHT
2247 if (pmac_backlight == info->bl_dev)
2248 pmac_backlight = NULL;
2249 #endif
2250
2251 backlight_device_unregister(info->bl_dev);
2252
2253 printk("aty: Backlight unloaded\n");
2254 }
2255 mutex_unlock(&info->bl_mutex);
2256
2257 #ifdef CONFIG_PMAC_BACKLIGHT
2258 mutex_unlock(&pmac_backlight_mutex);
2259 #endif
2260 }
2261
2262 #endif /* CONFIG_FB_ATY_BACKLIGHT */
2263
2264 static void __devinit aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
2265 {
2266 const int ragepro_tbl[] = {
2267 44, 50, 55, 66, 75, 80, 100
2268 };
2269 const int ragexl_tbl[] = {
2270 50, 66, 75, 83, 90, 95, 100, 105,
2271 110, 115, 120, 125, 133, 143, 166
2272 };
2273 const int *refresh_tbl;
2274 int i, size;
2275
2276 if (IS_XL(par->pci_id) || IS_MOBILITY(par->pci_id)) {
2277 refresh_tbl = ragexl_tbl;
2278 size = ARRAY_SIZE(ragexl_tbl);
2279 } else {
2280 refresh_tbl = ragepro_tbl;
2281 size = ARRAY_SIZE(ragepro_tbl);
2282 }
2283
2284 for (i=0; i < size; i++) {
2285 if (xclk < refresh_tbl[i])
2286 break;
2287 }
2288 par->mem_refresh_rate = i;
2289 }
2290
2291 /*
2292 * Initialisation
2293 */
2294
2295 static struct fb_info *fb_list = NULL;
2296
2297 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2298 static int __devinit atyfb_get_timings_from_lcd(struct atyfb_par *par,
2299 struct fb_var_screeninfo *var)
2300 {
2301 int ret = -EINVAL;
2302
2303 if (par->lcd_table != 0 && (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2304 *var = default_var;
2305 var->xres = var->xres_virtual = par->lcd_hdisp;
2306 var->right_margin = par->lcd_right_margin;
2307 var->left_margin = par->lcd_hblank_len -
2308 (par->lcd_right_margin + par->lcd_hsync_dly +
2309 par->lcd_hsync_len);
2310 var->hsync_len = par->lcd_hsync_len + par->lcd_hsync_dly;
2311 var->yres = var->yres_virtual = par->lcd_vdisp;
2312 var->lower_margin = par->lcd_lower_margin;
2313 var->upper_margin = par->lcd_vblank_len -
2314 (par->lcd_lower_margin + par->lcd_vsync_len);
2315 var->vsync_len = par->lcd_vsync_len;
2316 var->pixclock = par->lcd_pixclock;
2317 ret = 0;
2318 }
2319
2320 return ret;
2321 }
2322 #endif /* defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD) */
2323
2324 static int __devinit aty_init(struct fb_info *info, const char *name)
2325 {
2326 struct atyfb_par *par = (struct atyfb_par *) info->par;
2327 const char *ramname = NULL, *xtal;
2328 int gtb_memsize, has_var = 0;
2329 struct fb_var_screeninfo var;
2330 u8 pll_ref_div;
2331 u32 i;
2332 #if defined(CONFIG_PPC)
2333 int sense;
2334 #endif
2335
2336 init_waitqueue_head(&par->vblank.wait);
2337 spin_lock_init(&par->int_lock);
2338
2339 par->aty_cmap_regs =
2340 (struct aty_cmap_regs __iomem *) (par->ati_regbase + 0xc0);
2341
2342 #ifdef CONFIG_PPC_PMAC
2343 /* The Apple iBook1 uses non-standard memory frequencies. We detect it
2344 * and set the frequency manually. */
2345 if (machine_is_compatible("PowerBook2,1")) {
2346 par->pll_limits.mclk = 70;
2347 par->pll_limits.xclk = 53;
2348 }
2349 #endif
2350 if (pll)
2351 par->pll_limits.pll_max = pll;
2352 if (mclk)
2353 par->pll_limits.mclk = mclk;
2354 if (xclk)
2355 par->pll_limits.xclk = xclk;
2356
2357 aty_calc_mem_refresh(par, par->pll_limits.xclk);
2358 par->pll_per = 1000000/par->pll_limits.pll_max;
2359 par->mclk_per = 1000000/par->pll_limits.mclk;
2360 par->xclk_per = 1000000/par->pll_limits.xclk;
2361
2362 par->ref_clk_per = 1000000000000ULL / 14318180;
2363 xtal = "14.31818";
2364
2365 #ifdef CONFIG_FB_ATY_GX
2366 if (!M64_HAS(INTEGRATED)) {
2367 u32 stat0;
2368 u8 dac_type, dac_subtype, clk_type;
2369 stat0 = aty_ld_le32(CONFIG_STAT0, par);
2370 par->bus_type = (stat0 >> 0) & 0x07;
2371 par->ram_type = (stat0 >> 3) & 0x07;
2372 ramname = aty_gx_ram[par->ram_type];
2373 /* FIXME: clockchip/RAMDAC probing? */
2374 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07;
2375 #ifdef CONFIG_ATARI
2376 clk_type = CLK_ATI18818_1;
2377 dac_type = (stat0 >> 9) & 0x07;
2378 if (dac_type == 0x07)
2379 dac_subtype = DAC_ATT20C408;
2380 else
2381 dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type;
2382 #else
2383 dac_type = DAC_IBMRGB514;
2384 dac_subtype = DAC_IBMRGB514;
2385 clk_type = CLK_IBMRGB514;
2386 #endif
2387 switch (dac_subtype) {
2388 case DAC_IBMRGB514:
2389 par->dac_ops = &aty_dac_ibm514;
2390 break;
2391 case DAC_ATI68860_B:
2392 case DAC_ATI68860_C:
2393 par->dac_ops = &aty_dac_ati68860b;
2394 break;
2395 case DAC_ATT20C408:
2396 case DAC_ATT21C498:
2397 par->dac_ops = &aty_dac_att21c498;
2398 break;
2399 default:
2400 PRINTKI("aty_init: DAC type not implemented yet!\n");
2401 par->dac_ops = &aty_dac_unsupported;
2402 break;
2403 }
2404 switch (clk_type) {
2405 #ifdef CONFIG_ATARI
2406 case CLK_ATI18818_1:
2407 par->pll_ops = &aty_pll_ati18818_1;
2408 break;
2409 #else
2410 case CLK_IBMRGB514:
2411 par->pll_ops = &aty_pll_ibm514;
2412 break;
2413 #endif
2414 #if 0 /* dead code */
2415 case CLK_STG1703:
2416 par->pll_ops = &aty_pll_stg1703;
2417 break;
2418 case CLK_CH8398:
2419 par->pll_ops = &aty_pll_ch8398;
2420 break;
2421 case CLK_ATT20C408:
2422 par->pll_ops = &aty_pll_att20c408;
2423 break;
2424 #endif
2425 default:
2426 PRINTKI("aty_init: CLK type not implemented yet!");
2427 par->pll_ops = &aty_pll_unsupported;
2428 break;
2429 }
2430 }
2431 #endif /* CONFIG_FB_ATY_GX */
2432 #ifdef CONFIG_FB_ATY_CT
2433 if (M64_HAS(INTEGRATED)) {
2434 par->dac_ops = &aty_dac_ct;
2435 par->pll_ops = &aty_pll_ct;
2436 par->bus_type = PCI;
2437 par->ram_type = (aty_ld_le32(CONFIG_STAT0, par) & 0x07);
2438 ramname = aty_ct_ram[par->ram_type];
2439 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2440 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
2441 par->pll_limits.mclk = 63;
2442 }
2443
2444 if (M64_HAS(GTB_DSP)
2445 && (pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par))) {
2446 int diff1, diff2;
2447 diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
2448 diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
2449 if (diff1 < 0)
2450 diff1 = -diff1;
2451 if (diff2 < 0)
2452 diff2 = -diff2;
2453 if (diff2 < diff1) {
2454 par->ref_clk_per = 1000000000000ULL / 29498928;
2455 xtal = "29.498928";
2456 }
2457 }
2458 #endif /* CONFIG_FB_ATY_CT */
2459
2460 /* save previous video mode */
2461 aty_get_crtc(par, &saved_crtc);
2462 if(par->pll_ops->get_pll)
2463 par->pll_ops->get_pll(info, &saved_pll);
2464
2465 i = aty_ld_le32(MEM_CNTL, par);
2466 gtb_memsize = M64_HAS(GTB_DSP);
2467 if (gtb_memsize)
2468 switch (i & 0xF) { /* 0xF used instead of MEM_SIZE_ALIAS */
2469 case MEM_SIZE_512K:
2470 info->fix.smem_len = 0x80000;
2471 break;
2472 case MEM_SIZE_1M:
2473 info->fix.smem_len = 0x100000;
2474 break;
2475 case MEM_SIZE_2M_GTB:
2476 info->fix.smem_len = 0x200000;
2477 break;
2478 case MEM_SIZE_4M_GTB:
2479 info->fix.smem_len = 0x400000;
2480 break;
2481 case MEM_SIZE_6M_GTB:
2482 info->fix.smem_len = 0x600000;
2483 break;
2484 case MEM_SIZE_8M_GTB:
2485 info->fix.smem_len = 0x800000;
2486 break;
2487 default:
2488 info->fix.smem_len = 0x80000;
2489 } else
2490 switch (i & MEM_SIZE_ALIAS) {
2491 case MEM_SIZE_512K:
2492 info->fix.smem_len = 0x80000;
2493 break;
2494 case MEM_SIZE_1M:
2495 info->fix.smem_len = 0x100000;
2496 break;
2497 case MEM_SIZE_2M:
2498 info->fix.smem_len = 0x200000;
2499 break;
2500 case MEM_SIZE_4M:
2501 info->fix.smem_len = 0x400000;
2502 break;
2503 case MEM_SIZE_6M:
2504 info->fix.smem_len = 0x600000;
2505 break;
2506 case MEM_SIZE_8M:
2507 info->fix.smem_len = 0x800000;
2508 break;
2509 default:
2510 info->fix.smem_len = 0x80000;
2511 }
2512
2513 if (M64_HAS(MAGIC_VRAM_SIZE)) {
2514 if (aty_ld_le32(CONFIG_STAT1, par) & 0x40000000)
2515 info->fix.smem_len += 0x400000;
2516 }
2517
2518 if (vram) {
2519 info->fix.smem_len = vram * 1024;
2520 i = i & ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
2521 if (info->fix.smem_len <= 0x80000)
2522 i |= MEM_SIZE_512K;
2523 else if (info->fix.smem_len <= 0x100000)
2524 i |= MEM_SIZE_1M;
2525 else if (info->fix.smem_len <= 0x200000)
2526 i |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
2527 else if (info->fix.smem_len <= 0x400000)
2528 i |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
2529 else if (info->fix.smem_len <= 0x600000)
2530 i |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
2531 else
2532 i |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
2533 aty_st_le32(MEM_CNTL, i, par);
2534 }
2535
2536 /*
2537 * Reg Block 0 (CT-compatible block) is at mmio_start
2538 * Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
2539 */
2540 if (M64_HAS(GX)) {
2541 info->fix.mmio_len = 0x400;
2542 info->fix.accel = FB_ACCEL_ATI_MACH64GX;
2543 } else if (M64_HAS(CT)) {
2544 info->fix.mmio_len = 0x400;
2545 info->fix.accel = FB_ACCEL_ATI_MACH64CT;
2546 } else if (M64_HAS(VT)) {
2547 info->fix.mmio_start -= 0x400;
2548 info->fix.mmio_len = 0x800;
2549 info->fix.accel = FB_ACCEL_ATI_MACH64VT;
2550 } else {/* GT */
2551 info->fix.mmio_start -= 0x400;
2552 info->fix.mmio_len = 0x800;
2553 info->fix.accel = FB_ACCEL_ATI_MACH64GT;
2554 }
2555
2556 PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n",
2557 info->fix.smem_len == 0x80000 ? 512 : (info->fix.smem_len >> 20),
2558 info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname, xtal, par->pll_limits.pll_max,
2559 par->pll_limits.mclk, par->pll_limits.xclk);
2560
2561 #if defined(DEBUG) && defined(CONFIG_ATY_CT)
2562 if (M64_HAS(INTEGRATED)) {
2563 int i;
2564 printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL EXT_MEM_CNTL CRTC_GEN_CNTL "
2565 "DSP_CONFIG DSP_ON_OFF CLOCK_CNTL\n"
2566 "debug atyfb: %08x %08x %08x %08x %08x %08x %08x %08x\n"
2567 "debug atyfb: PLL",
2568 aty_ld_le32(BUS_CNTL, par), aty_ld_le32(DAC_CNTL, par),
2569 aty_ld_le32(MEM_CNTL, par), aty_ld_le32(EXT_MEM_CNTL, par),
2570 aty_ld_le32(CRTC_GEN_CNTL, par), aty_ld_le32(DSP_CONFIG, par),
2571 aty_ld_le32(DSP_ON_OFF, par), aty_ld_le32(CLOCK_CNTL, par));
2572 for (i = 0; i < 40; i++)
2573 printk(" %02x", aty_ld_pll_ct(i, par));
2574 printk("\n");
2575 }
2576 #endif
2577 if(par->pll_ops->init_pll)
2578 par->pll_ops->init_pll(info, &par->pll);
2579
2580 /*
2581 * Last page of 8 MB (4 MB on ISA) aperture is MMIO
2582 * FIXME: we should use the auxiliary aperture instead so we can access
2583 * the full 8 MB of video RAM on 8 MB boards
2584 */
2585
2586 if (!par->aux_start &&
2587 (info->fix.smem_len == 0x800000 || (par->bus_type == ISA && info->fix.smem_len == 0x400000)))
2588 info->fix.smem_len -= GUI_RESERVE;
2589
2590 /*
2591 * Disable register access through the linear aperture
2592 * if the auxiliary aperture is used so we can access
2593 * the full 8 MB of video RAM on 8 MB boards.
2594 */
2595 if (par->aux_start)
2596 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2597
2598 #ifdef CONFIG_MTRR
2599 par->mtrr_aper = -1;
2600 par->mtrr_reg = -1;
2601 if (!nomtrr) {
2602 /* Cover the whole resource. */
2603 par->mtrr_aper = mtrr_add(par->res_start, par->res_size, MTRR_TYPE_WRCOMB, 1);
2604 if (par->mtrr_aper >= 0 && !par->aux_start) {
2605 /* Make a hole for mmio. */
2606 par->mtrr_reg = mtrr_add(par->res_start + 0x800000 - GUI_RESERVE,
2607 GUI_RESERVE, MTRR_TYPE_UNCACHABLE, 1);
2608 if (par->mtrr_reg < 0) {
2609 mtrr_del(par->mtrr_aper, 0, 0);
2610 par->mtrr_aper = -1;
2611 }
2612 }
2613 }
2614 #endif
2615
2616 info->fbops = &atyfb_ops;
2617 info->pseudo_palette = pseudo_palette;
2618 info->flags = FBINFO_DEFAULT |
2619 FBINFO_HWACCEL_IMAGEBLIT |
2620 FBINFO_HWACCEL_FILLRECT |
2621 FBINFO_HWACCEL_COPYAREA |
2622 FBINFO_HWACCEL_YPAN;
2623
2624 #ifdef CONFIG_PMAC_BACKLIGHT
2625 if (M64_HAS(G3_PB_1_1) && machine_is_compatible("PowerBook1,1")) {
2626 /* these bits let the 101 powerbook wake up from sleep -- paulus */
2627 aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par)
2628 | (USE_F32KHZ | TRISTATE_MEM_EN), par);
2629 } else
2630 #endif
2631 if (M64_HAS(MOBIL_BUS)) {
2632 #ifdef CONFIG_FB_ATY_BACKLIGHT
2633 aty_bl_init (par);
2634 #endif
2635 }
2636
2637 memset(&var, 0, sizeof(var));
2638 #ifdef CONFIG_PPC
2639 if (machine_is(powermac)) {
2640 /*
2641 * FIXME: The NVRAM stuff should be put in a Mac-specific file, as it
2642 * applies to all Mac video cards
2643 */
2644 if (mode) {
2645 if (mac_find_mode(&var, info, mode, 8))
2646 has_var = 1;
2647 } else {
2648 if (default_vmode == VMODE_CHOOSE) {
2649 if (M64_HAS(G3_PB_1024x768))
2650 /* G3 PowerBook with 1024x768 LCD */
2651 default_vmode = VMODE_1024_768_60;
2652 else if (machine_is_compatible("iMac"))
2653 default_vmode = VMODE_1024_768_75;
2654 else if (machine_is_compatible
2655 ("PowerBook2,1"))
2656 /* iBook with 800x600 LCD */
2657 default_vmode = VMODE_800_600_60;
2658 else
2659 default_vmode = VMODE_640_480_67;
2660 sense = read_aty_sense(par);
2661 PRINTKI("monitor sense=%x, mode %d\n",
2662 sense, mac_map_monitor_sense(sense));
2663 }
2664 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
2665 default_vmode = VMODE_640_480_60;
2666 if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
2667 default_cmode = CMODE_8;
2668 if (!mac_vmode_to_var(default_vmode, default_cmode,
2669 &var))
2670 has_var = 1;
2671 }
2672 }
2673
2674 #endif /* !CONFIG_PPC */
2675
2676 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2677 if (!atyfb_get_timings_from_lcd(par, &var))
2678 has_var = 1;
2679 #endif
2680
2681 if (mode && fb_find_mode(&var, info, mode, NULL, 0, &defmode, 8))
2682 has_var = 1;
2683
2684 if (!has_var)
2685 var = default_var;
2686
2687 if (noaccel)
2688 var.accel_flags &= ~FB_ACCELF_TEXT;
2689 else
2690 var.accel_flags |= FB_ACCELF_TEXT;
2691
2692 if (comp_sync != -1) {
2693 if (!comp_sync)
2694 var.sync &= ~FB_SYNC_COMP_HIGH_ACT;
2695 else
2696 var.sync |= FB_SYNC_COMP_HIGH_ACT;
2697 }
2698
2699 if (var.yres == var.yres_virtual) {
2700 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
2701 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
2702 if (var.yres_virtual < var.yres)
2703 var.yres_virtual = var.yres;
2704 }
2705
2706 if (atyfb_check_var(&var, info)) {
2707 PRINTKE("can't set default video mode\n");
2708 goto aty_init_exit;
2709 }
2710
2711 #ifdef __sparc__
2712 atyfb_save_palette(par, 0);
2713 #endif
2714
2715 #ifdef CONFIG_FB_ATY_CT
2716 if (!noaccel && M64_HAS(INTEGRATED))
2717 aty_init_cursor(info);
2718 #endif /* CONFIG_FB_ATY_CT */
2719 info->var = var;
2720
2721 fb_alloc_cmap(&info->cmap, 256, 0);
2722
2723 if (register_framebuffer(info) < 0)
2724 goto aty_init_exit;
2725
2726 fb_list = info;
2727
2728 PRINTKI("fb%d: %s frame buffer device on %s\n",
2729 info->node, info->fix.id, name);
2730 return 0;
2731
2732 aty_init_exit:
2733 /* restore video mode */
2734 aty_set_crtc(par, &saved_crtc);
2735 par->pll_ops->set_pll(info, &saved_pll);
2736
2737 #ifdef CONFIG_MTRR
2738 if (par->mtrr_reg >= 0) {
2739 mtrr_del(par->mtrr_reg, 0, 0);
2740 par->mtrr_reg = -1;
2741 }
2742 if (par->mtrr_aper >= 0) {
2743 mtrr_del(par->mtrr_aper, 0, 0);
2744 par->mtrr_aper = -1;
2745 }
2746 #endif
2747 return -1;
2748 }
2749
2750 #ifdef CONFIG_ATARI
2751 static int __devinit store_video_par(char *video_str, unsigned char m64_num)
2752 {
2753 char *p;
2754 unsigned long vmembase, size, guiregbase;
2755
2756 PRINTKI("store_video_par() '%s' \n", video_str);
2757
2758 if (!(p = strsep(&video_str, ";")) || !*p)
2759 goto mach64_invalid;
2760 vmembase = simple_strtoul(p, NULL, 0);
2761 if (!(p = strsep(&video_str, ";")) || !*p)
2762 goto mach64_invalid;
2763 size = simple_strtoul(p, NULL, 0);
2764 if (!(p = strsep(&video_str, ";")) || !*p)
2765 goto mach64_invalid;
2766 guiregbase = simple_strtoul(p, NULL, 0);
2767
2768 phys_vmembase[m64_num] = vmembase;
2769 phys_size[m64_num] = size;
2770 phys_guiregbase[m64_num] = guiregbase;
2771 PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
2772 guiregbase);
2773 return 0;
2774
2775 mach64_invalid:
2776 phys_vmembase[m64_num] = 0;
2777 return -1;
2778 }
2779 #endif /* CONFIG_ATARI */
2780
2781 /*
2782 * Blank the display.
2783 */
2784
2785 static int atyfb_blank(int blank, struct fb_info *info)
2786 {
2787 struct atyfb_par *par = (struct atyfb_par *) info->par;
2788 u32 gen_cntl;
2789
2790 if (par->lock_blank || par->asleep)
2791 return 0;
2792
2793 #ifdef CONFIG_PMAC_BACKLIGHT
2794 if (machine_is(powermac) && blank > FB_BLANK_NORMAL) {
2795 mutex_lock(&info->bl_mutex);
2796 if (info->bl_dev) {
2797 down(&info->bl_dev->sem);
2798 info->bl_dev->props->power = FB_BLANK_POWERDOWN;
2799 info->bl_dev->props->update_status(info->bl_dev);
2800 up(&info->bl_dev->sem);
2801 }
2802 mutex_unlock(&info->bl_mutex);
2803 }
2804 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2805 if (par->lcd_table && blank > FB_BLANK_NORMAL &&
2806 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2807 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2808 pm &= ~PWR_BLON;
2809 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2810 }
2811 #endif
2812
2813 gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2814 switch (blank) {
2815 case FB_BLANK_UNBLANK:
2816 gen_cntl &= ~0x400004c;
2817 break;
2818 case FB_BLANK_NORMAL:
2819 gen_cntl |= 0x4000040;
2820 break;
2821 case FB_BLANK_VSYNC_SUSPEND:
2822 gen_cntl |= 0x4000048;
2823 break;
2824 case FB_BLANK_HSYNC_SUSPEND:
2825 gen_cntl |= 0x4000044;
2826 break;
2827 case FB_BLANK_POWERDOWN:
2828 gen_cntl |= 0x400004c;
2829 break;
2830 }
2831 aty_st_le32(CRTC_GEN_CNTL, gen_cntl, par);
2832
2833 #ifdef CONFIG_PMAC_BACKLIGHT
2834 if (machine_is(powermac) && blank <= FB_BLANK_NORMAL) {
2835 mutex_lock(&info->bl_mutex);
2836 if (info->bl_dev) {
2837 down(&info->bl_dev->sem);
2838 info->bl_dev->props->power = FB_BLANK_UNBLANK;
2839 info->bl_dev->props->update_status(info->bl_dev);
2840 up(&info->bl_dev->sem);
2841 }
2842 mutex_unlock(&info->bl_mutex);
2843 }
2844 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2845 if (par->lcd_table && blank <= FB_BLANK_NORMAL &&
2846 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2847 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2848 pm |= PWR_BLON;
2849 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2850 }
2851 #endif
2852
2853 return 0;
2854 }
2855
2856 static void aty_st_pal(u_int regno, u_int red, u_int green, u_int blue,
2857 const struct atyfb_par *par)
2858 {
2859 #ifdef CONFIG_ATARI
2860 out_8(&par->aty_cmap_regs->windex, regno);
2861 out_8(&par->aty_cmap_regs->lut, red);
2862 out_8(&par->aty_cmap_regs->lut, green);
2863 out_8(&par->aty_cmap_regs->lut, blue);
2864 #else
2865 writeb(regno, &par->aty_cmap_regs->windex);
2866 writeb(red, &par->aty_cmap_regs->lut);
2867 writeb(green, &par->aty_cmap_regs->lut);
2868 writeb(blue, &par->aty_cmap_regs->lut);
2869 #endif
2870 }
2871
2872 /*
2873 * Set a single color register. The values supplied are already
2874 * rounded down to the hardware's capabilities (according to the
2875 * entries in the var structure). Return != 0 for invalid regno.
2876 * !! 4 & 8 = PSEUDO, > 8 = DIRECTCOLOR
2877 */
2878
2879 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2880 u_int transp, struct fb_info *info)
2881 {
2882 struct atyfb_par *par = (struct atyfb_par *) info->par;
2883 int i, depth;
2884 u32 *pal = info->pseudo_palette;
2885
2886 depth = info->var.bits_per_pixel;
2887 if (depth == 16)
2888 depth = (info->var.green.length == 5) ? 15 : 16;
2889
2890 if (par->asleep)
2891 return 0;
2892
2893 if (regno > 255 ||
2894 (depth == 16 && regno > 63) ||
2895 (depth == 15 && regno > 31))
2896 return 1;
2897
2898 red >>= 8;
2899 green >>= 8;
2900 blue >>= 8;
2901
2902 par->palette[regno].red = red;
2903 par->palette[regno].green = green;
2904 par->palette[regno].blue = blue;
2905
2906 if (regno < 16) {
2907 switch (depth) {
2908 case 15:
2909 pal[regno] = (regno << 10) | (regno << 5) | regno;
2910 break;
2911 case 16:
2912 pal[regno] = (regno << 11) | (regno << 5) | regno;
2913 break;
2914 case 24:
2915 pal[regno] = (regno << 16) | (regno << 8) | regno;
2916 break;
2917 case 32:
2918 i = (regno << 8) | regno;
2919 pal[regno] = (i << 16) | i;
2920 break;
2921 }
2922 }
2923
2924 i = aty_ld_8(DAC_CNTL, par) & 0xfc;
2925 if (M64_HAS(EXTRA_BRIGHT))
2926 i |= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */
2927 aty_st_8(DAC_CNTL, i, par);
2928 aty_st_8(DAC_MASK, 0xff, par);
2929
2930 if (M64_HAS(INTEGRATED)) {
2931 if (depth == 16) {
2932 if (regno < 32)
2933 aty_st_pal(regno << 3, red,
2934 par->palette[regno<<1].green,
2935 blue, par);
2936 red = par->palette[regno>>1].red;
2937 blue = par->palette[regno>>1].blue;
2938 regno <<= 2;
2939 } else if (depth == 15) {
2940 regno <<= 3;
2941 for(i = 0; i < 8; i++) {
2942 aty_st_pal(regno + i, red, green, blue, par);
2943 }
2944 }
2945 }
2946 aty_st_pal(regno, red, green, blue, par);
2947
2948 return 0;
2949 }
2950
2951 #ifdef CONFIG_PCI
2952
2953 #ifdef __sparc__
2954
2955 extern void (*prom_palette) (int);
2956
2957 static int __devinit atyfb_setup_sparc(struct pci_dev *pdev,
2958 struct fb_info *info, unsigned long addr)
2959 {
2960 extern int con_is_present(void);
2961
2962 struct atyfb_par *par = info->par;
2963 struct pcidev_cookie *pcp;
2964 char prop[128];
2965 int node, len, i, j, ret;
2966 u32 mem, chip_id;
2967
2968 /* Do not attach when we have a serial console. */
2969 if (!con_is_present())
2970 return -ENXIO;
2971
2972 /*
2973 * Map memory-mapped registers.
2974 */
2975 par->ati_regbase = (void *)addr + 0x7ffc00UL;
2976 info->fix.mmio_start = addr + 0x7ffc00UL;
2977
2978 /*
2979 * Map in big-endian aperture.
2980 */
2981 info->screen_base = (char *) (addr + 0x800000UL);
2982 info->fix.smem_start = addr + 0x800000UL;
2983
2984 /*
2985 * Figure mmap addresses from PCI config space.
2986 * Split Framebuffer in big- and little-endian halfs.
2987 */
2988 for (i = 0; i < 6 && pdev->resource[i].start; i++)
2989 /* nothing */ ;
2990 j = i + 4;
2991
2992 par->mmap_map = kmalloc(j * sizeof(*par->mmap_map), GFP_ATOMIC);
2993 if (!par->mmap_map) {
2994 PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n");
2995 return -ENOMEM;
2996 }
2997 memset(par->mmap_map, 0, j * sizeof(*par->mmap_map));
2998
2999 for (i = 0, j = 2; i < 6 && pdev->resource[i].start; i++) {
3000 struct resource *rp = &pdev->resource[i];
3001 int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
3002 unsigned long base;
3003 u32 size, pbase;
3004
3005 base = rp->start;
3006
3007 io = (rp->flags & IORESOURCE_IO);
3008
3009 size = rp->end - base + 1;
3010
3011 pci_read_config_dword(pdev, breg, &pbase);
3012
3013 if (io)
3014 size &= ~1;
3015
3016 /*
3017 * Map the framebuffer a second time, this time without
3018 * the braindead _PAGE_IE setting. This is used by the
3019 * fixed Xserver, but we need to maintain the old mapping
3020 * to stay compatible with older ones...
3021 */
3022 if (base == addr) {
3023 par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK;
3024 par->mmap_map[j].poff = base & PAGE_MASK;
3025 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
3026 par->mmap_map[j].prot_mask = _PAGE_CACHE;
3027 par->mmap_map[j].prot_flag = _PAGE_E;
3028 j++;
3029 }
3030
3031 /*
3032 * Here comes the old framebuffer mapping with _PAGE_IE
3033 * set for the big endian half of the framebuffer...
3034 */
3035 if (base == addr) {
3036 par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
3037 par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK;
3038 par->mmap_map[j].size = 0x800000;
3039 par->mmap_map[j].prot_mask = _PAGE_CACHE;
3040 par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE;
3041 size -= 0x800000;
3042 j++;
3043 }
3044
3045 par->mmap_map[j].voff = pbase & PAGE_MASK;
3046 par->mmap_map[j].poff = base & PAGE_MASK;
3047 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
3048 par->mmap_map[j].prot_mask = _PAGE_CACHE;
3049 par->mmap_map[j].prot_flag = _PAGE_E;
3050 j++;
3051 }
3052
3053 if((ret = correct_chipset(par)))
3054 return ret;
3055
3056 if (IS_XL(pdev->device)) {
3057 /*
3058 * Fix PROMs idea of MEM_CNTL settings...
3059 */
3060 mem = aty_ld_le32(MEM_CNTL, par);
3061 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
3062 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
3063 switch (mem & 0x0f) {
3064 case 3:
3065 mem = (mem & ~(0x0f)) | 2;
3066 break;
3067 case 7:
3068 mem = (mem & ~(0x0f)) | 3;
3069 break;
3070 case 9:
3071 mem = (mem & ~(0x0f)) | 4;
3072 break;
3073 case 11:
3074 mem = (mem & ~(0x0f)) | 5;
3075 break;
3076 default:
3077 break;
3078 }
3079 if ((aty_ld_le32(CONFIG_STAT0, par) & 7) >= SDRAM)
3080 mem &= ~(0x00700000);
3081 }
3082 mem &= ~(0xcf80e000); /* Turn off all undocumented bits. */
3083 aty_st_le32(MEM_CNTL, mem, par);
3084 }
3085
3086 /*
3087 * If this is the console device, we will set default video
3088 * settings to what the PROM left us with.
3089 */
3090 node = prom_getchild(prom_root_node);
3091 node = prom_searchsiblings(node, "aliases");
3092 if (node) {
3093 len = prom_getproperty(node, "screen", prop, sizeof(prop));
3094 if (len > 0) {
3095 prop[len] = '\0';
3096 node = prom_finddevice(prop);
3097 } else
3098 node = 0;
3099 }
3100
3101 pcp = pdev->sysdata;
3102 if (node == pcp->prom_node->node) {
3103 struct fb_var_screeninfo *var = &default_var;
3104 unsigned int N, P, Q, M, T, R;
3105 u32 v_total, h_total;
3106 struct crtc crtc;
3107 u8 pll_regs[16];
3108 u8 clock_cntl;
3109
3110 crtc.vxres = prom_getintdefault(node, "width", 1024);
3111 crtc.vyres = prom_getintdefault(node, "height", 768);
3112 var->bits_per_pixel = prom_getintdefault(node, "depth", 8);
3113 var->xoffset = var->yoffset = 0;
3114 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
3115 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
3116 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
3117 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
3118 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
3119 aty_crtc_to_var(&crtc, var);
3120
3121 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
3122 v_total = var->yres + var->lower_margin + var->vsync_len + var->upper_margin;
3123
3124 /*
3125 * Read the PLL to figure actual Refresh Rate.
3126 */
3127 clock_cntl = aty_ld_8(CLOCK_CNTL, par);
3128 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */
3129 for (i = 0; i < 16; i++)
3130 pll_regs[i] = aty_ld_pll_ct(i, par);
3131
3132 /*
3133 * PLL Reference Divider M:
3134 */
3135 M = pll_regs[2];
3136
3137 /*
3138 * PLL Feedback Divider N (Dependant on CLOCK_CNTL):
3139 */
3140 N = pll_regs[7 + (clock_cntl & 3)];
3141
3142 /*
3143 * PLL Post Divider P (Dependant on CLOCK_CNTL):
3144 */
3145 P = 1 << (pll_regs[6] >> ((clock_cntl & 3) << 1));
3146
3147 /*
3148 * PLL Divider Q:
3149 */
3150 Q = N / P;
3151
3152 /*
3153 * Target Frequency:
3154 *
3155 * T * M
3156 * Q = -------
3157 * 2 * R
3158 *
3159 * where R is XTALIN (= 14318 or 29498 kHz).
3160 */
3161 if (IS_XL(pdev->device))
3162 R = 29498;
3163 else
3164 R = 14318;
3165
3166 T = 2 * Q * R / M;
3167
3168 default_var.pixclock = 1000000000 / T;
3169 }
3170
3171 return 0;
3172 }
3173
3174 #else /* __sparc__ */
3175
3176 #ifdef __i386__
3177 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3178 static void aty_init_lcd(struct atyfb_par *par, u32 bios_base)
3179 {
3180 u32 driv_inf_tab, sig;
3181 u16 lcd_ofs;
3182
3183 /* To support an LCD panel, we should know it's dimensions and
3184 * it's desired pixel clock.
3185 * There are two ways to do it:
3186 * - Check the startup video mode and calculate the panel
3187 * size from it. This is unreliable.
3188 * - Read it from the driver information table in the video BIOS.
3189 */
3190 /* Address of driver information table is at offset 0x78. */
3191 driv_inf_tab = bios_base + *((u16 *)(bios_base+0x78));
3192
3193 /* Check for the driver information table signature. */
3194 sig = (*(u32 *)driv_inf_tab);
3195 if ((sig == 0x54504c24) || /* Rage LT pro */
3196 (sig == 0x544d5224) || /* Rage mobility */
3197 (sig == 0x54435824) || /* Rage XC */
3198 (sig == 0x544c5824)) { /* Rage XL */
3199 PRINTKI("BIOS contains driver information table.\n");
3200 lcd_ofs = (*(u16 *)(driv_inf_tab + 10));
3201 par->lcd_table = 0;
3202 if (lcd_ofs != 0) {
3203 par->lcd_table = bios_base + lcd_ofs;
3204 }
3205 }
3206
3207 if (par->lcd_table != 0) {
3208 char model[24];
3209 char strbuf[16];
3210 char refresh_rates_buf[100];
3211 int id, tech, f, i, m, default_refresh_rate;
3212 char *txtcolour;
3213 char *txtmonitor;
3214 char *txtdual;
3215 char *txtformat;
3216 u16 width, height, panel_type, refresh_rates;
3217 u16 *lcdmodeptr;
3218 u32 format;
3219 u8 lcd_refresh_rates[16] = {50,56,60,67,70,72,75,76,85,90,100,120,140,150,160,200};
3220 /* The most important information is the panel size at
3221 * offset 25 and 27, but there's some other nice information
3222 * which we print to the screen.
3223 */
3224 id = *(u8 *)par->lcd_table;
3225 strncpy(model,(char *)par->lcd_table+1,24);
3226 model[23]=0;
3227
3228 width = par->lcd_width = *(u16 *)(par->lcd_table+25);
3229 height = par->lcd_height = *(u16 *)(par->lcd_table+27);
3230 panel_type = *(u16 *)(par->lcd_table+29);
3231 if (panel_type & 1)
3232 txtcolour = "colour";
3233 else
3234 txtcolour = "monochrome";
3235 if (panel_type & 2)
3236 txtdual = "dual (split) ";
3237 else
3238 txtdual = "";
3239 tech = (panel_type>>2) & 63;
3240 switch (tech) {
3241 case 0:
3242 txtmonitor = "passive matrix";
3243 break;
3244 case 1:
3245 txtmonitor = "active matrix";
3246 break;
3247 case 2:
3248 txtmonitor = "active addressed STN";
3249 break;
3250 case 3:
3251 txtmonitor = "EL";
3252 break;
3253 case 4:
3254 txtmonitor = "plasma";
3255 break;
3256 default:
3257 txtmonitor = "unknown";
3258 }
3259 format = *(u32 *)(par->lcd_table+57);
3260 if (tech == 0 || tech == 2) {
3261 switch (format & 7) {
3262 case 0:
3263 txtformat = "12 bit interface";
3264 break;
3265 case 1:
3266 txtformat = "16 bit interface";
3267 break;
3268 case 2:
3269 txtformat = "24 bit interface";
3270 break;
3271 default:
3272 txtformat = "unkown format";
3273 }
3274 } else {
3275 switch (format & 7) {
3276 case 0:
3277 txtformat = "8 colours";
3278 break;
3279 case 1:
3280 txtformat = "512 colours";
3281 break;
3282 case 2:
3283 txtformat = "4096 colours";
3284 break;
3285 case 4:
3286 txtformat = "262144 colours (LT mode)";
3287 break;
3288 case 5:
3289 txtformat = "16777216 colours";
3290 break;
3291 case 6:
3292 txtformat = "262144 colours (FDPI-2 mode)";
3293 break;
3294 default:
3295 txtformat = "unkown format";
3296 }
3297 }
3298 PRINTKI("%s%s %s monitor detected: %s\n",
3299 txtdual ,txtcolour, txtmonitor, model);
3300 PRINTKI(" id=%d, %dx%d pixels, %s\n",
3301 id, width, height, txtformat);
3302 refresh_rates_buf[0] = 0;
3303 refresh_rates = *(u16 *)(par->lcd_table+62);
3304 m = 1;
3305 f = 0;
3306 for (i=0;i<16;i++) {
3307 if (refresh_rates & m) {
3308 if (f == 0) {
3309 sprintf(strbuf, "%d", lcd_refresh_rates[i]);
3310 f++;
3311 } else {
3312 sprintf(strbuf, ",%d", lcd_refresh_rates[i]);
3313 }
3314 strcat(refresh_rates_buf,strbuf);
3315 }
3316 m = m << 1;
3317 }
3318 default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4;
3319 PRINTKI(" supports refresh rates [%s], default %d Hz\n",
3320 refresh_rates_buf, lcd_refresh_rates[default_refresh_rate]);
3321 par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate];
3322 /* We now need to determine the crtc parameters for the
3323 * LCD monitor. This is tricky, because they are not stored
3324 * individually in the BIOS. Instead, the BIOS contains a
3325 * table of display modes that work for this monitor.
3326 *
3327 * The idea is that we search for a mode of the same dimensions
3328 * as the dimensions of the LCD monitor. Say our LCD monitor
3329 * is 800x600 pixels, we search for a 800x600 monitor.
3330 * The CRTC parameters we find here are the ones that we need
3331 * to use to simulate other resolutions on the LCD screen.
3332 */
3333 lcdmodeptr = (u16 *)(par->lcd_table + 64);
3334 while (*lcdmodeptr != 0) {
3335 u32 modeptr;
3336 u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start;
3337 modeptr = bios_base + *lcdmodeptr;
3338
3339 mwidth = *((u16 *)(modeptr+0));
3340 mheight = *((u16 *)(modeptr+2));
3341
3342 if (mwidth == width && mheight == height) {
3343 par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9));
3344 par->lcd_htotal = *((u16 *)(modeptr+17)) & 511;
3345 par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511;
3346 lcd_hsync_start = *((u16 *)(modeptr+21)) & 511;
3347 par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7;
3348 par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63;
3349
3350 par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047;
3351 par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047;
3352 lcd_vsync_start = *((u16 *)(modeptr+28)) & 2047;
3353 par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31;
3354
3355 par->lcd_htotal = (par->lcd_htotal + 1) * 8;
3356 par->lcd_hdisp = (par->lcd_hdisp + 1) * 8;
3357 lcd_hsync_start = (lcd_hsync_start + 1) * 8;
3358 par->lcd_hsync_len = par->lcd_hsync_len * 8;
3359
3360 par->lcd_vtotal++;
3361 par->lcd_vdisp++;
3362 lcd_vsync_start++;
3363
3364 par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp;
3365 par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp;
3366 par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp;
3367 par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp;
3368 break;
3369 }
3370
3371 lcdmodeptr++;
3372 }
3373 if (*lcdmodeptr == 0) {
3374 PRINTKE("LCD monitor CRTC parameters not found!!!\n");
3375 /* To do: Switch to CRT if possible. */
3376 } else {
3377 PRINTKI(" LCD CRTC parameters: %d.%d %d %d %d %d %d %d %d %d\n",
3378 1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock,
3379 par->lcd_hdisp,
3380 par->lcd_hdisp + par->lcd_right_margin,
3381 par->lcd_hdisp + par->lcd_right_margin
3382 + par->lcd_hsync_dly + par->lcd_hsync_len,
3383 par->lcd_htotal,
3384 par->lcd_vdisp,
3385 par->lcd_vdisp + par->lcd_lower_margin,
3386 par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len,
3387 par->lcd_vtotal);
3388 PRINTKI(" : %d %d %d %d %d %d %d %d %d\n",
3389 par->lcd_pixclock,
3390 par->lcd_hblank_len - (par->lcd_right_margin +
3391 par->lcd_hsync_dly + par->lcd_hsync_len),
3392 par->lcd_hdisp,
3393 par->lcd_right_margin,
3394 par->lcd_hsync_len,
3395 par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len),
3396 par->lcd_vdisp,
3397 par->lcd_lower_margin,
3398 par->lcd_vsync_len);
3399 }
3400 }
3401 }
3402 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
3403
3404 static int __devinit init_from_bios(struct atyfb_par *par)
3405 {
3406 u32 bios_base, rom_addr;
3407 int ret;
3408
3409 rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
3410 bios_base = (unsigned long)ioremap(rom_addr, 0x10000);
3411
3412 /* The BIOS starts with 0xaa55. */
3413 if (*((u16 *)bios_base) == 0xaa55) {
3414
3415 u8 *bios_ptr;
3416 u16 rom_table_offset, freq_table_offset;
3417 PLL_BLOCK_MACH64 pll_block;
3418
3419 PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr, bios_base);
3420
3421 /* check for frequncy table */
3422 bios_ptr = (u8*)bios_base;
3423 rom_table_offset = (u16)(bios_ptr[0x48] | (bios_ptr[0x49] << 8));
3424 freq_table_offset = bios_ptr[rom_table_offset + 16] | (bios_ptr[rom_table_offset + 17] << 8);
3425 memcpy(&pll_block, bios_ptr + freq_table_offset, sizeof(PLL_BLOCK_MACH64));
3426
3427 PRINTKI("BIOS frequency table:\n");
3428 PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n",
3429 pll_block.PCLK_min_freq, pll_block.PCLK_max_freq,
3430 pll_block.ref_freq, pll_block.ref_divider);
3431 PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n",
3432 pll_block.MCLK_pwd, pll_block.MCLK_max_freq,
3433 pll_block.XCLK_max_freq, pll_block.SCLK_freq);
3434
3435 par->pll_limits.pll_min = pll_block.PCLK_min_freq/100;
3436 par->pll_limits.pll_max = pll_block.PCLK_max_freq/100;
3437 par->pll_limits.ref_clk = pll_block.ref_freq/100;
3438 par->pll_limits.ref_div = pll_block.ref_divider;
3439 par->pll_limits.sclk = pll_block.SCLK_freq/100;
3440 par->pll_limits.mclk = pll_block.MCLK_max_freq/100;
3441 par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100;
3442 par->pll_limits.xclk = pll_block.XCLK_max_freq/100;
3443 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3444 aty_init_lcd(par, bios_base);
3445 #endif
3446 ret = 0;
3447 } else {
3448 PRINTKE("no BIOS frequency table found, use parameters\n");
3449 ret = -ENXIO;
3450 }
3451 iounmap((void* __iomem )bios_base);
3452
3453 return ret;
3454 }
3455 #endif /* __i386__ */
3456
3457 static int __devinit atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info, unsigned long addr)
3458 {
3459 struct atyfb_par *par = info->par;
3460 u16 tmp;
3461 unsigned long raddr;
3462 struct resource *rrp;
3463 int ret = 0;
3464
3465 raddr = addr + 0x7ff000UL;
3466 rrp = &pdev->resource[2];
3467 if ((rrp->flags & IORESOURCE_MEM) && request_mem_region(rrp->start, rrp->end - rrp->start + 1, "atyfb")) {
3468 par->aux_start = rrp->start;
3469 par->aux_size = rrp->end - rrp->start + 1;
3470 raddr = rrp->start;
3471 PRINTKI("using auxiliary register aperture\n");
3472 }
3473
3474 info->fix.mmio_start = raddr;
3475 par->ati_regbase = ioremap(info->fix.mmio_start, 0x1000);
3476 if (par->ati_regbase == 0)
3477 return -ENOMEM;
3478
3479 info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00;
3480 par->ati_regbase += par->aux_start ? 0x400 : 0xc00;
3481
3482 /*
3483 * Enable memory-space accesses using config-space
3484 * command register.
3485 */
3486 pci_read_config_word(pdev, PCI_COMMAND, &tmp);
3487 if (!(tmp & PCI_COMMAND_MEMORY)) {
3488 tmp |= PCI_COMMAND_MEMORY;
3489 pci_write_config_word(pdev, PCI_COMMAND, tmp);
3490 }
3491 #ifdef __BIG_ENDIAN
3492 /* Use the big-endian aperture */
3493 addr += 0x800000;
3494 #endif
3495
3496 /* Map in frame buffer */
3497 info->fix.smem_start = addr;
3498 info->screen_base = ioremap(addr, 0x800000);
3499 if (info->screen_base == NULL) {
3500 ret = -ENOMEM;
3501 goto atyfb_setup_generic_fail;
3502 }
3503
3504 if((ret = correct_chipset(par)))
3505 goto atyfb_setup_generic_fail;
3506 #ifdef __i386__
3507 if((ret = init_from_bios(par)))
3508 goto atyfb_setup_generic_fail;
3509 #endif
3510 if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN))
3511 par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2;
3512 else
3513 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
3514
3515 /* according to ATI, we should use clock 3 for acelerated mode */
3516 par->clk_wr_offset = 3;
3517
3518 return 0;
3519
3520 atyfb_setup_generic_fail:
3521 iounmap(par->ati_regbase);
3522 par->ati_regbase = NULL;
3523 return ret;
3524 }
3525
3526 #endif /* !__sparc__ */
3527
3528 static int __devinit atyfb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3529 {
3530 unsigned long addr, res_start, res_size;
3531 struct fb_info *info;
3532 struct resource *rp;
3533 struct atyfb_par *par;
3534 int i, rc = -ENOMEM;
3535
3536 for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
3537 if (pdev->device == aty_chips[i].pci_id)
3538 break;
3539
3540 if (i < 0)
3541 return -ENODEV;
3542
3543 /* Enable device in PCI config */
3544 if (pci_enable_device(pdev)) {
3545 PRINTKE("Cannot enable PCI device\n");
3546 return -ENXIO;
3547 }
3548
3549 /* Find which resource to use */
3550 rp = &pdev->resource[0];
3551 if (rp->flags & IORESOURCE_IO)
3552 rp = &pdev->resource[1];
3553 addr = rp->start;
3554 if (!addr)
3555 return -ENXIO;
3556
3557 /* Reserve space */
3558 res_start = rp->start;
3559 res_size = rp->end - rp->start + 1;
3560 if (!request_mem_region (res_start, res_size, "atyfb"))
3561 return -EBUSY;
3562
3563 /* Allocate framebuffer */
3564 info = framebuffer_alloc(sizeof(struct atyfb_par), &pdev->dev);
3565 if (!info) {
3566 PRINTKE("atyfb_pci_probe() can't alloc fb_info\n");
3567 return -ENOMEM;
3568 }
3569 par = info->par;
3570 info->fix = atyfb_fix;
3571 info->device = &pdev->dev;
3572 par->pci_id = aty_chips[i].pci_id;
3573 par->res_start = res_start;
3574 par->res_size = res_size;
3575 par->irq = pdev->irq;
3576 par->pdev = pdev;
3577
3578 /* Setup "info" structure */
3579 #ifdef __sparc__
3580 rc = atyfb_setup_sparc(pdev, info, addr);
3581 #else
3582 rc = atyfb_setup_generic(pdev, info, addr);
3583 #endif
3584 if (rc)
3585 goto err_release_mem;
3586
3587 pci_set_drvdata(pdev, info);
3588
3589 /* Init chip & register framebuffer */
3590 if (aty_init(info, "PCI"))
3591 goto err_release_io;
3592
3593 #ifdef __sparc__
3594 if (!prom_palette)
3595 prom_palette = atyfb_palette;
3596
3597 /*
3598 * Add /dev/fb mmap values.
3599 */
3600 par->mmap_map[0].voff = 0x8000000000000000UL;
3601 par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK;
3602 par->mmap_map[0].size = info->fix.smem_len;
3603 par->mmap_map[0].prot_mask = _PAGE_CACHE;
3604 par->mmap_map[0].prot_flag = _PAGE_E;
3605 par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len;
3606 par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK;
3607 par->mmap_map[1].size = PAGE_SIZE;
3608 par->mmap_map[1].prot_mask = _PAGE_CACHE;
3609 par->mmap_map[1].prot_flag = _PAGE_E;
3610 #endif /* __sparc__ */
3611
3612 return 0;
3613
3614 err_release_io:
3615 #ifdef __sparc__
3616 kfree(par->mmap_map);
3617 #else
3618 if (par->ati_regbase)
3619 iounmap(par->ati_regbase);
3620 if (info->screen_base)
3621 iounmap(info->screen_base);
3622 #endif
3623 err_release_mem:
3624 if (par->aux_start)
3625 release_mem_region(par->aux_start, par->aux_size);
3626
3627 release_mem_region(par->res_start, par->res_size);
3628 framebuffer_release(info);
3629
3630 return rc;
3631 }
3632
3633 #endif /* CONFIG_PCI */
3634
3635 #ifdef CONFIG_ATARI
3636
3637 static int __devinit atyfb_atari_probe(void)
3638 {
3639 struct atyfb_par *par;
3640 struct fb_info *info;
3641 int m64_num;
3642 u32 clock_r;
3643
3644 for (m64_num = 0; m64_num < mach64_count; m64_num++) {
3645 if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
3646 !phys_guiregbase[m64_num]) {
3647 PRINTKI("phys_*[%d] parameters not set => returning early. \n", m64_num);
3648 continue;
3649 }
3650
3651 info = framebuffer_alloc(sizeof(struct atyfb_par), NULL);
3652 if (!info) {
3653 PRINTKE("atyfb_atari_probe() can't alloc fb_info\n");
3654 return -ENOMEM;
3655 }
3656 par = info->par;
3657
3658 info->fix = atyfb_fix;
3659
3660 par->irq = (unsigned int) -1; /* something invalid */
3661
3662 /*
3663 * Map the video memory (physical address given) to somewhere in the
3664 * kernel address space.
3665 */
3666 info->screen_base = ioremap(phys_vmembase[m64_num], phys_size[m64_num]);
3667 info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */
3668 par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) +
3669 0xFC00ul;
3670 info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */
3671
3672 aty_st_le32(CLOCK_CNTL, 0x12345678, par);
3673 clock_r = aty_ld_le32(CLOCK_CNTL, par);
3674
3675 switch (clock_r & 0x003F) {
3676 case 0x12:
3677 par->clk_wr_offset = 3; /* */
3678 break;
3679 case 0x34:
3680 par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
3681 break;
3682 case 0x16:
3683 par->clk_wr_offset = 1; /* */
3684 break;
3685 case 0x38:
3686 par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
3687 break;
3688 }
3689
3690 if (aty_init(info, "ISA bus")) {
3691 framebuffer_release(info);
3692 /* This is insufficient! kernel_map has added two large chunks!! */
3693 return -ENXIO;
3694 }
3695 }
3696 }
3697
3698 #endif /* CONFIG_ATARI */
3699
3700 static void __devexit atyfb_remove(struct fb_info *info)
3701 {
3702 struct atyfb_par *par = (struct atyfb_par *) info->par;
3703
3704 /* restore video mode */
3705 aty_set_crtc(par, &saved_crtc);
3706 par->pll_ops->set_pll(info, &saved_pll);
3707
3708 #ifdef CONFIG_FB_ATY_BACKLIGHT
3709 if (M64_HAS(MOBIL_BUS))
3710 aty_bl_exit(par);
3711 #endif
3712
3713 unregister_framebuffer(info);
3714
3715 #ifdef CONFIG_MTRR
3716 if (par->mtrr_reg >= 0) {
3717 mtrr_del(par->mtrr_reg, 0, 0);
3718 par->mtrr_reg = -1;
3719 }
3720 if (par->mtrr_aper >= 0) {
3721 mtrr_del(par->mtrr_aper, 0, 0);
3722 par->mtrr_aper = -1;
3723 }
3724 #endif
3725 #ifndef __sparc__
3726 if (par->ati_regbase)
3727 iounmap(par->ati_regbase);
3728 if (info->screen_base)
3729 iounmap(info->screen_base);
3730 #ifdef __BIG_ENDIAN
3731 if (info->sprite.addr)
3732 iounmap(info->sprite.addr);
3733 #endif
3734 #endif
3735 #ifdef __sparc__
3736 kfree(par->mmap_map);
3737 #endif
3738 if (par->aux_start)
3739 release_mem_region(par->aux_start, par->aux_size);
3740
3741 if (par->res_start)
3742 release_mem_region(par->res_start, par->res_size);
3743
3744 framebuffer_release(info);
3745 }
3746
3747 #ifdef CONFIG_PCI
3748
3749 static void __devexit atyfb_pci_remove(struct pci_dev *pdev)
3750 {
3751 struct fb_info *info = pci_get_drvdata(pdev);
3752
3753 atyfb_remove(info);
3754 }
3755
3756 /*
3757 * This driver uses its own matching table. That will be more difficult
3758 * to fix, so for now, we just match against any ATI ID and let the
3759 * probe() function find out what's up. That also mean we don't have
3760 * a module ID table though.
3761 */
3762 static struct pci_device_id atyfb_pci_tbl[] = {
3763 { PCI_VENDOR_ID_ATI, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
3764 PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0 },
3765 { 0, }
3766 };
3767
3768 static struct pci_driver atyfb_driver = {
3769 .name = "atyfb",
3770 .id_table = atyfb_pci_tbl,
3771 .probe = atyfb_pci_probe,
3772 .remove = __devexit_p(atyfb_pci_remove),
3773 #ifdef CONFIG_PM
3774 .suspend = atyfb_pci_suspend,
3775 .resume = atyfb_pci_resume,
3776 #endif /* CONFIG_PM */
3777 };
3778
3779 #endif /* CONFIG_PCI */
3780
3781 #ifndef MODULE
3782 static int __devinit atyfb_setup(char *options)
3783 {
3784 char *this_opt;
3785
3786 if (!options || !*options)
3787 return 0;
3788
3789 while ((this_opt = strsep(&options, ",")) != NULL) {
3790 if (!strncmp(this_opt, "noaccel", 7)) {
3791 noaccel = 1;
3792 #ifdef CONFIG_MTRR
3793 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3794 nomtrr = 1;
3795 #endif
3796 } else if (!strncmp(this_opt, "vram:", 5))
3797 vram = simple_strtoul(this_opt + 5, NULL, 0);
3798 else if (!strncmp(this_opt, "pll:", 4))
3799 pll = simple_strtoul(this_opt + 4, NULL, 0);
3800 else if (!strncmp(this_opt, "mclk:", 5))
3801 mclk = simple_strtoul(this_opt + 5, NULL, 0);
3802 else if (!strncmp(this_opt, "xclk:", 5))
3803 xclk = simple_strtoul(this_opt+5, NULL, 0);
3804 else if (!strncmp(this_opt, "comp_sync:", 10))
3805 comp_sync = simple_strtoul(this_opt+10, NULL, 0);
3806 #ifdef CONFIG_PPC
3807 else if (!strncmp(this_opt, "vmode:", 6)) {
3808 unsigned int vmode =
3809 simple_strtoul(this_opt + 6, NULL, 0);
3810 if (vmode > 0 && vmode <= VMODE_MAX)
3811 default_vmode = vmode;
3812 } else if (!strncmp(this_opt, "cmode:", 6)) {
3813 unsigned int cmode =
3814 simple_strtoul(this_opt + 6, NULL, 0);
3815 switch (cmode) {
3816 case 0:
3817 case 8:
3818 default_cmode = CMODE_8;
3819 break;
3820 case 15:
3821 case 16:
3822 default_cmode = CMODE_16;
3823 break;
3824 case 24:
3825 case 32:
3826 default_cmode = CMODE_32;
3827 break;
3828 }
3829 }
3830 #endif
3831 #ifdef CONFIG_ATARI
3832 /*
3833 * Why do we need this silly Mach64 argument?
3834 * We are already here because of mach64= so its redundant.
3835 */
3836 else if (MACH_IS_ATARI
3837 && (!strncmp(this_opt, "Mach64:", 7))) {
3838 static unsigned char m64_num;
3839 static char mach64_str[80];
3840 strlcpy(mach64_str, this_opt + 7, sizeof(mach64_str));
3841 if (!store_video_par(mach64_str, m64_num)) {
3842 m64_num++;
3843 mach64_count = m64_num;
3844 }
3845 }
3846 #endif
3847 else
3848 mode = this_opt;
3849 }
3850 return 0;
3851 }
3852 #endif /* MODULE */
3853
3854 static int __devinit atyfb_init(void)
3855 {
3856 #ifndef MODULE
3857 char *option = NULL;
3858
3859 if (fb_get_options("atyfb", &option))
3860 return -ENODEV;
3861 atyfb_setup(option);
3862 #endif
3863
3864 #ifdef CONFIG_PCI
3865 pci_register_driver(&atyfb_driver);
3866 #endif
3867 #ifdef CONFIG_ATARI
3868 atyfb_atari_probe();
3869 #endif
3870 return 0;
3871 }
3872
3873 static void __exit atyfb_exit(void)
3874 {
3875 #ifdef CONFIG_PCI
3876 pci_unregister_driver(&atyfb_driver);
3877 #endif
3878 }
3879
3880 module_init(atyfb_init);
3881 module_exit(atyfb_exit);
3882
3883 MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards");
3884 MODULE_LICENSE("GPL");
3885 module_param(noaccel, bool, 0);
3886 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
3887 module_param(vram, int, 0);
3888 MODULE_PARM_DESC(vram, "int: override size of video ram");
3889 module_param(pll, int, 0);
3890 MODULE_PARM_DESC(pll, "int: override video clock");
3891 module_param(mclk, int, 0);
3892 MODULE_PARM_DESC(mclk, "int: override memory clock");
3893 module_param(xclk, int, 0);
3894 MODULE_PARM_DESC(xclk, "int: override accelerated engine clock");
3895 module_param(comp_sync, int, 0);
3896 MODULE_PARM_DESC(comp_sync,
3897 "Set composite sync signal to low (0) or high (1)");
3898 module_param(mode, charp, 0);
3899 MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
3900 #ifdef CONFIG_MTRR
3901 module_param(nomtrr, bool, 0);
3902 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
3903 #endif
Linus' kernel tree