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[media] cx23885: add definitions for HVR1500 to support audio
[linux-2.6.git] / drivers / media / video / cx23885 / cx23885-cards.c
blob75d77c2db5c96beb499a22d24e84cd4c6c470307
1 /*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <linux/delay.h>
26 #include <media/cx25840.h>
27 #include <linux/firmware.h>
28 #include <misc/altera.h>
29
30 #include "cx23885.h"
31 #include "tuner-xc2028.h"
32 #include "netup-eeprom.h"
33 #include "netup-init.h"
34 #include "altera-ci.h"
35 #include "xc4000.h"
36 #include "xc5000.h"
37 #include "cx23888-ir.h"
38
39 static unsigned int netup_card_rev = 1;
40 module_param(netup_card_rev, int, 0644);
41 MODULE_PARM_DESC(netup_card_rev,
42 "NetUP Dual DVB-T/C CI card revision");
43 static unsigned int enable_885_ir;
44 module_param(enable_885_ir, int, 0644);
45 MODULE_PARM_DESC(enable_885_ir,
46 "Enable integrated IR controller for supported\n"
47 "\t\t CX2388[57] boards that are wired for it:\n"
48 "\t\t\tHVR-1250 (reported safe)\n"
49 "\t\t\tTeVii S470 (reported unsafe)\n"
50 "\t\t This can cause an interrupt storm with some cards.\n"
51 "\t\t Default: 0 [Disabled]");
52
53 /* ------------------------------------------------------------------ */
54 /* board config info */
55
56 struct cx23885_board cx23885_boards[] = {
57 [CX23885_BOARD_UNKNOWN] = {
58 .name = "UNKNOWN/GENERIC",
59 /* Ensure safe default for unknown boards */
60 .clk_freq = 0,
61 .input = {{
62 .type = CX23885_VMUX_COMPOSITE1,
63 .vmux = 0,
64 }, {
65 .type = CX23885_VMUX_COMPOSITE2,
66 .vmux = 1,
67 }, {
68 .type = CX23885_VMUX_COMPOSITE3,
69 .vmux = 2,
70 }, {
71 .type = CX23885_VMUX_COMPOSITE4,
72 .vmux = 3,
73 } },
74 },
75 [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
76 .name = "Hauppauge WinTV-HVR1800lp",
77 .portc = CX23885_MPEG_DVB,
78 .input = {{
79 .type = CX23885_VMUX_TELEVISION,
80 .vmux = 0,
81 .gpio0 = 0xff00,
82 }, {
83 .type = CX23885_VMUX_DEBUG,
84 .vmux = 0,
85 .gpio0 = 0xff01,
86 }, {
87 .type = CX23885_VMUX_COMPOSITE1,
88 .vmux = 1,
89 .gpio0 = 0xff02,
90 }, {
91 .type = CX23885_VMUX_SVIDEO,
92 .vmux = 2,
93 .gpio0 = 0xff02,
94 } },
95 },
96 [CX23885_BOARD_HAUPPAUGE_HVR1800] = {
97 .name = "Hauppauge WinTV-HVR1800",
98 .porta = CX23885_ANALOG_VIDEO,
99 .portb = CX23885_MPEG_ENCODER,
100 .portc = CX23885_MPEG_DVB,
101 .tuner_type = TUNER_PHILIPS_TDA8290,
102 .tuner_addr = 0x42, /* 0x84 >> 1 */
103 .tuner_bus = 1,
104 .input = {{
105 .type = CX23885_VMUX_TELEVISION,
106 .vmux = CX25840_VIN7_CH3 |
107 CX25840_VIN5_CH2 |
108 CX25840_VIN2_CH1,
109 .gpio0 = 0,
110 }, {
111 .type = CX23885_VMUX_COMPOSITE1,
112 .vmux = CX25840_VIN7_CH3 |
113 CX25840_VIN4_CH2 |
114 CX25840_VIN6_CH1,
115 .gpio0 = 0,
116 }, {
117 .type = CX23885_VMUX_SVIDEO,
118 .vmux = CX25840_VIN7_CH3 |
119 CX25840_VIN4_CH2 |
120 CX25840_VIN8_CH1 |
121 CX25840_SVIDEO_ON,
122 .gpio0 = 0,
123 } },
124 },
125 [CX23885_BOARD_HAUPPAUGE_HVR1250] = {
126 .name = "Hauppauge WinTV-HVR1250",
127 .portc = CX23885_MPEG_DVB,
128 .input = {{
129 .type = CX23885_VMUX_TELEVISION,
130 .vmux = 0,
131 .gpio0 = 0xff00,
132 }, {
133 .type = CX23885_VMUX_DEBUG,
134 .vmux = 0,
135 .gpio0 = 0xff01,
136 }, {
137 .type = CX23885_VMUX_COMPOSITE1,
138 .vmux = 1,
139 .gpio0 = 0xff02,
140 }, {
141 .type = CX23885_VMUX_SVIDEO,
142 .vmux = 2,
143 .gpio0 = 0xff02,
144 } },
145 },
146 [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
147 .name = "DViCO FusionHDTV5 Express",
148 .portb = CX23885_MPEG_DVB,
149 },
150 [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
151 .name = "Hauppauge WinTV-HVR1500Q",
152 .portc = CX23885_MPEG_DVB,
153 },
154 [CX23885_BOARD_HAUPPAUGE_HVR1500] = {
155 .name = "Hauppauge WinTV-HVR1500",
156 .porta = CX23885_ANALOG_VIDEO,
157 .portc = CX23885_MPEG_DVB,
158 .tuner_type = TUNER_XC2028,
159 .tuner_addr = 0x61, /* 0xc2 >> 1 */
160 .input = {{
161 .type = CX23885_VMUX_TELEVISION,
162 .vmux = CX25840_VIN7_CH3 |
163 CX25840_VIN5_CH2 |
164 CX25840_VIN2_CH1,
165 .gpio0 = 0,
166 }, {
167 .type = CX23885_VMUX_COMPOSITE1,
168 .vmux = CX25840_VIN7_CH3 |
169 CX25840_VIN4_CH2 |
170 CX25840_VIN6_CH1,
171 .gpio0 = 0,
172 }, {
173 .type = CX23885_VMUX_SVIDEO,
174 .vmux = CX25840_VIN7_CH3 |
175 CX25840_VIN4_CH2 |
176 CX25840_VIN8_CH1 |
177 CX25840_SVIDEO_ON,
178 .gpio0 = 0,
179 } },
180 },
181 [CX23885_BOARD_HAUPPAUGE_HVR1200] = {
182 .name = "Hauppauge WinTV-HVR1200",
183 .portc = CX23885_MPEG_DVB,
184 },
185 [CX23885_BOARD_HAUPPAUGE_HVR1700] = {
186 .name = "Hauppauge WinTV-HVR1700",
187 .portc = CX23885_MPEG_DVB,
188 },
189 [CX23885_BOARD_HAUPPAUGE_HVR1400] = {
190 .name = "Hauppauge WinTV-HVR1400",
191 .portc = CX23885_MPEG_DVB,
192 },
193 [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
194 .name = "DViCO FusionHDTV7 Dual Express",
195 .portb = CX23885_MPEG_DVB,
196 .portc = CX23885_MPEG_DVB,
197 },
198 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
199 .name = "DViCO FusionHDTV DVB-T Dual Express",
200 .portb = CX23885_MPEG_DVB,
201 .portc = CX23885_MPEG_DVB,
202 },
203 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
204 .name = "Leadtek Winfast PxDVR3200 H",
205 .portc = CX23885_MPEG_DVB,
206 },
207 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000] = {
208 .name = "Leadtek Winfast PxDVR3200 H XC4000",
209 .porta = CX23885_ANALOG_VIDEO,
210 .portc = CX23885_MPEG_DVB,
211 .tuner_type = TUNER_XC4000,
212 .tuner_addr = 0x61,
213 .radio_type = TUNER_XC4000,
214 .radio_addr = 0x61,
215 .input = {{
216 .type = CX23885_VMUX_TELEVISION,
217 .vmux = CX25840_VIN2_CH1 |
218 CX25840_VIN5_CH2 |
219 CX25840_NONE0_CH3,
220 }, {
221 .type = CX23885_VMUX_COMPOSITE1,
222 .vmux = CX25840_COMPOSITE1,
223 }, {
224 .type = CX23885_VMUX_SVIDEO,
225 .vmux = CX25840_SVIDEO_LUMA3 |
226 CX25840_SVIDEO_CHROMA4,
227 }, {
228 .type = CX23885_VMUX_COMPONENT,
229 .vmux = CX25840_VIN7_CH1 |
230 CX25840_VIN6_CH2 |
231 CX25840_VIN8_CH3 |
232 CX25840_COMPONENT_ON,
233 } },
234 },
235 [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
236 .name = "Compro VideoMate E650F",
237 .portc = CX23885_MPEG_DVB,
238 },
239 [CX23885_BOARD_TBS_6920] = {
240 .name = "TurboSight TBS 6920",
241 .portb = CX23885_MPEG_DVB,
242 },
243 [CX23885_BOARD_TEVII_S470] = {
244 .name = "TeVii S470",
245 .portb = CX23885_MPEG_DVB,
246 },
247 [CX23885_BOARD_DVBWORLD_2005] = {
248 .name = "DVBWorld DVB-S2 2005",
249 .portb = CX23885_MPEG_DVB,
250 },
251 [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
252 .ci_type = 1,
253 .name = "NetUP Dual DVB-S2 CI",
254 .portb = CX23885_MPEG_DVB,
255 .portc = CX23885_MPEG_DVB,
256 },
257 [CX23885_BOARD_HAUPPAUGE_HVR1270] = {
258 .name = "Hauppauge WinTV-HVR1270",
259 .portc = CX23885_MPEG_DVB,
260 },
261 [CX23885_BOARD_HAUPPAUGE_HVR1275] = {
262 .name = "Hauppauge WinTV-HVR1275",
263 .portc = CX23885_MPEG_DVB,
264 },
265 [CX23885_BOARD_HAUPPAUGE_HVR1255] = {
266 .name = "Hauppauge WinTV-HVR1255",
267 .portc = CX23885_MPEG_DVB,
268 },
269 [CX23885_BOARD_HAUPPAUGE_HVR1210] = {
270 .name = "Hauppauge WinTV-HVR1210",
271 .portc = CX23885_MPEG_DVB,
272 },
273 [CX23885_BOARD_MYGICA_X8506] = {
274 .name = "Mygica X8506 DMB-TH",
275 .tuner_type = TUNER_XC5000,
276 .tuner_addr = 0x61,
277 .tuner_bus = 1,
278 .porta = CX23885_ANALOG_VIDEO,
279 .portb = CX23885_MPEG_DVB,
280 .input = {
281 {
282 .type = CX23885_VMUX_TELEVISION,
283 .vmux = CX25840_COMPOSITE2,
284 },
285 {
286 .type = CX23885_VMUX_COMPOSITE1,
287 .vmux = CX25840_COMPOSITE8,
288 },
289 {
290 .type = CX23885_VMUX_SVIDEO,
291 .vmux = CX25840_SVIDEO_LUMA3 |
292 CX25840_SVIDEO_CHROMA4,
293 },
294 {
295 .type = CX23885_VMUX_COMPONENT,
296 .vmux = CX25840_COMPONENT_ON |
297 CX25840_VIN1_CH1 |
298 CX25840_VIN6_CH2 |
299 CX25840_VIN7_CH3,
300 },
301 },
302 },
303 [CX23885_BOARD_MAGICPRO_PROHDTVE2] = {
304 .name = "Magic-Pro ProHDTV Extreme 2",
305 .tuner_type = TUNER_XC5000,
306 .tuner_addr = 0x61,
307 .tuner_bus = 1,
308 .porta = CX23885_ANALOG_VIDEO,
309 .portb = CX23885_MPEG_DVB,
310 .input = {
311 {
312 .type = CX23885_VMUX_TELEVISION,
313 .vmux = CX25840_COMPOSITE2,
314 },
315 {
316 .type = CX23885_VMUX_COMPOSITE1,
317 .vmux = CX25840_COMPOSITE8,
318 },
319 {
320 .type = CX23885_VMUX_SVIDEO,
321 .vmux = CX25840_SVIDEO_LUMA3 |
322 CX25840_SVIDEO_CHROMA4,
323 },
324 {
325 .type = CX23885_VMUX_COMPONENT,
326 .vmux = CX25840_COMPONENT_ON |
327 CX25840_VIN1_CH1 |
328 CX25840_VIN6_CH2 |
329 CX25840_VIN7_CH3,
330 },
331 },
332 },
333 [CX23885_BOARD_HAUPPAUGE_HVR1850] = {
334 .name = "Hauppauge WinTV-HVR1850",
335 .portb = CX23885_MPEG_ENCODER,
336 .portc = CX23885_MPEG_DVB,
337 },
338 [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = {
339 .name = "Compro VideoMate E800",
340 .portc = CX23885_MPEG_DVB,
341 },
342 [CX23885_BOARD_HAUPPAUGE_HVR1290] = {
343 .name = "Hauppauge WinTV-HVR1290",
344 .portc = CX23885_MPEG_DVB,
345 },
346 [CX23885_BOARD_MYGICA_X8558PRO] = {
347 .name = "Mygica X8558 PRO DMB-TH",
348 .portb = CX23885_MPEG_DVB,
349 .portc = CX23885_MPEG_DVB,
350 },
351 [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = {
352 .name = "LEADTEK WinFast PxTV1200",
353 .porta = CX23885_ANALOG_VIDEO,
354 .tuner_type = TUNER_XC2028,
355 .tuner_addr = 0x61,
356 .tuner_bus = 1,
357 .input = {{
358 .type = CX23885_VMUX_TELEVISION,
359 .vmux = CX25840_VIN2_CH1 |
360 CX25840_VIN5_CH2 |
361 CX25840_NONE0_CH3,
362 }, {
363 .type = CX23885_VMUX_COMPOSITE1,
364 .vmux = CX25840_COMPOSITE1,
365 }, {
366 .type = CX23885_VMUX_SVIDEO,
367 .vmux = CX25840_SVIDEO_LUMA3 |
368 CX25840_SVIDEO_CHROMA4,
369 }, {
370 .type = CX23885_VMUX_COMPONENT,
371 .vmux = CX25840_VIN7_CH1 |
372 CX25840_VIN6_CH2 |
373 CX25840_VIN8_CH3 |
374 CX25840_COMPONENT_ON,
375 } },
376 },
377 [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = {
378 .name = "GoTView X5 3D Hybrid",
379 .tuner_type = TUNER_XC5000,
380 .tuner_addr = 0x64,
381 .tuner_bus = 1,
382 .porta = CX23885_ANALOG_VIDEO,
383 .portb = CX23885_MPEG_DVB,
384 .input = {{
385 .type = CX23885_VMUX_TELEVISION,
386 .vmux = CX25840_VIN2_CH1 |
387 CX25840_VIN5_CH2,
388 .gpio0 = 0x02,
389 }, {
390 .type = CX23885_VMUX_COMPOSITE1,
391 .vmux = CX23885_VMUX_COMPOSITE1,
392 }, {
393 .type = CX23885_VMUX_SVIDEO,
394 .vmux = CX25840_SVIDEO_LUMA3 |
395 CX25840_SVIDEO_CHROMA4,
396 } },
397 },
398 [CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = {
399 .ci_type = 2,
400 .name = "NetUP Dual DVB-T/C-CI RF",
401 .porta = CX23885_ANALOG_VIDEO,
402 .portb = CX23885_MPEG_DVB,
403 .portc = CX23885_MPEG_DVB,
404 .num_fds_portb = 2,
405 .num_fds_portc = 2,
406 .tuner_type = TUNER_XC5000,
407 .tuner_addr = 0x64,
408 .input = { {
409 .type = CX23885_VMUX_TELEVISION,
410 .vmux = CX25840_COMPOSITE1,
411 } },
412 },
413 };
414 const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
415
416 /* ------------------------------------------------------------------ */
417 /* PCI subsystem IDs */
418
419 struct cx23885_subid cx23885_subids[] = {
420 {
421 .subvendor = 0x0070,
422 .subdevice = 0x3400,
423 .card = CX23885_BOARD_UNKNOWN,
424 }, {
425 .subvendor = 0x0070,
426 .subdevice = 0x7600,
427 .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
428 }, {
429 .subvendor = 0x0070,
430 .subdevice = 0x7800,
431 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
432 }, {
433 .subvendor = 0x0070,
434 .subdevice = 0x7801,
435 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
436 }, {
437 .subvendor = 0x0070,
438 .subdevice = 0x7809,
439 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
440 }, {
441 .subvendor = 0x0070,
442 .subdevice = 0x7911,
443 .card = CX23885_BOARD_HAUPPAUGE_HVR1250,
444 }, {
445 .subvendor = 0x18ac,
446 .subdevice = 0xd500,
447 .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
448 }, {
449 .subvendor = 0x0070,
450 .subdevice = 0x7790,
451 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
452 }, {
453 .subvendor = 0x0070,
454 .subdevice = 0x7797,
455 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
456 }, {
457 .subvendor = 0x0070,
458 .subdevice = 0x7710,
459 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
460 }, {
461 .subvendor = 0x0070,
462 .subdevice = 0x7717,
463 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
464 }, {
465 .subvendor = 0x0070,
466 .subdevice = 0x71d1,
467 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
468 }, {
469 .subvendor = 0x0070,
470 .subdevice = 0x71d3,
471 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
472 }, {
473 .subvendor = 0x0070,
474 .subdevice = 0x8101,
475 .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
476 }, {
477 .subvendor = 0x0070,
478 .subdevice = 0x8010,
479 .card = CX23885_BOARD_HAUPPAUGE_HVR1400,
480 }, {
481 .subvendor = 0x18ac,
482 .subdevice = 0xd618,
483 .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
484 }, {
485 .subvendor = 0x18ac,
486 .subdevice = 0xdb78,
487 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
488 }, {
489 .subvendor = 0x107d,
490 .subdevice = 0x6681,
491 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
492 }, {
493 .subvendor = 0x107d,
494 .subdevice = 0x6f39,
495 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000,
496 }, {
497 .subvendor = 0x185b,
498 .subdevice = 0xe800,
499 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
500 }, {
501 .subvendor = 0x6920,
502 .subdevice = 0x8888,
503 .card = CX23885_BOARD_TBS_6920,
504 }, {
505 .subvendor = 0xd470,
506 .subdevice = 0x9022,
507 .card = CX23885_BOARD_TEVII_S470,
508 }, {
509 .subvendor = 0x0001,
510 .subdevice = 0x2005,
511 .card = CX23885_BOARD_DVBWORLD_2005,
512 }, {
513 .subvendor = 0x1b55,
514 .subdevice = 0x2a2c,
515 .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
516 }, {
517 .subvendor = 0x0070,
518 .subdevice = 0x2211,
519 .card = CX23885_BOARD_HAUPPAUGE_HVR1270,
520 }, {
521 .subvendor = 0x0070,
522 .subdevice = 0x2215,
523 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
524 }, {
525 .subvendor = 0x0070,
526 .subdevice = 0x221d,
527 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
528 }, {
529 .subvendor = 0x0070,
530 .subdevice = 0x2251,
531 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
532 }, {
533 .subvendor = 0x0070,
534 .subdevice = 0x2259,
535 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
536 }, {
537 .subvendor = 0x0070,
538 .subdevice = 0x2291,
539 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
540 }, {
541 .subvendor = 0x0070,
542 .subdevice = 0x2295,
543 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
544 }, {
545 .subvendor = 0x0070,
546 .subdevice = 0x2299,
547 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
548 }, {
549 .subvendor = 0x0070,
550 .subdevice = 0x229d,
551 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
552 }, {
553 .subvendor = 0x0070,
554 .subdevice = 0x22f0,
555 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
556 }, {
557 .subvendor = 0x0070,
558 .subdevice = 0x22f1,
559 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
560 }, {
561 .subvendor = 0x0070,
562 .subdevice = 0x22f2,
563 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
564 }, {
565 .subvendor = 0x0070,
566 .subdevice = 0x22f3,
567 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
568 }, {
569 .subvendor = 0x0070,
570 .subdevice = 0x22f4,
571 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
572 }, {
573 .subvendor = 0x0070,
574 .subdevice = 0x22f5,
575 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
576 }, {
577 .subvendor = 0x14f1,
578 .subdevice = 0x8651,
579 .card = CX23885_BOARD_MYGICA_X8506,
580 }, {
581 .subvendor = 0x14f1,
582 .subdevice = 0x8657,
583 .card = CX23885_BOARD_MAGICPRO_PROHDTVE2,
584 }, {
585 .subvendor = 0x0070,
586 .subdevice = 0x8541,
587 .card = CX23885_BOARD_HAUPPAUGE_HVR1850,
588 }, {
589 .subvendor = 0x1858,
590 .subdevice = 0xe800,
591 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800,
592 }, {
593 .subvendor = 0x0070,
594 .subdevice = 0x8551,
595 .card = CX23885_BOARD_HAUPPAUGE_HVR1290,
596 }, {
597 .subvendor = 0x14f1,
598 .subdevice = 0x8578,
599 .card = CX23885_BOARD_MYGICA_X8558PRO,
600 }, {
601 .subvendor = 0x107d,
602 .subdevice = 0x6f22,
603 .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200,
604 }, {
605 .subvendor = 0x5654,
606 .subdevice = 0x2390,
607 .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID,
608 }, {
609 .subvendor = 0x1b55,
610 .subdevice = 0xe2e4,
611 .card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF,
612 },
613 };
614 const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
615
616 void cx23885_card_list(struct cx23885_dev *dev)
617 {
618 int i;
619
620 if (0 == dev->pci->subsystem_vendor &&
621 0 == dev->pci->subsystem_device) {
622 printk(KERN_INFO
623 "%s: Board has no valid PCIe Subsystem ID and can't\n"
624 "%s: be autodetected. Pass card=<n> insmod option\n"
625 "%s: to workaround that. Redirect complaints to the\n"
626 "%s: vendor of the TV card. Best regards,\n"
627 "%s: -- tux\n",
628 dev->name, dev->name, dev->name, dev->name, dev->name);
629 } else {
630 printk(KERN_INFO
631 "%s: Your board isn't known (yet) to the driver.\n"
632 "%s: Try to pick one of the existing card configs via\n"
633 "%s: card=<n> insmod option. Updating to the latest\n"
634 "%s: version might help as well.\n",
635 dev->name, dev->name, dev->name, dev->name);
636 }
637 printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n",
638 dev->name);
639 for (i = 0; i < cx23885_bcount; i++)
640 printk(KERN_INFO "%s: card=%d -> %s\n",
641 dev->name, i, cx23885_boards[i].name);
642 }
643
644 static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
645 {
646 struct tveeprom tv;
647
648 tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv,
649 eeprom_data);
650
651 /* Make sure we support the board model */
652 switch (tv.model) {
653 case 22001:
654 /* WinTV-HVR1270 (PCIe, Retail, half height)
655 * ATSC/QAM and basic analog, IR Blast */
656 case 22009:
657 /* WinTV-HVR1210 (PCIe, Retail, half height)
658 * DVB-T and basic analog, IR Blast */
659 case 22011:
660 /* WinTV-HVR1270 (PCIe, Retail, half height)
661 * ATSC/QAM and basic analog, IR Recv */
662 case 22019:
663 /* WinTV-HVR1210 (PCIe, Retail, half height)
664 * DVB-T and basic analog, IR Recv */
665 case 22021:
666 /* WinTV-HVR1275 (PCIe, Retail, half height)
667 * ATSC/QAM and basic analog, IR Recv */
668 case 22029:
669 /* WinTV-HVR1210 (PCIe, Retail, half height)
670 * DVB-T and basic analog, IR Recv */
671 case 22101:
672 /* WinTV-HVR1270 (PCIe, Retail, full height)
673 * ATSC/QAM and basic analog, IR Blast */
674 case 22109:
675 /* WinTV-HVR1210 (PCIe, Retail, full height)
676 * DVB-T and basic analog, IR Blast */
677 case 22111:
678 /* WinTV-HVR1270 (PCIe, Retail, full height)
679 * ATSC/QAM and basic analog, IR Recv */
680 case 22119:
681 /* WinTV-HVR1210 (PCIe, Retail, full height)
682 * DVB-T and basic analog, IR Recv */
683 case 22121:
684 /* WinTV-HVR1275 (PCIe, Retail, full height)
685 * ATSC/QAM and basic analog, IR Recv */
686 case 22129:
687 /* WinTV-HVR1210 (PCIe, Retail, full height)
688 * DVB-T and basic analog, IR Recv */
689 case 71009:
690 /* WinTV-HVR1200 (PCIe, Retail, full height)
691 * DVB-T and basic analog */
692 case 71359:
693 /* WinTV-HVR1200 (PCIe, OEM, half height)
694 * DVB-T and basic analog */
695 case 71439:
696 /* WinTV-HVR1200 (PCIe, OEM, half height)
697 * DVB-T and basic analog */
698 case 71449:
699 /* WinTV-HVR1200 (PCIe, OEM, full height)
700 * DVB-T and basic analog */
701 case 71939:
702 /* WinTV-HVR1200 (PCIe, OEM, half height)
703 * DVB-T and basic analog */
704 case 71949:
705 /* WinTV-HVR1200 (PCIe, OEM, full height)
706 * DVB-T and basic analog */
707 case 71959:
708 /* WinTV-HVR1200 (PCIe, OEM, full height)
709 * DVB-T and basic analog */
710 case 71979:
711 /* WinTV-HVR1200 (PCIe, OEM, half height)
712 * DVB-T and basic analog */
713 case 71999:
714 /* WinTV-HVR1200 (PCIe, OEM, full height)
715 * DVB-T and basic analog */
716 case 76601:
717 /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual
718 channel ATSC and MPEG2 HW Encoder */
719 case 77001:
720 /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC
721 and Basic analog */
722 case 77011:
723 /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC
724 and Basic analog */
725 case 77041:
726 /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM
727 and Basic analog */
728 case 77051:
729 /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM
730 and Basic analog */
731 case 78011:
732 /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM,
733 Dual channel ATSC and MPEG2 HW Encoder */
734 case 78501:
735 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
736 Dual channel ATSC and MPEG2 HW Encoder */
737 case 78521:
738 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
739 Dual channel ATSC and MPEG2 HW Encoder */
740 case 78531:
741 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM,
742 Dual channel ATSC and MPEG2 HW Encoder */
743 case 78631:
744 /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM,
745 Dual channel ATSC and MPEG2 HW Encoder */
746 case 79001:
747 /* WinTV-HVR1250 (PCIe, Retail, IR, full height,
748 ATSC and Basic analog */
749 case 79101:
750 /* WinTV-HVR1250 (PCIe, Retail, IR, half height,
751 ATSC and Basic analog */
752 case 79501:
753 /* WinTV-HVR1250 (PCIe, No IR, half height,
754 ATSC [at least] and Basic analog) */
755 case 79561:
756 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
757 ATSC and Basic analog */
758 case 79571:
759 /* WinTV-HVR1250 (PCIe, OEM, No IR, full height,
760 ATSC and Basic analog */
761 case 79671:
762 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
763 ATSC and Basic analog */
764 case 80019:
765 /* WinTV-HVR1400 (Express Card, Retail, IR,
766 * DVB-T and Basic analog */
767 case 81509:
768 /* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
769 * DVB-T and MPEG2 HW Encoder */
770 case 81519:
771 /* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
772 * DVB-T and MPEG2 HW Encoder */
773 break;
774 case 85021:
775 /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM,
776 Dual channel ATSC and MPEG2 HW Encoder */
777 break;
778 case 85721:
779 /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR,
780 Dual channel ATSC and Basic analog */
781 break;
782 default:
783 printk(KERN_WARNING "%s: warning: "
784 "unknown hauppauge model #%d\n",
785 dev->name, tv.model);
786 break;
787 }
788
789 printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n",
790 dev->name, tv.model);
791 }
792
793 int cx23885_tuner_callback(void *priv, int component, int command, int arg)
794 {
795 struct cx23885_tsport *port = priv;
796 struct cx23885_dev *dev = port->dev;
797 u32 bitmask = 0;
798
799 if (command == XC2028_RESET_CLK)
800 return 0;
801
802 if (command != 0) {
803 printk(KERN_ERR "%s(): Unknown command 0x%x.\n",
804 __func__, command);
805 return -EINVAL;
806 }
807
808 switch (dev->board) {
809 case CX23885_BOARD_HAUPPAUGE_HVR1400:
810 case CX23885_BOARD_HAUPPAUGE_HVR1500:
811 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
812 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
813 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
814 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
815 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
816 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
817 /* Tuner Reset Command */
818 bitmask = 0x04;
819 break;
820 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
821 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
822 /* Two identical tuners on two different i2c buses,
823 * we need to reset the correct gpio. */
824 if (port->nr == 1)
825 bitmask = 0x01;
826 else if (port->nr == 2)
827 bitmask = 0x04;
828 break;
829 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
830 /* Tuner Reset Command */
831 bitmask = 0x02;
832 break;
833 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
834 altera_ci_tuner_reset(dev, port->nr);
835 break;
836 }
837
838 if (bitmask) {
839 /* Drive the tuner into reset and back out */
840 cx_clear(GP0_IO, bitmask);
841 mdelay(200);
842 cx_set(GP0_IO, bitmask);
843 }
844
845 return 0;
846 }
847
848 void cx23885_gpio_setup(struct cx23885_dev *dev)
849 {
850 switch (dev->board) {
851 case CX23885_BOARD_HAUPPAUGE_HVR1250:
852 /* GPIO-0 cx24227 demodulator reset */
853 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
854 break;
855 case CX23885_BOARD_HAUPPAUGE_HVR1500:
856 /* GPIO-0 cx24227 demodulator */
857 /* GPIO-2 xc3028 tuner */
858
859 /* Put the parts into reset */
860 cx_set(GP0_IO, 0x00050000);
861 cx_clear(GP0_IO, 0x00000005);
862 msleep(5);
863
864 /* Bring the parts out of reset */
865 cx_set(GP0_IO, 0x00050005);
866 break;
867 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
868 /* GPIO-0 cx24227 demodulator reset */
869 /* GPIO-2 xc5000 tuner reset */
870 cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
871 break;
872 case CX23885_BOARD_HAUPPAUGE_HVR1800:
873 /* GPIO-0 656_CLK */
874 /* GPIO-1 656_D0 */
875 /* GPIO-2 8295A Reset */
876 /* GPIO-3-10 cx23417 data0-7 */
877 /* GPIO-11-14 cx23417 addr0-3 */
878 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
879 /* GPIO-19 IR_RX */
880
881 /* CX23417 GPIO's */
882 /* EIO15 Zilog Reset */
883 /* EIO14 S5H1409/CX24227 Reset */
884 mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1);
885
886 /* Put the demod into reset and protect the eeprom */
887 mc417_gpio_clear(dev, GPIO_15 | GPIO_14);
888 mdelay(100);
889
890 /* Bring the demod and blaster out of reset */
891 mc417_gpio_set(dev, GPIO_15 | GPIO_14);
892 mdelay(100);
893
894 /* Force the TDA8295A into reset and back */
895 cx23885_gpio_enable(dev, GPIO_2, 1);
896 cx23885_gpio_set(dev, GPIO_2);
897 mdelay(20);
898 cx23885_gpio_clear(dev, GPIO_2);
899 mdelay(20);
900 cx23885_gpio_set(dev, GPIO_2);
901 mdelay(20);
902 break;
903 case CX23885_BOARD_HAUPPAUGE_HVR1200:
904 /* GPIO-0 tda10048 demodulator reset */
905 /* GPIO-2 tda18271 tuner reset */
906
907 /* Put the parts into reset and back */
908 cx_set(GP0_IO, 0x00050000);
909 mdelay(20);
910 cx_clear(GP0_IO, 0x00000005);
911 mdelay(20);
912 cx_set(GP0_IO, 0x00050005);
913 break;
914 case CX23885_BOARD_HAUPPAUGE_HVR1700:
915 /* GPIO-0 TDA10048 demodulator reset */
916 /* GPIO-2 TDA8295A Reset */
917 /* GPIO-3-10 cx23417 data0-7 */
918 /* GPIO-11-14 cx23417 addr0-3 */
919 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
920
921 /* The following GPIO's are on the interna AVCore (cx25840) */
922 /* GPIO-19 IR_RX */
923 /* GPIO-20 IR_TX 416/DVBT Select */
924 /* GPIO-21 IIS DAT */
925 /* GPIO-22 IIS WCLK */
926 /* GPIO-23 IIS BCLK */
927
928 /* Put the parts into reset and back */
929 cx_set(GP0_IO, 0x00050000);
930 mdelay(20);
931 cx_clear(GP0_IO, 0x00000005);
932 mdelay(20);
933 cx_set(GP0_IO, 0x00050005);
934 break;
935 case CX23885_BOARD_HAUPPAUGE_HVR1400:
936 /* GPIO-0 Dibcom7000p demodulator reset */
937 /* GPIO-2 xc3028L tuner reset */
938 /* GPIO-13 LED */
939
940 /* Put the parts into reset and back */
941 cx_set(GP0_IO, 0x00050000);
942 mdelay(20);
943 cx_clear(GP0_IO, 0x00000005);
944 mdelay(20);
945 cx_set(GP0_IO, 0x00050005);
946 break;
947 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
948 /* GPIO-0 xc5000 tuner reset i2c bus 0 */
949 /* GPIO-1 s5h1409 demod reset i2c bus 0 */
950 /* GPIO-2 xc5000 tuner reset i2c bus 1 */
951 /* GPIO-3 s5h1409 demod reset i2c bus 0 */
952
953 /* Put the parts into reset and back */
954 cx_set(GP0_IO, 0x000f0000);
955 mdelay(20);
956 cx_clear(GP0_IO, 0x0000000f);
957 mdelay(20);
958 cx_set(GP0_IO, 0x000f000f);
959 break;
960 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
961 /* GPIO-0 portb xc3028 reset */
962 /* GPIO-1 portb zl10353 reset */
963 /* GPIO-2 portc xc3028 reset */
964 /* GPIO-3 portc zl10353 reset */
965
966 /* Put the parts into reset and back */
967 cx_set(GP0_IO, 0x000f0000);
968 mdelay(20);
969 cx_clear(GP0_IO, 0x0000000f);
970 mdelay(20);
971 cx_set(GP0_IO, 0x000f000f);
972 break;
973 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
974 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
975 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
976 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
977 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
978 /* GPIO-2 xc3028 tuner reset */
979
980 /* The following GPIO's are on the internal AVCore (cx25840) */
981 /* GPIO-? zl10353 demod reset */
982
983 /* Put the parts into reset and back */
984 cx_set(GP0_IO, 0x00040000);
985 mdelay(20);
986 cx_clear(GP0_IO, 0x00000004);
987 mdelay(20);
988 cx_set(GP0_IO, 0x00040004);
989 break;
990 case CX23885_BOARD_TBS_6920:
991 cx_write(MC417_CTL, 0x00000036);
992 cx_write(MC417_OEN, 0x00001000);
993 cx_set(MC417_RWD, 0x00000002);
994 mdelay(200);
995 cx_clear(MC417_RWD, 0x00000800);
996 mdelay(200);
997 cx_set(MC417_RWD, 0x00000800);
998 mdelay(200);
999 break;
1000 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1001 /* GPIO-0 INTA from CiMax1
1002 GPIO-1 INTB from CiMax2
1003 GPIO-2 reset chips
1004 GPIO-3 to GPIO-10 data/addr for CA
1005 GPIO-11 ~CS0 to CiMax1
1006 GPIO-12 ~CS1 to CiMax2
1007 GPIO-13 ADL0 load LSB addr
1008 GPIO-14 ADL1 load MSB addr
1009 GPIO-15 ~RDY from CiMax
1010 GPIO-17 ~RD to CiMax
1011 GPIO-18 ~WR to CiMax
1012 */
1013 cx_set(GP0_IO, 0x00040000); /* GPIO as out */
1014 /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */
1015 cx_clear(GP0_IO, 0x00030004);
1016 mdelay(100);/* reset delay */
1017 cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
1018 cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */
1019 /* GPIO-15 IN as ~ACK, rest as OUT */
1020 cx_write(MC417_OEN, 0x00001000);
1021 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
1022 cx_write(MC417_RWD, 0x0000c300);
1023 /* enable irq */
1024 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
1025 break;
1026 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1027 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1028 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1029 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1030 /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */
1031 /* GPIO-6 I2C Gate which can isolate the demod from the bus */
1032 /* GPIO-9 Demod reset */
1033
1034 /* Put the parts into reset and back */
1035 cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1);
1036 cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5);
1037 cx23885_gpio_clear(dev, GPIO_9);
1038 mdelay(20);
1039 cx23885_gpio_set(dev, GPIO_9);
1040 break;
1041 case CX23885_BOARD_MYGICA_X8506:
1042 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1043 /* GPIO-0 (0)Analog / (1)Digital TV */
1044 /* GPIO-1 reset XC5000 */
1045 /* GPIO-2 reset LGS8GL5 / LGS8G75 */
1046 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1);
1047 cx23885_gpio_clear(dev, GPIO_1 | GPIO_2);
1048 mdelay(100);
1049 cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2);
1050 mdelay(100);
1051 break;
1052 case CX23885_BOARD_MYGICA_X8558PRO:
1053 /* GPIO-0 reset first ATBM8830 */
1054 /* GPIO-1 reset second ATBM8830 */
1055 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
1056 cx23885_gpio_clear(dev, GPIO_0 | GPIO_1);
1057 mdelay(100);
1058 cx23885_gpio_set(dev, GPIO_0 | GPIO_1);
1059 mdelay(100);
1060 break;
1061 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1062 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1063 /* GPIO-0 656_CLK */
1064 /* GPIO-1 656_D0 */
1065 /* GPIO-2 Wake# */
1066 /* GPIO-3-10 cx23417 data0-7 */
1067 /* GPIO-11-14 cx23417 addr0-3 */
1068 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1069 /* GPIO-19 IR_RX */
1070 /* GPIO-20 C_IR_TX */
1071 /* GPIO-21 I2S DAT */
1072 /* GPIO-22 I2S WCLK */
1073 /* GPIO-23 I2S BCLK */
1074 /* ALT GPIO: EXP GPIO LATCH */
1075
1076 /* CX23417 GPIO's */
1077 /* GPIO-14 S5H1411/CX24228 Reset */
1078 /* GPIO-13 EEPROM write protect */
1079 mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1);
1080
1081 /* Put the demod into reset and protect the eeprom */
1082 mc417_gpio_clear(dev, GPIO_14 | GPIO_13);
1083 mdelay(100);
1084
1085 /* Bring the demod out of reset */
1086 mc417_gpio_set(dev, GPIO_14);
1087 mdelay(100);
1088
1089 /* CX24228 GPIO */
1090 /* Connected to IF / Mux */
1091 break;
1092 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1093 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
1094 break;
1095 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1096 /* GPIO-0 ~INT in
1097 GPIO-1 TMS out
1098 GPIO-2 ~reset chips out
1099 GPIO-3 to GPIO-10 data/addr for CA in/out
1100 GPIO-11 ~CS out
1101 GPIO-12 ADDR out
1102 GPIO-13 ~WR out
1103 GPIO-14 ~RD out
1104 GPIO-15 ~RDY in
1105 GPIO-16 TCK out
1106 GPIO-17 TDO in
1107 GPIO-18 TDI out
1108 */
1109 cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */
1110 /* GPIO-0 as INT, reset & TMS low */
1111 cx_clear(GP0_IO, 0x00010006);
1112 mdelay(100);/* reset delay */
1113 cx_set(GP0_IO, 0x00000004); /* reset high */
1114 cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */
1115 /* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */
1116 cx_write(MC417_OEN, 0x00005000);
1117 /* ~RD, ~WR high; ADDR low; ~CS high */
1118 cx_write(MC417_RWD, 0x00000d00);
1119 /* enable irq */
1120 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
1121 break;
1122 }
1123 }
1124
1125 int cx23885_ir_init(struct cx23885_dev *dev)
1126 {
1127 static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = {
1128 {
1129 .flags = V4L2_SUBDEV_IO_PIN_INPUT,
1130 .pin = CX23885_PIN_IR_RX_GPIO19,
1131 .function = CX23885_PAD_IR_RX,
1132 .value = 0,
1133 .strength = CX25840_PIN_DRIVE_MEDIUM,
1134 }, {
1135 .flags = V4L2_SUBDEV_IO_PIN_OUTPUT,
1136 .pin = CX23885_PIN_IR_TX_GPIO20,
1137 .function = CX23885_PAD_IR_TX,
1138 .value = 0,
1139 .strength = CX25840_PIN_DRIVE_MEDIUM,
1140 }
1141 };
1142 const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg);
1143
1144 static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = {
1145 {
1146 .flags = V4L2_SUBDEV_IO_PIN_INPUT,
1147 .pin = CX23885_PIN_IR_RX_GPIO19,
1148 .function = CX23885_PAD_IR_RX,
1149 .value = 0,
1150 .strength = CX25840_PIN_DRIVE_MEDIUM,
1151 }
1152 };
1153 const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg);
1154
1155 struct v4l2_subdev_ir_parameters params;
1156 int ret = 0;
1157 switch (dev->board) {
1158 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1159 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1160 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1161 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1162 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1163 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1164 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1165 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1166 /* FIXME: Implement me */
1167 break;
1168 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1169 ret = cx23888_ir_probe(dev);
1170 if (ret)
1171 break;
1172 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
1173 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1174 ir_rx_pin_cfg_count, ir_rx_pin_cfg);
1175 break;
1176 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1177 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1178 ret = cx23888_ir_probe(dev);
1179 if (ret)
1180 break;
1181 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
1182 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1183 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
1184 /*
1185 * For these boards we need to invert the Tx output via the
1186 * IR controller to have the LED off while idle
1187 */
1188 v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, &params);
1189 params.enable = false;
1190 params.shutdown = false;
1191 params.invert_level = true;
1192 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
1193 params.shutdown = true;
1194 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
1195 break;
1196 case CX23885_BOARD_TEVII_S470:
1197 if (!enable_885_ir)
1198 break;
1199 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
1200 if (dev->sd_ir == NULL) {
1201 ret = -ENODEV;
1202 break;
1203 }
1204 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1205 ir_rx_pin_cfg_count, ir_rx_pin_cfg);
1206 break;
1207 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1208 if (!enable_885_ir)
1209 break;
1210 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
1211 if (dev->sd_ir == NULL) {
1212 ret = -ENODEV;
1213 break;
1214 }
1215 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1216 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
1217 break;
1218 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1219 request_module("ir-kbd-i2c");
1220 break;
1221 }
1222
1223 return ret;
1224 }
1225
1226 void cx23885_ir_fini(struct cx23885_dev *dev)
1227 {
1228 switch (dev->board) {
1229 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1230 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1231 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1232 cx23885_irq_remove(dev, PCI_MSK_IR);
1233 cx23888_ir_remove(dev);
1234 dev->sd_ir = NULL;
1235 break;
1236 case CX23885_BOARD_TEVII_S470:
1237 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1238 cx23885_irq_remove(dev, PCI_MSK_AV_CORE);
1239 /* sd_ir is a duplicate pointer to the AV Core, just clear it */
1240 dev->sd_ir = NULL;
1241 break;
1242 }
1243 }
1244
1245 int netup_jtag_io(void *device, int tms, int tdi, int read_tdo)
1246 {
1247 int data;
1248 int tdo = 0;
1249 struct cx23885_dev *dev = (struct cx23885_dev *)device;
1250 /*TMS*/
1251 data = ((cx_read(GP0_IO)) & (~0x00000002));
1252 data |= (tms ? 0x00020002 : 0x00020000);
1253 cx_write(GP0_IO, data);
1254
1255 /*TDI*/
1256 data = ((cx_read(MC417_RWD)) & (~0x0000a000));
1257 data |= (tdi ? 0x00008000 : 0);
1258 cx_write(MC417_RWD, data);
1259 if (read_tdo)
1260 tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/
1261
1262 cx_write(MC417_RWD, data | 0x00002000);
1263 udelay(1);
1264 /*TCK*/
1265 cx_write(MC417_RWD, data);
1266
1267 return tdo;
1268 }
1269
1270 void cx23885_ir_pci_int_enable(struct cx23885_dev *dev)
1271 {
1272 switch (dev->board) {
1273 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1274 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1275 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1276 if (dev->sd_ir)
1277 cx23885_irq_add_enable(dev, PCI_MSK_IR);
1278 break;
1279 case CX23885_BOARD_TEVII_S470:
1280 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1281 if (dev->sd_ir)
1282 cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE);
1283 break;
1284 }
1285 }
1286
1287 void cx23885_card_setup(struct cx23885_dev *dev)
1288 {
1289 struct cx23885_tsport *ts1 = &dev->ts1;
1290 struct cx23885_tsport *ts2 = &dev->ts2;
1291
1292 static u8 eeprom[256];
1293
1294 if (dev->i2c_bus[0].i2c_rc == 0) {
1295 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
1296 tveeprom_read(&dev->i2c_bus[0].i2c_client,
1297 eeprom, sizeof(eeprom));
1298 }
1299
1300 switch (dev->board) {
1301 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1302 if (dev->i2c_bus[0].i2c_rc == 0) {
1303 if (eeprom[0x80] != 0x84)
1304 hauppauge_eeprom(dev, eeprom+0xc0);
1305 else
1306 hauppauge_eeprom(dev, eeprom+0x80);
1307 }
1308 break;
1309 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1310 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1311 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1312 if (dev->i2c_bus[0].i2c_rc == 0)
1313 hauppauge_eeprom(dev, eeprom+0x80);
1314 break;
1315 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1316 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1317 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1318 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1319 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1320 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1321 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1322 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1323 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1324 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1325 if (dev->i2c_bus[0].i2c_rc == 0)
1326 hauppauge_eeprom(dev, eeprom+0xc0);
1327 break;
1328 }
1329
1330 switch (dev->board) {
1331 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
1332 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1333 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1334 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1335 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1336 /* break omitted intentionally */
1337 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
1338 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1339 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1340 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1341 break;
1342 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1343 /* Defaults for VID B - Analog encoder */
1344 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
1345 ts1->gen_ctrl_val = 0x10e;
1346 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1347 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1348
1349 /* APB_TSVALERR_POL (active low)*/
1350 ts1->vld_misc_val = 0x2000;
1351 ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
1352
1353 /* Defaults for VID C */
1354 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1355 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1356 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1357 break;
1358 case CX23885_BOARD_TBS_6920:
1359 ts1->gen_ctrl_val = 0x4; /* Parallel */
1360 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1361 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1362 break;
1363 case CX23885_BOARD_TEVII_S470:
1364 case CX23885_BOARD_DVBWORLD_2005:
1365 ts1->gen_ctrl_val = 0x5; /* Parallel */
1366 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1367 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1368 break;
1369 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1370 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1371 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1372 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1373 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1374 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1375 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1376 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1377 break;
1378 case CX23885_BOARD_MYGICA_X8506:
1379 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1380 ts1->gen_ctrl_val = 0x5; /* Parallel */
1381 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1382 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1383 break;
1384 case CX23885_BOARD_MYGICA_X8558PRO:
1385 ts1->gen_ctrl_val = 0x5; /* Parallel */
1386 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1387 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1388 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1389 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1390 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1391 break;
1392 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1393 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1394 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1395 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1396 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1397 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1398 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1399 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1400 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1401 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1402 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1403 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1404 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1405 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1406 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1407 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1408 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1409 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1410 default:
1411 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1412 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1413 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1414 }
1415
1416 /* Certain boards support analog, or require the avcore to be
1417 * loaded, ensure this happens.
1418 */
1419 switch (dev->board) {
1420 case CX23885_BOARD_TEVII_S470:
1421 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1422 /* Currently only enabled for the integrated IR controller */
1423 if (!enable_885_ir)
1424 break;
1425 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1426 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1427 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1428 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1429 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1430 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1431 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1432 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1433 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1434 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1435 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1436 case CX23885_BOARD_MYGICA_X8506:
1437 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1438 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1439 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
1440 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1441 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1442 dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
1443 &dev->i2c_bus[2].i2c_adap,
1444 "cx25840", 0x88 >> 1, NULL);
1445 if (dev->sd_cx25840) {
1446 dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE;
1447 v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
1448 }
1449 break;
1450 }
1451
1452 /* AUX-PLL 27MHz CLK */
1453 switch (dev->board) {
1454 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1455 netup_initialize(dev);
1456 break;
1457 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
1458 int ret;
1459 const struct firmware *fw;
1460 const char *filename = "dvb-netup-altera-01.fw";
1461 char *action = "configure";
1462 static struct netup_card_info cinfo;
1463 struct altera_config netup_config = {
1464 .dev = dev,
1465 .action = action,
1466 .jtag_io = netup_jtag_io,
1467 };
1468
1469 netup_initialize(dev);
1470
1471 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
1472 if (netup_card_rev)
1473 cinfo.rev = netup_card_rev;
1474
1475 switch (cinfo.rev) {
1476 case 0x4:
1477 filename = "dvb-netup-altera-04.fw";
1478 break;
1479 default:
1480 filename = "dvb-netup-altera-01.fw";
1481 break;
1482 }
1483 printk(KERN_INFO "NetUP card rev=0x%x fw_filename=%s\n",
1484 cinfo.rev, filename);
1485
1486 ret = request_firmware(&fw, filename, &dev->pci->dev);
1487 if (ret != 0)
1488 printk(KERN_ERR "did not find the firmware file. (%s) "
1489 "Please see linux/Documentation/dvb/ for more details "
1490 "on firmware-problems.", filename);
1491 else
1492 altera_init(&netup_config, fw);
1493
1494 release_firmware(fw);
1495 break;
1496 }
1497 }
1498 }
1499
1500 /* ------------------------------------------------------------------ */
Linus' kernel tree