2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
38 #include <asm/virtext.h>
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
47 MODULE_AUTHOR("Qumranet");
48 MODULE_LICENSE("GPL");
50 static int __read_mostly bypass_guest_pf
= 1;
51 module_param(bypass_guest_pf
, bool, S_IRUGO
);
53 static int __read_mostly enable_vpid
= 1;
54 module_param_named(vpid
, enable_vpid
, bool, 0444);
56 static int __read_mostly flexpriority_enabled
= 1;
57 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
59 static int __read_mostly enable_ept
= 1;
60 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
62 static int __read_mostly enable_unrestricted_guest
= 1;
63 module_param_named(unrestricted_guest
,
64 enable_unrestricted_guest
, bool, S_IRUGO
);
66 static int __read_mostly emulate_invalid_guest_state
= 0;
67 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
69 static int __read_mostly vmm_exclusive
= 1;
70 module_param(vmm_exclusive
, bool, S_IRUGO
);
72 static int __read_mostly yield_on_hlt
= 1;
73 module_param(yield_on_hlt
, bool, S_IRUGO
);
75 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
76 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
77 #define KVM_GUEST_CR0_MASK \
78 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
79 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
80 (X86_CR0_WP | X86_CR0_NE)
81 #define KVM_VM_CR0_ALWAYS_ON \
82 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
83 #define KVM_CR4_GUEST_OWNED_BITS \
84 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
87 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
88 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
90 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
93 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
94 * ple_gap: upper bound on the amount of time between two successive
95 * executions of PAUSE in a loop. Also indicate if ple enabled.
96 * According to test, this time is usually small than 41 cycles.
97 * ple_window: upper bound on the amount of time a guest is allowed to execute
98 * in a PAUSE loop. Tests indicate that most spinlocks are held for
99 * less than 2^12 cycles
100 * Time is measured based on a counter that runs at the same rate as the TSC,
101 * refer SDM volume 3b section 21.6.13 & 22.1.3.
103 #define KVM_VMX_DEFAULT_PLE_GAP 41
104 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
105 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
106 module_param(ple_gap
, int, S_IRUGO
);
108 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
109 module_param(ple_window
, int, S_IRUGO
);
111 #define NR_AUTOLOAD_MSRS 1
119 struct shared_msr_entry
{
126 struct kvm_vcpu vcpu
;
127 struct list_head local_vcpus_link
;
128 unsigned long host_rsp
;
132 u32 idt_vectoring_info
;
133 struct shared_msr_entry
*guest_msrs
;
137 u64 msr_host_kernel_gs_base
;
138 u64 msr_guest_kernel_gs_base
;
141 struct msr_autoload
{
143 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
144 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
148 u16 fs_sel
, gs_sel
, ldt_sel
;
149 int gs_ldt_reload_needed
;
150 int fs_reload_needed
;
155 struct kvm_save_segment
{
160 } tr
, es
, ds
, fs
, gs
;
163 bool emulation_required
;
165 /* Support for vnmi-less CPUs */
166 int soft_vnmi_blocked
;
168 s64 vnmi_blocked_time
;
174 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
176 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
179 static int init_rmode(struct kvm
*kvm
);
180 static u64
construct_eptp(unsigned long root_hpa
);
181 static void kvm_cpu_vmxon(u64 addr
);
182 static void kvm_cpu_vmxoff(void);
184 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
185 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
186 static DEFINE_PER_CPU(struct list_head
, vcpus_on_cpu
);
187 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
189 static unsigned long *vmx_io_bitmap_a
;
190 static unsigned long *vmx_io_bitmap_b
;
191 static unsigned long *vmx_msr_bitmap_legacy
;
192 static unsigned long *vmx_msr_bitmap_longmode
;
194 static bool cpu_has_load_ia32_efer
;
196 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
197 static DEFINE_SPINLOCK(vmx_vpid_lock
);
199 static struct vmcs_config
{
203 u32 pin_based_exec_ctrl
;
204 u32 cpu_based_exec_ctrl
;
205 u32 cpu_based_2nd_exec_ctrl
;
210 static struct vmx_capability
{
215 #define VMX_SEGMENT_FIELD(seg) \
216 [VCPU_SREG_##seg] = { \
217 .selector = GUEST_##seg##_SELECTOR, \
218 .base = GUEST_##seg##_BASE, \
219 .limit = GUEST_##seg##_LIMIT, \
220 .ar_bytes = GUEST_##seg##_AR_BYTES, \
223 static struct kvm_vmx_segment_field
{
228 } kvm_vmx_segment_fields
[] = {
229 VMX_SEGMENT_FIELD(CS
),
230 VMX_SEGMENT_FIELD(DS
),
231 VMX_SEGMENT_FIELD(ES
),
232 VMX_SEGMENT_FIELD(FS
),
233 VMX_SEGMENT_FIELD(GS
),
234 VMX_SEGMENT_FIELD(SS
),
235 VMX_SEGMENT_FIELD(TR
),
236 VMX_SEGMENT_FIELD(LDTR
),
239 static u64 host_efer
;
241 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
244 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
245 * away by decrementing the array size.
247 static const u32 vmx_msr_index
[] = {
249 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
251 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
253 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
255 static inline bool is_page_fault(u32 intr_info
)
257 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
258 INTR_INFO_VALID_MASK
)) ==
259 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
262 static inline bool is_no_device(u32 intr_info
)
264 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
265 INTR_INFO_VALID_MASK
)) ==
266 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
269 static inline bool is_invalid_opcode(u32 intr_info
)
271 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
272 INTR_INFO_VALID_MASK
)) ==
273 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
276 static inline bool is_external_interrupt(u32 intr_info
)
278 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
279 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
282 static inline bool is_machine_check(u32 intr_info
)
284 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
285 INTR_INFO_VALID_MASK
)) ==
286 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
289 static inline bool cpu_has_vmx_msr_bitmap(void)
291 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
294 static inline bool cpu_has_vmx_tpr_shadow(void)
296 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
299 static inline bool vm_need_tpr_shadow(struct kvm
*kvm
)
301 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
304 static inline bool cpu_has_secondary_exec_ctrls(void)
306 return vmcs_config
.cpu_based_exec_ctrl
&
307 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
310 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
312 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
313 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
316 static inline bool cpu_has_vmx_flexpriority(void)
318 return cpu_has_vmx_tpr_shadow() &&
319 cpu_has_vmx_virtualize_apic_accesses();
322 static inline bool cpu_has_vmx_ept_execute_only(void)
324 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
327 static inline bool cpu_has_vmx_eptp_uncacheable(void)
329 return vmx_capability
.ept
& VMX_EPTP_UC_BIT
;
332 static inline bool cpu_has_vmx_eptp_writeback(void)
334 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
337 static inline bool cpu_has_vmx_ept_2m_page(void)
339 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
342 static inline bool cpu_has_vmx_ept_1g_page(void)
344 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
347 static inline bool cpu_has_vmx_ept_4levels(void)
349 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
352 static inline bool cpu_has_vmx_invept_individual_addr(void)
354 return vmx_capability
.ept
& VMX_EPT_EXTENT_INDIVIDUAL_BIT
;
357 static inline bool cpu_has_vmx_invept_context(void)
359 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
362 static inline bool cpu_has_vmx_invept_global(void)
364 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
367 static inline bool cpu_has_vmx_invvpid_single(void)
369 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
372 static inline bool cpu_has_vmx_invvpid_global(void)
374 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
377 static inline bool cpu_has_vmx_ept(void)
379 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
380 SECONDARY_EXEC_ENABLE_EPT
;
383 static inline bool cpu_has_vmx_unrestricted_guest(void)
385 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
386 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
389 static inline bool cpu_has_vmx_ple(void)
391 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
392 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
395 static inline bool vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
397 return flexpriority_enabled
&& irqchip_in_kernel(kvm
);
400 static inline bool cpu_has_vmx_vpid(void)
402 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
403 SECONDARY_EXEC_ENABLE_VPID
;
406 static inline bool cpu_has_vmx_rdtscp(void)
408 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
409 SECONDARY_EXEC_RDTSCP
;
412 static inline bool cpu_has_virtual_nmis(void)
414 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
417 static inline bool cpu_has_vmx_wbinvd_exit(void)
419 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
420 SECONDARY_EXEC_WBINVD_EXITING
;
423 static inline bool report_flexpriority(void)
425 return flexpriority_enabled
;
428 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
432 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
433 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
438 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
444 } operand
= { vpid
, 0, gva
};
446 asm volatile (__ex(ASM_VMX_INVVPID
)
447 /* CF==1 or ZF==1 --> rc = -1 */
449 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
452 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
456 } operand
= {eptp
, gpa
};
458 asm volatile (__ex(ASM_VMX_INVEPT
)
459 /* CF==1 or ZF==1 --> rc = -1 */
460 "; ja 1f ; ud2 ; 1:\n"
461 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
464 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
468 i
= __find_msr_index(vmx
, msr
);
470 return &vmx
->guest_msrs
[i
];
474 static void vmcs_clear(struct vmcs
*vmcs
)
476 u64 phys_addr
= __pa(vmcs
);
479 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
480 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
483 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
487 static void vmcs_load(struct vmcs
*vmcs
)
489 u64 phys_addr
= __pa(vmcs
);
492 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
493 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
496 printk(KERN_ERR
"kvm: vmptrld %p/%llx fail\n",
500 static void __vcpu_clear(void *arg
)
502 struct vcpu_vmx
*vmx
= arg
;
503 int cpu
= raw_smp_processor_id();
505 if (vmx
->vcpu
.cpu
== cpu
)
506 vmcs_clear(vmx
->vmcs
);
507 if (per_cpu(current_vmcs
, cpu
) == vmx
->vmcs
)
508 per_cpu(current_vmcs
, cpu
) = NULL
;
509 list_del(&vmx
->local_vcpus_link
);
514 static void vcpu_clear(struct vcpu_vmx
*vmx
)
516 if (vmx
->vcpu
.cpu
== -1)
518 smp_call_function_single(vmx
->vcpu
.cpu
, __vcpu_clear
, vmx
, 1);
521 static inline void vpid_sync_vcpu_single(struct vcpu_vmx
*vmx
)
526 if (cpu_has_vmx_invvpid_single())
527 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
530 static inline void vpid_sync_vcpu_global(void)
532 if (cpu_has_vmx_invvpid_global())
533 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
536 static inline void vpid_sync_context(struct vcpu_vmx
*vmx
)
538 if (cpu_has_vmx_invvpid_single())
539 vpid_sync_vcpu_single(vmx
);
541 vpid_sync_vcpu_global();
544 static inline void ept_sync_global(void)
546 if (cpu_has_vmx_invept_global())
547 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
550 static inline void ept_sync_context(u64 eptp
)
553 if (cpu_has_vmx_invept_context())
554 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
560 static inline void ept_sync_individual_addr(u64 eptp
, gpa_t gpa
)
563 if (cpu_has_vmx_invept_individual_addr())
564 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR
,
567 ept_sync_context(eptp
);
571 static unsigned long vmcs_readl(unsigned long field
)
573 unsigned long value
= 0;
575 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX
)
576 : "+a"(value
) : "d"(field
) : "cc");
580 static u16
vmcs_read16(unsigned long field
)
582 return vmcs_readl(field
);
585 static u32
vmcs_read32(unsigned long field
)
587 return vmcs_readl(field
);
590 static u64
vmcs_read64(unsigned long field
)
593 return vmcs_readl(field
);
595 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
599 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
601 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
602 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
606 static void vmcs_writel(unsigned long field
, unsigned long value
)
610 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
611 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
613 vmwrite_error(field
, value
);
616 static void vmcs_write16(unsigned long field
, u16 value
)
618 vmcs_writel(field
, value
);
621 static void vmcs_write32(unsigned long field
, u32 value
)
623 vmcs_writel(field
, value
);
626 static void vmcs_write64(unsigned long field
, u64 value
)
628 vmcs_writel(field
, value
);
629 #ifndef CONFIG_X86_64
631 vmcs_writel(field
+1, value
>> 32);
635 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
637 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
640 static void vmcs_set_bits(unsigned long field
, u32 mask
)
642 vmcs_writel(field
, vmcs_readl(field
) | mask
);
645 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
649 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
650 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
651 if ((vcpu
->guest_debug
&
652 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
653 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
654 eb
|= 1u << BP_VECTOR
;
655 if (to_vmx(vcpu
)->rmode
.vm86_active
)
658 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
659 if (vcpu
->fpu_active
)
660 eb
&= ~(1u << NM_VECTOR
);
661 vmcs_write32(EXCEPTION_BITMAP
, eb
);
664 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
667 struct msr_autoload
*m
= &vmx
->msr_autoload
;
669 if (msr
== MSR_EFER
&& cpu_has_load_ia32_efer
) {
670 vmcs_clear_bits(VM_ENTRY_CONTROLS
, VM_ENTRY_LOAD_IA32_EFER
);
671 vmcs_clear_bits(VM_EXIT_CONTROLS
, VM_EXIT_LOAD_IA32_EFER
);
675 for (i
= 0; i
< m
->nr
; ++i
)
676 if (m
->guest
[i
].index
== msr
)
682 m
->guest
[i
] = m
->guest
[m
->nr
];
683 m
->host
[i
] = m
->host
[m
->nr
];
684 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
685 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
688 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
689 u64 guest_val
, u64 host_val
)
692 struct msr_autoload
*m
= &vmx
->msr_autoload
;
694 if (msr
== MSR_EFER
&& cpu_has_load_ia32_efer
) {
695 vmcs_write64(GUEST_IA32_EFER
, guest_val
);
696 vmcs_write64(HOST_IA32_EFER
, host_val
);
697 vmcs_set_bits(VM_ENTRY_CONTROLS
, VM_ENTRY_LOAD_IA32_EFER
);
698 vmcs_set_bits(VM_EXIT_CONTROLS
, VM_EXIT_LOAD_IA32_EFER
);
702 for (i
= 0; i
< m
->nr
; ++i
)
703 if (m
->guest
[i
].index
== msr
)
708 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
709 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
712 m
->guest
[i
].index
= msr
;
713 m
->guest
[i
].value
= guest_val
;
714 m
->host
[i
].index
= msr
;
715 m
->host
[i
].value
= host_val
;
718 static void reload_tss(void)
721 * VT restores TR but not its size. Useless.
723 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
724 struct desc_struct
*descs
;
726 descs
= (void *)gdt
->address
;
727 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
731 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
736 guest_efer
= vmx
->vcpu
.arch
.efer
;
739 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
742 ignore_bits
= EFER_NX
| EFER_SCE
;
744 ignore_bits
|= EFER_LMA
| EFER_LME
;
745 /* SCE is meaningful only in long mode on Intel */
746 if (guest_efer
& EFER_LMA
)
747 ignore_bits
&= ~(u64
)EFER_SCE
;
749 guest_efer
&= ~ignore_bits
;
750 guest_efer
|= host_efer
& ignore_bits
;
751 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
752 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
754 clear_atomic_switch_msr(vmx
, MSR_EFER
);
755 /* On ept, can't emulate nx, and must switch nx atomically */
756 if (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
)) {
757 guest_efer
= vmx
->vcpu
.arch
.efer
;
758 if (!(guest_efer
& EFER_LMA
))
759 guest_efer
&= ~EFER_LME
;
760 add_atomic_switch_msr(vmx
, MSR_EFER
, guest_efer
, host_efer
);
767 static unsigned long segment_base(u16 selector
)
769 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
770 struct desc_struct
*d
;
771 unsigned long table_base
;
774 if (!(selector
& ~3))
777 table_base
= gdt
->address
;
779 if (selector
& 4) { /* from ldt */
780 u16 ldt_selector
= kvm_read_ldt();
782 if (!(ldt_selector
& ~3))
785 table_base
= segment_base(ldt_selector
);
787 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
788 v
= get_desc_base(d
);
790 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
791 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
796 static inline unsigned long kvm_read_tr_base(void)
799 asm("str %0" : "=g"(tr
));
800 return segment_base(tr
);
803 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
805 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
808 if (vmx
->host_state
.loaded
)
811 vmx
->host_state
.loaded
= 1;
813 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
814 * allow segment selectors with cpl > 0 or ti == 1.
816 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
817 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
818 savesegment(fs
, vmx
->host_state
.fs_sel
);
819 if (!(vmx
->host_state
.fs_sel
& 7)) {
820 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
821 vmx
->host_state
.fs_reload_needed
= 0;
823 vmcs_write16(HOST_FS_SELECTOR
, 0);
824 vmx
->host_state
.fs_reload_needed
= 1;
826 savesegment(gs
, vmx
->host_state
.gs_sel
);
827 if (!(vmx
->host_state
.gs_sel
& 7))
828 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
830 vmcs_write16(HOST_GS_SELECTOR
, 0);
831 vmx
->host_state
.gs_ldt_reload_needed
= 1;
835 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
836 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
838 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
839 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
843 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
844 if (is_long_mode(&vmx
->vcpu
))
845 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
847 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
848 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
849 vmx
->guest_msrs
[i
].data
,
850 vmx
->guest_msrs
[i
].mask
);
853 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
855 if (!vmx
->host_state
.loaded
)
858 ++vmx
->vcpu
.stat
.host_state_reload
;
859 vmx
->host_state
.loaded
= 0;
861 if (is_long_mode(&vmx
->vcpu
))
862 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
864 if (vmx
->host_state
.gs_ldt_reload_needed
) {
865 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
867 load_gs_index(vmx
->host_state
.gs_sel
);
869 loadsegment(gs
, vmx
->host_state
.gs_sel
);
872 if (vmx
->host_state
.fs_reload_needed
)
873 loadsegment(fs
, vmx
->host_state
.fs_sel
);
876 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
878 if (current_thread_info()->status
& TS_USEDFPU
)
880 load_gdt(&__get_cpu_var(host_gdt
));
883 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
886 __vmx_load_host_state(vmx
);
891 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
892 * vcpu mutex is already taken.
894 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
896 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
897 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
900 kvm_cpu_vmxon(phys_addr
);
901 else if (vcpu
->cpu
!= cpu
)
904 if (per_cpu(current_vmcs
, cpu
) != vmx
->vmcs
) {
905 per_cpu(current_vmcs
, cpu
) = vmx
->vmcs
;
906 vmcs_load(vmx
->vmcs
);
909 if (vcpu
->cpu
!= cpu
) {
910 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
911 unsigned long sysenter_esp
;
913 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
915 list_add(&vmx
->local_vcpus_link
,
916 &per_cpu(vcpus_on_cpu
, cpu
));
920 * Linux uses per-cpu TSS and GDT, so set these when switching
923 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
924 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
926 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
927 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
931 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
933 __vmx_load_host_state(to_vmx(vcpu
));
934 if (!vmm_exclusive
) {
935 __vcpu_clear(to_vmx(vcpu
));
940 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
944 if (vcpu
->fpu_active
)
946 vcpu
->fpu_active
= 1;
947 cr0
= vmcs_readl(GUEST_CR0
);
948 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
949 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
950 vmcs_writel(GUEST_CR0
, cr0
);
951 update_exception_bitmap(vcpu
);
952 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
953 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
956 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
958 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
960 vmx_decache_cr0_guest_bits(vcpu
);
961 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
962 update_exception_bitmap(vcpu
);
963 vcpu
->arch
.cr0_guest_owned_bits
= 0;
964 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
965 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
968 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
970 unsigned long rflags
, save_rflags
;
972 rflags
= vmcs_readl(GUEST_RFLAGS
);
973 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
974 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
975 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
976 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
981 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
983 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
984 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
985 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
987 vmcs_writel(GUEST_RFLAGS
, rflags
);
990 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
992 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
995 if (interruptibility
& GUEST_INTR_STATE_STI
)
996 ret
|= KVM_X86_SHADOW_INT_STI
;
997 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
998 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
1003 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1005 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1006 u32 interruptibility
= interruptibility_old
;
1008 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
1010 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
1011 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
1012 else if (mask
& KVM_X86_SHADOW_INT_STI
)
1013 interruptibility
|= GUEST_INTR_STATE_STI
;
1015 if ((interruptibility
!= interruptibility_old
))
1016 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
1019 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
1023 rip
= kvm_rip_read(vcpu
);
1024 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
1025 kvm_rip_write(vcpu
, rip
);
1027 /* skipping an emulated instruction also counts */
1028 vmx_set_interrupt_shadow(vcpu
, 0);
1031 static void vmx_clear_hlt(struct kvm_vcpu
*vcpu
)
1033 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1034 * explicitly skip the instruction because if the HLT state is set, then
1035 * the instruction is already executing and RIP has already been
1037 if (!yield_on_hlt
&&
1038 vmcs_read32(GUEST_ACTIVITY_STATE
) == GUEST_ACTIVITY_HLT
)
1039 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
1042 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
1043 bool has_error_code
, u32 error_code
,
1046 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1047 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
1049 if (has_error_code
) {
1050 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
1051 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
1054 if (vmx
->rmode
.vm86_active
) {
1055 if (kvm_inject_realmode_interrupt(vcpu
, nr
) != EMULATE_DONE
)
1056 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
1060 if (kvm_exception_is_soft(nr
)) {
1061 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
1062 vmx
->vcpu
.arch
.event_exit_inst_len
);
1063 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
1065 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
1067 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
1068 vmx_clear_hlt(vcpu
);
1071 static bool vmx_rdtscp_supported(void)
1073 return cpu_has_vmx_rdtscp();
1077 * Swap MSR entry in host/guest MSR entry array.
1079 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
1081 struct shared_msr_entry tmp
;
1083 tmp
= vmx
->guest_msrs
[to
];
1084 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
1085 vmx
->guest_msrs
[from
] = tmp
;
1089 * Set up the vmcs to automatically save and restore system
1090 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1091 * mode, as fiddling with msrs is very expensive.
1093 static void setup_msrs(struct vcpu_vmx
*vmx
)
1095 int save_nmsrs
, index
;
1096 unsigned long *msr_bitmap
;
1098 vmx_load_host_state(vmx
);
1100 #ifdef CONFIG_X86_64
1101 if (is_long_mode(&vmx
->vcpu
)) {
1102 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
1104 move_msr_up(vmx
, index
, save_nmsrs
++);
1105 index
= __find_msr_index(vmx
, MSR_LSTAR
);
1107 move_msr_up(vmx
, index
, save_nmsrs
++);
1108 index
= __find_msr_index(vmx
, MSR_CSTAR
);
1110 move_msr_up(vmx
, index
, save_nmsrs
++);
1111 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
1112 if (index
>= 0 && vmx
->rdtscp_enabled
)
1113 move_msr_up(vmx
, index
, save_nmsrs
++);
1115 * MSR_STAR is only needed on long mode guests, and only
1116 * if efer.sce is enabled.
1118 index
= __find_msr_index(vmx
, MSR_STAR
);
1119 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
1120 move_msr_up(vmx
, index
, save_nmsrs
++);
1123 index
= __find_msr_index(vmx
, MSR_EFER
);
1124 if (index
>= 0 && update_transition_efer(vmx
, index
))
1125 move_msr_up(vmx
, index
, save_nmsrs
++);
1127 vmx
->save_nmsrs
= save_nmsrs
;
1129 if (cpu_has_vmx_msr_bitmap()) {
1130 if (is_long_mode(&vmx
->vcpu
))
1131 msr_bitmap
= vmx_msr_bitmap_longmode
;
1133 msr_bitmap
= vmx_msr_bitmap_legacy
;
1135 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
1140 * reads and returns guest's timestamp counter "register"
1141 * guest_tsc = host_tsc + tsc_offset -- 21.3
1143 static u64
guest_read_tsc(void)
1145 u64 host_tsc
, tsc_offset
;
1148 tsc_offset
= vmcs_read64(TSC_OFFSET
);
1149 return host_tsc
+ tsc_offset
;
1153 * writes 'offset' into guest's timestamp counter offset register
1155 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
1157 vmcs_write64(TSC_OFFSET
, offset
);
1160 static void vmx_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
)
1162 u64 offset
= vmcs_read64(TSC_OFFSET
);
1163 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
1167 * Reads an msr value (of 'msr_index') into 'pdata'.
1168 * Returns 0 on success, non-0 otherwise.
1169 * Assumes vcpu_load() was already called.
1171 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
1174 struct shared_msr_entry
*msr
;
1177 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
1181 switch (msr_index
) {
1182 #ifdef CONFIG_X86_64
1184 data
= vmcs_readl(GUEST_FS_BASE
);
1187 data
= vmcs_readl(GUEST_GS_BASE
);
1189 case MSR_KERNEL_GS_BASE
:
1190 vmx_load_host_state(to_vmx(vcpu
));
1191 data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
1195 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
1197 data
= guest_read_tsc();
1199 case MSR_IA32_SYSENTER_CS
:
1200 data
= vmcs_read32(GUEST_SYSENTER_CS
);
1202 case MSR_IA32_SYSENTER_EIP
:
1203 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
1205 case MSR_IA32_SYSENTER_ESP
:
1206 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
1209 if (!to_vmx(vcpu
)->rdtscp_enabled
)
1211 /* Otherwise falls through */
1213 vmx_load_host_state(to_vmx(vcpu
));
1214 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
1216 vmx_load_host_state(to_vmx(vcpu
));
1220 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
1228 * Writes msr value into into the appropriate "register".
1229 * Returns 0 on success, non-0 otherwise.
1230 * Assumes vcpu_load() was already called.
1232 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
1234 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1235 struct shared_msr_entry
*msr
;
1238 switch (msr_index
) {
1240 vmx_load_host_state(vmx
);
1241 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
1243 #ifdef CONFIG_X86_64
1245 vmcs_writel(GUEST_FS_BASE
, data
);
1248 vmcs_writel(GUEST_GS_BASE
, data
);
1250 case MSR_KERNEL_GS_BASE
:
1251 vmx_load_host_state(vmx
);
1252 vmx
->msr_guest_kernel_gs_base
= data
;
1255 case MSR_IA32_SYSENTER_CS
:
1256 vmcs_write32(GUEST_SYSENTER_CS
, data
);
1258 case MSR_IA32_SYSENTER_EIP
:
1259 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
1261 case MSR_IA32_SYSENTER_ESP
:
1262 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
1265 kvm_write_tsc(vcpu
, data
);
1267 case MSR_IA32_CR_PAT
:
1268 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
1269 vmcs_write64(GUEST_IA32_PAT
, data
);
1270 vcpu
->arch
.pat
= data
;
1273 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
1276 if (!vmx
->rdtscp_enabled
)
1278 /* Check reserved bit, higher 32 bits should be zero */
1279 if ((data
>> 32) != 0)
1281 /* Otherwise falls through */
1283 msr
= find_msr_entry(vmx
, msr_index
);
1285 vmx_load_host_state(vmx
);
1289 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
1295 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
1297 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
1300 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
1303 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
1305 case VCPU_EXREG_PDPTR
:
1307 ept_save_pdptrs(vcpu
);
1314 static void set_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
1316 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1317 vmcs_writel(GUEST_DR7
, dbg
->arch
.debugreg
[7]);
1319 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
1321 update_exception_bitmap(vcpu
);
1324 static __init
int cpu_has_kvm_support(void)
1326 return cpu_has_vmx();
1329 static __init
int vmx_disabled_by_bios(void)
1333 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
1334 if (msr
& FEATURE_CONTROL_LOCKED
) {
1335 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
1338 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
1339 && !tboot_enabled()) {
1340 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
1341 " activate TXT before enabling KVM\n");
1347 /* locked but not enabled */
1350 static void kvm_cpu_vmxon(u64 addr
)
1352 asm volatile (ASM_VMX_VMXON_RAX
1353 : : "a"(&addr
), "m"(addr
)
1357 static int hardware_enable(void *garbage
)
1359 int cpu
= raw_smp_processor_id();
1360 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1363 if (read_cr4() & X86_CR4_VMXE
)
1366 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu
, cpu
));
1367 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
1369 test_bits
= FEATURE_CONTROL_LOCKED
;
1370 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
1371 if (tboot_enabled())
1372 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
1374 if ((old
& test_bits
) != test_bits
) {
1375 /* enable and lock */
1376 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
1378 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
1380 if (vmm_exclusive
) {
1381 kvm_cpu_vmxon(phys_addr
);
1385 store_gdt(&__get_cpu_var(host_gdt
));
1390 static void vmclear_local_vcpus(void)
1392 int cpu
= raw_smp_processor_id();
1393 struct vcpu_vmx
*vmx
, *n
;
1395 list_for_each_entry_safe(vmx
, n
, &per_cpu(vcpus_on_cpu
, cpu
),
1401 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1404 static void kvm_cpu_vmxoff(void)
1406 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
1409 static void hardware_disable(void *garbage
)
1411 if (vmm_exclusive
) {
1412 vmclear_local_vcpus();
1415 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
1418 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
1419 u32 msr
, u32
*result
)
1421 u32 vmx_msr_low
, vmx_msr_high
;
1422 u32 ctl
= ctl_min
| ctl_opt
;
1424 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
1426 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
1427 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
1429 /* Ensure minimum (required) set of control bits are supported. */
1437 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
1439 u32 vmx_msr_low
, vmx_msr_high
;
1441 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
1442 return vmx_msr_high
& ctl
;
1445 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
1447 u32 vmx_msr_low
, vmx_msr_high
;
1448 u32 min
, opt
, min2
, opt2
;
1449 u32 _pin_based_exec_control
= 0;
1450 u32 _cpu_based_exec_control
= 0;
1451 u32 _cpu_based_2nd_exec_control
= 0;
1452 u32 _vmexit_control
= 0;
1453 u32 _vmentry_control
= 0;
1455 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
1456 opt
= PIN_BASED_VIRTUAL_NMIS
;
1457 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
1458 &_pin_based_exec_control
) < 0)
1462 #ifdef CONFIG_X86_64
1463 CPU_BASED_CR8_LOAD_EXITING
|
1464 CPU_BASED_CR8_STORE_EXITING
|
1466 CPU_BASED_CR3_LOAD_EXITING
|
1467 CPU_BASED_CR3_STORE_EXITING
|
1468 CPU_BASED_USE_IO_BITMAPS
|
1469 CPU_BASED_MOV_DR_EXITING
|
1470 CPU_BASED_USE_TSC_OFFSETING
|
1471 CPU_BASED_MWAIT_EXITING
|
1472 CPU_BASED_MONITOR_EXITING
|
1473 CPU_BASED_INVLPG_EXITING
;
1476 min
|= CPU_BASED_HLT_EXITING
;
1478 opt
= CPU_BASED_TPR_SHADOW
|
1479 CPU_BASED_USE_MSR_BITMAPS
|
1480 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1481 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
1482 &_cpu_based_exec_control
) < 0)
1484 #ifdef CONFIG_X86_64
1485 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
1486 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
1487 ~CPU_BASED_CR8_STORE_EXITING
;
1489 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
1491 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
1492 SECONDARY_EXEC_WBINVD_EXITING
|
1493 SECONDARY_EXEC_ENABLE_VPID
|
1494 SECONDARY_EXEC_ENABLE_EPT
|
1495 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
1496 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
1497 SECONDARY_EXEC_RDTSCP
;
1498 if (adjust_vmx_controls(min2
, opt2
,
1499 MSR_IA32_VMX_PROCBASED_CTLS2
,
1500 &_cpu_based_2nd_exec_control
) < 0)
1503 #ifndef CONFIG_X86_64
1504 if (!(_cpu_based_2nd_exec_control
&
1505 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
1506 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
1508 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
1509 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1511 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
1512 CPU_BASED_CR3_STORE_EXITING
|
1513 CPU_BASED_INVLPG_EXITING
);
1514 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
1515 vmx_capability
.ept
, vmx_capability
.vpid
);
1519 #ifdef CONFIG_X86_64
1520 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
1522 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
;
1523 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
1524 &_vmexit_control
) < 0)
1528 opt
= VM_ENTRY_LOAD_IA32_PAT
;
1529 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
1530 &_vmentry_control
) < 0)
1533 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
1535 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1536 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
1539 #ifdef CONFIG_X86_64
1540 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1541 if (vmx_msr_high
& (1u<<16))
1545 /* Require Write-Back (WB) memory type for VMCS accesses. */
1546 if (((vmx_msr_high
>> 18) & 15) != 6)
1549 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
1550 vmcs_conf
->order
= get_order(vmcs_config
.size
);
1551 vmcs_conf
->revision_id
= vmx_msr_low
;
1553 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
1554 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
1555 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
1556 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
1557 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
1559 cpu_has_load_ia32_efer
=
1560 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
1561 VM_ENTRY_LOAD_IA32_EFER
)
1562 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
1563 VM_EXIT_LOAD_IA32_EFER
);
1568 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
1570 int node
= cpu_to_node(cpu
);
1574 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
1577 vmcs
= page_address(pages
);
1578 memset(vmcs
, 0, vmcs_config
.size
);
1579 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
1583 static struct vmcs
*alloc_vmcs(void)
1585 return alloc_vmcs_cpu(raw_smp_processor_id());
1588 static void free_vmcs(struct vmcs
*vmcs
)
1590 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
1593 static void free_kvm_area(void)
1597 for_each_possible_cpu(cpu
) {
1598 free_vmcs(per_cpu(vmxarea
, cpu
));
1599 per_cpu(vmxarea
, cpu
) = NULL
;
1603 static __init
int alloc_kvm_area(void)
1607 for_each_possible_cpu(cpu
) {
1610 vmcs
= alloc_vmcs_cpu(cpu
);
1616 per_cpu(vmxarea
, cpu
) = vmcs
;
1621 static __init
int hardware_setup(void)
1623 if (setup_vmcs_config(&vmcs_config
) < 0)
1626 if (boot_cpu_has(X86_FEATURE_NX
))
1627 kvm_enable_efer_bits(EFER_NX
);
1629 if (!cpu_has_vmx_vpid())
1632 if (!cpu_has_vmx_ept() ||
1633 !cpu_has_vmx_ept_4levels()) {
1635 enable_unrestricted_guest
= 0;
1638 if (!cpu_has_vmx_unrestricted_guest())
1639 enable_unrestricted_guest
= 0;
1641 if (!cpu_has_vmx_flexpriority())
1642 flexpriority_enabled
= 0;
1644 if (!cpu_has_vmx_tpr_shadow())
1645 kvm_x86_ops
->update_cr8_intercept
= NULL
;
1647 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
1648 kvm_disable_largepages();
1650 if (!cpu_has_vmx_ple())
1653 return alloc_kvm_area();
1656 static __exit
void hardware_unsetup(void)
1661 static void fix_pmode_dataseg(int seg
, struct kvm_save_segment
*save
)
1663 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1665 if (vmcs_readl(sf
->base
) == save
->base
&& (save
->base
& AR_S_MASK
)) {
1666 vmcs_write16(sf
->selector
, save
->selector
);
1667 vmcs_writel(sf
->base
, save
->base
);
1668 vmcs_write32(sf
->limit
, save
->limit
);
1669 vmcs_write32(sf
->ar_bytes
, save
->ar
);
1671 u32 dpl
= (vmcs_read16(sf
->selector
) & SELECTOR_RPL_MASK
)
1673 vmcs_write32(sf
->ar_bytes
, 0x93 | dpl
);
1677 static void enter_pmode(struct kvm_vcpu
*vcpu
)
1679 unsigned long flags
;
1680 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1682 vmx
->emulation_required
= 1;
1683 vmx
->rmode
.vm86_active
= 0;
1685 vmcs_writel(GUEST_TR_BASE
, vmx
->rmode
.tr
.base
);
1686 vmcs_write32(GUEST_TR_LIMIT
, vmx
->rmode
.tr
.limit
);
1687 vmcs_write32(GUEST_TR_AR_BYTES
, vmx
->rmode
.tr
.ar
);
1689 flags
= vmcs_readl(GUEST_RFLAGS
);
1690 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
1691 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
1692 vmcs_writel(GUEST_RFLAGS
, flags
);
1694 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
1695 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
1697 update_exception_bitmap(vcpu
);
1699 if (emulate_invalid_guest_state
)
1702 fix_pmode_dataseg(VCPU_SREG_ES
, &vmx
->rmode
.es
);
1703 fix_pmode_dataseg(VCPU_SREG_DS
, &vmx
->rmode
.ds
);
1704 fix_pmode_dataseg(VCPU_SREG_GS
, &vmx
->rmode
.gs
);
1705 fix_pmode_dataseg(VCPU_SREG_FS
, &vmx
->rmode
.fs
);
1707 vmcs_write16(GUEST_SS_SELECTOR
, 0);
1708 vmcs_write32(GUEST_SS_AR_BYTES
, 0x93);
1710 vmcs_write16(GUEST_CS_SELECTOR
,
1711 vmcs_read16(GUEST_CS_SELECTOR
) & ~SELECTOR_RPL_MASK
);
1712 vmcs_write32(GUEST_CS_AR_BYTES
, 0x9b);
1715 static gva_t
rmode_tss_base(struct kvm
*kvm
)
1717 if (!kvm
->arch
.tss_addr
) {
1718 struct kvm_memslots
*slots
;
1721 slots
= kvm_memslots(kvm
);
1722 base_gfn
= slots
->memslots
[0].base_gfn
+
1723 kvm
->memslots
->memslots
[0].npages
- 3;
1724 return base_gfn
<< PAGE_SHIFT
;
1726 return kvm
->arch
.tss_addr
;
1729 static void fix_rmode_seg(int seg
, struct kvm_save_segment
*save
)
1731 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1733 save
->selector
= vmcs_read16(sf
->selector
);
1734 save
->base
= vmcs_readl(sf
->base
);
1735 save
->limit
= vmcs_read32(sf
->limit
);
1736 save
->ar
= vmcs_read32(sf
->ar_bytes
);
1737 vmcs_write16(sf
->selector
, save
->base
>> 4);
1738 vmcs_write32(sf
->base
, save
->base
& 0xfffff);
1739 vmcs_write32(sf
->limit
, 0xffff);
1740 vmcs_write32(sf
->ar_bytes
, 0xf3);
1743 static void enter_rmode(struct kvm_vcpu
*vcpu
)
1745 unsigned long flags
;
1746 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1748 if (enable_unrestricted_guest
)
1751 vmx
->emulation_required
= 1;
1752 vmx
->rmode
.vm86_active
= 1;
1754 vmx
->rmode
.tr
.base
= vmcs_readl(GUEST_TR_BASE
);
1755 vmcs_writel(GUEST_TR_BASE
, rmode_tss_base(vcpu
->kvm
));
1757 vmx
->rmode
.tr
.limit
= vmcs_read32(GUEST_TR_LIMIT
);
1758 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
1760 vmx
->rmode
.tr
.ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
1761 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
1763 flags
= vmcs_readl(GUEST_RFLAGS
);
1764 vmx
->rmode
.save_rflags
= flags
;
1766 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1768 vmcs_writel(GUEST_RFLAGS
, flags
);
1769 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
1770 update_exception_bitmap(vcpu
);
1772 if (emulate_invalid_guest_state
)
1773 goto continue_rmode
;
1775 vmcs_write16(GUEST_SS_SELECTOR
, vmcs_readl(GUEST_SS_BASE
) >> 4);
1776 vmcs_write32(GUEST_SS_LIMIT
, 0xffff);
1777 vmcs_write32(GUEST_SS_AR_BYTES
, 0xf3);
1779 vmcs_write32(GUEST_CS_AR_BYTES
, 0xf3);
1780 vmcs_write32(GUEST_CS_LIMIT
, 0xffff);
1781 if (vmcs_readl(GUEST_CS_BASE
) == 0xffff0000)
1782 vmcs_writel(GUEST_CS_BASE
, 0xf0000);
1783 vmcs_write16(GUEST_CS_SELECTOR
, vmcs_readl(GUEST_CS_BASE
) >> 4);
1785 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.es
);
1786 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.ds
);
1787 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.gs
);
1788 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.fs
);
1791 kvm_mmu_reset_context(vcpu
);
1792 init_rmode(vcpu
->kvm
);
1795 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
1797 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1798 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
1804 * Force kernel_gs_base reloading before EFER changes, as control
1805 * of this msr depends on is_long_mode().
1807 vmx_load_host_state(to_vmx(vcpu
));
1808 vcpu
->arch
.efer
= efer
;
1809 if (efer
& EFER_LMA
) {
1810 vmcs_write32(VM_ENTRY_CONTROLS
,
1811 vmcs_read32(VM_ENTRY_CONTROLS
) |
1812 VM_ENTRY_IA32E_MODE
);
1815 vmcs_write32(VM_ENTRY_CONTROLS
,
1816 vmcs_read32(VM_ENTRY_CONTROLS
) &
1817 ~VM_ENTRY_IA32E_MODE
);
1819 msr
->data
= efer
& ~EFER_LME
;
1824 #ifdef CONFIG_X86_64
1826 static void enter_lmode(struct kvm_vcpu
*vcpu
)
1830 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
1831 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
1832 printk(KERN_DEBUG
"%s: tss fixup for long mode. \n",
1834 vmcs_write32(GUEST_TR_AR_BYTES
,
1835 (guest_tr_ar
& ~AR_TYPE_MASK
)
1836 | AR_TYPE_BUSY_64_TSS
);
1838 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
1841 static void exit_lmode(struct kvm_vcpu
*vcpu
)
1843 vmcs_write32(VM_ENTRY_CONTROLS
,
1844 vmcs_read32(VM_ENTRY_CONTROLS
)
1845 & ~VM_ENTRY_IA32E_MODE
);
1846 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
1851 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
1853 vpid_sync_context(to_vmx(vcpu
));
1855 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
1857 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
1861 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
1863 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
1865 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
1866 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
1869 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
1871 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
1873 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
1874 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
1877 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
1879 if (!test_bit(VCPU_EXREG_PDPTR
,
1880 (unsigned long *)&vcpu
->arch
.regs_dirty
))
1883 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
1884 vmcs_write64(GUEST_PDPTR0
, vcpu
->arch
.mmu
.pdptrs
[0]);
1885 vmcs_write64(GUEST_PDPTR1
, vcpu
->arch
.mmu
.pdptrs
[1]);
1886 vmcs_write64(GUEST_PDPTR2
, vcpu
->arch
.mmu
.pdptrs
[2]);
1887 vmcs_write64(GUEST_PDPTR3
, vcpu
->arch
.mmu
.pdptrs
[3]);
1891 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
1893 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
1894 vcpu
->arch
.mmu
.pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
1895 vcpu
->arch
.mmu
.pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
1896 vcpu
->arch
.mmu
.pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
1897 vcpu
->arch
.mmu
.pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
1900 __set_bit(VCPU_EXREG_PDPTR
,
1901 (unsigned long *)&vcpu
->arch
.regs_avail
);
1902 __set_bit(VCPU_EXREG_PDPTR
,
1903 (unsigned long *)&vcpu
->arch
.regs_dirty
);
1906 static void vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
1908 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
1910 struct kvm_vcpu
*vcpu
)
1912 if (!(cr0
& X86_CR0_PG
)) {
1913 /* From paging/starting to nonpaging */
1914 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
1915 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
1916 (CPU_BASED_CR3_LOAD_EXITING
|
1917 CPU_BASED_CR3_STORE_EXITING
));
1918 vcpu
->arch
.cr0
= cr0
;
1919 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
1920 } else if (!is_paging(vcpu
)) {
1921 /* From nonpaging to paging */
1922 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
1923 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
1924 ~(CPU_BASED_CR3_LOAD_EXITING
|
1925 CPU_BASED_CR3_STORE_EXITING
));
1926 vcpu
->arch
.cr0
= cr0
;
1927 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
1930 if (!(cr0
& X86_CR0_WP
))
1931 *hw_cr0
&= ~X86_CR0_WP
;
1934 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1936 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1937 unsigned long hw_cr0
;
1939 if (enable_unrestricted_guest
)
1940 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST
)
1941 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
1943 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
) | KVM_VM_CR0_ALWAYS_ON
;
1945 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
1948 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
1951 #ifdef CONFIG_X86_64
1952 if (vcpu
->arch
.efer
& EFER_LME
) {
1953 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
1955 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
1961 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
1963 if (!vcpu
->fpu_active
)
1964 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
1966 vmcs_writel(CR0_READ_SHADOW
, cr0
);
1967 vmcs_writel(GUEST_CR0
, hw_cr0
);
1968 vcpu
->arch
.cr0
= cr0
;
1971 static u64
construct_eptp(unsigned long root_hpa
)
1975 /* TODO write the value reading from MSR */
1976 eptp
= VMX_EPT_DEFAULT_MT
|
1977 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
1978 eptp
|= (root_hpa
& PAGE_MASK
);
1983 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
1985 unsigned long guest_cr3
;
1990 eptp
= construct_eptp(cr3
);
1991 vmcs_write64(EPT_POINTER
, eptp
);
1992 guest_cr3
= is_paging(vcpu
) ? vcpu
->arch
.cr3
:
1993 vcpu
->kvm
->arch
.ept_identity_map_addr
;
1994 ept_load_pdptrs(vcpu
);
1997 vmx_flush_tlb(vcpu
);
1998 vmcs_writel(GUEST_CR3
, guest_cr3
);
2001 static void vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
2003 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
2004 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
2006 vcpu
->arch
.cr4
= cr4
;
2008 if (!is_paging(vcpu
)) {
2009 hw_cr4
&= ~X86_CR4_PAE
;
2010 hw_cr4
|= X86_CR4_PSE
;
2011 } else if (!(cr4
& X86_CR4_PAE
)) {
2012 hw_cr4
&= ~X86_CR4_PAE
;
2016 vmcs_writel(CR4_READ_SHADOW
, cr4
);
2017 vmcs_writel(GUEST_CR4
, hw_cr4
);
2020 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
2022 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2024 return vmcs_readl(sf
->base
);
2027 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
2028 struct kvm_segment
*var
, int seg
)
2030 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2033 var
->base
= vmcs_readl(sf
->base
);
2034 var
->limit
= vmcs_read32(sf
->limit
);
2035 var
->selector
= vmcs_read16(sf
->selector
);
2036 ar
= vmcs_read32(sf
->ar_bytes
);
2037 if ((ar
& AR_UNUSABLE_MASK
) && !emulate_invalid_guest_state
)
2039 var
->type
= ar
& 15;
2040 var
->s
= (ar
>> 4) & 1;
2041 var
->dpl
= (ar
>> 5) & 3;
2042 var
->present
= (ar
>> 7) & 1;
2043 var
->avl
= (ar
>> 12) & 1;
2044 var
->l
= (ar
>> 13) & 1;
2045 var
->db
= (ar
>> 14) & 1;
2046 var
->g
= (ar
>> 15) & 1;
2047 var
->unusable
= (ar
>> 16) & 1;
2050 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
2052 if (!is_protmode(vcpu
))
2055 if (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) /* if virtual 8086 */
2058 return vmcs_read16(GUEST_CS_SELECTOR
) & 3;
2061 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
2068 ar
= var
->type
& 15;
2069 ar
|= (var
->s
& 1) << 4;
2070 ar
|= (var
->dpl
& 3) << 5;
2071 ar
|= (var
->present
& 1) << 7;
2072 ar
|= (var
->avl
& 1) << 12;
2073 ar
|= (var
->l
& 1) << 13;
2074 ar
|= (var
->db
& 1) << 14;
2075 ar
|= (var
->g
& 1) << 15;
2077 if (ar
== 0) /* a 0 value means unusable */
2078 ar
= AR_UNUSABLE_MASK
;
2083 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
2084 struct kvm_segment
*var
, int seg
)
2086 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2087 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2090 if (vmx
->rmode
.vm86_active
&& seg
== VCPU_SREG_TR
) {
2091 vmx
->rmode
.tr
.selector
= var
->selector
;
2092 vmx
->rmode
.tr
.base
= var
->base
;
2093 vmx
->rmode
.tr
.limit
= var
->limit
;
2094 vmx
->rmode
.tr
.ar
= vmx_segment_access_rights(var
);
2097 vmcs_writel(sf
->base
, var
->base
);
2098 vmcs_write32(sf
->limit
, var
->limit
);
2099 vmcs_write16(sf
->selector
, var
->selector
);
2100 if (vmx
->rmode
.vm86_active
&& var
->s
) {
2102 * Hack real-mode segments into vm86 compatibility.
2104 if (var
->base
== 0xffff0000 && var
->selector
== 0xf000)
2105 vmcs_writel(sf
->base
, 0xf0000);
2108 ar
= vmx_segment_access_rights(var
);
2111 * Fix the "Accessed" bit in AR field of segment registers for older
2113 * IA32 arch specifies that at the time of processor reset the
2114 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2115 * is setting it to 0 in the usedland code. This causes invalid guest
2116 * state vmexit when "unrestricted guest" mode is turned on.
2117 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2118 * tree. Newer qemu binaries with that qemu fix would not need this
2121 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
2122 ar
|= 0x1; /* Accessed */
2124 vmcs_write32(sf
->ar_bytes
, ar
);
2127 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
2129 u32 ar
= vmcs_read32(GUEST_CS_AR_BYTES
);
2131 *db
= (ar
>> 14) & 1;
2132 *l
= (ar
>> 13) & 1;
2135 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2137 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
2138 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
2141 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2143 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
2144 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
2147 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2149 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
2150 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
2153 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2155 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
2156 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
2159 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
2161 struct kvm_segment var
;
2164 vmx_get_segment(vcpu
, &var
, seg
);
2165 ar
= vmx_segment_access_rights(&var
);
2167 if (var
.base
!= (var
.selector
<< 4))
2169 if (var
.limit
!= 0xffff)
2177 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
2179 struct kvm_segment cs
;
2180 unsigned int cs_rpl
;
2182 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
2183 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
2187 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
2191 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
2192 if (cs
.dpl
> cs_rpl
)
2195 if (cs
.dpl
!= cs_rpl
)
2201 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2205 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
2207 struct kvm_segment ss
;
2208 unsigned int ss_rpl
;
2210 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
2211 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
2215 if (ss
.type
!= 3 && ss
.type
!= 7)
2219 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
2227 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
2229 struct kvm_segment var
;
2232 vmx_get_segment(vcpu
, &var
, seg
);
2233 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
2241 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
2242 if (var
.dpl
< rpl
) /* DPL < RPL */
2246 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2252 static bool tr_valid(struct kvm_vcpu
*vcpu
)
2254 struct kvm_segment tr
;
2256 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
2260 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
2262 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
2270 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
2272 struct kvm_segment ldtr
;
2274 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
2278 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
2288 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
2290 struct kvm_segment cs
, ss
;
2292 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
2293 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
2295 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
2296 (ss
.selector
& SELECTOR_RPL_MASK
));
2300 * Check if guest state is valid. Returns true if valid, false if
2302 * We assume that registers are always usable
2304 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
2306 /* real mode guest state checks */
2307 if (!is_protmode(vcpu
)) {
2308 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
2310 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
2312 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
2314 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
2316 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
2318 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
2321 /* protected mode guest state checks */
2322 if (!cs_ss_rpl_check(vcpu
))
2324 if (!code_segment_valid(vcpu
))
2326 if (!stack_segment_valid(vcpu
))
2328 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
2330 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
2332 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
2334 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
2336 if (!tr_valid(vcpu
))
2338 if (!ldtr_valid(vcpu
))
2342 * - Add checks on RIP
2343 * - Add checks on RFLAGS
2349 static int init_rmode_tss(struct kvm
*kvm
)
2351 gfn_t fn
= rmode_tss_base(kvm
) >> PAGE_SHIFT
;
2356 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
2359 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
2360 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
2361 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
2364 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
2367 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
2371 r
= kvm_write_guest_page(kvm
, fn
, &data
,
2372 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
2382 static int init_rmode_identity_map(struct kvm
*kvm
)
2385 pfn_t identity_map_pfn
;
2390 if (unlikely(!kvm
->arch
.ept_identity_pagetable
)) {
2391 printk(KERN_ERR
"EPT: identity-mapping pagetable "
2392 "haven't been allocated!\n");
2395 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
2398 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
2399 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
2402 /* Set up identity-mapping pagetable for EPT in real mode */
2403 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
2404 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
2405 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
2406 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
2407 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
2411 kvm
->arch
.ept_identity_pagetable_done
= true;
2417 static void seg_setup(int seg
)
2419 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2422 vmcs_write16(sf
->selector
, 0);
2423 vmcs_writel(sf
->base
, 0);
2424 vmcs_write32(sf
->limit
, 0xffff);
2425 if (enable_unrestricted_guest
) {
2427 if (seg
== VCPU_SREG_CS
)
2428 ar
|= 0x08; /* code segment */
2432 vmcs_write32(sf
->ar_bytes
, ar
);
2435 static int alloc_apic_access_page(struct kvm
*kvm
)
2437 struct kvm_userspace_memory_region kvm_userspace_mem
;
2440 mutex_lock(&kvm
->slots_lock
);
2441 if (kvm
->arch
.apic_access_page
)
2443 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
2444 kvm_userspace_mem
.flags
= 0;
2445 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
2446 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
2447 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
2451 kvm
->arch
.apic_access_page
= gfn_to_page(kvm
, 0xfee00);
2453 mutex_unlock(&kvm
->slots_lock
);
2457 static int alloc_identity_pagetable(struct kvm
*kvm
)
2459 struct kvm_userspace_memory_region kvm_userspace_mem
;
2462 mutex_lock(&kvm
->slots_lock
);
2463 if (kvm
->arch
.ept_identity_pagetable
)
2465 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
2466 kvm_userspace_mem
.flags
= 0;
2467 kvm_userspace_mem
.guest_phys_addr
=
2468 kvm
->arch
.ept_identity_map_addr
;
2469 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
2470 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
2474 kvm
->arch
.ept_identity_pagetable
= gfn_to_page(kvm
,
2475 kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
);
2477 mutex_unlock(&kvm
->slots_lock
);
2481 static void allocate_vpid(struct vcpu_vmx
*vmx
)
2488 spin_lock(&vmx_vpid_lock
);
2489 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
2490 if (vpid
< VMX_NR_VPIDS
) {
2492 __set_bit(vpid
, vmx_vpid_bitmap
);
2494 spin_unlock(&vmx_vpid_lock
);
2497 static void free_vpid(struct vcpu_vmx
*vmx
)
2501 spin_lock(&vmx_vpid_lock
);
2503 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
2504 spin_unlock(&vmx_vpid_lock
);
2507 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
, u32 msr
)
2509 int f
= sizeof(unsigned long);
2511 if (!cpu_has_vmx_msr_bitmap())
2515 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2516 * have the write-low and read-high bitmap offsets the wrong way round.
2517 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2519 if (msr
<= 0x1fff) {
2520 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
); /* read-low */
2521 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
); /* write-low */
2522 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
2524 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
); /* read-high */
2525 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
); /* write-high */
2529 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
2532 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
, msr
);
2533 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
, msr
);
2537 * Sets up the vmcs for emulated real mode.
2539 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
2541 u32 host_sysenter_cs
, msr_low
, msr_high
;
2547 unsigned long kvm_vmx_return
;
2551 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
2552 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
2554 if (cpu_has_vmx_msr_bitmap())
2555 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
2557 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
2560 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
2561 vmcs_config
.pin_based_exec_ctrl
);
2563 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
2564 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
2565 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2566 #ifdef CONFIG_X86_64
2567 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
2568 CPU_BASED_CR8_LOAD_EXITING
;
2572 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
2573 CPU_BASED_CR3_LOAD_EXITING
|
2574 CPU_BASED_INVLPG_EXITING
;
2575 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
2577 if (cpu_has_secondary_exec_ctrls()) {
2578 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
2579 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
2581 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
2583 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
2585 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
2586 enable_unrestricted_guest
= 0;
2588 if (!enable_unrestricted_guest
)
2589 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2591 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
2592 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
2596 vmcs_write32(PLE_GAP
, ple_gap
);
2597 vmcs_write32(PLE_WINDOW
, ple_window
);
2600 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, !!bypass_guest_pf
);
2601 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, !!bypass_guest_pf
);
2602 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
2604 vmcs_writel(HOST_CR0
, read_cr0() | X86_CR0_TS
); /* 22.2.3 */
2605 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
2606 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2608 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
2609 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
2610 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
2611 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
2612 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
2613 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
2614 #ifdef CONFIG_X86_64
2615 rdmsrl(MSR_FS_BASE
, a
);
2616 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
2617 rdmsrl(MSR_GS_BASE
, a
);
2618 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
2620 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
2621 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
2624 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
2626 native_store_idt(&dt
);
2627 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
2629 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return
));
2630 vmcs_writel(HOST_RIP
, kvm_vmx_return
); /* 22.2.5 */
2631 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
2632 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
2633 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
2634 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
2635 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
2637 rdmsr(MSR_IA32_SYSENTER_CS
, host_sysenter_cs
, junk
);
2638 vmcs_write32(HOST_IA32_SYSENTER_CS
, host_sysenter_cs
);
2639 rdmsrl(MSR_IA32_SYSENTER_ESP
, a
);
2640 vmcs_writel(HOST_IA32_SYSENTER_ESP
, a
); /* 22.2.3 */
2641 rdmsrl(MSR_IA32_SYSENTER_EIP
, a
);
2642 vmcs_writel(HOST_IA32_SYSENTER_EIP
, a
); /* 22.2.3 */
2644 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
2645 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
2646 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
2647 vmcs_write64(HOST_IA32_PAT
, host_pat
);
2649 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2650 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
2651 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
2652 /* Write the default value follow host pat */
2653 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
2654 /* Keep arch.pat sync with GUEST_IA32_PAT */
2655 vmx
->vcpu
.arch
.pat
= host_pat
;
2658 for (i
= 0; i
< NR_VMX_MSR
; ++i
) {
2659 u32 index
= vmx_msr_index
[i
];
2660 u32 data_low
, data_high
;
2663 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
2665 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
2667 vmx
->guest_msrs
[j
].index
= i
;
2668 vmx
->guest_msrs
[j
].data
= 0;
2669 vmx
->guest_msrs
[j
].mask
= -1ull;
2673 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
2675 /* 22.2.1, 20.8.1 */
2676 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs_config
.vmentry_ctrl
);
2678 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
2679 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
2681 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
2682 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
2684 kvm_write_tsc(&vmx
->vcpu
, 0);
2689 static int init_rmode(struct kvm
*kvm
)
2693 idx
= srcu_read_lock(&kvm
->srcu
);
2694 if (!init_rmode_tss(kvm
))
2696 if (!init_rmode_identity_map(kvm
))
2701 srcu_read_unlock(&kvm
->srcu
, idx
);
2705 static int vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
2707 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2711 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
));
2712 if (!init_rmode(vmx
->vcpu
.kvm
)) {
2717 vmx
->rmode
.vm86_active
= 0;
2719 vmx
->soft_vnmi_blocked
= 0;
2721 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
2722 kvm_set_cr8(&vmx
->vcpu
, 0);
2723 msr
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
2724 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
2725 msr
|= MSR_IA32_APICBASE_BSP
;
2726 kvm_set_apic_base(&vmx
->vcpu
, msr
);
2728 ret
= fx_init(&vmx
->vcpu
);
2732 seg_setup(VCPU_SREG_CS
);
2734 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2735 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2737 if (kvm_vcpu_is_bsp(&vmx
->vcpu
)) {
2738 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
2739 vmcs_writel(GUEST_CS_BASE
, 0x000f0000);
2741 vmcs_write16(GUEST_CS_SELECTOR
, vmx
->vcpu
.arch
.sipi_vector
<< 8);
2742 vmcs_writel(GUEST_CS_BASE
, vmx
->vcpu
.arch
.sipi_vector
<< 12);
2745 seg_setup(VCPU_SREG_DS
);
2746 seg_setup(VCPU_SREG_ES
);
2747 seg_setup(VCPU_SREG_FS
);
2748 seg_setup(VCPU_SREG_GS
);
2749 seg_setup(VCPU_SREG_SS
);
2751 vmcs_write16(GUEST_TR_SELECTOR
, 0);
2752 vmcs_writel(GUEST_TR_BASE
, 0);
2753 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
2754 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
2756 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
2757 vmcs_writel(GUEST_LDTR_BASE
, 0);
2758 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
2759 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
2761 vmcs_write32(GUEST_SYSENTER_CS
, 0);
2762 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
2763 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
2765 vmcs_writel(GUEST_RFLAGS
, 0x02);
2766 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
2767 kvm_rip_write(vcpu
, 0xfff0);
2769 kvm_rip_write(vcpu
, 0);
2770 kvm_register_write(vcpu
, VCPU_REGS_RSP
, 0);
2772 vmcs_writel(GUEST_DR7
, 0x400);
2774 vmcs_writel(GUEST_GDTR_BASE
, 0);
2775 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
2777 vmcs_writel(GUEST_IDTR_BASE
, 0);
2778 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
2780 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
2781 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
2782 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
2784 /* Special registers */
2785 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
2789 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
2791 if (cpu_has_vmx_tpr_shadow()) {
2792 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
2793 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
2794 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
2795 page_to_phys(vmx
->vcpu
.arch
.apic
->regs_page
));
2796 vmcs_write32(TPR_THRESHOLD
, 0);
2799 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
2800 vmcs_write64(APIC_ACCESS_ADDR
,
2801 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
2804 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
2806 vmx
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
2807 vmx_set_cr0(&vmx
->vcpu
, kvm_read_cr0(vcpu
)); /* enter rmode */
2808 vmx_set_cr4(&vmx
->vcpu
, 0);
2809 vmx_set_efer(&vmx
->vcpu
, 0);
2810 vmx_fpu_activate(&vmx
->vcpu
);
2811 update_exception_bitmap(&vmx
->vcpu
);
2813 vpid_sync_context(vmx
);
2817 /* HACK: Don't enable emulation on guest boot/reset */
2818 vmx
->emulation_required
= 0;
2824 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
2826 u32 cpu_based_vm_exec_control
;
2828 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
2829 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
2830 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
2833 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
2835 u32 cpu_based_vm_exec_control
;
2837 if (!cpu_has_virtual_nmis()) {
2838 enable_irq_window(vcpu
);
2842 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
2843 enable_irq_window(vcpu
);
2846 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
2847 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
2848 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
2851 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
2853 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2855 int irq
= vcpu
->arch
.interrupt
.nr
;
2857 trace_kvm_inj_virq(irq
);
2859 ++vcpu
->stat
.irq_injections
;
2860 if (vmx
->rmode
.vm86_active
) {
2861 if (kvm_inject_realmode_interrupt(vcpu
, irq
) != EMULATE_DONE
)
2862 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2865 intr
= irq
| INTR_INFO_VALID_MASK
;
2866 if (vcpu
->arch
.interrupt
.soft
) {
2867 intr
|= INTR_TYPE_SOFT_INTR
;
2868 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2869 vmx
->vcpu
.arch
.event_exit_inst_len
);
2871 intr
|= INTR_TYPE_EXT_INTR
;
2872 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
2873 vmx_clear_hlt(vcpu
);
2876 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
2878 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2880 if (!cpu_has_virtual_nmis()) {
2882 * Tracking the NMI-blocked state in software is built upon
2883 * finding the next open IRQ window. This, in turn, depends on
2884 * well-behaving guests: They have to keep IRQs disabled at
2885 * least as long as the NMI handler runs. Otherwise we may
2886 * cause NMI nesting, maybe breaking the guest. But as this is
2887 * highly unlikely, we can live with the residual risk.
2889 vmx
->soft_vnmi_blocked
= 1;
2890 vmx
->vnmi_blocked_time
= 0;
2893 ++vcpu
->stat
.nmi_injections
;
2894 if (vmx
->rmode
.vm86_active
) {
2895 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
) != EMULATE_DONE
)
2896 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2899 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
2900 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
2901 vmx_clear_hlt(vcpu
);
2904 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
2906 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
2909 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
2910 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
2911 | GUEST_INTR_STATE_NMI
));
2914 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
2916 if (!cpu_has_virtual_nmis())
2917 return to_vmx(vcpu
)->soft_vnmi_blocked
;
2918 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
2921 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
2923 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2925 if (!cpu_has_virtual_nmis()) {
2926 if (vmx
->soft_vnmi_blocked
!= masked
) {
2927 vmx
->soft_vnmi_blocked
= masked
;
2928 vmx
->vnmi_blocked_time
= 0;
2932 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
2933 GUEST_INTR_STATE_NMI
);
2935 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
2936 GUEST_INTR_STATE_NMI
);
2940 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
2942 return (vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
2943 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
2944 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
2947 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
2950 struct kvm_userspace_memory_region tss_mem
= {
2951 .slot
= TSS_PRIVATE_MEMSLOT
,
2952 .guest_phys_addr
= addr
,
2953 .memory_size
= PAGE_SIZE
* 3,
2957 ret
= kvm_set_memory_region(kvm
, &tss_mem
, 0);
2960 kvm
->arch
.tss_addr
= addr
;
2964 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
2965 int vec
, u32 err_code
)
2968 * Instruction with address size override prefix opcode 0x67
2969 * Cause the #SS fault with 0 error code in VM86 mode.
2971 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0)
2972 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
)
2975 * Forward all other exceptions that are valid in real mode.
2976 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2977 * the required debugging infrastructure rework.
2981 if (vcpu
->guest_debug
&
2982 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
2984 kvm_queue_exception(vcpu
, vec
);
2988 * Update instruction length as we may reinject the exception
2989 * from user space while in guest debugging mode.
2991 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
2992 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2993 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
3004 kvm_queue_exception(vcpu
, vec
);
3011 * Trigger machine check on the host. We assume all the MSRs are already set up
3012 * by the CPU and that we still run on the same CPU as the MCE occurred on.
3013 * We pass a fake environment to the machine check handler because we want
3014 * the guest to be always treated like user space, no matter what context
3015 * it used internally.
3017 static void kvm_machine_check(void)
3019 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3020 struct pt_regs regs
= {
3021 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
3022 .flags
= X86_EFLAGS_IF
,
3025 do_machine_check(®s
, 0);
3029 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
3031 /* already handled by vcpu_run */
3035 static int handle_exception(struct kvm_vcpu
*vcpu
)
3037 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3038 struct kvm_run
*kvm_run
= vcpu
->run
;
3039 u32 intr_info
, ex_no
, error_code
;
3040 unsigned long cr2
, rip
, dr6
;
3042 enum emulation_result er
;
3044 vect_info
= vmx
->idt_vectoring_info
;
3045 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
3047 if (is_machine_check(intr_info
))
3048 return handle_machine_check(vcpu
);
3050 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
3051 !is_page_fault(intr_info
)) {
3052 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
3053 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
3054 vcpu
->run
->internal
.ndata
= 2;
3055 vcpu
->run
->internal
.data
[0] = vect_info
;
3056 vcpu
->run
->internal
.data
[1] = intr_info
;
3060 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
3061 return 1; /* already handled by vmx_vcpu_run() */
3063 if (is_no_device(intr_info
)) {
3064 vmx_fpu_activate(vcpu
);
3068 if (is_invalid_opcode(intr_info
)) {
3069 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
3070 if (er
!= EMULATE_DONE
)
3071 kvm_queue_exception(vcpu
, UD_VECTOR
);
3076 rip
= kvm_rip_read(vcpu
);
3077 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
3078 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
3079 if (is_page_fault(intr_info
)) {
3080 /* EPT won't cause page fault directly */
3083 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
3084 trace_kvm_page_fault(cr2
, error_code
);
3086 if (kvm_event_needs_reinjection(vcpu
))
3087 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
3088 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
3091 if (vmx
->rmode
.vm86_active
&&
3092 handle_rmode_exception(vcpu
, intr_info
& INTR_INFO_VECTOR_MASK
,
3094 if (vcpu
->arch
.halt_request
) {
3095 vcpu
->arch
.halt_request
= 0;
3096 return kvm_emulate_halt(vcpu
);
3101 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
3104 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
3105 if (!(vcpu
->guest_debug
&
3106 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
3107 vcpu
->arch
.dr6
= dr6
| DR6_FIXED_1
;
3108 kvm_queue_exception(vcpu
, DB_VECTOR
);
3111 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
3112 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
3116 * Update instruction length as we may reinject #BP from
3117 * user space while in guest debugging mode. Reading it for
3118 * #DB as well causes no harm, it is not used in that case.
3120 vmx
->vcpu
.arch
.event_exit_inst_len
=
3121 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
3122 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
3123 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
3124 kvm_run
->debug
.arch
.exception
= ex_no
;
3127 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
3128 kvm_run
->ex
.exception
= ex_no
;
3129 kvm_run
->ex
.error_code
= error_code
;
3135 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
3137 ++vcpu
->stat
.irq_exits
;
3141 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
3143 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
3147 static int handle_io(struct kvm_vcpu
*vcpu
)
3149 unsigned long exit_qualification
;
3150 int size
, in
, string
;
3153 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3154 string
= (exit_qualification
& 16) != 0;
3155 in
= (exit_qualification
& 8) != 0;
3157 ++vcpu
->stat
.io_exits
;
3160 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
3162 port
= exit_qualification
>> 16;
3163 size
= (exit_qualification
& 7) + 1;
3164 skip_emulated_instruction(vcpu
);
3166 return kvm_fast_pio_out(vcpu
, size
, port
);
3170 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
3173 * Patch in the VMCALL instruction:
3175 hypercall
[0] = 0x0f;
3176 hypercall
[1] = 0x01;
3177 hypercall
[2] = 0xc1;
3180 static int handle_cr(struct kvm_vcpu
*vcpu
)
3182 unsigned long exit_qualification
, val
;
3187 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3188 cr
= exit_qualification
& 15;
3189 reg
= (exit_qualification
>> 8) & 15;
3190 switch ((exit_qualification
>> 4) & 3) {
3191 case 0: /* mov to cr */
3192 val
= kvm_register_read(vcpu
, reg
);
3193 trace_kvm_cr_write(cr
, val
);
3196 err
= kvm_set_cr0(vcpu
, val
);
3197 kvm_complete_insn_gp(vcpu
, err
);
3200 err
= kvm_set_cr3(vcpu
, val
);
3201 kvm_complete_insn_gp(vcpu
, err
);
3204 err
= kvm_set_cr4(vcpu
, val
);
3205 kvm_complete_insn_gp(vcpu
, err
);
3208 u8 cr8_prev
= kvm_get_cr8(vcpu
);
3209 u8 cr8
= kvm_register_read(vcpu
, reg
);
3210 err
= kvm_set_cr8(vcpu
, cr8
);
3211 kvm_complete_insn_gp(vcpu
, err
);
3212 if (irqchip_in_kernel(vcpu
->kvm
))
3214 if (cr8_prev
<= cr8
)
3216 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
3222 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
3223 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
3224 skip_emulated_instruction(vcpu
);
3225 vmx_fpu_activate(vcpu
);
3227 case 1: /*mov from cr*/
3230 kvm_register_write(vcpu
, reg
, vcpu
->arch
.cr3
);
3231 trace_kvm_cr_read(cr
, vcpu
->arch
.cr3
);
3232 skip_emulated_instruction(vcpu
);
3235 val
= kvm_get_cr8(vcpu
);
3236 kvm_register_write(vcpu
, reg
, val
);
3237 trace_kvm_cr_read(cr
, val
);
3238 skip_emulated_instruction(vcpu
);
3243 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
3244 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
3245 kvm_lmsw(vcpu
, val
);
3247 skip_emulated_instruction(vcpu
);
3252 vcpu
->run
->exit_reason
= 0;
3253 pr_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
3254 (int)(exit_qualification
>> 4) & 3, cr
);
3258 static int handle_dr(struct kvm_vcpu
*vcpu
)
3260 unsigned long exit_qualification
;
3263 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3264 if (!kvm_require_cpl(vcpu
, 0))
3266 dr
= vmcs_readl(GUEST_DR7
);
3269 * As the vm-exit takes precedence over the debug trap, we
3270 * need to emulate the latter, either for the host or the
3271 * guest debugging itself.
3273 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
3274 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
3275 vcpu
->run
->debug
.arch
.dr7
= dr
;
3276 vcpu
->run
->debug
.arch
.pc
=
3277 vmcs_readl(GUEST_CS_BASE
) +
3278 vmcs_readl(GUEST_RIP
);
3279 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
3280 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
3283 vcpu
->arch
.dr7
&= ~DR7_GD
;
3284 vcpu
->arch
.dr6
|= DR6_BD
;
3285 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
3286 kvm_queue_exception(vcpu
, DB_VECTOR
);
3291 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3292 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
3293 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
3294 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
3296 if (!kvm_get_dr(vcpu
, dr
, &val
))
3297 kvm_register_write(vcpu
, reg
, val
);
3299 kvm_set_dr(vcpu
, dr
, vcpu
->arch
.regs
[reg
]);
3300 skip_emulated_instruction(vcpu
);
3304 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
3306 vmcs_writel(GUEST_DR7
, val
);
3309 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
3311 kvm_emulate_cpuid(vcpu
);
3315 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
3317 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
3320 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
3321 trace_kvm_msr_read_ex(ecx
);
3322 kvm_inject_gp(vcpu
, 0);
3326 trace_kvm_msr_read(ecx
, data
);
3328 /* FIXME: handling of bits 32:63 of rax, rdx */
3329 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
3330 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
3331 skip_emulated_instruction(vcpu
);
3335 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
3337 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
3338 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
3339 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
3341 if (vmx_set_msr(vcpu
, ecx
, data
) != 0) {
3342 trace_kvm_msr_write_ex(ecx
, data
);
3343 kvm_inject_gp(vcpu
, 0);
3347 trace_kvm_msr_write(ecx
, data
);
3348 skip_emulated_instruction(vcpu
);
3352 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
3354 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
3358 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
3360 u32 cpu_based_vm_exec_control
;
3362 /* clear pending irq */
3363 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
3364 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
3365 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
3367 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
3369 ++vcpu
->stat
.irq_window_exits
;
3372 * If the user space waits to inject interrupts, exit as soon as
3375 if (!irqchip_in_kernel(vcpu
->kvm
) &&
3376 vcpu
->run
->request_interrupt_window
&&
3377 !kvm_cpu_has_interrupt(vcpu
)) {
3378 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
3384 static int handle_halt(struct kvm_vcpu
*vcpu
)
3386 skip_emulated_instruction(vcpu
);
3387 return kvm_emulate_halt(vcpu
);
3390 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
3392 skip_emulated_instruction(vcpu
);
3393 kvm_emulate_hypercall(vcpu
);
3397 static int handle_vmx_insn(struct kvm_vcpu
*vcpu
)
3399 kvm_queue_exception(vcpu
, UD_VECTOR
);
3403 static int handle_invd(struct kvm_vcpu
*vcpu
)
3405 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
3408 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
3410 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3412 kvm_mmu_invlpg(vcpu
, exit_qualification
);
3413 skip_emulated_instruction(vcpu
);
3417 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
3419 skip_emulated_instruction(vcpu
);
3420 kvm_emulate_wbinvd(vcpu
);
3424 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
3426 u64 new_bv
= kvm_read_edx_eax(vcpu
);
3427 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
3429 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
3430 skip_emulated_instruction(vcpu
);
3434 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
3436 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
3439 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
3441 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3442 unsigned long exit_qualification
;
3443 bool has_error_code
= false;
3446 int reason
, type
, idt_v
;
3448 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
3449 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
3451 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3453 reason
= (u32
)exit_qualification
>> 30;
3454 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
3456 case INTR_TYPE_NMI_INTR
:
3457 vcpu
->arch
.nmi_injected
= false;
3458 if (cpu_has_virtual_nmis())
3459 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
3460 GUEST_INTR_STATE_NMI
);
3462 case INTR_TYPE_EXT_INTR
:
3463 case INTR_TYPE_SOFT_INTR
:
3464 kvm_clear_interrupt_queue(vcpu
);
3466 case INTR_TYPE_HARD_EXCEPTION
:
3467 if (vmx
->idt_vectoring_info
&
3468 VECTORING_INFO_DELIVER_CODE_MASK
) {
3469 has_error_code
= true;
3471 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
3474 case INTR_TYPE_SOFT_EXCEPTION
:
3475 kvm_clear_exception_queue(vcpu
);
3481 tss_selector
= exit_qualification
;
3483 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
3484 type
!= INTR_TYPE_EXT_INTR
&&
3485 type
!= INTR_TYPE_NMI_INTR
))
3486 skip_emulated_instruction(vcpu
);
3488 if (kvm_task_switch(vcpu
, tss_selector
, reason
,
3489 has_error_code
, error_code
) == EMULATE_FAIL
) {
3490 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
3491 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
3492 vcpu
->run
->internal
.ndata
= 0;
3496 /* clear all local breakpoint enable flags */
3497 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~55);
3500 * TODO: What about debug traps on tss switch?
3501 * Are we supposed to inject them and update dr6?
3507 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
3509 unsigned long exit_qualification
;
3513 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3515 if (exit_qualification
& (1 << 6)) {
3516 printk(KERN_ERR
"EPT: GPA exceeds GAW!\n");
3520 gla_validity
= (exit_qualification
>> 7) & 0x3;
3521 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
3522 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
3523 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3524 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
3525 vmcs_readl(GUEST_LINEAR_ADDRESS
));
3526 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
3527 (long unsigned int)exit_qualification
);
3528 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3529 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
3533 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
3534 trace_kvm_page_fault(gpa
, exit_qualification
);
3535 return kvm_mmu_page_fault(vcpu
, gpa
, exit_qualification
& 0x3, NULL
, 0);
3538 static u64
ept_rsvd_mask(u64 spte
, int level
)
3543 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
3544 mask
|= (1ULL << i
);
3547 /* bits 7:3 reserved */
3549 else if (level
== 2) {
3550 if (spte
& (1ULL << 7))
3551 /* 2MB ref, bits 20:12 reserved */
3554 /* bits 6:3 reserved */
3561 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
3564 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
3566 /* 010b (write-only) */
3567 WARN_ON((spte
& 0x7) == 0x2);
3569 /* 110b (write/execute) */
3570 WARN_ON((spte
& 0x7) == 0x6);
3572 /* 100b (execute-only) and value not supported by logical processor */
3573 if (!cpu_has_vmx_ept_execute_only())
3574 WARN_ON((spte
& 0x7) == 0x4);
3578 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
3580 if (rsvd_bits
!= 0) {
3581 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
3582 __func__
, rsvd_bits
);
3586 if (level
== 1 || (level
== 2 && (spte
& (1ULL << 7)))) {
3587 u64 ept_mem_type
= (spte
& 0x38) >> 3;
3589 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
3590 ept_mem_type
== 7) {
3591 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
3592 __func__
, ept_mem_type
);
3599 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
3605 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
3607 printk(KERN_ERR
"EPT: Misconfiguration.\n");
3608 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
3610 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
3612 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
3613 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
3615 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3616 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
3621 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
3623 u32 cpu_based_vm_exec_control
;
3625 /* clear pending NMI */
3626 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
3627 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
3628 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
3629 ++vcpu
->stat
.nmi_window_exits
;
3630 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
3635 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
3637 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3638 enum emulation_result err
= EMULATE_DONE
;
3641 bool intr_window_requested
;
3643 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
3644 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
3646 while (!guest_state_valid(vcpu
)) {
3647 if (intr_window_requested
3648 && (kvm_get_rflags(&vmx
->vcpu
) & X86_EFLAGS_IF
))
3649 return handle_interrupt_window(&vmx
->vcpu
);
3651 err
= emulate_instruction(vcpu
, 0);
3653 if (err
== EMULATE_DO_MMIO
) {
3658 if (err
!= EMULATE_DONE
)
3661 if (signal_pending(current
))
3667 vmx
->emulation_required
= 0;
3673 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3674 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3676 static int handle_pause(struct kvm_vcpu
*vcpu
)
3678 skip_emulated_instruction(vcpu
);
3679 kvm_vcpu_on_spin(vcpu
);
3684 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
3686 kvm_queue_exception(vcpu
, UD_VECTOR
);
3691 * The exit handlers return 1 if the exit was handled fully and guest execution
3692 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3693 * to be done to userspace and return 0.
3695 static int (*kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
3696 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
3697 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
3698 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
3699 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
3700 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
3701 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
3702 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
3703 [EXIT_REASON_CPUID
] = handle_cpuid
,
3704 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
3705 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
3706 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
3707 [EXIT_REASON_HLT
] = handle_halt
,
3708 [EXIT_REASON_INVD
] = handle_invd
,
3709 [EXIT_REASON_INVLPG
] = handle_invlpg
,
3710 [EXIT_REASON_VMCALL
] = handle_vmcall
,
3711 [EXIT_REASON_VMCLEAR
] = handle_vmx_insn
,
3712 [EXIT_REASON_VMLAUNCH
] = handle_vmx_insn
,
3713 [EXIT_REASON_VMPTRLD
] = handle_vmx_insn
,
3714 [EXIT_REASON_VMPTRST
] = handle_vmx_insn
,
3715 [EXIT_REASON_VMREAD
] = handle_vmx_insn
,
3716 [EXIT_REASON_VMRESUME
] = handle_vmx_insn
,
3717 [EXIT_REASON_VMWRITE
] = handle_vmx_insn
,
3718 [EXIT_REASON_VMOFF
] = handle_vmx_insn
,
3719 [EXIT_REASON_VMON
] = handle_vmx_insn
,
3720 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
3721 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
3722 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
3723 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
3724 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
3725 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
3726 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
3727 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
3728 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
3729 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_invalid_op
,
3730 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_invalid_op
,
3733 static const int kvm_vmx_max_exit_handlers
=
3734 ARRAY_SIZE(kvm_vmx_exit_handlers
);
3736 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
3738 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
3739 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
3743 * The guest has exited. See if we can fix it or if we need userspace
3746 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
3748 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3749 u32 exit_reason
= vmx
->exit_reason
;
3750 u32 vectoring_info
= vmx
->idt_vectoring_info
;
3752 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
3754 /* If guest state is invalid, start emulating */
3755 if (vmx
->emulation_required
&& emulate_invalid_guest_state
)
3756 return handle_invalid_guest_state(vcpu
);
3758 /* Access CR3 don't cause VMExit in paging mode, so we need
3759 * to sync with guest real CR3. */
3760 if (enable_ept
&& is_paging(vcpu
))
3761 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3763 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
3764 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
3765 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
3770 if (unlikely(vmx
->fail
)) {
3771 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
3772 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
3773 = vmcs_read32(VM_INSTRUCTION_ERROR
);
3777 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
3778 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
3779 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
3780 exit_reason
!= EXIT_REASON_TASK_SWITCH
))
3781 printk(KERN_WARNING
"%s: unexpected, valid vectoring info "
3782 "(0x%x) and exit reason is 0x%x\n",
3783 __func__
, vectoring_info
, exit_reason
);
3785 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
)) {
3786 if (vmx_interrupt_allowed(vcpu
)) {
3787 vmx
->soft_vnmi_blocked
= 0;
3788 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
3789 vcpu
->arch
.nmi_pending
) {
3791 * This CPU don't support us in finding the end of an
3792 * NMI-blocked window if the guest runs with IRQs
3793 * disabled. So we pull the trigger after 1 s of
3794 * futile waiting, but inform the user about this.
3796 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
3797 "state on VCPU %d after 1 s timeout\n",
3798 __func__
, vcpu
->vcpu_id
);
3799 vmx
->soft_vnmi_blocked
= 0;
3803 if (exit_reason
< kvm_vmx_max_exit_handlers
3804 && kvm_vmx_exit_handlers
[exit_reason
])
3805 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
3807 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3808 vcpu
->run
->hw
.hardware_exit_reason
= exit_reason
;
3813 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
3815 if (irr
== -1 || tpr
< irr
) {
3816 vmcs_write32(TPR_THRESHOLD
, 0);
3820 vmcs_write32(TPR_THRESHOLD
, irr
);
3823 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
3825 u32 exit_intr_info
= vmx
->exit_intr_info
;
3827 /* Handle machine checks before interrupts are enabled */
3828 if ((vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
)
3829 || (vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
3830 && is_machine_check(exit_intr_info
)))
3831 kvm_machine_check();
3833 /* We need to handle NMIs before interrupts are enabled */
3834 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
3835 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
3836 kvm_before_handle_nmi(&vmx
->vcpu
);
3838 kvm_after_handle_nmi(&vmx
->vcpu
);
3842 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
3844 u32 exit_intr_info
= vmx
->exit_intr_info
;
3847 bool idtv_info_valid
;
3849 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
3851 if (cpu_has_virtual_nmis()) {
3852 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
3853 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
3855 * SDM 3: 27.7.1.2 (September 2008)
3856 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3857 * a guest IRET fault.
3858 * SDM 3: 23.2.2 (September 2008)
3859 * Bit 12 is undefined in any of the following cases:
3860 * If the VM exit sets the valid bit in the IDT-vectoring
3861 * information field.
3862 * If the VM exit is due to a double fault.
3864 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
3865 vector
!= DF_VECTOR
&& !idtv_info_valid
)
3866 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
3867 GUEST_INTR_STATE_NMI
);
3868 } else if (unlikely(vmx
->soft_vnmi_blocked
))
3869 vmx
->vnmi_blocked_time
+=
3870 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
3873 static void __vmx_complete_interrupts(struct vcpu_vmx
*vmx
,
3874 u32 idt_vectoring_info
,
3875 int instr_len_field
,
3876 int error_code_field
)
3880 bool idtv_info_valid
;
3882 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
3884 vmx
->vcpu
.arch
.nmi_injected
= false;
3885 kvm_clear_exception_queue(&vmx
->vcpu
);
3886 kvm_clear_interrupt_queue(&vmx
->vcpu
);
3888 if (!idtv_info_valid
)
3891 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
3893 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
3894 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
3897 case INTR_TYPE_NMI_INTR
:
3898 vmx
->vcpu
.arch
.nmi_injected
= true;
3900 * SDM 3: 27.7.1.2 (September 2008)
3901 * Clear bit "block by NMI" before VM entry if a NMI
3904 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
3905 GUEST_INTR_STATE_NMI
);
3907 case INTR_TYPE_SOFT_EXCEPTION
:
3908 vmx
->vcpu
.arch
.event_exit_inst_len
=
3909 vmcs_read32(instr_len_field
);
3911 case INTR_TYPE_HARD_EXCEPTION
:
3912 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
3913 u32 err
= vmcs_read32(error_code_field
);
3914 kvm_queue_exception_e(&vmx
->vcpu
, vector
, err
);
3916 kvm_queue_exception(&vmx
->vcpu
, vector
);
3918 case INTR_TYPE_SOFT_INTR
:
3919 vmx
->vcpu
.arch
.event_exit_inst_len
=
3920 vmcs_read32(instr_len_field
);
3922 case INTR_TYPE_EXT_INTR
:
3923 kvm_queue_interrupt(&vmx
->vcpu
, vector
,
3924 type
== INTR_TYPE_SOFT_INTR
);
3931 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
3933 __vmx_complete_interrupts(vmx
, vmx
->idt_vectoring_info
,
3934 VM_EXIT_INSTRUCTION_LEN
,
3935 IDT_VECTORING_ERROR_CODE
);
3938 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
3940 __vmx_complete_interrupts(to_vmx(vcpu
),
3941 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
3942 VM_ENTRY_INSTRUCTION_LEN
,
3943 VM_ENTRY_EXCEPTION_ERROR_CODE
);
3945 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
3948 #ifdef CONFIG_X86_64
3956 static void vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
3958 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3960 /* Record the guest's net vcpu time for enforced NMI injections. */
3961 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
3962 vmx
->entry_time
= ktime_get();
3964 /* Don't enter VMX if guest state is invalid, let the exit handler
3965 start emulation until we arrive back to a valid state */
3966 if (vmx
->emulation_required
&& emulate_invalid_guest_state
)
3969 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
3970 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
3971 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
3972 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
3974 /* When single-stepping over STI and MOV SS, we must clear the
3975 * corresponding interruptibility bits in the guest state. Otherwise
3976 * vmentry fails as it then expects bit 14 (BS) in pending debug
3977 * exceptions being set, but that's not correct for the guest debugging
3979 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
3980 vmx_set_interrupt_shadow(vcpu
, 0);
3983 /* Store host registers */
3984 "push %%"R
"dx; push %%"R
"bp;"
3986 "cmp %%"R
"sp, %c[host_rsp](%0) \n\t"
3988 "mov %%"R
"sp, %c[host_rsp](%0) \n\t"
3989 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
3991 /* Reload cr2 if changed */
3992 "mov %c[cr2](%0), %%"R
"ax \n\t"
3993 "mov %%cr2, %%"R
"dx \n\t"
3994 "cmp %%"R
"ax, %%"R
"dx \n\t"
3996 "mov %%"R
"ax, %%cr2 \n\t"
3998 /* Check if vmlaunch of vmresume is needed */
3999 "cmpl $0, %c[launched](%0) \n\t"
4000 /* Load guest registers. Don't clobber flags. */
4001 "mov %c[rax](%0), %%"R
"ax \n\t"
4002 "mov %c[rbx](%0), %%"R
"bx \n\t"
4003 "mov %c[rdx](%0), %%"R
"dx \n\t"
4004 "mov %c[rsi](%0), %%"R
"si \n\t"
4005 "mov %c[rdi](%0), %%"R
"di \n\t"
4006 "mov %c[rbp](%0), %%"R
"bp \n\t"
4007 #ifdef CONFIG_X86_64
4008 "mov %c[r8](%0), %%r8 \n\t"
4009 "mov %c[r9](%0), %%r9 \n\t"
4010 "mov %c[r10](%0), %%r10 \n\t"
4011 "mov %c[r11](%0), %%r11 \n\t"
4012 "mov %c[r12](%0), %%r12 \n\t"
4013 "mov %c[r13](%0), %%r13 \n\t"
4014 "mov %c[r14](%0), %%r14 \n\t"
4015 "mov %c[r15](%0), %%r15 \n\t"
4017 "mov %c[rcx](%0), %%"R
"cx \n\t" /* kills %0 (ecx) */
4019 /* Enter guest mode */
4020 "jne .Llaunched \n\t"
4021 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
4022 "jmp .Lkvm_vmx_return \n\t"
4023 ".Llaunched: " __ex(ASM_VMX_VMRESUME
) "\n\t"
4024 ".Lkvm_vmx_return: "
4025 /* Save guest registers, load host registers, keep flags */
4026 "xchg %0, (%%"R
"sp) \n\t"
4027 "mov %%"R
"ax, %c[rax](%0) \n\t"
4028 "mov %%"R
"bx, %c[rbx](%0) \n\t"
4029 "push"Q
" (%%"R
"sp); pop"Q
" %c[rcx](%0) \n\t"
4030 "mov %%"R
"dx, %c[rdx](%0) \n\t"
4031 "mov %%"R
"si, %c[rsi](%0) \n\t"
4032 "mov %%"R
"di, %c[rdi](%0) \n\t"
4033 "mov %%"R
"bp, %c[rbp](%0) \n\t"
4034 #ifdef CONFIG_X86_64
4035 "mov %%r8, %c[r8](%0) \n\t"
4036 "mov %%r9, %c[r9](%0) \n\t"
4037 "mov %%r10, %c[r10](%0) \n\t"
4038 "mov %%r11, %c[r11](%0) \n\t"
4039 "mov %%r12, %c[r12](%0) \n\t"
4040 "mov %%r13, %c[r13](%0) \n\t"
4041 "mov %%r14, %c[r14](%0) \n\t"
4042 "mov %%r15, %c[r15](%0) \n\t"
4044 "mov %%cr2, %%"R
"ax \n\t"
4045 "mov %%"R
"ax, %c[cr2](%0) \n\t"
4047 "pop %%"R
"bp; pop %%"R
"bp; pop %%"R
"dx \n\t"
4048 "setbe %c[fail](%0) \n\t"
4049 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
4050 [launched
]"i"(offsetof(struct vcpu_vmx
, launched
)),
4051 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
4052 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
4053 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
4054 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
4055 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
4056 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
4057 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
4058 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
4059 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
4060 #ifdef CONFIG_X86_64
4061 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
4062 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
4063 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
4064 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
4065 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
4066 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
4067 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
4068 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
4070 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
))
4072 , R
"ax", R
"bx", R
"di", R
"si"
4073 #ifdef CONFIG_X86_64
4074 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4078 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
4079 | (1 << VCPU_EXREG_PDPTR
));
4080 vcpu
->arch
.regs_dirty
= 0;
4082 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
4084 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS
));
4087 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
4088 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
4090 vmx_complete_atomic_exit(vmx
);
4091 vmx_recover_nmi_blocking(vmx
);
4092 vmx_complete_interrupts(vmx
);
4098 static void vmx_free_vmcs(struct kvm_vcpu
*vcpu
)
4100 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4104 free_vmcs(vmx
->vmcs
);
4109 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
4111 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4114 vmx_free_vmcs(vcpu
);
4115 kfree(vmx
->guest_msrs
);
4116 kvm_vcpu_uninit(vcpu
);
4117 kmem_cache_free(kvm_vcpu_cache
, vmx
);
4120 static inline void vmcs_init(struct vmcs
*vmcs
)
4122 u64 phys_addr
= __pa(per_cpu(vmxarea
, raw_smp_processor_id()));
4125 kvm_cpu_vmxon(phys_addr
);
4133 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
4136 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
4140 return ERR_PTR(-ENOMEM
);
4144 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
4148 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
4149 if (!vmx
->guest_msrs
) {
4154 vmx
->vmcs
= alloc_vmcs();
4158 vmcs_init(vmx
->vmcs
);
4161 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
4162 vmx
->vcpu
.cpu
= cpu
;
4163 err
= vmx_vcpu_setup(vmx
);
4164 vmx_vcpu_put(&vmx
->vcpu
);
4168 if (vm_need_virtualize_apic_accesses(kvm
))
4169 if (alloc_apic_access_page(kvm
) != 0)
4173 if (!kvm
->arch
.ept_identity_map_addr
)
4174 kvm
->arch
.ept_identity_map_addr
=
4175 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
4176 if (alloc_identity_pagetable(kvm
) != 0)
4183 free_vmcs(vmx
->vmcs
);
4185 kfree(vmx
->guest_msrs
);
4187 kvm_vcpu_uninit(&vmx
->vcpu
);
4190 kmem_cache_free(kvm_vcpu_cache
, vmx
);
4191 return ERR_PTR(err
);
4194 static void __init
vmx_check_processor_compat(void *rtn
)
4196 struct vmcs_config vmcs_conf
;
4199 if (setup_vmcs_config(&vmcs_conf
) < 0)
4201 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
4202 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
4203 smp_processor_id());
4208 static int get_ept_level(void)
4210 return VMX_EPT_DEFAULT_GAW
+ 1;
4213 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
4217 /* For VT-d and EPT combination
4218 * 1. MMIO: always map as UC
4220 * a. VT-d without snooping control feature: can't guarantee the
4221 * result, try to trust guest.
4222 * b. VT-d with snooping control feature: snooping control feature of
4223 * VT-d engine can guarantee the cache correctness. Just set it
4224 * to WB to keep consistent with host. So the same as item 3.
4225 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4226 * consistent with host MTRR
4229 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
4230 else if (vcpu
->kvm
->arch
.iommu_domain
&&
4231 !(vcpu
->kvm
->arch
.iommu_flags
& KVM_IOMMU_CACHE_COHERENCY
))
4232 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
4233 VMX_EPT_MT_EPTE_SHIFT
;
4235 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
4241 #define _ER(x) { EXIT_REASON_##x, #x }
4243 static const struct trace_print_flags vmx_exit_reasons_str
[] = {
4245 _ER(EXTERNAL_INTERRUPT
),
4247 _ER(PENDING_INTERRUPT
),
4267 _ER(IO_INSTRUCTION
),
4270 _ER(MWAIT_INSTRUCTION
),
4271 _ER(MONITOR_INSTRUCTION
),
4272 _ER(PAUSE_INSTRUCTION
),
4273 _ER(MCE_DURING_VMENTRY
),
4274 _ER(TPR_BELOW_THRESHOLD
),
4284 static int vmx_get_lpage_level(void)
4286 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
4287 return PT_DIRECTORY_LEVEL
;
4289 /* For shadow and EPT supported 1GB page */
4290 return PT_PDPE_LEVEL
;
4293 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
4295 struct kvm_cpuid_entry2
*best
;
4296 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4299 vmx
->rdtscp_enabled
= false;
4300 if (vmx_rdtscp_supported()) {
4301 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
4302 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
4303 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
4304 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
4305 vmx
->rdtscp_enabled
= true;
4307 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
4308 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4315 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
4319 static struct kvm_x86_ops vmx_x86_ops
= {
4320 .cpu_has_kvm_support
= cpu_has_kvm_support
,
4321 .disabled_by_bios
= vmx_disabled_by_bios
,
4322 .hardware_setup
= hardware_setup
,
4323 .hardware_unsetup
= hardware_unsetup
,
4324 .check_processor_compatibility
= vmx_check_processor_compat
,
4325 .hardware_enable
= hardware_enable
,
4326 .hardware_disable
= hardware_disable
,
4327 .cpu_has_accelerated_tpr
= report_flexpriority
,
4329 .vcpu_create
= vmx_create_vcpu
,
4330 .vcpu_free
= vmx_free_vcpu
,
4331 .vcpu_reset
= vmx_vcpu_reset
,
4333 .prepare_guest_switch
= vmx_save_host_state
,
4334 .vcpu_load
= vmx_vcpu_load
,
4335 .vcpu_put
= vmx_vcpu_put
,
4337 .set_guest_debug
= set_guest_debug
,
4338 .get_msr
= vmx_get_msr
,
4339 .set_msr
= vmx_set_msr
,
4340 .get_segment_base
= vmx_get_segment_base
,
4341 .get_segment
= vmx_get_segment
,
4342 .set_segment
= vmx_set_segment
,
4343 .get_cpl
= vmx_get_cpl
,
4344 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
4345 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
4346 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
4347 .set_cr0
= vmx_set_cr0
,
4348 .set_cr3
= vmx_set_cr3
,
4349 .set_cr4
= vmx_set_cr4
,
4350 .set_efer
= vmx_set_efer
,
4351 .get_idt
= vmx_get_idt
,
4352 .set_idt
= vmx_set_idt
,
4353 .get_gdt
= vmx_get_gdt
,
4354 .set_gdt
= vmx_set_gdt
,
4355 .set_dr7
= vmx_set_dr7
,
4356 .cache_reg
= vmx_cache_reg
,
4357 .get_rflags
= vmx_get_rflags
,
4358 .set_rflags
= vmx_set_rflags
,
4359 .fpu_activate
= vmx_fpu_activate
,
4360 .fpu_deactivate
= vmx_fpu_deactivate
,
4362 .tlb_flush
= vmx_flush_tlb
,
4364 .run
= vmx_vcpu_run
,
4365 .handle_exit
= vmx_handle_exit
,
4366 .skip_emulated_instruction
= skip_emulated_instruction
,
4367 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
4368 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
4369 .patch_hypercall
= vmx_patch_hypercall
,
4370 .set_irq
= vmx_inject_irq
,
4371 .set_nmi
= vmx_inject_nmi
,
4372 .queue_exception
= vmx_queue_exception
,
4373 .cancel_injection
= vmx_cancel_injection
,
4374 .interrupt_allowed
= vmx_interrupt_allowed
,
4375 .nmi_allowed
= vmx_nmi_allowed
,
4376 .get_nmi_mask
= vmx_get_nmi_mask
,
4377 .set_nmi_mask
= vmx_set_nmi_mask
,
4378 .enable_nmi_window
= enable_nmi_window
,
4379 .enable_irq_window
= enable_irq_window
,
4380 .update_cr8_intercept
= update_cr8_intercept
,
4382 .set_tss_addr
= vmx_set_tss_addr
,
4383 .get_tdp_level
= get_ept_level
,
4384 .get_mt_mask
= vmx_get_mt_mask
,
4386 .get_exit_info
= vmx_get_exit_info
,
4387 .exit_reasons_str
= vmx_exit_reasons_str
,
4389 .get_lpage_level
= vmx_get_lpage_level
,
4391 .cpuid_update
= vmx_cpuid_update
,
4393 .rdtscp_supported
= vmx_rdtscp_supported
,
4395 .set_supported_cpuid
= vmx_set_supported_cpuid
,
4397 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
4399 .write_tsc_offset
= vmx_write_tsc_offset
,
4400 .adjust_tsc_offset
= vmx_adjust_tsc_offset
,
4402 .set_tdp_cr3
= vmx_set_cr3
,
4405 static int __init
vmx_init(void)
4409 rdmsrl_safe(MSR_EFER
, &host_efer
);
4411 for (i
= 0; i
< NR_VMX_MSR
; ++i
)
4412 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
4414 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
4415 if (!vmx_io_bitmap_a
)
4418 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
4419 if (!vmx_io_bitmap_b
) {
4424 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
4425 if (!vmx_msr_bitmap_legacy
) {
4430 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
4431 if (!vmx_msr_bitmap_longmode
) {
4437 * Allow direct access to the PC debug port (it is often used for I/O
4438 * delays, but the vmexits simply slow things down).
4440 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
4441 clear_bit(0x80, vmx_io_bitmap_a
);
4443 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
4445 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
4446 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
4448 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
4450 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
4451 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
4455 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
4456 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
4457 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
4458 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
4459 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
4460 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
4463 bypass_guest_pf
= 0;
4464 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4465 VMX_EPT_EXECUTABLE_MASK
);
4470 if (bypass_guest_pf
)
4471 kvm_mmu_set_nonpresent_ptes(~0xffeull
, 0ull);
4476 free_page((unsigned long)vmx_msr_bitmap_longmode
);
4478 free_page((unsigned long)vmx_msr_bitmap_legacy
);
4480 free_page((unsigned long)vmx_io_bitmap_b
);
4482 free_page((unsigned long)vmx_io_bitmap_a
);
4486 static void __exit
vmx_exit(void)
4488 free_page((unsigned long)vmx_msr_bitmap_legacy
);
4489 free_page((unsigned long)vmx_msr_bitmap_longmode
);
4490 free_page((unsigned long)vmx_io_bitmap_b
);
4491 free_page((unsigned long)vmx_io_bitmap_a
);
4496 module_init(vmx_init
)
4497 module_exit(vmx_exit
)