| blob | 1e6d9cc06ca0198133445dc0163758f766928888 |
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 *
12 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
13 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
14 *
15 * This file contains the low-level support and setup for the
16 * PowerPC-64 platform, including trap and interrupt dispatch.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version
21 * 2 of the License, or (at your option) any later version.
22 */
24 #include <linux/threads.h>
25 #include <asm/reg.h>
26 #include <asm/page.h>
27 #include <asm/mmu.h>
28 #include <asm/ppc_asm.h>
29 #include <asm/asm-offsets.h>
30 #include <asm/bug.h>
31 #include <asm/cputable.h>
32 #include <asm/setup.h>
33 #include <asm/hvcall.h>
34 #include <asm/iseries/lpar_map.h>
35 #include <asm/thread_info.h>
36 #include <asm/firmware.h>
37 #include <asm/page_64.h>
39 #define DO_SOFT_DISABLE
41 /*
42 * We layout physical memory as follows:
43 * 0x0000 - 0x00ff : Secondary processor spin code
44 * 0x0100 - 0x2fff : pSeries Interrupt prologs
45 * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs
46 * 0x6000 - 0x6fff : Initial (CPU0) segment table
47 * 0x7000 - 0x7fff : FWNMI data area
48 * 0x8000 - : Early init and support code
49 */
51 /*
52 * SPRG Usage
53 *
54 * Register Definition
55 *
56 * SPRG0 reserved for hypervisor
57 * SPRG1 temp - used to save gpr
58 * SPRG2 temp - used to save gpr
59 * SPRG3 virt addr of paca
60 */
62 /*
63 * Entering into this code we make the following assumptions:
64 * For pSeries:
65 * 1. The MMU is off & open firmware is running in real mode.
66 * 2. The kernel is entered at __start
67 *
68 * For iSeries:
69 * 1. The MMU is on (as it always is for iSeries)
70 * 2. The kernel is entered at system_reset_iSeries
71 */
73 .text
74 .globl _stext
75 _stext:
76 _GLOBAL(__start)
77 /* NOP this out unconditionally */
78 BEGIN_FTR_SECTION
79 b .__start_initialization_multiplatform
80 END_FTR_SECTION(0, 1)
82 /* Catch branch to 0 in real mode */
83 trap
85 /* Secondary processors spin on this value until it goes to 1. */
86 .globl __secondary_hold_spinloop
87 __secondary_hold_spinloop:
88 .llong 0x0
90 /* Secondary processors write this value with their cpu # */
91 /* after they enter the spin loop immediately below. */
92 .globl __secondary_hold_acknowledge
93 __secondary_hold_acknowledge:
94 .llong 0x0
96 #ifdef CONFIG_PPC_ISERIES
97 /*
98 * At offset 0x20, there is a pointer to iSeries LPAR data.
99 * This is required by the hypervisor
100 */
101 . = 0x20
102 .llong hvReleaseData-KERNELBASE
103 #endif /* CONFIG_PPC_ISERIES */
105 . = 0x60
106 /*
107 * The following code is used to hold secondary processors
108 * in a spin loop after they have entered the kernel, but
109 * before the bulk of the kernel has been relocated. This code
110 * is relocated to physical address 0x60 before prom_init is run.
111 * All of it must fit below the first exception vector at 0x100.
112 */
113 _GLOBAL(__secondary_hold)
114 mfmsr r24
115 ori r24,r24,MSR_RI
116 mtmsrd r24 /* RI on */
118 /* Grab our physical cpu number */
119 mr r24,r3
121 /* Tell the master cpu we're here */
122 /* Relocation is off & we are located at an address less */
123 /* than 0x100, so only need to grab low order offset. */
124 std r24,__secondary_hold_acknowledge@l(0)
125 sync
127 /* All secondary cpus wait here until told to start. */
128 100: ld r4,__secondary_hold_spinloop@l(0)
129 cmpdi 0,r4,1
130 bne 100b
132 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
133 LOAD_REG_IMMEDIATE(r4, .generic_secondary_smp_init)
134 mtctr r4
135 mr r3,r24
136 bctr
137 #else
138 BUG_OPCODE
139 #endif
141 /* This value is used to mark exception frames on the stack. */
142 .section ".toc","aw"
143 exception_marker:
144 .tc ID_72656773_68657265[TC],0x7265677368657265
145 .text
147 /*
148 * The following macros define the code that appears as
149 * the prologue to each of the exception handlers. They
150 * are split into two parts to allow a single kernel binary
151 * to be used for pSeries and iSeries.
152 * LOL. One day... - paulus
153 */
155 /*
156 * We make as much of the exception code common between native
157 * exception handlers (including pSeries LPAR) and iSeries LPAR
158 * implementations as possible.
159 */
161 /*
162 * This is the start of the interrupt handlers for pSeries
163 * This code runs with relocation off.
164 */
165 #define EX_R9 0
166 #define EX_R10 8
167 #define EX_R11 16
168 #define EX_R12 24
169 #define EX_R13 32
170 #define EX_SRR0 40
171 #define EX_DAR 48
172 #define EX_DSISR 56
173 #define EX_CCR 60
174 #define EX_R3 64
175 #define EX_LR 72
177 /*
178 * We're short on space and time in the exception prolog, so we can't
179 * use the normal SET_REG_IMMEDIATE macro. Normally we just need the
180 * low halfword of the address, but for Kdump we need the whole low
181 * word.
182 */
183 #ifdef CONFIG_CRASH_DUMP
184 #define LOAD_HANDLER(reg, label) \
185 oris reg,reg,(label)@h; /* virt addr of handler ... */ \
186 ori reg,reg,(label)@l; /* .. and the rest */
187 #else
188 #define LOAD_HANDLER(reg, label) \
189 ori reg,reg,(label)@l; /* virt addr of handler ... */
190 #endif
192 /*
193 * Equal to EXCEPTION_PROLOG_PSERIES, except that it forces 64bit mode.
194 * The firmware calls the registered system_reset_fwnmi and
195 * machine_check_fwnmi handlers in 32bit mode if the cpu happens to run
196 * a 32bit application at the time of the event.
197 * This firmware bug is present on POWER4 and JS20.
198 */
199 #define EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(area, label) \
200 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
201 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
202 std r10,area+EX_R10(r13); \
203 std r11,area+EX_R11(r13); \
204 std r12,area+EX_R12(r13); \
205 mfspr r9,SPRN_SPRG1; \
206 std r9,area+EX_R13(r13); \
207 mfcr r9; \
208 clrrdi r12,r13,32; /* get high part of &label */ \
209 mfmsr r10; \
210 /* force 64bit mode */ \
211 li r11,5; /* MSR_SF_LG|MSR_ISF_LG */ \
212 rldimi r10,r11,61,0; /* insert into top 3 bits */ \
213 /* done 64bit mode */ \
214 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
215 LOAD_HANDLER(r12,label) \
216 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
217 mtspr SPRN_SRR0,r12; \
218 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
219 mtspr SPRN_SRR1,r10; \
220 rfid; \
221 b . /* prevent speculative execution */
223 #define EXCEPTION_PROLOG_PSERIES(area, label) \
224 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
225 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
226 std r10,area+EX_R10(r13); \
227 std r11,area+EX_R11(r13); \
228 std r12,area+EX_R12(r13); \
229 mfspr r9,SPRN_SPRG1; \
230 std r9,area+EX_R13(r13); \
231 mfcr r9; \
232 clrrdi r12,r13,32; /* get high part of &label */ \
233 mfmsr r10; \
234 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
235 LOAD_HANDLER(r12,label) \
236 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
237 mtspr SPRN_SRR0,r12; \
238 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
239 mtspr SPRN_SRR1,r10; \
240 rfid; \
241 b . /* prevent speculative execution */
243 /*
244 * This is the start of the interrupt handlers for iSeries
245 * This code runs with relocation on.
246 */
247 #define EXCEPTION_PROLOG_ISERIES_1(area) \
248 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
249 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
250 std r10,area+EX_R10(r13); \
251 std r11,area+EX_R11(r13); \
252 std r12,area+EX_R12(r13); \
253 mfspr r9,SPRN_SPRG1; \
254 std r9,area+EX_R13(r13); \
255 mfcr r9
257 #define EXCEPTION_PROLOG_ISERIES_2 \
258 mfmsr r10; \
259 ld r12,PACALPPACAPTR(r13); \
260 ld r11,LPPACASRR0(r12); \
261 ld r12,LPPACASRR1(r12); \
262 ori r10,r10,MSR_RI; \
263 mtmsrd r10,1
265 /*
266 * The common exception prolog is used for all except a few exceptions
267 * such as a segment miss on a kernel address. We have to be prepared
268 * to take another exception from the point where we first touch the
269 * kernel stack onwards.
270 *
271 * On entry r13 points to the paca, r9-r13 are saved in the paca,
272 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
273 * SRR1, and relocation is on.
274 */
275 #define EXCEPTION_PROLOG_COMMON(n, area) \
276 andi. r10,r12,MSR_PR; /* See if coming from user */ \
277 mr r10,r1; /* Save r1 */ \
278 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
279 beq- 1f; \
280 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
281 1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
282 bge- cr1,2f; /* abort if it is */ \
283 b 3f; \
284 2: li r1,(n); /* will be reloaded later */ \
285 sth r1,PACA_TRAP_SAVE(r13); \
286 b bad_stack; \
287 3: std r9,_CCR(r1); /* save CR in stackframe */ \
288 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
289 std r12,_MSR(r1); /* save SRR1 in stackframe */ \
290 std r10,0(r1); /* make stack chain pointer */ \
291 std r0,GPR0(r1); /* save r0 in stackframe */ \
292 std r10,GPR1(r1); /* save r1 in stackframe */ \
293 ACCOUNT_CPU_USER_ENTRY(r9, r10); \
294 std r2,GPR2(r1); /* save r2 in stackframe */ \
295 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
296 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
297 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
298 ld r10,area+EX_R10(r13); \
299 std r9,GPR9(r1); \
300 std r10,GPR10(r1); \
301 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
302 ld r10,area+EX_R12(r13); \
303 ld r11,area+EX_R13(r13); \
304 std r9,GPR11(r1); \
305 std r10,GPR12(r1); \
306 std r11,GPR13(r1); \
307 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
308 mflr r9; /* save LR in stackframe */ \
309 std r9,_LINK(r1); \
310 mfctr r10; /* save CTR in stackframe */ \
311 std r10,_CTR(r1); \
312 lbz r10,PACASOFTIRQEN(r13); \
313 mfspr r11,SPRN_XER; /* save XER in stackframe */ \
314 std r10,SOFTE(r1); \
315 std r11,_XER(r1); \
316 li r9,(n)+1; \
317 std r9,_TRAP(r1); /* set trap number */ \
318 li r10,0; \
319 ld r11,exception_marker@toc(r2); \
320 std r10,RESULT(r1); /* clear regs->result */ \
321 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
323 /*
324 * Exception vectors.
325 */
326 #define STD_EXCEPTION_PSERIES(n, label) \
327 . = n; \
328 .globl label##_pSeries; \
329 label##_pSeries: \
330 HMT_MEDIUM; \
331 mtspr SPRN_SPRG1,r13; /* save r13 */ \
332 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
334 #define HSTD_EXCEPTION_PSERIES(n, label) \
335 . = n; \
336 .globl label##_pSeries; \
337 label##_pSeries: \
338 HMT_MEDIUM; \
339 mtspr SPRN_SPRG1,r20; /* save r20 */ \
340 mfspr r20,SPRN_HSRR0; /* copy HSRR0 to SRR0 */ \
341 mtspr SPRN_SRR0,r20; \
342 mfspr r20,SPRN_HSRR1; /* copy HSRR0 to SRR0 */ \
343 mtspr SPRN_SRR1,r20; \
344 mfspr r20,SPRN_SPRG1; /* restore r20 */ \
345 mtspr SPRN_SPRG1,r13; /* save r13 */ \
346 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
349 #define MASKABLE_EXCEPTION_PSERIES(n, label) \
350 . = n; \
351 .globl label##_pSeries; \
352 label##_pSeries: \
353 HMT_MEDIUM; \
354 mtspr SPRN_SPRG1,r13; /* save r13 */ \
355 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
356 std r9,PACA_EXGEN+EX_R9(r13); /* save r9, r10 */ \
357 std r10,PACA_EXGEN+EX_R10(r13); \
358 lbz r10,PACASOFTIRQEN(r13); \
359 mfcr r9; \
360 cmpwi r10,0; \
361 beq masked_interrupt; \
362 mfspr r10,SPRN_SPRG1; \
363 std r10,PACA_EXGEN+EX_R13(r13); \
364 std r11,PACA_EXGEN+EX_R11(r13); \
365 std r12,PACA_EXGEN+EX_R12(r13); \
366 clrrdi r12,r13,32; /* get high part of &label */ \
367 mfmsr r10; \
368 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
369 LOAD_HANDLER(r12,label##_common) \
370 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
371 mtspr SPRN_SRR0,r12; \
372 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
373 mtspr SPRN_SRR1,r10; \
374 rfid; \
375 b . /* prevent speculative execution */
377 #define STD_EXCEPTION_ISERIES(n, label, area) \
378 .globl label##_iSeries; \
379 label##_iSeries: \
380 HMT_MEDIUM; \
381 mtspr SPRN_SPRG1,r13; /* save r13 */ \
382 EXCEPTION_PROLOG_ISERIES_1(area); \
383 EXCEPTION_PROLOG_ISERIES_2; \
384 b label##_common
386 #define MASKABLE_EXCEPTION_ISERIES(n, label) \
387 .globl label##_iSeries; \
388 label##_iSeries: \
389 HMT_MEDIUM; \
390 mtspr SPRN_SPRG1,r13; /* save r13 */ \
391 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \
392 lbz r10,PACASOFTIRQEN(r13); \
393 cmpwi 0,r10,0; \
394 beq- label##_iSeries_masked; \
395 EXCEPTION_PROLOG_ISERIES_2; \
396 b label##_common; \
398 #ifdef CONFIG_PPC_ISERIES
399 #define DISABLE_INTS \
400 li r11,0; \
401 stb r11,PACASOFTIRQEN(r13); \
402 BEGIN_FW_FTR_SECTION; \
403 stb r11,PACAHARDIRQEN(r13); \
404 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES); \
405 BEGIN_FW_FTR_SECTION; \
406 mfmsr r10; \
407 ori r10,r10,MSR_EE; \
408 mtmsrd r10,1; \
409 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
411 #else
412 #define DISABLE_INTS \
413 li r11,0; \
414 stb r11,PACASOFTIRQEN(r13); \
415 stb r11,PACAHARDIRQEN(r13)
417 #endif /* CONFIG_PPC_ISERIES */
419 #define ENABLE_INTS \
420 ld r12,_MSR(r1); \
421 mfmsr r11; \
422 rlwimi r11,r12,0,MSR_EE; \
423 mtmsrd r11,1
425 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \
426 .align 7; \
427 .globl label##_common; \
428 label##_common: \
429 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
430 DISABLE_INTS; \
431 bl .save_nvgprs; \
432 addi r3,r1,STACK_FRAME_OVERHEAD; \
433 bl hdlr; \
434 b .ret_from_except
436 /*
437 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur
438 * in the idle task and therefore need the special idle handling.
439 */
440 #define STD_EXCEPTION_COMMON_IDLE(trap, label, hdlr) \
441 .align 7; \
442 .globl label##_common; \
443 label##_common: \
444 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
445 FINISH_NAP; \
446 DISABLE_INTS; \
447 bl .save_nvgprs; \
448 addi r3,r1,STACK_FRAME_OVERHEAD; \
449 bl hdlr; \
450 b .ret_from_except
452 #define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \
453 .align 7; \
454 .globl label##_common; \
455 label##_common: \
456 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
457 FINISH_NAP; \
458 DISABLE_INTS; \
459 bl .ppc64_runlatch_on; \
460 addi r3,r1,STACK_FRAME_OVERHEAD; \
461 bl hdlr; \
462 b .ret_from_except_lite
464 /*
465 * When the idle code in power4_idle puts the CPU into NAP mode,
466 * it has to do so in a loop, and relies on the external interrupt
467 * and decrementer interrupt entry code to get it out of the loop.
468 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
469 * to signal that it is in the loop and needs help to get out.
470 */
471 #ifdef CONFIG_PPC_970_NAP
472 #define FINISH_NAP \
473 BEGIN_FTR_SECTION \
474 clrrdi r11,r1,THREAD_SHIFT; \
475 ld r9,TI_LOCAL_FLAGS(r11); \
476 andi. r10,r9,_TLF_NAPPING; \
477 bnel power4_fixup_nap; \
478 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
479 #else
480 #define FINISH_NAP
481 #endif
483 /*
484 * Start of pSeries system interrupt routines
485 */
486 . = 0x100
487 .globl __start_interrupts
488 __start_interrupts:
490 STD_EXCEPTION_PSERIES(0x100, system_reset)
492 . = 0x200
493 _machine_check_pSeries:
494 HMT_MEDIUM
495 mtspr SPRN_SPRG1,r13 /* save r13 */
496 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
498 . = 0x300
499 .globl data_access_pSeries
500 data_access_pSeries:
501 HMT_MEDIUM
502 mtspr SPRN_SPRG1,r13
503 BEGIN_FTR_SECTION
504 mtspr SPRN_SPRG2,r12
505 mfspr r13,SPRN_DAR
506 mfspr r12,SPRN_DSISR
507 srdi r13,r13,60
508 rlwimi r13,r12,16,0x20
509 mfcr r12
510 cmpwi r13,0x2c
511 beq do_stab_bolted_pSeries
512 mtcrf 0x80,r12
513 mfspr r12,SPRN_SPRG2
514 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
515 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
517 . = 0x380
518 .globl data_access_slb_pSeries
519 data_access_slb_pSeries:
520 HMT_MEDIUM
521 mtspr SPRN_SPRG1,r13
522 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
523 std r3,PACA_EXSLB+EX_R3(r13)
524 mfspr r3,SPRN_DAR
525 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
526 mfcr r9
527 #ifdef __DISABLED__
528 /* Keep that around for when we re-implement dynamic VSIDs */
529 cmpdi r3,0
530 bge slb_miss_user_pseries
531 #endif /* __DISABLED__ */
532 std r10,PACA_EXSLB+EX_R10(r13)
533 std r11,PACA_EXSLB+EX_R11(r13)
534 std r12,PACA_EXSLB+EX_R12(r13)
535 mfspr r10,SPRN_SPRG1
536 std r10,PACA_EXSLB+EX_R13(r13)
537 mfspr r12,SPRN_SRR1 /* and SRR1 */
538 b .slb_miss_realmode /* Rel. branch works in real mode */
540 STD_EXCEPTION_PSERIES(0x400, instruction_access)
542 . = 0x480
543 .globl instruction_access_slb_pSeries
544 instruction_access_slb_pSeries:
545 HMT_MEDIUM
546 mtspr SPRN_SPRG1,r13
547 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
548 std r3,PACA_EXSLB+EX_R3(r13)
549 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
550 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
551 mfcr r9
552 #ifdef __DISABLED__
553 /* Keep that around for when we re-implement dynamic VSIDs */
554 cmpdi r3,0
555 bge slb_miss_user_pseries
556 #endif /* __DISABLED__ */
557 std r10,PACA_EXSLB+EX_R10(r13)
558 std r11,PACA_EXSLB+EX_R11(r13)
559 std r12,PACA_EXSLB+EX_R12(r13)
560 mfspr r10,SPRN_SPRG1
561 std r10,PACA_EXSLB+EX_R13(r13)
562 mfspr r12,SPRN_SRR1 /* and SRR1 */
563 b .slb_miss_realmode /* Rel. branch works in real mode */
565 MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt)
566 STD_EXCEPTION_PSERIES(0x600, alignment)
567 STD_EXCEPTION_PSERIES(0x700, program_check)
568 STD_EXCEPTION_PSERIES(0x800, fp_unavailable)
569 MASKABLE_EXCEPTION_PSERIES(0x900, decrementer)
570 STD_EXCEPTION_PSERIES(0xa00, trap_0a)
571 STD_EXCEPTION_PSERIES(0xb00, trap_0b)
573 . = 0xc00
574 .globl system_call_pSeries
575 system_call_pSeries:
576 HMT_MEDIUM
577 mr r9,r13
578 mfmsr r10
579 mfspr r13,SPRN_SPRG3
580 mfspr r11,SPRN_SRR0
581 clrrdi r12,r13,32
582 oris r12,r12,system_call_common@h
583 ori r12,r12,system_call_common@l
584 mtspr SPRN_SRR0,r12
585 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
586 mfspr r12,SPRN_SRR1
587 mtspr SPRN_SRR1,r10
588 rfid
589 b . /* prevent speculative execution */
591 STD_EXCEPTION_PSERIES(0xd00, single_step)
592 STD_EXCEPTION_PSERIES(0xe00, trap_0e)
594 /* We need to deal with the Altivec unavailable exception
595 * here which is at 0xf20, thus in the middle of the
596 * prolog code of the PerformanceMonitor one. A little
597 * trickery is thus necessary
598 */
599 . = 0xf00
600 b performance_monitor_pSeries
602 STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable)
604 #ifdef CONFIG_CBE_RAS
605 HSTD_EXCEPTION_PSERIES(0x1200, cbe_system_error)
606 #endif /* CONFIG_CBE_RAS */
607 STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint)
608 #ifdef CONFIG_CBE_RAS
609 HSTD_EXCEPTION_PSERIES(0x1600, cbe_maintenance)
610 #endif /* CONFIG_CBE_RAS */
611 STD_EXCEPTION_PSERIES(0x1700, altivec_assist)
612 #ifdef CONFIG_CBE_RAS
613 HSTD_EXCEPTION_PSERIES(0x1800, cbe_thermal)
614 #endif /* CONFIG_CBE_RAS */
616 . = 0x3000
618 /*** pSeries interrupt support ***/
620 /* moved from 0xf00 */
621 STD_EXCEPTION_PSERIES(., performance_monitor)
623 /*
624 * An interrupt came in while soft-disabled; clear EE in SRR1,
625 * clear paca->hard_enabled and return.
626 */
627 masked_interrupt:
628 stb r10,PACAHARDIRQEN(r13)
629 mtcrf 0x80,r9
630 ld r9,PACA_EXGEN+EX_R9(r13)
631 mfspr r10,SPRN_SRR1
632 rldicl r10,r10,48,1 /* clear MSR_EE */
633 rotldi r10,r10,16
634 mtspr SPRN_SRR1,r10
635 ld r10,PACA_EXGEN+EX_R10(r13)
636 mfspr r13,SPRN_SPRG1
637 rfid
638 b .
640 .align 7
641 do_stab_bolted_pSeries:
642 mtcrf 0x80,r12
643 mfspr r12,SPRN_SPRG2
644 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
646 /*
647 * We have some room here we use that to put
648 * the peries slb miss user trampoline code so it's reasonably
649 * away from slb_miss_user_common to avoid problems with rfid
650 *
651 * This is used for when the SLB miss handler has to go virtual,
652 * which doesn't happen for now anymore but will once we re-implement
653 * dynamic VSIDs for shared page tables
654 */
655 #ifdef __DISABLED__
656 slb_miss_user_pseries:
657 std r10,PACA_EXGEN+EX_R10(r13)
658 std r11,PACA_EXGEN+EX_R11(r13)
659 std r12,PACA_EXGEN+EX_R12(r13)
660 mfspr r10,SPRG1
661 ld r11,PACA_EXSLB+EX_R9(r13)
662 ld r12,PACA_EXSLB+EX_R3(r13)
663 std r10,PACA_EXGEN+EX_R13(r13)
664 std r11,PACA_EXGEN+EX_R9(r13)
665 std r12,PACA_EXGEN+EX_R3(r13)
666 clrrdi r12,r13,32
667 mfmsr r10
668 mfspr r11,SRR0 /* save SRR0 */
669 ori r12,r12,slb_miss_user_common@l /* virt addr of handler */
670 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
671 mtspr SRR0,r12
672 mfspr r12,SRR1 /* and SRR1 */
673 mtspr SRR1,r10
674 rfid
675 b . /* prevent spec. execution */
676 #endif /* __DISABLED__ */
678 /*
679 * Vectors for the FWNMI option. Share common code.
680 */
681 .globl system_reset_fwnmi
682 .align 7
683 system_reset_fwnmi:
684 HMT_MEDIUM
685 mtspr SPRN_SPRG1,r13 /* save r13 */
686 EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXGEN, system_reset_common)
688 .globl machine_check_fwnmi
689 .align 7
690 machine_check_fwnmi:
691 HMT_MEDIUM
692 mtspr SPRN_SPRG1,r13 /* save r13 */
693 EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXMC, machine_check_common)
695 #ifdef CONFIG_PPC_ISERIES
696 /*** ISeries-LPAR interrupt handlers ***/
698 STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC)
700 .globl data_access_iSeries
701 data_access_iSeries:
702 mtspr SPRN_SPRG1,r13
703 BEGIN_FTR_SECTION
704 mtspr SPRN_SPRG2,r12
705 mfspr r13,SPRN_DAR
706 mfspr r12,SPRN_DSISR
707 srdi r13,r13,60
708 rlwimi r13,r12,16,0x20
709 mfcr r12
710 cmpwi r13,0x2c
711 beq .do_stab_bolted_iSeries
712 mtcrf 0x80,r12
713 mfspr r12,SPRN_SPRG2
714 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
715 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN)
716 EXCEPTION_PROLOG_ISERIES_2
717 b data_access_common
719 .do_stab_bolted_iSeries:
720 mtcrf 0x80,r12
721 mfspr r12,SPRN_SPRG2
722 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
723 EXCEPTION_PROLOG_ISERIES_2
724 b .do_stab_bolted
726 .globl data_access_slb_iSeries
727 data_access_slb_iSeries:
728 mtspr SPRN_SPRG1,r13 /* save r13 */
729 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
730 std r3,PACA_EXSLB+EX_R3(r13)
731 mfspr r3,SPRN_DAR
732 std r9,PACA_EXSLB+EX_R9(r13)
733 mfcr r9
734 #ifdef __DISABLED__
735 cmpdi r3,0
736 bge slb_miss_user_iseries
737 #endif
738 std r10,PACA_EXSLB+EX_R10(r13)
739 std r11,PACA_EXSLB+EX_R11(r13)
740 std r12,PACA_EXSLB+EX_R12(r13)
741 mfspr r10,SPRN_SPRG1
742 std r10,PACA_EXSLB+EX_R13(r13)
743 ld r12,PACALPPACAPTR(r13)
744 ld r12,LPPACASRR1(r12)
745 b .slb_miss_realmode
747 STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN)
749 .globl instruction_access_slb_iSeries
750 instruction_access_slb_iSeries:
751 mtspr SPRN_SPRG1,r13 /* save r13 */
752 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
753 std r3,PACA_EXSLB+EX_R3(r13)
754 ld r3,PACALPPACAPTR(r13)
755 ld r3,LPPACASRR0(r3) /* get SRR0 value */
756 std r9,PACA_EXSLB+EX_R9(r13)
757 mfcr r9
758 #ifdef __DISABLED__
759 cmpdi r3,0
760 bge .slb_miss_user_iseries
761 #endif
762 std r10,PACA_EXSLB+EX_R10(r13)
763 std r11,PACA_EXSLB+EX_R11(r13)
764 std r12,PACA_EXSLB+EX_R12(r13)
765 mfspr r10,SPRN_SPRG1
766 std r10,PACA_EXSLB+EX_R13(r13)
767 ld r12,PACALPPACAPTR(r13)
768 ld r12,LPPACASRR1(r12)
769 b .slb_miss_realmode
771 #ifdef __DISABLED__
772 slb_miss_user_iseries:
773 std r10,PACA_EXGEN+EX_R10(r13)
774 std r11,PACA_EXGEN+EX_R11(r13)
775 std r12,PACA_EXGEN+EX_R12(r13)
776 mfspr r10,SPRG1
777 ld r11,PACA_EXSLB+EX_R9(r13)
778 ld r12,PACA_EXSLB+EX_R3(r13)
779 std r10,PACA_EXGEN+EX_R13(r13)
780 std r11,PACA_EXGEN+EX_R9(r13)
781 std r12,PACA_EXGEN+EX_R3(r13)
782 EXCEPTION_PROLOG_ISERIES_2
783 b slb_miss_user_common
784 #endif
786 MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt)
787 STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN)
788 STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN)
789 STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN)
790 MASKABLE_EXCEPTION_ISERIES(0x900, decrementer)
791 STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN)
792 STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN)
794 .globl system_call_iSeries
795 system_call_iSeries:
796 mr r9,r13
797 mfspr r13,SPRN_SPRG3
798 EXCEPTION_PROLOG_ISERIES_2
799 b system_call_common
801 STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN)
802 STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN)
803 STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN)
805 .globl system_reset_iSeries
806 system_reset_iSeries:
807 mfspr r13,SPRN_SPRG3 /* Get paca address */
808 mfmsr r24
809 ori r24,r24,MSR_RI
810 mtmsrd r24 /* RI on */
811 lhz r24,PACAPACAINDEX(r13) /* Get processor # */
812 cmpwi 0,r24,0 /* Are we processor 0? */
813 bne 1f
814 b .__start_initialization_iSeries /* Start up the first processor */
815 1: mfspr r4,SPRN_CTRLF
816 li r5,CTRL_RUNLATCH /* Turn off the run light */
817 andc r4,r4,r5
818 mtspr SPRN_CTRLT,r4
820 1:
821 HMT_LOW
822 #ifdef CONFIG_SMP
823 lbz r23,PACAPROCSTART(r13) /* Test if this processor
824 * should start */
825 sync
826 LOAD_REG_IMMEDIATE(r3,current_set)
827 sldi r28,r24,3 /* get current_set[cpu#] */
828 ldx r3,r3,r28
829 addi r1,r3,THREAD_SIZE
830 subi r1,r1,STACK_FRAME_OVERHEAD
832 cmpwi 0,r23,0
833 beq iSeries_secondary_smp_loop /* Loop until told to go */
834 bne __secondary_start /* Loop until told to go */
835 iSeries_secondary_smp_loop:
836 /* Let the Hypervisor know we are alive */
837 /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
838 lis r3,0x8002
839 rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */
840 #else /* CONFIG_SMP */
841 /* Yield the processor. This is required for non-SMP kernels
842 which are running on multi-threaded machines. */
843 lis r3,0x8000
844 rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */
845 addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */
846 li r4,0 /* "yield timed" */
847 li r5,-1 /* "yield forever" */
848 #endif /* CONFIG_SMP */
849 li r0,-1 /* r0=-1 indicates a Hypervisor call */
850 sc /* Invoke the hypervisor via a system call */
851 mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */
852 b 1b /* If SMP not configured, secondaries
853 * loop forever */
855 decrementer_iSeries_masked:
856 /* We may not have a valid TOC pointer in here. */
857 li r11,1
858 ld r12,PACALPPACAPTR(r13)
859 stb r11,LPPACADECRINT(r12)
860 LOAD_REG_IMMEDIATE(r12, tb_ticks_per_jiffy)
861 lwz r12,0(r12)
862 mtspr SPRN_DEC,r12
863 /* fall through */
865 hardware_interrupt_iSeries_masked:
866 mtcrf 0x80,r9 /* Restore regs */
867 ld r12,PACALPPACAPTR(r13)
868 ld r11,LPPACASRR0(r12)
869 ld r12,LPPACASRR1(r12)
870 mtspr SPRN_SRR0,r11
871 mtspr SPRN_SRR1,r12
872 ld r9,PACA_EXGEN+EX_R9(r13)
873 ld r10,PACA_EXGEN+EX_R10(r13)
874 ld r11,PACA_EXGEN+EX_R11(r13)
875 ld r12,PACA_EXGEN+EX_R12(r13)
876 ld r13,PACA_EXGEN+EX_R13(r13)
877 rfid
878 b . /* prevent speculative execution */
879 #endif /* CONFIG_PPC_ISERIES */
881 /*** Common interrupt handlers ***/
883 STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
885 /*
886 * Machine check is different because we use a different
887 * save area: PACA_EXMC instead of PACA_EXGEN.
888 */
889 .align 7
890 .globl machine_check_common
891 machine_check_common:
892 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
893 FINISH_NAP
894 DISABLE_INTS
895 bl .save_nvgprs
896 addi r3,r1,STACK_FRAME_OVERHEAD
897 bl .machine_check_exception
898 b .ret_from_except
900 STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt)
901 STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
902 STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
903 STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
904 STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
905 STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception)
906 STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
907 #ifdef CONFIG_ALTIVEC
908 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
909 #else
910 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception)
911 #endif
912 #ifdef CONFIG_CBE_RAS
913 STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception)
914 STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception)
915 STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception)
916 #endif /* CONFIG_CBE_RAS */
918 /*
919 * Here we have detected that the kernel stack pointer is bad.
920 * R9 contains the saved CR, r13 points to the paca,
921 * r10 contains the (bad) kernel stack pointer,
922 * r11 and r12 contain the saved SRR0 and SRR1.
923 * We switch to using an emergency stack, save the registers there,
924 * and call kernel_bad_stack(), which panics.
925 */
926 bad_stack:
927 ld r1,PACAEMERGSP(r13)
928 subi r1,r1,64+INT_FRAME_SIZE
929 std r9,_CCR(r1)
930 std r10,GPR1(r1)
931 std r11,_NIP(r1)
932 std r12,_MSR(r1)
933 mfspr r11,SPRN_DAR
934 mfspr r12,SPRN_DSISR
935 std r11,_DAR(r1)
936 std r12,_DSISR(r1)
937 mflr r10
938 mfctr r11
939 mfxer r12
940 std r10,_LINK(r1)
941 std r11,_CTR(r1)
942 std r12,_XER(r1)
943 SAVE_GPR(0,r1)
944 SAVE_GPR(2,r1)
945 SAVE_4GPRS(3,r1)
946 SAVE_2GPRS(7,r1)
947 SAVE_10GPRS(12,r1)
948 SAVE_10GPRS(22,r1)
949 lhz r12,PACA_TRAP_SAVE(r13)
950 std r12,_TRAP(r1)
951 addi r11,r1,INT_FRAME_SIZE
952 std r11,0(r1)
953 li r12,0
954 std r12,0(r11)
955 ld r2,PACATOC(r13)
956 1: addi r3,r1,STACK_FRAME_OVERHEAD
957 bl .kernel_bad_stack
958 b 1b
960 /*
961 * Return from an exception with minimal checks.
962 * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
963 * If interrupts have been enabled, or anything has been
964 * done that might have changed the scheduling status of
965 * any task or sent any task a signal, you should use
966 * ret_from_except or ret_from_except_lite instead of this.
967 */
968 fast_exc_return_irq: /* restores irq state too */
969 ld r3,SOFTE(r1)
970 ld r12,_MSR(r1)
971 stb r3,PACASOFTIRQEN(r13) /* restore paca->soft_enabled */
972 rldicl r4,r12,49,63 /* get MSR_EE to LSB */
973 stb r4,PACAHARDIRQEN(r13) /* restore paca->hard_enabled */
974 b 1f
976 .globl fast_exception_return
977 fast_exception_return:
978 ld r12,_MSR(r1)
979 1: ld r11,_NIP(r1)
980 andi. r3,r12,MSR_RI /* check if RI is set */
981 beq- unrecov_fer
983 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
984 andi. r3,r12,MSR_PR
985 beq 2f
986 ACCOUNT_CPU_USER_EXIT(r3, r4)
987 2:
988 #endif
990 ld r3,_CCR(r1)
991 ld r4,_LINK(r1)
992 ld r5,_CTR(r1)
993 ld r6,_XER(r1)
994 mtcr r3
995 mtlr r4
996 mtctr r5
997 mtxer r6
998 REST_GPR(0, r1)
999 REST_8GPRS(2, r1)
1001 mfmsr r10
1002 rldicl r10,r10,48,1 /* clear EE */
1003 rldicr r10,r10,16,61 /* clear RI (LE is 0 already) */
1004 mtmsrd r10,1
1006 mtspr SPRN_SRR1,r12
1007 mtspr SPRN_SRR0,r11
1008 REST_4GPRS(10, r1)
1009 ld r1,GPR1(r1)
1010 rfid
1011 b . /* prevent speculative execution */
1013 unrecov_fer:
1014 bl .save_nvgprs
1015 1: addi r3,r1,STACK_FRAME_OVERHEAD
1016 bl .unrecoverable_exception
1017 b 1b
1019 /*
1020 * Here r13 points to the paca, r9 contains the saved CR,
1021 * SRR0 and SRR1 are saved in r11 and r12,
1022 * r9 - r13 are saved in paca->exgen.
1023 */
1024 .align 7
1025 .globl data_access_common
1026 data_access_common:
1027 mfspr r10,SPRN_DAR
1028 std r10,PACA_EXGEN+EX_DAR(r13)
1029 mfspr r10,SPRN_DSISR
1030 stw r10,PACA_EXGEN+EX_DSISR(r13)
1031 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
1032 ld r3,PACA_EXGEN+EX_DAR(r13)
1033 lwz r4,PACA_EXGEN+EX_DSISR(r13)
1034 li r5,0x300
1035 b .do_hash_page /* Try to handle as hpte fault */
1037 .align 7
1038 .globl instruction_access_common
1039 instruction_access_common:
1040 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
1041 ld r3,_NIP(r1)
1042 andis. r4,r12,0x5820
1043 li r5,0x400
1044 b .do_hash_page /* Try to handle as hpte fault */
1046 /*
1047 * Here is the common SLB miss user that is used when going to virtual
1048 * mode for SLB misses, that is currently not used
1049 */
1050 #ifdef __DISABLED__
1051 .align 7
1052 .globl slb_miss_user_common
1053 slb_miss_user_common:
1054 mflr r10
1055 std r3,PACA_EXGEN+EX_DAR(r13)
1056 stw r9,PACA_EXGEN+EX_CCR(r13)
1057 std r10,PACA_EXGEN+EX_LR(r13)
1058 std r11,PACA_EXGEN+EX_SRR0(r13)
1059 bl .slb_allocate_user
1061 ld r10,PACA_EXGEN+EX_LR(r13)
1062 ld r3,PACA_EXGEN+EX_R3(r13)
1063 lwz r9,PACA_EXGEN+EX_CCR(r13)
1064 ld r11,PACA_EXGEN+EX_SRR0(r13)
1065 mtlr r10
1066 beq- slb_miss_fault
1068 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
1069 beq- unrecov_user_slb
1070 mfmsr r10
1072 .machine push
1073 .machine "power4"
1074 mtcrf 0x80,r9
1075 .machine pop
1077 clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */
1078 mtmsrd r10,1
1080 mtspr SRR0,r11
1081 mtspr SRR1,r12
1083 ld r9,PACA_EXGEN+EX_R9(r13)
1084 ld r10,PACA_EXGEN+EX_R10(r13)
1085 ld r11,PACA_EXGEN+EX_R11(r13)
1086 ld r12,PACA_EXGEN+EX_R12(r13)
1087 ld r13,PACA_EXGEN+EX_R13(r13)
1088 rfid
1089 b .
1091 slb_miss_fault:
1092 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN)
1093 ld r4,PACA_EXGEN+EX_DAR(r13)
1094 li r5,0
1095 std r4,_DAR(r1)
1096 std r5,_DSISR(r1)
1097 b handle_page_fault
1099 unrecov_user_slb:
1100 EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN)
1101 DISABLE_INTS
1102 bl .save_nvgprs
1103 1: addi r3,r1,STACK_FRAME_OVERHEAD
1104 bl .unrecoverable_exception
1105 b 1b
1107 #endif /* __DISABLED__ */
1110 /*
1111 * r13 points to the PACA, r9 contains the saved CR,
1112 * r12 contain the saved SRR1, SRR0 is still ready for return
1113 * r3 has the faulting address
1114 * r9 - r13 are saved in paca->exslb.
1115 * r3 is saved in paca->slb_r3
1116 * We assume we aren't going to take any exceptions during this procedure.
1117 */
1118 _GLOBAL(slb_miss_realmode)
1119 mflr r10
1121 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1122 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
1124 bl .slb_allocate_realmode
1126 /* All done -- return from exception. */
1128 ld r10,PACA_EXSLB+EX_LR(r13)
1129 ld r3,PACA_EXSLB+EX_R3(r13)
1130 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1131 #ifdef CONFIG_PPC_ISERIES
1132 BEGIN_FW_FTR_SECTION
1133 ld r11,PACALPPACAPTR(r13)
1134 ld r11,LPPACASRR0(r11) /* get SRR0 value */
1135 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1136 #endif /* CONFIG_PPC_ISERIES */
1138 mtlr r10
1140 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
1141 beq- unrecov_slb
1143 .machine push
1144 .machine "power4"
1145 mtcrf 0x80,r9
1146 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
1147 .machine pop
1149 #ifdef CONFIG_PPC_ISERIES
1150 BEGIN_FW_FTR_SECTION
1151 mtspr SPRN_SRR0,r11
1152 mtspr SPRN_SRR1,r12
1153 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1154 #endif /* CONFIG_PPC_ISERIES */
1155 ld r9,PACA_EXSLB+EX_R9(r13)
1156 ld r10,PACA_EXSLB+EX_R10(r13)
1157 ld r11,PACA_EXSLB+EX_R11(r13)
1158 ld r12,PACA_EXSLB+EX_R12(r13)
1159 ld r13,PACA_EXSLB+EX_R13(r13)
1160 rfid
1161 b . /* prevent speculative execution */
1163 unrecov_slb:
1164 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
1165 DISABLE_INTS
1166 bl .save_nvgprs
1167 1: addi r3,r1,STACK_FRAME_OVERHEAD
1168 bl .unrecoverable_exception
1169 b 1b
1171 .align 7
1172 .globl hardware_interrupt_common
1173 .globl hardware_interrupt_entry
1174 hardware_interrupt_common:
1175 EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
1176 FINISH_NAP
1177 hardware_interrupt_entry:
1178 DISABLE_INTS
1179 bl .ppc64_runlatch_on
1180 addi r3,r1,STACK_FRAME_OVERHEAD
1181 bl .do_IRQ
1182 b .ret_from_except_lite
1184 #ifdef CONFIG_PPC_970_NAP
1185 power4_fixup_nap:
1186 andc r9,r9,r10
1187 std r9,TI_LOCAL_FLAGS(r11)
1188 ld r10,_LINK(r1) /* make idle task do the */
1189 std r10,_NIP(r1) /* equivalent of a blr */
1190 blr
1191 #endif
1193 .align 7
1194 .globl alignment_common
1195 alignment_common:
1196 mfspr r10,SPRN_DAR
1197 std r10,PACA_EXGEN+EX_DAR(r13)
1198 mfspr r10,SPRN_DSISR
1199 stw r10,PACA_EXGEN+EX_DSISR(r13)
1200 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
1201 ld r3,PACA_EXGEN+EX_DAR(r13)
1202 lwz r4,PACA_EXGEN+EX_DSISR(r13)
1203 std r3,_DAR(r1)
1204 std r4,_DSISR(r1)
1205 bl .save_nvgprs
1206 addi r3,r1,STACK_FRAME_OVERHEAD
1207 ENABLE_INTS
1208 bl .alignment_exception
1209 b .ret_from_except
1211 .align 7
1212 .globl program_check_common
1213 program_check_common:
1214 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
1215 bl .save_nvgprs
1216 addi r3,r1,STACK_FRAME_OVERHEAD
1217 ENABLE_INTS
1218 bl .program_check_exception
1219 b .ret_from_except
1221 .align 7
1222 .globl fp_unavailable_common
1223 fp_unavailable_common:
1224 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
1225 bne 1f /* if from user, just load it up */
1226 bl .save_nvgprs
1227 addi r3,r1,STACK_FRAME_OVERHEAD
1228 ENABLE_INTS
1229 bl .kernel_fp_unavailable_exception
1230 BUG_OPCODE
1231 1: b .load_up_fpu
1233 .align 7
1234 .globl altivec_unavailable_common
1235 altivec_unavailable_common:
1236 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1237 #ifdef CONFIG_ALTIVEC
1238 BEGIN_FTR_SECTION
1239 bne .load_up_altivec /* if from user, just load it up */
1240 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1241 #endif
1242 bl .save_nvgprs
1243 addi r3,r1,STACK_FRAME_OVERHEAD
1244 ENABLE_INTS
1245 bl .altivec_unavailable_exception
1246 b .ret_from_except
1248 #ifdef CONFIG_ALTIVEC
1249 /*
1250 * load_up_altivec(unused, unused, tsk)
1251 * Disable VMX for the task which had it previously,
1252 * and save its vector registers in its thread_struct.
1253 * Enables the VMX for use in the kernel on return.
1254 * On SMP we know the VMX is free, since we give it up every
1255 * switch (ie, no lazy save of the vector registers).
1256 * On entry: r13 == 'current' && last_task_used_altivec != 'current'
1257 */
1258 _STATIC(load_up_altivec)
1259 mfmsr r5 /* grab the current MSR */
1260 oris r5,r5,MSR_VEC@h
1261 mtmsrd r5 /* enable use of VMX now */
1262 isync
1264 /*
1265 * For SMP, we don't do lazy VMX switching because it just gets too
1266 * horrendously complex, especially when a task switches from one CPU
1267 * to another. Instead we call giveup_altvec in switch_to.
1268 * VRSAVE isn't dealt with here, that is done in the normal context
1269 * switch code. Note that we could rely on vrsave value to eventually
1270 * avoid saving all of the VREGs here...
1271 */
1272 #ifndef CONFIG_SMP
1273 ld r3,last_task_used_altivec@got(r2)
1274 ld r4,0(r3)
1275 cmpdi 0,r4,0
1276 beq 1f
1277 /* Save VMX state to last_task_used_altivec's THREAD struct */
1278 addi r4,r4,THREAD
1279 SAVE_32VRS(0,r5,r4)
1280 mfvscr vr0
1281 li r10,THREAD_VSCR
1282 stvx vr0,r10,r4
1283 /* Disable VMX for last_task_used_altivec */
1284 ld r5,PT_REGS(r4)
1285 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1286 lis r6,MSR_VEC@h
1287 andc r4,r4,r6
1288 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1289 1:
1290 #endif /* CONFIG_SMP */
1291 /* Hack: if we get an altivec unavailable trap with VRSAVE
1292 * set to all zeros, we assume this is a broken application
1293 * that fails to set it properly, and thus we switch it to
1294 * all 1's
1295 */
1296 mfspr r4,SPRN_VRSAVE
1297 cmpdi 0,r4,0
1298 bne+ 1f
1299 li r4,-1
1300 mtspr SPRN_VRSAVE,r4
1301 1:
1302 /* enable use of VMX after return */
1303 ld r4,PACACURRENT(r13)
1304 addi r5,r4,THREAD /* Get THREAD */
1305 oris r12,r12,MSR_VEC@h
1306 std r12,_MSR(r1)
1307 li r4,1
1308 li r10,THREAD_VSCR
1309 stw r4,THREAD_USED_VR(r5)
1310 lvx vr0,r10,r5
1311 mtvscr vr0
1312 REST_32VRS(0,r4,r5)
1313 #ifndef CONFIG_SMP
1314 /* Update last_task_used_math to 'current' */
1315 subi r4,r5,THREAD /* Back to 'current' */
1316 std r4,0(r3)
1317 #endif /* CONFIG_SMP */
1318 /* restore registers and return */
1319 b fast_exception_return
1320 #endif /* CONFIG_ALTIVEC */
1322 /*
1323 * Hash table stuff
1324 */
1325 .align 7
1326 _GLOBAL(do_hash_page)
1327 std r3,_DAR(r1)
1328 std r4,_DSISR(r1)
1330 andis. r0,r4,0xa450 /* weird error? */
1331 bne- handle_page_fault /* if not, try to insert a HPTE */
1332 BEGIN_FTR_SECTION
1333 andis. r0,r4,0x0020 /* Is it a segment table fault? */
1334 bne- do_ste_alloc /* If so handle it */
1335 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
1337 /*
1338 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
1339 * accessing a userspace segment (even from the kernel). We assume
1340 * kernel addresses always have the high bit set.
1341 */
1342 rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */
1343 rotldi r0,r3,15 /* Move high bit into MSR_PR posn */
1344 orc r0,r12,r0 /* MSR_PR | ~high_bit */
1345 rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */
1346 ori r4,r4,1 /* add _PAGE_PRESENT */
1347 rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */
1349 /*
1350 * On iSeries, we soft-disable interrupts here, then
1351 * hard-enable interrupts so that the hash_page code can spin on
1352 * the hash_table_lock without problems on a shared processor.
1353 */
1354 DISABLE_INTS
1356 /*
1357 * r3 contains the faulting address
1358 * r4 contains the required access permissions
1359 * r5 contains the trap number
1360 *
1361 * at return r3 = 0 for success
1362 */
1363 bl .hash_page /* build HPTE if possible */
1364 cmpdi r3,0 /* see if hash_page succeeded */
1366 #ifdef DO_SOFT_DISABLE
1367 BEGIN_FW_FTR_SECTION
1368 /*
1369 * If we had interrupts soft-enabled at the point where the
1370 * DSI/ISI occurred, and an interrupt came in during hash_page,
1371 * handle it now.
1372 * We jump to ret_from_except_lite rather than fast_exception_return
1373 * because ret_from_except_lite will check for and handle pending
1374 * interrupts if necessary.
1375 */
1376 beq 13f
1377 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1378 #endif
1379 BEGIN_FW_FTR_SECTION
1380 /*
1381 * Here we have interrupts hard-disabled, so it is sufficient
1382 * to restore paca->{soft,hard}_enable and get out.
1383 */
1384 beq fast_exc_return_irq /* Return from exception on success */
1385 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
1387 /* For a hash failure, we don't bother re-enabling interrupts */
1388 ble- 12f
1390 /*
1391 * hash_page couldn't handle it, set soft interrupt enable back
1392 * to what it was before the trap. Note that .local_irq_restore
1393 * handles any interrupts pending at this point.
1394 */
1395 ld r3,SOFTE(r1)
1396 bl .local_irq_restore
1397 b 11f
1399 /* Here we have a page fault that hash_page can't handle. */
1400 handle_page_fault:
1401 ENABLE_INTS
1402 11: ld r4,_DAR(r1)
1403 ld r5,_DSISR(r1)
1404 addi r3,r1,STACK_FRAME_OVERHEAD
1405 bl .do_page_fault
1406 cmpdi r3,0
1407 beq+ 13f
1408 bl .save_nvgprs
1409 mr r5,r3
1410 addi r3,r1,STACK_FRAME_OVERHEAD
1411 lwz r4,_DAR(r1)
1412 bl .bad_page_fault
1413 b .ret_from_except
1415 13: b .ret_from_except_lite
1417 /* We have a page fault that hash_page could handle but HV refused
1418 * the PTE insertion
1419 */
1420 12: bl .save_nvgprs
1421 addi r3,r1,STACK_FRAME_OVERHEAD
1422 lwz r4,_DAR(r1)
1423 bl .low_hash_fault
1424 b .ret_from_except
1426 /* here we have a segment miss */
1427 do_ste_alloc:
1428 bl .ste_allocate /* try to insert stab entry */
1429 cmpdi r3,0
1430 bne- handle_page_fault
1431 b fast_exception_return
1433 /*
1434 * r13 points to the PACA, r9 contains the saved CR,
1435 * r11 and r12 contain the saved SRR0 and SRR1.
1436 * r9 - r13 are saved in paca->exslb.
1437 * We assume we aren't going to take any exceptions during this procedure.
1438 * We assume (DAR >> 60) == 0xc.
1439 */
1440 .align 7
1441 _GLOBAL(do_stab_bolted)
1442 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1443 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */
1445 /* Hash to the primary group */
1446 ld r10,PACASTABVIRT(r13)
1447 mfspr r11,SPRN_DAR
1448 srdi r11,r11,28
1449 rldimi r10,r11,7,52 /* r10 = first ste of the group */
1451 /* Calculate VSID */
1452 /* This is a kernel address, so protovsid = ESID */
1453 ASM_VSID_SCRAMBLE(r11, r9)
1454 rldic r9,r11,12,16 /* r9 = vsid << 12 */
1456 /* Search the primary group for a free entry */
1457 1: ld r11,0(r10) /* Test valid bit of the current ste */
1458 andi. r11,r11,0x80
1459 beq 2f
1460 addi r10,r10,16
1461 andi. r11,r10,0x70
1462 bne 1b
1464 /* Stick for only searching the primary group for now. */
1465 /* At least for now, we use a very simple random castout scheme */
1466 /* Use the TB as a random number ; OR in 1 to avoid entry 0 */
1467 mftb r11
1468 rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */
1469 ori r11,r11,0x10
1471 /* r10 currently points to an ste one past the group of interest */
1472 /* make it point to the randomly selected entry */
1473 subi r10,r10,128
1474 or r10,r10,r11 /* r10 is the entry to invalidate */
1476 isync /* mark the entry invalid */
1477 ld r11,0(r10)
1478 rldicl r11,r11,56,1 /* clear the valid bit */
1479 rotldi r11,r11,8
1480 std r11,0(r10)
1481 sync
1483 clrrdi r11,r11,28 /* Get the esid part of the ste */
1484 slbie r11
1486 2: std r9,8(r10) /* Store the vsid part of the ste */
1487 eieio
1489 mfspr r11,SPRN_DAR /* Get the new esid */
1490 clrrdi r11,r11,28 /* Permits a full 32b of ESID */
1491 ori r11,r11,0x90 /* Turn on valid and kp */
1492 std r11,0(r10) /* Put new entry back into the stab */
1494 sync
1496 /* All done -- return from exception. */
1497 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1498 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */
1500 andi. r10,r12,MSR_RI
1501 beq- unrecov_slb
1503 mtcrf 0x80,r9 /* restore CR */
1505 mfmsr r10
1506 clrrdi r10,r10,2
1507 mtmsrd r10,1
1509 mtspr SPRN_SRR0,r11
1510 mtspr SPRN_SRR1,r12
1511 ld r9,PACA_EXSLB+EX_R9(r13)
1512 ld r10,PACA_EXSLB+EX_R10(r13)
1513 ld r11,PACA_EXSLB+EX_R11(r13)
1514 ld r12,PACA_EXSLB+EX_R12(r13)
1515 ld r13,PACA_EXSLB+EX_R13(r13)
1516 rfid
1517 b . /* prevent speculative execution */
1519 /*
1520 * Space for CPU0's segment table.
1521 *
1522 * On iSeries, the hypervisor must fill in at least one entry before
1523 * we get control (with relocate on). The address is given to the hv
1524 * as a page number (see xLparMap below), so this must be at a
1525 * fixed address (the linker can't compute (u64)&initial_stab >>
1526 * PAGE_SHIFT).
1527 */
1528 . = STAB0_OFFSET /* 0x6000 */
1529 .globl initial_stab
1530 initial_stab:
1531 .space 4096
1533 /*
1534 * Data area reserved for FWNMI option.
1535 * This address (0x7000) is fixed by the RPA.
1536 */
1537 .= 0x7000
1538 .globl fwnmi_data_area
1539 fwnmi_data_area:
1541 /* iSeries does not use the FWNMI stuff, so it is safe to put
1542 * this here, even if we later allow kernels that will boot on
1543 * both pSeries and iSeries */
1544 #ifdef CONFIG_PPC_ISERIES
1545 . = LPARMAP_PHYS
1546 .globl xLparMap
1547 xLparMap:
1548 .quad HvEsidsToMap /* xNumberEsids */
1549 .quad HvRangesToMap /* xNumberRanges */
1550 .quad STAB0_PAGE /* xSegmentTableOffs */
1551 .zero 40 /* xRsvd */
1552 /* xEsids (HvEsidsToMap entries of 2 quads) */
1553 .quad PAGE_OFFSET_ESID /* xKernelEsid */
1554 .quad PAGE_OFFSET_VSID /* xKernelVsid */
1555 .quad VMALLOC_START_ESID /* xKernelEsid */
1556 .quad VMALLOC_START_VSID /* xKernelVsid */
1557 /* xRanges (HvRangesToMap entries of 3 quads) */
1558 .quad HvPagesToMap /* xPages */
1559 .quad 0 /* xOffset */
1560 .quad PAGE_OFFSET_VSID << (SID_SHIFT - HW_PAGE_SHIFT) /* xVPN */
1562 #endif /* CONFIG_PPC_ISERIES */
1564 . = 0x8000
1566 /*
1567 * On pSeries and most other platforms, secondary processors spin
1568 * in the following code.
1569 * At entry, r3 = this processor's number (physical cpu id)
1570 */
1571 _GLOBAL(generic_secondary_smp_init)
1572 mr r24,r3
1574 /* turn on 64-bit mode */
1575 bl .enable_64b_mode
1577 /* Set up a paca value for this processor. Since we have the
1578 * physical cpu id in r24, we need to search the pacas to find
1579 * which logical id maps to our physical one.
1580 */
1581 LOAD_REG_IMMEDIATE(r13, paca) /* Get base vaddr of paca array */
1582 li r5,0 /* logical cpu id */
1583 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
1584 cmpw r6,r24 /* Compare to our id */
1585 beq 2f
1586 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
1587 addi r5,r5,1
1588 cmpwi r5,NR_CPUS
1589 blt 1b
1591 mr r3,r24 /* not found, copy phys to r3 */
1592 b .kexec_wait /* next kernel might do better */
1594 2: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1595 /* From now on, r24 is expected to be logical cpuid */
1596 mr r24,r5
1597 3: HMT_LOW
1598 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
1599 /* start. */
1600 sync
1602 #ifndef CONFIG_SMP
1603 b 3b /* Never go on non-SMP */
1604 #else
1605 cmpwi 0,r23,0
1606 beq 3b /* Loop until told to go */
1608 /* See if we need to call a cpu state restore handler */
1609 LOAD_REG_IMMEDIATE(r23, cur_cpu_spec)
1610 ld r23,0(r23)
1611 ld r23,CPU_SPEC_RESTORE(r23)
1612 cmpdi 0,r23,0
1613 beq 4f
1614 ld r23,0(r23)
1615 mtctr r23
1616 bctrl
1618 4: /* Create a temp kernel stack for use before relocation is on. */
1619 ld r1,PACAEMERGSP(r13)
1620 subi r1,r1,STACK_FRAME_OVERHEAD
1622 b __secondary_start
1623 #endif
1625 #ifdef CONFIG_PPC_ISERIES
1626 _INIT_STATIC(__start_initialization_iSeries)
1627 /* Clear out the BSS */
1628 LOAD_REG_IMMEDIATE(r11,__bss_stop)
1629 LOAD_REG_IMMEDIATE(r8,__bss_start)
1630 sub r11,r11,r8 /* bss size */
1631 addi r11,r11,7 /* round up to an even double word */
1632 rldicl. r11,r11,61,3 /* shift right by 3 */
1633 beq 4f
1634 addi r8,r8,-8
1635 li r0,0
1636 mtctr r11 /* zero this many doublewords */
1637 3: stdu r0,8(r8)
1638 bdnz 3b
1639 4:
1640 LOAD_REG_IMMEDIATE(r1,init_thread_union)
1641 addi r1,r1,THREAD_SIZE
1642 li r0,0
1643 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1645 LOAD_REG_IMMEDIATE(r2,__toc_start)
1646 addi r2,r2,0x4000
1647 addi r2,r2,0x4000
1649 bl .iSeries_early_setup
1650 bl .early_setup
1652 /* relocation is on at this point */
1654 b .start_here_common
1655 #endif /* CONFIG_PPC_ISERIES */
1658 _STATIC(__mmu_off)
1659 mfmsr r3
1660 andi. r0,r3,MSR_IR|MSR_DR
1661 beqlr
1662 andc r3,r3,r0
1663 mtspr SPRN_SRR0,r4
1664 mtspr SPRN_SRR1,r3
1665 sync
1666 rfid
1667 b . /* prevent speculative execution */
1670 /*
1671 * Here is our main kernel entry point. We support currently 2 kind of entries
1672 * depending on the value of r5.
1673 *
1674 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
1675 * in r3...r7
1676 *
1677 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
1678 * DT block, r4 is a physical pointer to the kernel itself
1679 *
1680 */
1681 _GLOBAL(__start_initialization_multiplatform)
1682 /*
1683 * Are we booted from a PROM Of-type client-interface ?
1684 */
1685 cmpldi cr0,r5,0
1686 beq 1f
1687 b .__boot_from_prom /* yes -> prom */
1688 1:
1689 /* Save parameters */
1690 mr r31,r3
1691 mr r30,r4
1693 /* Make sure we are running in 64 bits mode */
1694 bl .enable_64b_mode
1696 /* Setup some critical 970 SPRs before switching MMU off */
1697 mfspr r0,SPRN_PVR
1698 srwi r0,r0,16
1699 cmpwi r0,0x39 /* 970 */
1700 beq 1f
1701 cmpwi r0,0x3c /* 970FX */
1702 beq 1f
1703 cmpwi r0,0x44 /* 970MP */
1704 beq 1f
1705 cmpwi r0,0x45 /* 970GX */
1706 bne 2f
1707 1: bl .__cpu_preinit_ppc970
1708 2:
1710 /* Switch off MMU if not already */
1711 LOAD_REG_IMMEDIATE(r4, .__after_prom_start - KERNELBASE)
1712 add r4,r4,r30
1713 bl .__mmu_off
1714 b .__after_prom_start
1716 _INIT_STATIC(__boot_from_prom)
1717 /* Save parameters */
1718 mr r31,r3
1719 mr r30,r4
1720 mr r29,r5
1721 mr r28,r6
1722 mr r27,r7
1724 /*
1725 * Align the stack to 16-byte boundary
1726 * Depending on the size and layout of the ELF sections in the initial
1727 * boot binary, the stack pointer will be unalignet on PowerMac
1728 */
1729 rldicr r1,r1,0,59
1731 /* Make sure we are running in 64 bits mode */
1732 bl .enable_64b_mode
1734 /* put a relocation offset into r3 */
1735 bl .reloc_offset
1737 LOAD_REG_IMMEDIATE(r2,__toc_start)
1738 addi r2,r2,0x4000
1739 addi r2,r2,0x4000
1741 /* Relocate the TOC from a virt addr to a real addr */
1742 add r2,r2,r3
1744 /* Restore parameters */
1745 mr r3,r31
1746 mr r4,r30
1747 mr r5,r29
1748 mr r6,r28
1749 mr r7,r27
1751 /* Do all of the interaction with OF client interface */
1752 bl .prom_init
1753 /* We never return */
1754 trap
1756 _STATIC(__after_prom_start)
1758 /*
1759 * We need to run with __start at physical address PHYSICAL_START.
1760 * This will leave some code in the first 256B of
1761 * real memory, which are reserved for software use.
1762 * The remainder of the first page is loaded with the fixed
1763 * interrupt vectors. The next two pages are filled with
1764 * unknown exception placeholders.
1765 *
1766 * Note: This process overwrites the OF exception vectors.
1767 * r26 == relocation offset
1768 * r27 == KERNELBASE
1769 */
1770 bl .reloc_offset
1771 mr r26,r3
1772 LOAD_REG_IMMEDIATE(r27, KERNELBASE)
1774 LOAD_REG_IMMEDIATE(r3, PHYSICAL_START) /* target addr */
1776 // XXX FIXME: Use phys returned by OF (r30)
1777 add r4,r27,r26 /* source addr */
1778 /* current address of _start */
1779 /* i.e. where we are running */
1780 /* the source addr */
1782 cmpdi r4,0 /* In some cases the loader may */
1783 bne 1f
1784 b .start_here_multiplatform /* have already put us at zero */
1785 /* so we can skip the copy. */
1786 1: LOAD_REG_IMMEDIATE(r5,copy_to_here) /* # bytes of memory to copy */
1787 sub r5,r5,r27
1789 li r6,0x100 /* Start offset, the first 0x100 */
1790 /* bytes were copied earlier. */
1792 bl .copy_and_flush /* copy the first n bytes */
1793 /* this includes the code being */
1794 /* executed here. */
1796 LOAD_REG_IMMEDIATE(r0, 4f) /* Jump to the copy of this code */
1797 mtctr r0 /* that we just made/relocated */
1798 bctr
1800 4: LOAD_REG_IMMEDIATE(r5,klimit)
1801 add r5,r5,r26
1802 ld r5,0(r5) /* get the value of klimit */
1803 sub r5,r5,r27
1804 bl .copy_and_flush /* copy the rest */
1805 b .start_here_multiplatform
1807 /*
1808 * Copy routine used to copy the kernel to start at physical address 0
1809 * and flush and invalidate the caches as needed.
1810 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
1811 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
1812 *
1813 * Note: this routine *only* clobbers r0, r6 and lr
1814 */
1815 _GLOBAL(copy_and_flush)
1816 addi r5,r5,-8
1817 addi r6,r6,-8
1818 4: li r0,8 /* Use the smallest common */
1819 /* denominator cache line */
1820 /* size. This results in */
1821 /* extra cache line flushes */
1822 /* but operation is correct. */
1823 /* Can't get cache line size */
1824 /* from NACA as it is being */
1825 /* moved too. */
1827 mtctr r0 /* put # words/line in ctr */
1828 3: addi r6,r6,8 /* copy a cache line */
1829 ldx r0,r6,r4
1830 stdx r0,r6,r3
1831 bdnz 3b
1832 dcbst r6,r3 /* write it to memory */
1833 sync
1834 icbi r6,r3 /* flush the icache line */
1835 cmpld 0,r6,r5
1836 blt 4b
1837 sync
1838 addi r5,r5,8
1839 addi r6,r6,8
1840 blr
1842 .align 8
1843 copy_to_here:
1845 #ifdef CONFIG_SMP
1846 #ifdef CONFIG_PPC_PMAC
1847 /*
1848 * On PowerMac, secondary processors starts from the reset vector, which
1849 * is temporarily turned into a call to one of the functions below.
1850 */
1851 .section ".text";
1852 .align 2 ;
1854 .globl __secondary_start_pmac_0
1855 __secondary_start_pmac_0:
1856 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
1857 li r24,0
1858 b 1f
1859 li r24,1
1860 b 1f
1861 li r24,2
1862 b 1f
1863 li r24,3
1864 1:
1866 _GLOBAL(pmac_secondary_start)
1867 /* turn on 64-bit mode */
1868 bl .enable_64b_mode
1870 /* Copy some CPU settings from CPU 0 */
1871 bl .__restore_cpu_ppc970
1873 /* pSeries do that early though I don't think we really need it */
1874 mfmsr r3
1875 ori r3,r3,MSR_RI
1876 mtmsrd r3 /* RI on */
1878 /* Set up a paca value for this processor. */
1879 LOAD_REG_IMMEDIATE(r4, paca) /* Get base vaddr of paca array */
1880 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
1881 add r13,r13,r4 /* for this processor. */
1882 mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1884 /* Create a temp kernel stack for use before relocation is on. */
1885 ld r1,PACAEMERGSP(r13)
1886 subi r1,r1,STACK_FRAME_OVERHEAD
1888 b __secondary_start
1890 #endif /* CONFIG_PPC_PMAC */
1892 /*
1893 * This function is called after the master CPU has released the
1894 * secondary processors. The execution environment is relocation off.
1895 * The paca for this processor has the following fields initialized at
1896 * this point:
1897 * 1. Processor number
1898 * 2. Segment table pointer (virtual address)
1899 * On entry the following are set:
1900 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
1901 * r24 = cpu# (in Linux terms)
1902 * r13 = paca virtual address
1903 * SPRG3 = paca virtual address
1904 */
1905 __secondary_start:
1906 /* Set thread priority to MEDIUM */
1907 HMT_MEDIUM
1909 /* Load TOC */
1910 ld r2,PACATOC(r13)
1912 /* Do early setup for that CPU (stab, slb, hash table pointer) */
1913 bl .early_setup_secondary
1915 /* Initialize the kernel stack. Just a repeat for iSeries. */
1916 LOAD_REG_ADDR(r3, current_set)
1917 sldi r28,r24,3 /* get current_set[cpu#] */
1918 ldx r1,r3,r28
1919 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1920 std r1,PACAKSAVE(r13)
1922 /* Clear backchain so we get nice backtraces */
1923 li r7,0
1924 mtlr r7
1926 /* enable MMU and jump to start_secondary */
1927 LOAD_REG_ADDR(r3, .start_secondary_prolog)
1928 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
1929 #ifdef CONFIG_PPC_ISERIES
1930 BEGIN_FW_FTR_SECTION
1931 ori r4,r4,MSR_EE
1932 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1933 #endif
1934 BEGIN_FW_FTR_SECTION
1935 stb r7,PACASOFTIRQEN(r13)
1936 stb r7,PACAHARDIRQEN(r13)
1937 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
1939 mtspr SPRN_SRR0,r3
1940 mtspr SPRN_SRR1,r4
1941 rfid
1942 b . /* prevent speculative execution */
1944 /*
1945 * Running with relocation on at this point. All we want to do is
1946 * zero the stack back-chain pointer before going into C code.
1947 */
1948 _GLOBAL(start_secondary_prolog)
1949 li r3,0
1950 std r3,0(r1) /* Zero the stack frame pointer */
1951 bl .start_secondary
1952 b .
1953 #endif
1955 /*
1956 * This subroutine clobbers r11 and r12
1957 */
1958 _GLOBAL(enable_64b_mode)
1959 mfmsr r11 /* grab the current MSR */
1960 li r12,1
1961 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
1962 or r11,r11,r12
1963 li r12,1
1964 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
1965 or r11,r11,r12
1966 mtmsrd r11
1967 isync
1968 blr
1970 /*
1971 * This is where the main kernel code starts.
1972 */
1973 _INIT_STATIC(start_here_multiplatform)
1974 /* get a new offset, now that the kernel has moved. */
1975 bl .reloc_offset
1976 mr r26,r3
1978 /* Clear out the BSS. It may have been done in prom_init,
1979 * already but that's irrelevant since prom_init will soon
1980 * be detached from the kernel completely. Besides, we need
1981 * to clear it now for kexec-style entry.
1982 */
1983 LOAD_REG_IMMEDIATE(r11,__bss_stop)
1984 LOAD_REG_IMMEDIATE(r8,__bss_start)
1985 sub r11,r11,r8 /* bss size */
1986 addi r11,r11,7 /* round up to an even double word */
1987 rldicl. r11,r11,61,3 /* shift right by 3 */
1988 beq 4f
1989 addi r8,r8,-8
1990 li r0,0
1991 mtctr r11 /* zero this many doublewords */
1992 3: stdu r0,8(r8)
1993 bdnz 3b
1994 4:
1996 mfmsr r6
1997 ori r6,r6,MSR_RI
1998 mtmsrd r6 /* RI on */
2000 /* The following gets the stack and TOC set up with the regs */
2001 /* pointing to the real addr of the kernel stack. This is */
2002 /* all done to support the C function call below which sets */
2003 /* up the htab. This is done because we have relocated the */
2004 /* kernel but are still running in real mode. */
2006 LOAD_REG_IMMEDIATE(r3,init_thread_union)
2007 add r3,r3,r26
2009 /* set up a stack pointer (physical address) */
2010 addi r1,r3,THREAD_SIZE
2011 li r0,0
2012 stdu r0,-STACK_FRAME_OVERHEAD(r1)
2014 /* set up the TOC (physical address) */
2015 LOAD_REG_IMMEDIATE(r2,__toc_start)
2016 addi r2,r2,0x4000
2017 addi r2,r2,0x4000
2018 add r2,r2,r26
2020 /* Do very early kernel initializations, including initial hash table,
2021 * stab and slb setup before we turn on relocation. */
2023 /* Restore parameters passed from prom_init/kexec */
2024 mr r3,r31
2025 bl .early_setup
2027 LOAD_REG_IMMEDIATE(r3, .start_here_common)
2028 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
2029 mtspr SPRN_SRR0,r3
2030 mtspr SPRN_SRR1,r4
2031 rfid
2032 b . /* prevent speculative execution */
2034 /* This is where all platforms converge execution */
2035 _INIT_STATIC(start_here_common)
2036 /* relocation is on at this point */
2038 /* The following code sets up the SP and TOC now that we are */
2039 /* running with translation enabled. */
2041 LOAD_REG_IMMEDIATE(r3,init_thread_union)
2043 /* set up the stack */
2044 addi r1,r3,THREAD_SIZE
2045 li r0,0
2046 stdu r0,-STACK_FRAME_OVERHEAD(r1)
2048 /* ptr to current */
2049 LOAD_REG_IMMEDIATE(r4, init_task)
2050 std r4,PACACURRENT(r13)
2052 /* Load the TOC */
2053 ld r2,PACATOC(r13)
2054 std r1,PACAKSAVE(r13)
2056 bl .setup_system
2058 /* Load up the kernel context */
2059 5:
2060 li r5,0
2061 stb r5,PACASOFTIRQEN(r13) /* Soft Disabled */
2062 #ifdef CONFIG_PPC_ISERIES
2063 BEGIN_FW_FTR_SECTION
2064 mfmsr r5
2065 ori r5,r5,MSR_EE /* Hard Enabled */
2066 mtmsrd r5
2067 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
2068 #endif
2069 BEGIN_FW_FTR_SECTION
2070 stb r5,PACAHARDIRQEN(r13)
2071 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
2073 bl .start_kernel
2075 /* Not reached */
2076 BUG_OPCODE
2078 /*
2079 * We put a few things here that have to be page-aligned.
2080 * This stuff goes at the beginning of the bss, which is page-aligned.
2081 */
2082 .section ".bss"
2084 .align PAGE_SHIFT
2086 .globl empty_zero_page
2087 empty_zero_page:
2088 .space PAGE_SIZE
2090 .globl swapper_pg_dir
2091 swapper_pg_dir:
2092 .space PAGE_SIZE
2094 /*
2095 * This space gets a copy of optional info passed to us by the bootstrap
2096 * Used to pass parameters into the kernel like root=/dev/sda1, etc.
2097 */
2098 .globl cmd_line
2099 cmd_line:
2100 .space COMMAND_LINE_SIZE