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lib/scatterlist: factor out sg_miter_get_next_page() from sg_miter_next()
[linux-2.6.git] / drivers / i2c / busses / i2c-omap.c
blob142b694d1c60a1ca528860a03b45c1a913dcb145
1 /*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Copyright (C) 2005 Nokia Corporation
6 * Copyright (C) 2004 - 2007 Texas Instruments.
7 *
8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31 #include <linux/module.h>
32 #include <linux/delay.h>
33 #include <linux/i2c.h>
34 #include <linux/err.h>
35 #include <linux/interrupt.h>
36 #include <linux/completion.h>
37 #include <linux/platform_device.h>
38 #include <linux/clk.h>
39 #include <linux/io.h>
40 #include <linux/of.h>
41 #include <linux/of_i2c.h>
42 #include <linux/of_device.h>
43 #include <linux/slab.h>
44 #include <linux/i2c-omap.h>
45 #include <linux/pm_runtime.h>
46 #include <linux/pinctrl/consumer.h>
47
48 /* I2C controller revisions */
49 #define OMAP_I2C_OMAP1_REV_2 0x20
50
51 /* I2C controller revisions present on specific hardware */
52 #define OMAP_I2C_REV_ON_2430 0x00000036
53 #define OMAP_I2C_REV_ON_3430_3530 0x0000003C
54 #define OMAP_I2C_REV_ON_3630 0x00000040
55 #define OMAP_I2C_REV_ON_4430_PLUS 0x50400002
56
57 /* timeout waiting for the controller to respond */
58 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
59
60 /* timeout for pm runtime autosuspend */
61 #define OMAP_I2C_PM_TIMEOUT 1000 /* ms */
62
63 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
64 enum {
65 OMAP_I2C_REV_REG = 0,
66 OMAP_I2C_IE_REG,
67 OMAP_I2C_STAT_REG,
68 OMAP_I2C_IV_REG,
69 OMAP_I2C_WE_REG,
70 OMAP_I2C_SYSS_REG,
71 OMAP_I2C_BUF_REG,
72 OMAP_I2C_CNT_REG,
73 OMAP_I2C_DATA_REG,
74 OMAP_I2C_SYSC_REG,
75 OMAP_I2C_CON_REG,
76 OMAP_I2C_OA_REG,
77 OMAP_I2C_SA_REG,
78 OMAP_I2C_PSC_REG,
79 OMAP_I2C_SCLL_REG,
80 OMAP_I2C_SCLH_REG,
81 OMAP_I2C_SYSTEST_REG,
82 OMAP_I2C_BUFSTAT_REG,
83 /* only on OMAP4430 */
84 OMAP_I2C_IP_V2_REVNB_LO,
85 OMAP_I2C_IP_V2_REVNB_HI,
86 OMAP_I2C_IP_V2_IRQSTATUS_RAW,
87 OMAP_I2C_IP_V2_IRQENABLE_SET,
88 OMAP_I2C_IP_V2_IRQENABLE_CLR,
89 };
90
91 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
92 #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
93 #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
94 #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
95 #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
96 #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
97 #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
98 #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
99
100 /* I2C Status Register (OMAP_I2C_STAT): */
101 #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
102 #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
103 #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
104 #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
105 #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
106 #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
107 #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
108 #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
109 #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
110 #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
111 #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
112 #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
113
114 /* I2C WE wakeup enable register */
115 #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
116 #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
117 #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
118 #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
119 #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
120 #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
121 #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
122 #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
123 #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
124 #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
125
126 #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
127 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
128 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
129 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
130 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
131
132 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
133 #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
134 #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
135 #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
136 #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
137
138 /* I2C Configuration Register (OMAP_I2C_CON): */
139 #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
140 #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
141 #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
142 #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
143 #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
144 #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
145 #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
146 #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
147 #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
148 #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
149
150 /* I2C SCL time value when Master */
151 #define OMAP_I2C_SCLL_HSSCLL 8
152 #define OMAP_I2C_SCLH_HSSCLH 8
153
154 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
155 #ifdef DEBUG
156 #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
157 #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
158 #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
159 #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
160 #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
161 #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
162 #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
163 #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
164 #endif
165
166 /* OCP_SYSSTATUS bit definitions */
167 #define SYSS_RESETDONE_MASK (1 << 0)
168
169 /* OCP_SYSCONFIG bit definitions */
170 #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
171 #define SYSC_SIDLEMODE_MASK (0x3 << 3)
172 #define SYSC_ENAWAKEUP_MASK (1 << 2)
173 #define SYSC_SOFTRESET_MASK (1 << 1)
174 #define SYSC_AUTOIDLE_MASK (1 << 0)
175
176 #define SYSC_IDLEMODE_SMART 0x2
177 #define SYSC_CLOCKACTIVITY_FCLK 0x2
178
179 /* Errata definitions */
180 #define I2C_OMAP_ERRATA_I207 (1 << 0)
181 #define I2C_OMAP_ERRATA_I462 (1 << 1)
182
183 #define OMAP_I2C_IP_V2_INTERRUPTS_MASK 0x6FFF
184
185 struct omap_i2c_dev {
186 spinlock_t lock; /* IRQ synchronization */
187 struct device *dev;
188 void __iomem *base; /* virtual */
189 int irq;
190 int reg_shift; /* bit shift for I2C register addresses */
191 struct completion cmd_complete;
192 struct resource *ioarea;
193 u32 latency; /* maximum mpu wkup latency */
194 void (*set_mpu_wkup_lat)(struct device *dev,
195 long latency);
196 u32 speed; /* Speed of bus in kHz */
197 u32 flags;
198 u16 scheme;
199 u16 cmd_err;
200 u8 *buf;
201 u8 *regs;
202 size_t buf_len;
203 struct i2c_adapter adapter;
204 u8 threshold;
205 u8 fifo_size; /* use as flag and value
206 * fifo_size==0 implies no fifo
207 * if set, should be trsh+1
208 */
209 u32 rev;
210 unsigned b_hw:1; /* bad h/w fixes */
211 unsigned receiver:1; /* true when we're in receiver mode */
212 u16 iestate; /* Saved interrupt register */
213 u16 pscstate;
214 u16 scllstate;
215 u16 sclhstate;
216 u16 syscstate;
217 u16 westate;
218 u16 errata;
219
220 struct pinctrl *pins;
221 };
222
223 static const u8 reg_map_ip_v1[] = {
224 [OMAP_I2C_REV_REG] = 0x00,
225 [OMAP_I2C_IE_REG] = 0x01,
226 [OMAP_I2C_STAT_REG] = 0x02,
227 [OMAP_I2C_IV_REG] = 0x03,
228 [OMAP_I2C_WE_REG] = 0x03,
229 [OMAP_I2C_SYSS_REG] = 0x04,
230 [OMAP_I2C_BUF_REG] = 0x05,
231 [OMAP_I2C_CNT_REG] = 0x06,
232 [OMAP_I2C_DATA_REG] = 0x07,
233 [OMAP_I2C_SYSC_REG] = 0x08,
234 [OMAP_I2C_CON_REG] = 0x09,
235 [OMAP_I2C_OA_REG] = 0x0a,
236 [OMAP_I2C_SA_REG] = 0x0b,
237 [OMAP_I2C_PSC_REG] = 0x0c,
238 [OMAP_I2C_SCLL_REG] = 0x0d,
239 [OMAP_I2C_SCLH_REG] = 0x0e,
240 [OMAP_I2C_SYSTEST_REG] = 0x0f,
241 [OMAP_I2C_BUFSTAT_REG] = 0x10,
242 };
243
244 static const u8 reg_map_ip_v2[] = {
245 [OMAP_I2C_REV_REG] = 0x04,
246 [OMAP_I2C_IE_REG] = 0x2c,
247 [OMAP_I2C_STAT_REG] = 0x28,
248 [OMAP_I2C_IV_REG] = 0x34,
249 [OMAP_I2C_WE_REG] = 0x34,
250 [OMAP_I2C_SYSS_REG] = 0x90,
251 [OMAP_I2C_BUF_REG] = 0x94,
252 [OMAP_I2C_CNT_REG] = 0x98,
253 [OMAP_I2C_DATA_REG] = 0x9c,
254 [OMAP_I2C_SYSC_REG] = 0x10,
255 [OMAP_I2C_CON_REG] = 0xa4,
256 [OMAP_I2C_OA_REG] = 0xa8,
257 [OMAP_I2C_SA_REG] = 0xac,
258 [OMAP_I2C_PSC_REG] = 0xb0,
259 [OMAP_I2C_SCLL_REG] = 0xb4,
260 [OMAP_I2C_SCLH_REG] = 0xb8,
261 [OMAP_I2C_SYSTEST_REG] = 0xbC,
262 [OMAP_I2C_BUFSTAT_REG] = 0xc0,
263 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
264 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
265 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
266 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
267 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
268 };
269
270 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
271 int reg, u16 val)
272 {
273 __raw_writew(val, i2c_dev->base +
274 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
275 }
276
277 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
278 {
279 return __raw_readw(i2c_dev->base +
280 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
281 }
282
283 static void __omap_i2c_init(struct omap_i2c_dev *dev)
284 {
285
286 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
287
288 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
289 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
290
291 /* SCL low and high time values */
292 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
293 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
294 if (dev->rev >= OMAP_I2C_REV_ON_3430_3530)
295 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
296
297 /* Take the I2C module out of reset: */
298 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
299
300 /*
301 * Don't write to this register if the IE state is 0 as it can
302 * cause deadlock.
303 */
304 if (dev->iestate)
305 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
306 }
307
308 static int omap_i2c_reset(struct omap_i2c_dev *dev)
309 {
310 unsigned long timeout;
311 u16 sysc;
312
313 if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
314 sysc = omap_i2c_read_reg(dev, OMAP_I2C_SYSC_REG);
315
316 /* Disable I2C controller before soft reset */
317 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
318 omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
319 ~(OMAP_I2C_CON_EN));
320
321 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
322 /* For some reason we need to set the EN bit before the
323 * reset done bit gets set. */
324 timeout = jiffies + OMAP_I2C_TIMEOUT;
325 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
326 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
327 SYSS_RESETDONE_MASK)) {
328 if (time_after(jiffies, timeout)) {
329 dev_warn(dev->dev, "timeout waiting "
330 "for controller reset\n");
331 return -ETIMEDOUT;
332 }
333 msleep(1);
334 }
335
336 /* SYSC register is cleared by the reset; rewrite it */
337 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, sysc);
338
339 }
340 return 0;
341 }
342
343 static int omap_i2c_init(struct omap_i2c_dev *dev)
344 {
345 u16 psc = 0, scll = 0, sclh = 0;
346 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
347 unsigned long fclk_rate = 12000000;
348 unsigned long internal_clk = 0;
349 struct clk *fclk;
350
351 if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) {
352 /*
353 * Enabling all wakup sources to stop I2C freezing on
354 * WFI instruction.
355 * REVISIT: Some wkup sources might not be needed.
356 */
357 dev->westate = OMAP_I2C_WE_ALL;
358 }
359
360 if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
361 /*
362 * The I2C functional clock is the armxor_ck, so there's
363 * no need to get "armxor_ck" separately. Now, if OMAP2420
364 * always returns 12MHz for the functional clock, we can
365 * do this bit unconditionally.
366 */
367 fclk = clk_get(dev->dev, "fck");
368 fclk_rate = clk_get_rate(fclk);
369 clk_put(fclk);
370
371 /* TRM for 5912 says the I2C clock must be prescaled to be
372 * between 7 - 12 MHz. The XOR input clock is typically
373 * 12, 13 or 19.2 MHz. So we should have code that produces:
374 *
375 * XOR MHz Divider Prescaler
376 * 12 1 0
377 * 13 2 1
378 * 19.2 2 1
379 */
380 if (fclk_rate > 12000000)
381 psc = fclk_rate / 12000000;
382 }
383
384 if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
385
386 /*
387 * HSI2C controller internal clk rate should be 19.2 Mhz for
388 * HS and for all modes on 2430. On 34xx we can use lower rate
389 * to get longer filter period for better noise suppression.
390 * The filter is iclk (fclk for HS) period.
391 */
392 if (dev->speed > 400 ||
393 dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
394 internal_clk = 19200;
395 else if (dev->speed > 100)
396 internal_clk = 9600;
397 else
398 internal_clk = 4000;
399 fclk = clk_get(dev->dev, "fck");
400 fclk_rate = clk_get_rate(fclk) / 1000;
401 clk_put(fclk);
402
403 /* Compute prescaler divisor */
404 psc = fclk_rate / internal_clk;
405 psc = psc - 1;
406
407 /* If configured for High Speed */
408 if (dev->speed > 400) {
409 unsigned long scl;
410
411 /* For first phase of HS mode */
412 scl = internal_clk / 400;
413 fsscll = scl - (scl / 3) - 7;
414 fssclh = (scl / 3) - 5;
415
416 /* For second phase of HS mode */
417 scl = fclk_rate / dev->speed;
418 hsscll = scl - (scl / 3) - 7;
419 hssclh = (scl / 3) - 5;
420 } else if (dev->speed > 100) {
421 unsigned long scl;
422
423 /* Fast mode */
424 scl = internal_clk / dev->speed;
425 fsscll = scl - (scl / 3) - 7;
426 fssclh = (scl / 3) - 5;
427 } else {
428 /* Standard mode */
429 fsscll = internal_clk / (dev->speed * 2) - 7;
430 fssclh = internal_clk / (dev->speed * 2) - 5;
431 }
432 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
433 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
434 } else {
435 /* Program desired operating rate */
436 fclk_rate /= (psc + 1) * 1000;
437 if (psc > 2)
438 psc = 2;
439 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
440 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
441 }
442
443 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
444 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
445 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
446 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
447
448 dev->pscstate = psc;
449 dev->scllstate = scll;
450 dev->sclhstate = sclh;
451
452 __omap_i2c_init(dev);
453
454 return 0;
455 }
456
457 /*
458 * Waiting on Bus Busy
459 */
460 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
461 {
462 unsigned long timeout;
463
464 timeout = jiffies + OMAP_I2C_TIMEOUT;
465 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
466 if (time_after(jiffies, timeout)) {
467 dev_warn(dev->dev, "timeout waiting for bus ready\n");
468 return -ETIMEDOUT;
469 }
470 msleep(1);
471 }
472
473 return 0;
474 }
475
476 static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx)
477 {
478 u16 buf;
479
480 if (dev->flags & OMAP_I2C_FLAG_NO_FIFO)
481 return;
482
483 /*
484 * Set up notification threshold based on message size. We're doing
485 * this to try and avoid draining feature as much as possible. Whenever
486 * we have big messages to transfer (bigger than our total fifo size)
487 * then we might use draining feature to transfer the remaining bytes.
488 */
489
490 dev->threshold = clamp(size, (u8) 1, dev->fifo_size);
491
492 buf = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
493
494 if (is_rx) {
495 /* Clear RX Threshold */
496 buf &= ~(0x3f << 8);
497 buf |= ((dev->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;
498 } else {
499 /* Clear TX Threshold */
500 buf &= ~0x3f;
501 buf |= (dev->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;
502 }
503
504 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
505
506 if (dev->rev < OMAP_I2C_REV_ON_3630)
507 dev->b_hw = 1; /* Enable hardware fixes */
508
509 /* calculate wakeup latency constraint for MPU */
510 if (dev->set_mpu_wkup_lat != NULL)
511 dev->latency = (1000000 * dev->threshold) /
512 (1000 * dev->speed / 8);
513 }
514
515 /*
516 * Low level master read/write transaction.
517 */
518 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
519 struct i2c_msg *msg, int stop)
520 {
521 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
522 unsigned long timeout;
523 u16 w;
524
525 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
526 msg->addr, msg->len, msg->flags, stop);
527
528 if (msg->len == 0)
529 return -EINVAL;
530
531 dev->receiver = !!(msg->flags & I2C_M_RD);
532 omap_i2c_resize_fifo(dev, msg->len, dev->receiver);
533
534 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
535
536 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
537 dev->buf = msg->buf;
538 dev->buf_len = msg->len;
539
540 /* make sure writes to dev->buf_len are ordered */
541 barrier();
542
543 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
544
545 /* Clear the FIFO Buffers */
546 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
547 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
548 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
549
550 INIT_COMPLETION(dev->cmd_complete);
551 dev->cmd_err = 0;
552
553 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
554
555 /* High speed configuration */
556 if (dev->speed > 400)
557 w |= OMAP_I2C_CON_OPMODE_HS;
558
559 if (msg->flags & I2C_M_STOP)
560 stop = 1;
561 if (msg->flags & I2C_M_TEN)
562 w |= OMAP_I2C_CON_XA;
563 if (!(msg->flags & I2C_M_RD))
564 w |= OMAP_I2C_CON_TRX;
565
566 if (!dev->b_hw && stop)
567 w |= OMAP_I2C_CON_STP;
568
569 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
570
571 /*
572 * Don't write stt and stp together on some hardware.
573 */
574 if (dev->b_hw && stop) {
575 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
576 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
577 while (con & OMAP_I2C_CON_STT) {
578 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
579
580 /* Let the user know if i2c is in a bad state */
581 if (time_after(jiffies, delay)) {
582 dev_err(dev->dev, "controller timed out "
583 "waiting for start condition to finish\n");
584 return -ETIMEDOUT;
585 }
586 cpu_relax();
587 }
588
589 w |= OMAP_I2C_CON_STP;
590 w &= ~OMAP_I2C_CON_STT;
591 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
592 }
593
594 /*
595 * REVISIT: We should abort the transfer on signals, but the bus goes
596 * into arbitration and we're currently unable to recover from it.
597 */
598 timeout = wait_for_completion_timeout(&dev->cmd_complete,
599 OMAP_I2C_TIMEOUT);
600 if (timeout == 0) {
601 dev_err(dev->dev, "controller timed out\n");
602 omap_i2c_reset(dev);
603 __omap_i2c_init(dev);
604 return -ETIMEDOUT;
605 }
606
607 if (likely(!dev->cmd_err))
608 return 0;
609
610 /* We have an error */
611 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
612 OMAP_I2C_STAT_XUDF)) {
613 omap_i2c_reset(dev);
614 __omap_i2c_init(dev);
615 return -EIO;
616 }
617
618 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
619 if (msg->flags & I2C_M_IGNORE_NAK)
620 return 0;
621 if (stop) {
622 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
623 w |= OMAP_I2C_CON_STP;
624 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
625 }
626 return -EREMOTEIO;
627 }
628 return -EIO;
629 }
630
631
632 /*
633 * Prepare controller for a transaction and call omap_i2c_xfer_msg
634 * to do the work during IRQ processing.
635 */
636 static int
637 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
638 {
639 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
640 int i;
641 int r;
642
643 r = pm_runtime_get_sync(dev->dev);
644 if (IS_ERR_VALUE(r))
645 goto out;
646
647 r = omap_i2c_wait_for_bb(dev);
648 if (r < 0)
649 goto out;
650
651 if (dev->set_mpu_wkup_lat != NULL)
652 dev->set_mpu_wkup_lat(dev->dev, dev->latency);
653
654 for (i = 0; i < num; i++) {
655 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
656 if (r != 0)
657 break;
658 }
659
660 if (r == 0)
661 r = num;
662
663 omap_i2c_wait_for_bb(dev);
664
665 if (dev->set_mpu_wkup_lat != NULL)
666 dev->set_mpu_wkup_lat(dev->dev, -1);
667
668 out:
669 pm_runtime_mark_last_busy(dev->dev);
670 pm_runtime_put_autosuspend(dev->dev);
671 return r;
672 }
673
674 static u32
675 omap_i2c_func(struct i2c_adapter *adap)
676 {
677 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
678 I2C_FUNC_PROTOCOL_MANGLING;
679 }
680
681 static inline void
682 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
683 {
684 dev->cmd_err |= err;
685 complete(&dev->cmd_complete);
686 }
687
688 static inline void
689 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
690 {
691 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
692 }
693
694 static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
695 {
696 /*
697 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
698 * Not applicable for OMAP4.
699 * Under certain rare conditions, RDR could be set again
700 * when the bus is busy, then ignore the interrupt and
701 * clear the interrupt.
702 */
703 if (stat & OMAP_I2C_STAT_RDR) {
704 /* Step 1: If RDR is set, clear it */
705 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
706
707 /* Step 2: */
708 if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
709 & OMAP_I2C_STAT_BB)) {
710
711 /* Step 3: */
712 if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
713 & OMAP_I2C_STAT_RDR) {
714 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
715 dev_dbg(dev->dev, "RDR when bus is busy.\n");
716 }
717
718 }
719 }
720 }
721
722 /* rev1 devices are apparently only on some 15xx */
723 #ifdef CONFIG_ARCH_OMAP15XX
724
725 static irqreturn_t
726 omap_i2c_omap1_isr(int this_irq, void *dev_id)
727 {
728 struct omap_i2c_dev *dev = dev_id;
729 u16 iv, w;
730
731 if (pm_runtime_suspended(dev->dev))
732 return IRQ_NONE;
733
734 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
735 switch (iv) {
736 case 0x00: /* None */
737 break;
738 case 0x01: /* Arbitration lost */
739 dev_err(dev->dev, "Arbitration lost\n");
740 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
741 break;
742 case 0x02: /* No acknowledgement */
743 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
744 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
745 break;
746 case 0x03: /* Register access ready */
747 omap_i2c_complete_cmd(dev, 0);
748 break;
749 case 0x04: /* Receive data ready */
750 if (dev->buf_len) {
751 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
752 *dev->buf++ = w;
753 dev->buf_len--;
754 if (dev->buf_len) {
755 *dev->buf++ = w >> 8;
756 dev->buf_len--;
757 }
758 } else
759 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
760 break;
761 case 0x05: /* Transmit data ready */
762 if (dev->buf_len) {
763 w = *dev->buf++;
764 dev->buf_len--;
765 if (dev->buf_len) {
766 w |= *dev->buf++ << 8;
767 dev->buf_len--;
768 }
769 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
770 } else
771 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
772 break;
773 default:
774 return IRQ_NONE;
775 }
776
777 return IRQ_HANDLED;
778 }
779 #else
780 #define omap_i2c_omap1_isr NULL
781 #endif
782
783 /*
784 * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing
785 * data to DATA_REG. Otherwise some data bytes can be lost while transferring
786 * them from the memory to the I2C interface.
787 */
788 static int errata_omap3_i462(struct omap_i2c_dev *dev)
789 {
790 unsigned long timeout = 10000;
791 u16 stat;
792
793 do {
794 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
795 if (stat & OMAP_I2C_STAT_XUDF)
796 break;
797
798 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
799 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY |
800 OMAP_I2C_STAT_XDR));
801 if (stat & OMAP_I2C_STAT_NACK) {
802 dev->cmd_err |= OMAP_I2C_STAT_NACK;
803 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
804 }
805
806 if (stat & OMAP_I2C_STAT_AL) {
807 dev_err(dev->dev, "Arbitration lost\n");
808 dev->cmd_err |= OMAP_I2C_STAT_AL;
809 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
810 }
811
812 return -EIO;
813 }
814
815 cpu_relax();
816 } while (--timeout);
817
818 if (!timeout) {
819 dev_err(dev->dev, "timeout waiting on XUDF bit\n");
820 return 0;
821 }
822
823 return 0;
824 }
825
826 static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes,
827 bool is_rdr)
828 {
829 u16 w;
830
831 while (num_bytes--) {
832 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
833 *dev->buf++ = w;
834 dev->buf_len--;
835
836 /*
837 * Data reg in 2430, omap3 and
838 * omap4 is 8 bit wide
839 */
840 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
841 *dev->buf++ = w >> 8;
842 dev->buf_len--;
843 }
844 }
845 }
846
847 static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes,
848 bool is_xdr)
849 {
850 u16 w;
851
852 while (num_bytes--) {
853 w = *dev->buf++;
854 dev->buf_len--;
855
856 /*
857 * Data reg in 2430, omap3 and
858 * omap4 is 8 bit wide
859 */
860 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
861 w |= *dev->buf++ << 8;
862 dev->buf_len--;
863 }
864
865 if (dev->errata & I2C_OMAP_ERRATA_I462) {
866 int ret;
867
868 ret = errata_omap3_i462(dev);
869 if (ret < 0)
870 return ret;
871 }
872
873 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
874 }
875
876 return 0;
877 }
878
879 static irqreturn_t
880 omap_i2c_isr(int irq, void *dev_id)
881 {
882 struct omap_i2c_dev *dev = dev_id;
883 irqreturn_t ret = IRQ_HANDLED;
884 u16 mask;
885 u16 stat;
886
887 spin_lock(&dev->lock);
888 mask = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
889 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
890
891 if (stat & mask)
892 ret = IRQ_WAKE_THREAD;
893
894 spin_unlock(&dev->lock);
895
896 return ret;
897 }
898
899 static irqreturn_t
900 omap_i2c_isr_thread(int this_irq, void *dev_id)
901 {
902 struct omap_i2c_dev *dev = dev_id;
903 unsigned long flags;
904 u16 bits;
905 u16 stat;
906 int err = 0, count = 0;
907
908 spin_lock_irqsave(&dev->lock, flags);
909 do {
910 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
911 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
912 stat &= bits;
913
914 /* If we're in receiver mode, ignore XDR/XRDY */
915 if (dev->receiver)
916 stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY);
917 else
918 stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY);
919
920 if (!stat) {
921 /* my work here is done */
922 goto out;
923 }
924
925 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
926 if (count++ == 100) {
927 dev_warn(dev->dev, "Too much work in one IRQ\n");
928 break;
929 }
930
931 if (stat & OMAP_I2C_STAT_NACK) {
932 err |= OMAP_I2C_STAT_NACK;
933 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
934 break;
935 }
936
937 if (stat & OMAP_I2C_STAT_AL) {
938 dev_err(dev->dev, "Arbitration lost\n");
939 err |= OMAP_I2C_STAT_AL;
940 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
941 break;
942 }
943
944 /*
945 * ProDB0017052: Clear ARDY bit twice
946 */
947 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
948 OMAP_I2C_STAT_AL)) {
949 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY |
950 OMAP_I2C_STAT_RDR |
951 OMAP_I2C_STAT_XRDY |
952 OMAP_I2C_STAT_XDR |
953 OMAP_I2C_STAT_ARDY));
954 break;
955 }
956
957 if (stat & OMAP_I2C_STAT_RDR) {
958 u8 num_bytes = 1;
959
960 if (dev->fifo_size)
961 num_bytes = dev->buf_len;
962
963 omap_i2c_receive_data(dev, num_bytes, true);
964
965 if (dev->errata & I2C_OMAP_ERRATA_I207)
966 i2c_omap_errata_i207(dev, stat);
967
968 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
969 continue;
970 }
971
972 if (stat & OMAP_I2C_STAT_RRDY) {
973 u8 num_bytes = 1;
974
975 if (dev->threshold)
976 num_bytes = dev->threshold;
977
978 omap_i2c_receive_data(dev, num_bytes, false);
979 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
980 continue;
981 }
982
983 if (stat & OMAP_I2C_STAT_XDR) {
984 u8 num_bytes = 1;
985 int ret;
986
987 if (dev->fifo_size)
988 num_bytes = dev->buf_len;
989
990 ret = omap_i2c_transmit_data(dev, num_bytes, true);
991 if (ret < 0)
992 break;
993
994 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR);
995 continue;
996 }
997
998 if (stat & OMAP_I2C_STAT_XRDY) {
999 u8 num_bytes = 1;
1000 int ret;
1001
1002 if (dev->threshold)
1003 num_bytes = dev->threshold;
1004
1005 ret = omap_i2c_transmit_data(dev, num_bytes, false);
1006 if (ret < 0)
1007 break;
1008
1009 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
1010 continue;
1011 }
1012
1013 if (stat & OMAP_I2C_STAT_ROVR) {
1014 dev_err(dev->dev, "Receive overrun\n");
1015 err |= OMAP_I2C_STAT_ROVR;
1016 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR);
1017 break;
1018 }
1019
1020 if (stat & OMAP_I2C_STAT_XUDF) {
1021 dev_err(dev->dev, "Transmit underflow\n");
1022 err |= OMAP_I2C_STAT_XUDF;
1023 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF);
1024 break;
1025 }
1026 } while (stat);
1027
1028 omap_i2c_complete_cmd(dev, err);
1029
1030 out:
1031 spin_unlock_irqrestore(&dev->lock, flags);
1032
1033 return IRQ_HANDLED;
1034 }
1035
1036 static const struct i2c_algorithm omap_i2c_algo = {
1037 .master_xfer = omap_i2c_xfer,
1038 .functionality = omap_i2c_func,
1039 };
1040
1041 #ifdef CONFIG_OF
1042 static struct omap_i2c_bus_platform_data omap3_pdata = {
1043 .rev = OMAP_I2C_IP_VERSION_1,
1044 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
1045 };
1046
1047 static struct omap_i2c_bus_platform_data omap4_pdata = {
1048 .rev = OMAP_I2C_IP_VERSION_2,
1049 };
1050
1051 static const struct of_device_id omap_i2c_of_match[] = {
1052 {
1053 .compatible = "ti,omap4-i2c",
1054 .data = &omap4_pdata,
1055 },
1056 {
1057 .compatible = "ti,omap3-i2c",
1058 .data = &omap3_pdata,
1059 },
1060 { },
1061 };
1062 MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
1063 #endif
1064
1065 #define OMAP_I2C_SCHEME(rev) ((rev & 0xc000) >> 14)
1066
1067 #define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4)
1068 #define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf)
1069
1070 #define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7)
1071 #define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f)
1072 #define OMAP_I2C_SCHEME_0 0
1073 #define OMAP_I2C_SCHEME_1 1
1074
1075 static int
1076 omap_i2c_probe(struct platform_device *pdev)
1077 {
1078 struct omap_i2c_dev *dev;
1079 struct i2c_adapter *adap;
1080 struct resource *mem;
1081 const struct omap_i2c_bus_platform_data *pdata =
1082 pdev->dev.platform_data;
1083 struct device_node *node = pdev->dev.of_node;
1084 const struct of_device_id *match;
1085 int irq;
1086 int r;
1087 u32 rev;
1088 u16 minor, major;
1089
1090 irq = platform_get_irq(pdev, 0);
1091 if (irq < 0) {
1092 dev_err(&pdev->dev, "no irq resource?\n");
1093 return irq;
1094 }
1095
1096 dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
1097 if (!dev) {
1098 dev_err(&pdev->dev, "Menory allocation failed\n");
1099 return -ENOMEM;
1100 }
1101
1102 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1103 dev->base = devm_ioremap_resource(&pdev->dev, mem);
1104 if (IS_ERR(dev->base))
1105 return PTR_ERR(dev->base);
1106
1107 match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
1108 if (match) {
1109 u32 freq = 100000; /* default to 100000 Hz */
1110
1111 pdata = match->data;
1112 dev->flags = pdata->flags;
1113
1114 of_property_read_u32(node, "clock-frequency", &freq);
1115 /* convert DT freq value in Hz into kHz for speed */
1116 dev->speed = freq / 1000;
1117 } else if (pdata != NULL) {
1118 dev->speed = pdata->clkrate;
1119 dev->flags = pdata->flags;
1120 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
1121 }
1122
1123 dev->pins = devm_pinctrl_get_select_default(&pdev->dev);
1124 if (IS_ERR(dev->pins)) {
1125 if (PTR_ERR(dev->pins) == -EPROBE_DEFER)
1126 return -EPROBE_DEFER;
1127
1128 dev_warn(&pdev->dev, "did not get pins for i2c error: %li\n",
1129 PTR_ERR(dev->pins));
1130 dev->pins = NULL;
1131 }
1132
1133 dev->dev = &pdev->dev;
1134 dev->irq = irq;
1135
1136 spin_lock_init(&dev->lock);
1137
1138 platform_set_drvdata(pdev, dev);
1139 init_completion(&dev->cmd_complete);
1140
1141 dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
1142
1143 pm_runtime_enable(dev->dev);
1144 pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT);
1145 pm_runtime_use_autosuspend(dev->dev);
1146
1147 r = pm_runtime_get_sync(dev->dev);
1148 if (IS_ERR_VALUE(r))
1149 goto err_free_mem;
1150
1151 /*
1152 * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2.
1153 * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset.
1154 * Also since the omap_i2c_read_reg uses reg_map_ip_* a
1155 * raw_readw is done.
1156 */
1157 rev = __raw_readw(dev->base + 0x04);
1158
1159 dev->scheme = OMAP_I2C_SCHEME(rev);
1160 switch (dev->scheme) {
1161 case OMAP_I2C_SCHEME_0:
1162 dev->regs = (u8 *)reg_map_ip_v1;
1163 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG);
1164 minor = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
1165 major = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
1166 break;
1167 case OMAP_I2C_SCHEME_1:
1168 /* FALLTHROUGH */
1169 default:
1170 dev->regs = (u8 *)reg_map_ip_v2;
1171 rev = (rev << 16) |
1172 omap_i2c_read_reg(dev, OMAP_I2C_IP_V2_REVNB_LO);
1173 minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev);
1174 major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev);
1175 dev->rev = rev;
1176 }
1177
1178 dev->errata = 0;
1179
1180 if (dev->rev >= OMAP_I2C_REV_ON_2430 &&
1181 dev->rev < OMAP_I2C_REV_ON_4430_PLUS)
1182 dev->errata |= I2C_OMAP_ERRATA_I207;
1183
1184 if (dev->rev <= OMAP_I2C_REV_ON_3430_3530)
1185 dev->errata |= I2C_OMAP_ERRATA_I462;
1186
1187 if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) {
1188 u16 s;
1189
1190 /* Set up the fifo size - Get total size */
1191 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1192 dev->fifo_size = 0x8 << s;
1193
1194 /*
1195 * Set up notification threshold as half the total available
1196 * size. This is to ensure that we can handle the status on int
1197 * call back latencies.
1198 */
1199
1200 dev->fifo_size = (dev->fifo_size / 2);
1201
1202 if (dev->rev < OMAP_I2C_REV_ON_3630)
1203 dev->b_hw = 1; /* Enable hardware fixes */
1204
1205 /* calculate wakeup latency constraint for MPU */
1206 if (dev->set_mpu_wkup_lat != NULL)
1207 dev->latency = (1000000 * dev->fifo_size) /
1208 (1000 * dev->speed / 8);
1209 }
1210
1211 /* reset ASAP, clearing any IRQs */
1212 omap_i2c_init(dev);
1213
1214 if (dev->rev < OMAP_I2C_OMAP1_REV_2)
1215 r = devm_request_irq(&pdev->dev, dev->irq, omap_i2c_omap1_isr,
1216 IRQF_NO_SUSPEND, pdev->name, dev);
1217 else
1218 r = devm_request_threaded_irq(&pdev->dev, dev->irq,
1219 omap_i2c_isr, omap_i2c_isr_thread,
1220 IRQF_NO_SUSPEND | IRQF_ONESHOT,
1221 pdev->name, dev);
1222
1223 if (r) {
1224 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
1225 goto err_unuse_clocks;
1226 }
1227
1228 adap = &dev->adapter;
1229 i2c_set_adapdata(adap, dev);
1230 adap->owner = THIS_MODULE;
1231 adap->class = I2C_CLASS_HWMON;
1232 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
1233 adap->algo = &omap_i2c_algo;
1234 adap->dev.parent = &pdev->dev;
1235 adap->dev.of_node = pdev->dev.of_node;
1236
1237 /* i2c device drivers may be active on return from add_adapter() */
1238 adap->nr = pdev->id;
1239 r = i2c_add_numbered_adapter(adap);
1240 if (r) {
1241 dev_err(dev->dev, "failure adding adapter\n");
1242 goto err_unuse_clocks;
1243 }
1244
1245 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr,
1246 major, minor, dev->speed);
1247
1248 of_i2c_register_devices(adap);
1249
1250 pm_runtime_mark_last_busy(dev->dev);
1251 pm_runtime_put_autosuspend(dev->dev);
1252
1253 return 0;
1254
1255 err_unuse_clocks:
1256 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1257 pm_runtime_put(dev->dev);
1258 pm_runtime_disable(&pdev->dev);
1259 err_free_mem:
1260
1261 return r;
1262 }
1263
1264 static int omap_i2c_remove(struct platform_device *pdev)
1265 {
1266 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
1267 int ret;
1268
1269 i2c_del_adapter(&dev->adapter);
1270 ret = pm_runtime_get_sync(&pdev->dev);
1271 if (IS_ERR_VALUE(ret))
1272 return ret;
1273
1274 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1275 pm_runtime_put(&pdev->dev);
1276 pm_runtime_disable(&pdev->dev);
1277 return 0;
1278 }
1279
1280 #ifdef CONFIG_PM
1281 #ifdef CONFIG_PM_RUNTIME
1282 static int omap_i2c_runtime_suspend(struct device *dev)
1283 {
1284 struct platform_device *pdev = to_platform_device(dev);
1285 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
1286
1287 _dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG);
1288
1289 if (_dev->scheme == OMAP_I2C_SCHEME_0)
1290 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);
1291 else
1292 omap_i2c_write_reg(_dev, OMAP_I2C_IP_V2_IRQENABLE_CLR,
1293 OMAP_I2C_IP_V2_INTERRUPTS_MASK);
1294
1295 if (_dev->rev < OMAP_I2C_OMAP1_REV_2) {
1296 omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */
1297 } else {
1298 omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate);
1299
1300 /* Flush posted write */
1301 omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG);
1302 }
1303
1304 return 0;
1305 }
1306
1307 static int omap_i2c_runtime_resume(struct device *dev)
1308 {
1309 struct platform_device *pdev = to_platform_device(dev);
1310 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
1311
1312 if (!_dev->regs)
1313 return 0;
1314
1315 __omap_i2c_init(_dev);
1316
1317 return 0;
1318 }
1319 #endif /* CONFIG_PM_RUNTIME */
1320
1321 static struct dev_pm_ops omap_i2c_pm_ops = {
1322 SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend,
1323 omap_i2c_runtime_resume, NULL)
1324 };
1325 #define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops)
1326 #else
1327 #define OMAP_I2C_PM_OPS NULL
1328 #endif /* CONFIG_PM */
1329
1330 static struct platform_driver omap_i2c_driver = {
1331 .probe = omap_i2c_probe,
1332 .remove = omap_i2c_remove,
1333 .driver = {
1334 .name = "omap_i2c",
1335 .owner = THIS_MODULE,
1336 .pm = OMAP_I2C_PM_OPS,
1337 .of_match_table = of_match_ptr(omap_i2c_of_match),
1338 },
1339 };
1340
1341 /* I2C may be needed to bring up other drivers */
1342 static int __init
1343 omap_i2c_init_driver(void)
1344 {
1345 return platform_driver_register(&omap_i2c_driver);
1346 }
1347 subsys_initcall(omap_i2c_init_driver);
1348
1349 static void __exit omap_i2c_exit_driver(void)
1350 {
1351 platform_driver_unregister(&omap_i2c_driver);
1352 }
1353 module_exit(omap_i2c_exit_driver);
1354
1355 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1356 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1357 MODULE_LICENSE("GPL");
1358 MODULE_ALIAS("platform:omap_i2c");
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