2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/console.h>
29 #include <linux/slab.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include <linux/efi.h>
36 #include "radeon_reg.h"
40 static const char radeon_family_name
[][16] = {
104 #if defined(CONFIG_VGA_SWITCHEROO)
105 bool radeon_is_px(void);
107 static inline bool radeon_is_px(void) { return false; }
111 * radeon_program_register_sequence - program an array of registers.
113 * @rdev: radeon_device pointer
114 * @registers: pointer to the register array
115 * @array_size: size of the register array
117 * Programs an array or registers with and and or masks.
118 * This is a helper for setting golden registers.
120 void radeon_program_register_sequence(struct radeon_device
*rdev
,
121 const u32
*registers
,
122 const u32 array_size
)
124 u32 tmp
, reg
, and_mask
, or_mask
;
130 for (i
= 0; i
< array_size
; i
+=3) {
131 reg
= registers
[i
+ 0];
132 and_mask
= registers
[i
+ 1];
133 or_mask
= registers
[i
+ 2];
135 if (and_mask
== 0xffffffff) {
147 * radeon_surface_init - Clear GPU surface registers.
149 * @rdev: radeon_device pointer
151 * Clear GPU surface registers (r1xx-r5xx).
153 void radeon_surface_init(struct radeon_device
*rdev
)
155 /* FIXME: check this out */
156 if (rdev
->family
< CHIP_R600
) {
159 for (i
= 0; i
< RADEON_GEM_MAX_SURFACES
; i
++) {
160 if (rdev
->surface_regs
[i
].bo
)
161 radeon_bo_get_surface_reg(rdev
->surface_regs
[i
].bo
);
163 radeon_clear_surface_reg(rdev
, i
);
165 /* enable surfaces */
166 WREG32(RADEON_SURFACE_CNTL
, 0);
171 * GPU scratch registers helpers function.
174 * radeon_scratch_init - Init scratch register driver information.
176 * @rdev: radeon_device pointer
178 * Init CP scratch register driver information (r1xx-r5xx)
180 void radeon_scratch_init(struct radeon_device
*rdev
)
184 /* FIXME: check this out */
185 if (rdev
->family
< CHIP_R300
) {
186 rdev
->scratch
.num_reg
= 5;
188 rdev
->scratch
.num_reg
= 7;
190 rdev
->scratch
.reg_base
= RADEON_SCRATCH_REG0
;
191 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
192 rdev
->scratch
.free
[i
] = true;
193 rdev
->scratch
.reg
[i
] = rdev
->scratch
.reg_base
+ (i
* 4);
198 * radeon_scratch_get - Allocate a scratch register
200 * @rdev: radeon_device pointer
201 * @reg: scratch register mmio offset
203 * Allocate a CP scratch register for use by the driver (all asics).
204 * Returns 0 on success or -EINVAL on failure.
206 int radeon_scratch_get(struct radeon_device
*rdev
, uint32_t *reg
)
210 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
211 if (rdev
->scratch
.free
[i
]) {
212 rdev
->scratch
.free
[i
] = false;
213 *reg
= rdev
->scratch
.reg
[i
];
221 * radeon_scratch_free - Free a scratch register
223 * @rdev: radeon_device pointer
224 * @reg: scratch register mmio offset
226 * Free a CP scratch register allocated for use by the driver (all asics)
228 void radeon_scratch_free(struct radeon_device
*rdev
, uint32_t reg
)
232 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
233 if (rdev
->scratch
.reg
[i
] == reg
) {
234 rdev
->scratch
.free
[i
] = true;
241 * GPU doorbell aperture helpers function.
244 * radeon_doorbell_init - Init doorbell driver information.
246 * @rdev: radeon_device pointer
248 * Init doorbell driver information (CIK)
249 * Returns 0 on success, error on failure.
251 int radeon_doorbell_init(struct radeon_device
*rdev
)
255 /* doorbell bar mapping */
256 rdev
->doorbell
.base
= pci_resource_start(rdev
->pdev
, 2);
257 rdev
->doorbell
.size
= pci_resource_len(rdev
->pdev
, 2);
259 /* limit to 4 MB for now */
260 if (rdev
->doorbell
.size
> (4 * 1024 * 1024))
261 rdev
->doorbell
.size
= 4 * 1024 * 1024;
263 rdev
->doorbell
.ptr
= ioremap(rdev
->doorbell
.base
, rdev
->doorbell
.size
);
264 if (rdev
->doorbell
.ptr
== NULL
) {
267 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev
->doorbell
.base
);
268 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev
->doorbell
.size
);
270 rdev
->doorbell
.num_pages
= rdev
->doorbell
.size
/ PAGE_SIZE
;
272 for (i
= 0; i
< rdev
->doorbell
.num_pages
; i
++) {
273 rdev
->doorbell
.free
[i
] = true;
279 * radeon_doorbell_fini - Tear down doorbell driver information.
281 * @rdev: radeon_device pointer
283 * Tear down doorbell driver information (CIK)
285 void radeon_doorbell_fini(struct radeon_device
*rdev
)
287 iounmap(rdev
->doorbell
.ptr
);
288 rdev
->doorbell
.ptr
= NULL
;
292 * radeon_doorbell_get - Allocate a doorbell page
294 * @rdev: radeon_device pointer
295 * @doorbell: doorbell page number
297 * Allocate a doorbell page for use by the driver (all asics).
298 * Returns 0 on success or -EINVAL on failure.
300 int radeon_doorbell_get(struct radeon_device
*rdev
, u32
*doorbell
)
304 for (i
= 0; i
< rdev
->doorbell
.num_pages
; i
++) {
305 if (rdev
->doorbell
.free
[i
]) {
306 rdev
->doorbell
.free
[i
] = false;
315 * radeon_doorbell_free - Free a doorbell page
317 * @rdev: radeon_device pointer
318 * @doorbell: doorbell page number
320 * Free a doorbell page allocated for use by the driver (all asics)
322 void radeon_doorbell_free(struct radeon_device
*rdev
, u32 doorbell
)
324 if (doorbell
< rdev
->doorbell
.num_pages
)
325 rdev
->doorbell
.free
[doorbell
] = true;
330 * Writeback is the the method by which the the GPU updates special pages
331 * in memory with the status of certain GPU events (fences, ring pointers,
336 * radeon_wb_disable - Disable Writeback
338 * @rdev: radeon_device pointer
340 * Disables Writeback (all asics). Used for suspend.
342 void radeon_wb_disable(struct radeon_device
*rdev
)
344 rdev
->wb
.enabled
= false;
348 * radeon_wb_fini - Disable Writeback and free memory
350 * @rdev: radeon_device pointer
352 * Disables Writeback and frees the Writeback memory (all asics).
353 * Used at driver shutdown.
355 void radeon_wb_fini(struct radeon_device
*rdev
)
357 radeon_wb_disable(rdev
);
358 if (rdev
->wb
.wb_obj
) {
359 if (!radeon_bo_reserve(rdev
->wb
.wb_obj
, false)) {
360 radeon_bo_kunmap(rdev
->wb
.wb_obj
);
361 radeon_bo_unpin(rdev
->wb
.wb_obj
);
362 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
364 radeon_bo_unref(&rdev
->wb
.wb_obj
);
366 rdev
->wb
.wb_obj
= NULL
;
371 * radeon_wb_init- Init Writeback driver info and allocate memory
373 * @rdev: radeon_device pointer
375 * Disables Writeback and frees the Writeback memory (all asics).
376 * Used at driver startup.
377 * Returns 0 on success or an -error on failure.
379 int radeon_wb_init(struct radeon_device
*rdev
)
383 if (rdev
->wb
.wb_obj
== NULL
) {
384 r
= radeon_bo_create(rdev
, RADEON_GPU_PAGE_SIZE
, PAGE_SIZE
, true,
385 RADEON_GEM_DOMAIN_GTT
, NULL
, &rdev
->wb
.wb_obj
);
387 dev_warn(rdev
->dev
, "(%d) create WB bo failed\n", r
);
390 r
= radeon_bo_reserve(rdev
->wb
.wb_obj
, false);
391 if (unlikely(r
!= 0)) {
392 radeon_wb_fini(rdev
);
395 r
= radeon_bo_pin(rdev
->wb
.wb_obj
, RADEON_GEM_DOMAIN_GTT
,
398 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
399 dev_warn(rdev
->dev
, "(%d) pin WB bo failed\n", r
);
400 radeon_wb_fini(rdev
);
403 r
= radeon_bo_kmap(rdev
->wb
.wb_obj
, (void **)&rdev
->wb
.wb
);
404 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
406 dev_warn(rdev
->dev
, "(%d) map WB bo failed\n", r
);
407 radeon_wb_fini(rdev
);
412 /* clear wb memory */
413 memset((char *)rdev
->wb
.wb
, 0, RADEON_GPU_PAGE_SIZE
);
414 /* disable event_write fences */
415 rdev
->wb
.use_event
= false;
416 /* disabled via module param */
417 if (radeon_no_wb
== 1) {
418 rdev
->wb
.enabled
= false;
420 if (rdev
->flags
& RADEON_IS_AGP
) {
421 /* often unreliable on AGP */
422 rdev
->wb
.enabled
= false;
423 } else if (rdev
->family
< CHIP_R300
) {
424 /* often unreliable on pre-r300 */
425 rdev
->wb
.enabled
= false;
427 rdev
->wb
.enabled
= true;
428 /* event_write fences are only available on r600+ */
429 if (rdev
->family
>= CHIP_R600
) {
430 rdev
->wb
.use_event
= true;
434 /* always use writeback/events on NI, APUs */
435 if (rdev
->family
>= CHIP_PALM
) {
436 rdev
->wb
.enabled
= true;
437 rdev
->wb
.use_event
= true;
440 dev_info(rdev
->dev
, "WB %sabled\n", rdev
->wb
.enabled
? "en" : "dis");
446 * radeon_vram_location - try to find VRAM location
447 * @rdev: radeon device structure holding all necessary informations
448 * @mc: memory controller structure holding memory informations
449 * @base: base address at which to put VRAM
451 * Function will place try to place VRAM at base address provided
452 * as parameter (which is so far either PCI aperture address or
453 * for IGP TOM base address).
455 * If there is not enough space to fit the unvisible VRAM in the 32bits
456 * address space then we limit the VRAM size to the aperture.
458 * If we are using AGP and if the AGP aperture doesn't allow us to have
459 * room for all the VRAM than we restrict the VRAM to the PCI aperture
460 * size and print a warning.
462 * This function will never fails, worst case are limiting VRAM.
464 * Note: GTT start, end, size should be initialized before calling this
465 * function on AGP platform.
467 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
468 * this shouldn't be a problem as we are using the PCI aperture as a reference.
469 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
472 * Note: we use mc_vram_size as on some board we need to program the mc to
473 * cover the whole aperture even if VRAM size is inferior to aperture size
474 * Novell bug 204882 + along with lots of ubuntu ones
476 * Note: when limiting vram it's safe to overwritte real_vram_size because
477 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
478 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
481 * Note: IGP TOM addr should be the same as the aperture addr, we don't
482 * explicitly check for that thought.
484 * FIXME: when reducing VRAM size align new size on power of 2.
486 void radeon_vram_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
, u64 base
)
488 uint64_t limit
= (uint64_t)radeon_vram_limit
<< 20;
490 mc
->vram_start
= base
;
491 if (mc
->mc_vram_size
> (rdev
->mc
.mc_mask
- base
+ 1)) {
492 dev_warn(rdev
->dev
, "limiting VRAM to PCI aperture size\n");
493 mc
->real_vram_size
= mc
->aper_size
;
494 mc
->mc_vram_size
= mc
->aper_size
;
496 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
497 if (rdev
->flags
& RADEON_IS_AGP
&& mc
->vram_end
> mc
->gtt_start
&& mc
->vram_start
<= mc
->gtt_end
) {
498 dev_warn(rdev
->dev
, "limiting VRAM to PCI aperture size\n");
499 mc
->real_vram_size
= mc
->aper_size
;
500 mc
->mc_vram_size
= mc
->aper_size
;
502 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
503 if (limit
&& limit
< mc
->real_vram_size
)
504 mc
->real_vram_size
= limit
;
505 dev_info(rdev
->dev
, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
506 mc
->mc_vram_size
>> 20, mc
->vram_start
,
507 mc
->vram_end
, mc
->real_vram_size
>> 20);
511 * radeon_gtt_location - try to find GTT location
512 * @rdev: radeon device structure holding all necessary informations
513 * @mc: memory controller structure holding memory informations
515 * Function will place try to place GTT before or after VRAM.
517 * If GTT size is bigger than space left then we ajust GTT size.
518 * Thus function will never fails.
520 * FIXME: when reducing GTT size align new size on power of 2.
522 void radeon_gtt_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
)
524 u64 size_af
, size_bf
;
526 size_af
= ((rdev
->mc
.mc_mask
- mc
->vram_end
) + mc
->gtt_base_align
) & ~mc
->gtt_base_align
;
527 size_bf
= mc
->vram_start
& ~mc
->gtt_base_align
;
528 if (size_bf
> size_af
) {
529 if (mc
->gtt_size
> size_bf
) {
530 dev_warn(rdev
->dev
, "limiting GTT\n");
531 mc
->gtt_size
= size_bf
;
533 mc
->gtt_start
= (mc
->vram_start
& ~mc
->gtt_base_align
) - mc
->gtt_size
;
535 if (mc
->gtt_size
> size_af
) {
536 dev_warn(rdev
->dev
, "limiting GTT\n");
537 mc
->gtt_size
= size_af
;
539 mc
->gtt_start
= (mc
->vram_end
+ 1 + mc
->gtt_base_align
) & ~mc
->gtt_base_align
;
541 mc
->gtt_end
= mc
->gtt_start
+ mc
->gtt_size
- 1;
542 dev_info(rdev
->dev
, "GTT: %lluM 0x%016llX - 0x%016llX\n",
543 mc
->gtt_size
>> 20, mc
->gtt_start
, mc
->gtt_end
);
547 * GPU helpers function.
550 * radeon_card_posted - check if the hw has already been initialized
552 * @rdev: radeon_device pointer
554 * Check if the asic has been initialized (all asics).
555 * Used at driver startup.
556 * Returns true if initialized or false if not.
558 bool radeon_card_posted(struct radeon_device
*rdev
)
562 /* required for EFI mode on macbook2,1 which uses an r5xx asic */
563 if (efi_enabled(EFI_BOOT
) &&
564 (rdev
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_APPLE
) &&
565 (rdev
->family
< CHIP_R600
))
568 if (ASIC_IS_NODCE(rdev
))
571 /* first check CRTCs */
572 if (ASIC_IS_DCE4(rdev
)) {
573 reg
= RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
) |
574 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
575 if (rdev
->num_crtc
>= 4) {
576 reg
|= RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
) |
577 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
579 if (rdev
->num_crtc
>= 6) {
580 reg
|= RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
) |
581 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
583 if (reg
& EVERGREEN_CRTC_MASTER_EN
)
585 } else if (ASIC_IS_AVIVO(rdev
)) {
586 reg
= RREG32(AVIVO_D1CRTC_CONTROL
) |
587 RREG32(AVIVO_D2CRTC_CONTROL
);
588 if (reg
& AVIVO_CRTC_EN
) {
592 reg
= RREG32(RADEON_CRTC_GEN_CNTL
) |
593 RREG32(RADEON_CRTC2_GEN_CNTL
);
594 if (reg
& RADEON_CRTC_EN
) {
600 /* then check MEM_SIZE, in case the crtcs are off */
601 if (rdev
->family
>= CHIP_R600
)
602 reg
= RREG32(R600_CONFIG_MEMSIZE
);
604 reg
= RREG32(RADEON_CONFIG_MEMSIZE
);
614 * radeon_update_bandwidth_info - update display bandwidth params
616 * @rdev: radeon_device pointer
618 * Used when sclk/mclk are switched or display modes are set.
619 * params are used to calculate display watermarks (all asics)
621 void radeon_update_bandwidth_info(struct radeon_device
*rdev
)
624 u32 sclk
= rdev
->pm
.current_sclk
;
625 u32 mclk
= rdev
->pm
.current_mclk
;
627 /* sclk/mclk in Mhz */
628 a
.full
= dfixed_const(100);
629 rdev
->pm
.sclk
.full
= dfixed_const(sclk
);
630 rdev
->pm
.sclk
.full
= dfixed_div(rdev
->pm
.sclk
, a
);
631 rdev
->pm
.mclk
.full
= dfixed_const(mclk
);
632 rdev
->pm
.mclk
.full
= dfixed_div(rdev
->pm
.mclk
, a
);
634 if (rdev
->flags
& RADEON_IS_IGP
) {
635 a
.full
= dfixed_const(16);
636 /* core_bandwidth = sclk(Mhz) * 16 */
637 rdev
->pm
.core_bandwidth
.full
= dfixed_div(rdev
->pm
.sclk
, a
);
642 * radeon_boot_test_post_card - check and possibly initialize the hw
644 * @rdev: radeon_device pointer
646 * Check if the asic is initialized and if not, attempt to initialize
648 * Returns true if initialized or false if not.
650 bool radeon_boot_test_post_card(struct radeon_device
*rdev
)
652 if (radeon_card_posted(rdev
))
656 DRM_INFO("GPU not posted. posting now...\n");
657 if (rdev
->is_atom_bios
)
658 atom_asic_init(rdev
->mode_info
.atom_context
);
660 radeon_combios_asic_init(rdev
->ddev
);
663 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
669 * radeon_dummy_page_init - init dummy page used by the driver
671 * @rdev: radeon_device pointer
673 * Allocate the dummy page used by the driver (all asics).
674 * This dummy page is used by the driver as a filler for gart entries
675 * when pages are taken out of the GART
676 * Returns 0 on sucess, -ENOMEM on failure.
678 int radeon_dummy_page_init(struct radeon_device
*rdev
)
680 if (rdev
->dummy_page
.page
)
682 rdev
->dummy_page
.page
= alloc_page(GFP_DMA32
| GFP_KERNEL
| __GFP_ZERO
);
683 if (rdev
->dummy_page
.page
== NULL
)
685 rdev
->dummy_page
.addr
= pci_map_page(rdev
->pdev
, rdev
->dummy_page
.page
,
686 0, PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
687 if (pci_dma_mapping_error(rdev
->pdev
, rdev
->dummy_page
.addr
)) {
688 dev_err(&rdev
->pdev
->dev
, "Failed to DMA MAP the dummy page\n");
689 __free_page(rdev
->dummy_page
.page
);
690 rdev
->dummy_page
.page
= NULL
;
697 * radeon_dummy_page_fini - free dummy page used by the driver
699 * @rdev: radeon_device pointer
701 * Frees the dummy page used by the driver (all asics).
703 void radeon_dummy_page_fini(struct radeon_device
*rdev
)
705 if (rdev
->dummy_page
.page
== NULL
)
707 pci_unmap_page(rdev
->pdev
, rdev
->dummy_page
.addr
,
708 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
709 __free_page(rdev
->dummy_page
.page
);
710 rdev
->dummy_page
.page
= NULL
;
714 /* ATOM accessor methods */
716 * ATOM is an interpreted byte code stored in tables in the vbios. The
717 * driver registers callbacks to access registers and the interpreter
718 * in the driver parses the tables and executes then to program specific
719 * actions (set display modes, asic init, etc.). See radeon_atombios.c,
720 * atombios.h, and atom.c
724 * cail_pll_read - read PLL register
726 * @info: atom card_info pointer
727 * @reg: PLL register offset
729 * Provides a PLL register accessor for the atom interpreter (r4xx+).
730 * Returns the value of the PLL register.
732 static uint32_t cail_pll_read(struct card_info
*info
, uint32_t reg
)
734 struct radeon_device
*rdev
= info
->dev
->dev_private
;
737 r
= rdev
->pll_rreg(rdev
, reg
);
742 * cail_pll_write - write PLL register
744 * @info: atom card_info pointer
745 * @reg: PLL register offset
746 * @val: value to write to the pll register
748 * Provides a PLL register accessor for the atom interpreter (r4xx+).
750 static void cail_pll_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
752 struct radeon_device
*rdev
= info
->dev
->dev_private
;
754 rdev
->pll_wreg(rdev
, reg
, val
);
758 * cail_mc_read - read MC (Memory Controller) register
760 * @info: atom card_info pointer
761 * @reg: MC register offset
763 * Provides an MC register accessor for the atom interpreter (r4xx+).
764 * Returns the value of the MC register.
766 static uint32_t cail_mc_read(struct card_info
*info
, uint32_t reg
)
768 struct radeon_device
*rdev
= info
->dev
->dev_private
;
771 r
= rdev
->mc_rreg(rdev
, reg
);
776 * cail_mc_write - write MC (Memory Controller) register
778 * @info: atom card_info pointer
779 * @reg: MC register offset
780 * @val: value to write to the pll register
782 * Provides a MC register accessor for the atom interpreter (r4xx+).
784 static void cail_mc_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
786 struct radeon_device
*rdev
= info
->dev
->dev_private
;
788 rdev
->mc_wreg(rdev
, reg
, val
);
792 * cail_reg_write - write MMIO register
794 * @info: atom card_info pointer
795 * @reg: MMIO register offset
796 * @val: value to write to the pll register
798 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
800 static void cail_reg_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
802 struct radeon_device
*rdev
= info
->dev
->dev_private
;
808 * cail_reg_read - read MMIO register
810 * @info: atom card_info pointer
811 * @reg: MMIO register offset
813 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
814 * Returns the value of the MMIO register.
816 static uint32_t cail_reg_read(struct card_info
*info
, uint32_t reg
)
818 struct radeon_device
*rdev
= info
->dev
->dev_private
;
826 * cail_ioreg_write - write IO register
828 * @info: atom card_info pointer
829 * @reg: IO register offset
830 * @val: value to write to the pll register
832 * Provides a IO register accessor for the atom interpreter (r4xx+).
834 static void cail_ioreg_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
836 struct radeon_device
*rdev
= info
->dev
->dev_private
;
838 WREG32_IO(reg
*4, val
);
842 * cail_ioreg_read - read IO register
844 * @info: atom card_info pointer
845 * @reg: IO register offset
847 * Provides an IO register accessor for the atom interpreter (r4xx+).
848 * Returns the value of the IO register.
850 static uint32_t cail_ioreg_read(struct card_info
*info
, uint32_t reg
)
852 struct radeon_device
*rdev
= info
->dev
->dev_private
;
855 r
= RREG32_IO(reg
*4);
860 * radeon_atombios_init - init the driver info and callbacks for atombios
862 * @rdev: radeon_device pointer
864 * Initializes the driver info and register access callbacks for the
865 * ATOM interpreter (r4xx+).
866 * Returns 0 on sucess, -ENOMEM on failure.
867 * Called at driver startup.
869 int radeon_atombios_init(struct radeon_device
*rdev
)
871 struct card_info
*atom_card_info
=
872 kzalloc(sizeof(struct card_info
), GFP_KERNEL
);
877 rdev
->mode_info
.atom_card_info
= atom_card_info
;
878 atom_card_info
->dev
= rdev
->ddev
;
879 atom_card_info
->reg_read
= cail_reg_read
;
880 atom_card_info
->reg_write
= cail_reg_write
;
881 /* needed for iio ops */
883 atom_card_info
->ioreg_read
= cail_ioreg_read
;
884 atom_card_info
->ioreg_write
= cail_ioreg_write
;
886 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
887 atom_card_info
->ioreg_read
= cail_reg_read
;
888 atom_card_info
->ioreg_write
= cail_reg_write
;
890 atom_card_info
->mc_read
= cail_mc_read
;
891 atom_card_info
->mc_write
= cail_mc_write
;
892 atom_card_info
->pll_read
= cail_pll_read
;
893 atom_card_info
->pll_write
= cail_pll_write
;
895 rdev
->mode_info
.atom_context
= atom_parse(atom_card_info
, rdev
->bios
);
896 if (!rdev
->mode_info
.atom_context
) {
897 radeon_atombios_fini(rdev
);
901 mutex_init(&rdev
->mode_info
.atom_context
->mutex
);
902 radeon_atom_initialize_bios_scratch_regs(rdev
->ddev
);
903 atom_allocate_fb_scratch(rdev
->mode_info
.atom_context
);
908 * radeon_atombios_fini - free the driver info and callbacks for atombios
910 * @rdev: radeon_device pointer
912 * Frees the driver info and register access callbacks for the ATOM
913 * interpreter (r4xx+).
914 * Called at driver shutdown.
916 void radeon_atombios_fini(struct radeon_device
*rdev
)
918 if (rdev
->mode_info
.atom_context
) {
919 kfree(rdev
->mode_info
.atom_context
->scratch
);
921 kfree(rdev
->mode_info
.atom_context
);
922 rdev
->mode_info
.atom_context
= NULL
;
923 kfree(rdev
->mode_info
.atom_card_info
);
924 rdev
->mode_info
.atom_card_info
= NULL
;
929 * COMBIOS is the bios format prior to ATOM. It provides
930 * command tables similar to ATOM, but doesn't have a unified
931 * parser. See radeon_combios.c
935 * radeon_combios_init - init the driver info for combios
937 * @rdev: radeon_device pointer
939 * Initializes the driver info for combios (r1xx-r3xx).
940 * Returns 0 on sucess.
941 * Called at driver startup.
943 int radeon_combios_init(struct radeon_device
*rdev
)
945 radeon_combios_initialize_bios_scratch_regs(rdev
->ddev
);
950 * radeon_combios_fini - free the driver info for combios
952 * @rdev: radeon_device pointer
954 * Frees the driver info for combios (r1xx-r3xx).
955 * Called at driver shutdown.
957 void radeon_combios_fini(struct radeon_device
*rdev
)
961 /* if we get transitioned to only one device, take VGA back */
963 * radeon_vga_set_decode - enable/disable vga decode
965 * @cookie: radeon_device pointer
966 * @state: enable/disable vga decode
968 * Enable/disable vga decode (all asics).
969 * Returns VGA resource flags.
971 static unsigned int radeon_vga_set_decode(void *cookie
, bool state
)
973 struct radeon_device
*rdev
= cookie
;
974 radeon_vga_set_state(rdev
, state
);
976 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
977 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
979 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
983 * radeon_check_pot_argument - check that argument is a power of two
985 * @arg: value to check
987 * Validates that a certain argument is a power of two (all asics).
988 * Returns true if argument is valid.
990 static bool radeon_check_pot_argument(int arg
)
992 return (arg
& (arg
- 1)) == 0;
996 * radeon_check_arguments - validate module params
998 * @rdev: radeon_device pointer
1000 * Validates certain module parameters and updates
1001 * the associated values used by the driver (all asics).
1003 static void radeon_check_arguments(struct radeon_device
*rdev
)
1005 /* vramlimit must be a power of two */
1006 if (!radeon_check_pot_argument(radeon_vram_limit
)) {
1007 dev_warn(rdev
->dev
, "vram limit (%d) must be a power of 2\n",
1009 radeon_vram_limit
= 0;
1012 if (radeon_gart_size
== -1) {
1013 /* default to a larger gart size on newer asics */
1014 if (rdev
->family
>= CHIP_RV770
)
1015 radeon_gart_size
= 1024;
1017 radeon_gart_size
= 512;
1019 /* gtt size must be power of two and greater or equal to 32M */
1020 if (radeon_gart_size
< 32) {
1021 dev_warn(rdev
->dev
, "gart size (%d) too small\n",
1023 if (rdev
->family
>= CHIP_RV770
)
1024 radeon_gart_size
= 1024;
1026 radeon_gart_size
= 512;
1027 } else if (!radeon_check_pot_argument(radeon_gart_size
)) {
1028 dev_warn(rdev
->dev
, "gart size (%d) must be a power of 2\n",
1030 if (rdev
->family
>= CHIP_RV770
)
1031 radeon_gart_size
= 1024;
1033 radeon_gart_size
= 512;
1035 rdev
->mc
.gtt_size
= (uint64_t)radeon_gart_size
<< 20;
1037 /* AGP mode can only be -1, 1, 2, 4, 8 */
1038 switch (radeon_agpmode
) {
1047 dev_warn(rdev
->dev
, "invalid AGP mode %d (valid mode: "
1048 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode
);
1055 * radeon_switcheroo_quirk_long_wakeup - return true if longer d3 delay is
1056 * needed for waking up.
1058 * @pdev: pci dev pointer
1060 static bool radeon_switcheroo_quirk_long_wakeup(struct pci_dev
*pdev
)
1063 /* 6600m in a macbook pro */
1064 if (pdev
->subsystem_vendor
== PCI_VENDOR_ID_APPLE
&&
1065 pdev
->subsystem_device
== 0x00e2) {
1066 printk(KERN_INFO
"radeon: quirking longer d3 wakeup delay\n");
1074 * radeon_switcheroo_set_state - set switcheroo state
1076 * @pdev: pci dev pointer
1077 * @state: vga switcheroo state
1079 * Callback for the switcheroo driver. Suspends or resumes the
1080 * the asics before or after it is powered up using ACPI methods.
1082 static void radeon_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
1084 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1086 if (radeon_is_px() && state
== VGA_SWITCHEROO_OFF
)
1089 if (state
== VGA_SWITCHEROO_ON
) {
1090 unsigned d3_delay
= dev
->pdev
->d3_delay
;
1092 printk(KERN_INFO
"radeon: switched on\n");
1093 /* don't suspend or resume card normally */
1094 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1096 if (d3_delay
< 20 && radeon_switcheroo_quirk_long_wakeup(pdev
))
1097 dev
->pdev
->d3_delay
= 20;
1099 radeon_resume_kms(dev
, true, true);
1101 dev
->pdev
->d3_delay
= d3_delay
;
1103 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
1104 drm_kms_helper_poll_enable(dev
);
1106 printk(KERN_INFO
"radeon: switched off\n");
1107 drm_kms_helper_poll_disable(dev
);
1108 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1109 radeon_suspend_kms(dev
, true, true);
1110 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
1115 * radeon_switcheroo_can_switch - see if switcheroo state can change
1117 * @pdev: pci dev pointer
1119 * Callback for the switcheroo driver. Check of the switcheroo
1120 * state can be changed.
1121 * Returns true if the state can be changed, false if not.
1123 static bool radeon_switcheroo_can_switch(struct pci_dev
*pdev
)
1125 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1128 spin_lock(&dev
->count_lock
);
1129 can_switch
= (dev
->open_count
== 0);
1130 spin_unlock(&dev
->count_lock
);
1134 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops
= {
1135 .set_gpu_state
= radeon_switcheroo_set_state
,
1137 .can_switch
= radeon_switcheroo_can_switch
,
1141 * radeon_device_init - initialize the driver
1143 * @rdev: radeon_device pointer
1144 * @pdev: drm dev pointer
1145 * @pdev: pci dev pointer
1146 * @flags: driver flags
1148 * Initializes the driver info and hw (all asics).
1149 * Returns 0 for success or an error on failure.
1150 * Called at driver startup.
1152 int radeon_device_init(struct radeon_device
*rdev
,
1153 struct drm_device
*ddev
,
1154 struct pci_dev
*pdev
,
1159 bool runtime
= false;
1161 rdev
->shutdown
= false;
1162 rdev
->dev
= &pdev
->dev
;
1165 rdev
->flags
= flags
;
1166 rdev
->family
= flags
& RADEON_FAMILY_MASK
;
1167 rdev
->is_atom_bios
= false;
1168 rdev
->usec_timeout
= RADEON_MAX_USEC_TIMEOUT
;
1169 rdev
->mc
.gtt_size
= 512 * 1024 * 1024;
1170 rdev
->accel_working
= false;
1171 /* set up ring ids */
1172 for (i
= 0; i
< RADEON_NUM_RINGS
; i
++) {
1173 rdev
->ring
[i
].idx
= i
;
1176 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
1177 radeon_family_name
[rdev
->family
], pdev
->vendor
, pdev
->device
,
1178 pdev
->subsystem_vendor
, pdev
->subsystem_device
);
1180 /* mutex initialization are all done here so we
1181 * can recall function without having locking issues */
1182 mutex_init(&rdev
->ring_lock
);
1183 mutex_init(&rdev
->dc_hw_i2c_mutex
);
1184 atomic_set(&rdev
->ih
.lock
, 0);
1185 mutex_init(&rdev
->gem
.mutex
);
1186 mutex_init(&rdev
->pm
.mutex
);
1187 mutex_init(&rdev
->gpu_clock_mutex
);
1188 mutex_init(&rdev
->srbm_mutex
);
1189 init_rwsem(&rdev
->pm
.mclk_lock
);
1190 init_rwsem(&rdev
->exclusive_lock
);
1191 init_waitqueue_head(&rdev
->irq
.vblank_queue
);
1192 r
= radeon_gem_init(rdev
);
1195 /* initialize vm here */
1196 mutex_init(&rdev
->vm_manager
.lock
);
1197 /* Adjust VM size here.
1198 * Currently set to 4GB ((1 << 20) 4k pages).
1199 * Max GPUVM size for cayman and SI is 40 bits.
1201 rdev
->vm_manager
.max_pfn
= 1 << 20;
1202 INIT_LIST_HEAD(&rdev
->vm_manager
.lru_vm
);
1204 /* Set asic functions */
1205 r
= radeon_asic_init(rdev
);
1208 radeon_check_arguments(rdev
);
1210 /* all of the newer IGP chips have an internal gart
1211 * However some rs4xx report as AGP, so remove that here.
1213 if ((rdev
->family
>= CHIP_RS400
) &&
1214 (rdev
->flags
& RADEON_IS_IGP
)) {
1215 rdev
->flags
&= ~RADEON_IS_AGP
;
1218 if (rdev
->flags
& RADEON_IS_AGP
&& radeon_agpmode
== -1) {
1219 radeon_agp_disable(rdev
);
1222 /* Set the internal MC address mask
1223 * This is the max address of the GPU's
1224 * internal address space.
1226 if (rdev
->family
>= CHIP_CAYMAN
)
1227 rdev
->mc
.mc_mask
= 0xffffffffffULL
; /* 40 bit MC */
1228 else if (rdev
->family
>= CHIP_CEDAR
)
1229 rdev
->mc
.mc_mask
= 0xfffffffffULL
; /* 36 bit MC */
1231 rdev
->mc
.mc_mask
= 0xffffffffULL
; /* 32 bit MC */
1233 /* set DMA mask + need_dma32 flags.
1234 * PCIE - can handle 40-bits.
1235 * IGP - can handle 40-bits
1236 * AGP - generally dma32 is safest
1237 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1239 rdev
->need_dma32
= false;
1240 if (rdev
->flags
& RADEON_IS_AGP
)
1241 rdev
->need_dma32
= true;
1242 if ((rdev
->flags
& RADEON_IS_PCI
) &&
1243 (rdev
->family
<= CHIP_RS740
))
1244 rdev
->need_dma32
= true;
1246 dma_bits
= rdev
->need_dma32
? 32 : 40;
1247 r
= pci_set_dma_mask(rdev
->pdev
, DMA_BIT_MASK(dma_bits
));
1249 rdev
->need_dma32
= true;
1251 printk(KERN_WARNING
"radeon: No suitable DMA available.\n");
1253 r
= pci_set_consistent_dma_mask(rdev
->pdev
, DMA_BIT_MASK(dma_bits
));
1255 pci_set_consistent_dma_mask(rdev
->pdev
, DMA_BIT_MASK(32));
1256 printk(KERN_WARNING
"radeon: No coherent DMA available.\n");
1259 /* Registers mapping */
1260 /* TODO: block userspace mapping of io register */
1261 spin_lock_init(&rdev
->mmio_idx_lock
);
1262 spin_lock_init(&rdev
->smc_idx_lock
);
1263 spin_lock_init(&rdev
->pll_idx_lock
);
1264 spin_lock_init(&rdev
->mc_idx_lock
);
1265 spin_lock_init(&rdev
->pcie_idx_lock
);
1266 spin_lock_init(&rdev
->pciep_idx_lock
);
1267 spin_lock_init(&rdev
->pif_idx_lock
);
1268 spin_lock_init(&rdev
->cg_idx_lock
);
1269 spin_lock_init(&rdev
->uvd_idx_lock
);
1270 spin_lock_init(&rdev
->rcu_idx_lock
);
1271 spin_lock_init(&rdev
->didt_idx_lock
);
1272 spin_lock_init(&rdev
->end_idx_lock
);
1273 if (rdev
->family
>= CHIP_BONAIRE
) {
1274 rdev
->rmmio_base
= pci_resource_start(rdev
->pdev
, 5);
1275 rdev
->rmmio_size
= pci_resource_len(rdev
->pdev
, 5);
1277 rdev
->rmmio_base
= pci_resource_start(rdev
->pdev
, 2);
1278 rdev
->rmmio_size
= pci_resource_len(rdev
->pdev
, 2);
1280 rdev
->rmmio
= ioremap(rdev
->rmmio_base
, rdev
->rmmio_size
);
1281 if (rdev
->rmmio
== NULL
) {
1284 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev
->rmmio_base
);
1285 DRM_INFO("register mmio size: %u\n", (unsigned)rdev
->rmmio_size
);
1287 /* doorbell bar mapping */
1288 if (rdev
->family
>= CHIP_BONAIRE
)
1289 radeon_doorbell_init(rdev
);
1291 /* io port mapping */
1292 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
1293 if (pci_resource_flags(rdev
->pdev
, i
) & IORESOURCE_IO
) {
1294 rdev
->rio_mem_size
= pci_resource_len(rdev
->pdev
, i
);
1295 rdev
->rio_mem
= pci_iomap(rdev
->pdev
, i
, rdev
->rio_mem_size
);
1299 if (rdev
->rio_mem
== NULL
)
1300 DRM_ERROR("Unable to find PCI I/O BAR\n");
1302 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1303 /* this will fail for cards that aren't VGA class devices, just
1305 vga_client_register(rdev
->pdev
, rdev
, NULL
, radeon_vga_set_decode
);
1307 if (radeon_runtime_pm
== 1)
1309 if ((radeon_runtime_pm
== -1) && radeon_is_px())
1311 vga_switcheroo_register_client(rdev
->pdev
, &radeon_switcheroo_ops
, runtime
);
1313 vga_switcheroo_init_domain_pm_ops(rdev
->dev
, &rdev
->vga_pm_domain
);
1315 r
= radeon_init(rdev
);
1319 r
= radeon_ib_ring_tests(rdev
);
1321 DRM_ERROR("ib ring test failed (%d).\n", r
);
1323 r
= radeon_gem_debugfs_init(rdev
);
1325 DRM_ERROR("registering gem debugfs failed (%d).\n", r
);
1328 if (rdev
->flags
& RADEON_IS_AGP
&& !rdev
->accel_working
) {
1329 /* Acceleration not working on AGP card try again
1330 * with fallback to PCI or PCIE GART
1332 radeon_asic_reset(rdev
);
1334 radeon_agp_disable(rdev
);
1335 r
= radeon_init(rdev
);
1339 if ((radeon_testing
& 1)) {
1340 if (rdev
->accel_working
)
1341 radeon_test_moves(rdev
);
1343 DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
1345 if ((radeon_testing
& 2)) {
1346 if (rdev
->accel_working
)
1347 radeon_test_syncing(rdev
);
1349 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
1351 if (radeon_benchmarking
) {
1352 if (rdev
->accel_working
)
1353 radeon_benchmark(rdev
, radeon_benchmarking
);
1355 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
1360 static void radeon_debugfs_remove_files(struct radeon_device
*rdev
);
1363 * radeon_device_fini - tear down the driver
1365 * @rdev: radeon_device pointer
1367 * Tear down the driver info (all asics).
1368 * Called at driver shutdown.
1370 void radeon_device_fini(struct radeon_device
*rdev
)
1372 DRM_INFO("radeon: finishing device.\n");
1373 rdev
->shutdown
= true;
1374 /* evict vram memory */
1375 radeon_bo_evict_vram(rdev
);
1377 vga_switcheroo_unregister_client(rdev
->pdev
);
1378 vga_client_register(rdev
->pdev
, NULL
, NULL
, NULL
);
1380 pci_iounmap(rdev
->pdev
, rdev
->rio_mem
);
1381 rdev
->rio_mem
= NULL
;
1382 iounmap(rdev
->rmmio
);
1384 if (rdev
->family
>= CHIP_BONAIRE
)
1385 radeon_doorbell_fini(rdev
);
1386 radeon_debugfs_remove_files(rdev
);
1394 * radeon_suspend_kms - initiate device suspend
1396 * @pdev: drm dev pointer
1397 * @state: suspend state
1399 * Puts the hw in the suspend state (all asics).
1400 * Returns 0 for success or an error on failure.
1401 * Called at driver suspend.
1403 int radeon_suspend_kms(struct drm_device
*dev
, bool suspend
, bool fbcon
)
1405 struct radeon_device
*rdev
;
1406 struct drm_crtc
*crtc
;
1407 struct drm_connector
*connector
;
1409 bool force_completion
= false;
1411 if (dev
== NULL
|| dev
->dev_private
== NULL
) {
1415 rdev
= dev
->dev_private
;
1417 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1420 drm_kms_helper_poll_disable(dev
);
1422 /* turn off display hw */
1423 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
1424 drm_helper_connector_dpms(connector
, DRM_MODE_DPMS_OFF
);
1427 /* unpin the front buffers */
1428 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
1429 struct radeon_framebuffer
*rfb
= to_radeon_framebuffer(crtc
->fb
);
1430 struct radeon_bo
*robj
;
1432 if (rfb
== NULL
|| rfb
->obj
== NULL
) {
1435 robj
= gem_to_radeon_bo(rfb
->obj
);
1436 /* don't unpin kernel fb objects */
1437 if (!radeon_fbdev_robj_is_fb(rdev
, robj
)) {
1438 r
= radeon_bo_reserve(robj
, false);
1440 radeon_bo_unpin(robj
);
1441 radeon_bo_unreserve(robj
);
1445 /* evict vram memory */
1446 radeon_bo_evict_vram(rdev
);
1448 mutex_lock(&rdev
->ring_lock
);
1449 /* wait for gpu to finish processing current batch */
1450 for (i
= 0; i
< RADEON_NUM_RINGS
; i
++) {
1451 r
= radeon_fence_wait_empty_locked(rdev
, i
);
1453 /* delay GPU reset to resume */
1454 force_completion
= true;
1457 if (force_completion
) {
1458 radeon_fence_driver_force_completion(rdev
);
1460 mutex_unlock(&rdev
->ring_lock
);
1462 radeon_save_bios_scratch_regs(rdev
);
1464 radeon_pm_suspend(rdev
);
1465 radeon_suspend(rdev
);
1466 radeon_hpd_fini(rdev
);
1467 /* evict remaining vram memory */
1468 radeon_bo_evict_vram(rdev
);
1470 radeon_agp_suspend(rdev
);
1472 pci_save_state(dev
->pdev
);
1474 /* Shut down the device */
1475 pci_disable_device(dev
->pdev
);
1476 pci_set_power_state(dev
->pdev
, PCI_D3hot
);
1481 radeon_fbdev_set_suspend(rdev
, 1);
1488 * radeon_resume_kms - initiate device resume
1490 * @pdev: drm dev pointer
1492 * Bring the hw back to operating state (all asics).
1493 * Returns 0 for success or an error on failure.
1494 * Called at driver resume.
1496 int radeon_resume_kms(struct drm_device
*dev
, bool resume
, bool fbcon
)
1498 struct drm_connector
*connector
;
1499 struct radeon_device
*rdev
= dev
->dev_private
;
1502 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1509 pci_set_power_state(dev
->pdev
, PCI_D0
);
1510 pci_restore_state(dev
->pdev
);
1511 if (pci_enable_device(dev
->pdev
)) {
1517 /* resume AGP if in use */
1518 radeon_agp_resume(rdev
);
1519 radeon_resume(rdev
);
1521 r
= radeon_ib_ring_tests(rdev
);
1523 DRM_ERROR("ib ring test failed (%d).\n", r
);
1525 radeon_pm_resume(rdev
);
1526 radeon_restore_bios_scratch_regs(rdev
);
1529 radeon_fbdev_set_suspend(rdev
, 0);
1533 /* init dig PHYs, disp eng pll */
1534 if (rdev
->is_atom_bios
) {
1535 radeon_atom_encoder_init(rdev
);
1536 radeon_atom_disp_eng_pll_init(rdev
);
1537 /* turn on the BL */
1538 if (rdev
->mode_info
.bl_encoder
) {
1539 u8 bl_level
= radeon_get_backlight_level(rdev
,
1540 rdev
->mode_info
.bl_encoder
);
1541 radeon_set_backlight_level(rdev
, rdev
->mode_info
.bl_encoder
,
1545 /* reset hpd state */
1546 radeon_hpd_init(rdev
);
1547 /* blat the mode back in */
1548 drm_helper_resume_force_mode(dev
);
1549 /* turn on display hw */
1550 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
1551 drm_helper_connector_dpms(connector
, DRM_MODE_DPMS_ON
);
1554 drm_kms_helper_poll_enable(dev
);
1559 * radeon_gpu_reset - reset the asic
1561 * @rdev: radeon device pointer
1563 * Attempt the reset the GPU if it has hung (all asics).
1564 * Returns 0 for success or an error on failure.
1566 int radeon_gpu_reset(struct radeon_device
*rdev
)
1568 unsigned ring_sizes
[RADEON_NUM_RINGS
];
1569 uint32_t *ring_data
[RADEON_NUM_RINGS
];
1576 down_write(&rdev
->exclusive_lock
);
1577 radeon_save_bios_scratch_regs(rdev
);
1579 resched
= ttm_bo_lock_delayed_workqueue(&rdev
->mman
.bdev
);
1580 radeon_pm_suspend(rdev
);
1581 radeon_suspend(rdev
);
1583 for (i
= 0; i
< RADEON_NUM_RINGS
; ++i
) {
1584 ring_sizes
[i
] = radeon_ring_backup(rdev
, &rdev
->ring
[i
],
1586 if (ring_sizes
[i
]) {
1588 dev_info(rdev
->dev
, "Saved %d dwords of commands "
1589 "on ring %d.\n", ring_sizes
[i
], i
);
1594 r
= radeon_asic_reset(rdev
);
1596 dev_info(rdev
->dev
, "GPU reset succeeded, trying to resume\n");
1597 radeon_resume(rdev
);
1600 radeon_restore_bios_scratch_regs(rdev
);
1603 for (i
= 0; i
< RADEON_NUM_RINGS
; ++i
) {
1604 radeon_ring_restore(rdev
, &rdev
->ring
[i
],
1605 ring_sizes
[i
], ring_data
[i
]);
1607 ring_data
[i
] = NULL
;
1610 r
= radeon_ib_ring_tests(rdev
);
1612 dev_err(rdev
->dev
, "ib ring test failed (%d).\n", r
);
1615 radeon_suspend(rdev
);
1620 radeon_fence_driver_force_completion(rdev
);
1621 for (i
= 0; i
< RADEON_NUM_RINGS
; ++i
) {
1622 kfree(ring_data
[i
]);
1626 radeon_pm_resume(rdev
);
1627 drm_helper_resume_force_mode(rdev
->ddev
);
1629 ttm_bo_unlock_delayed_workqueue(&rdev
->mman
.bdev
, resched
);
1631 /* bad news, how to tell it to userspace ? */
1632 dev_info(rdev
->dev
, "GPU reset failed\n");
1635 up_write(&rdev
->exclusive_lock
);
1643 int radeon_debugfs_add_files(struct radeon_device
*rdev
,
1644 struct drm_info_list
*files
,
1649 for (i
= 0; i
< rdev
->debugfs_count
; i
++) {
1650 if (rdev
->debugfs
[i
].files
== files
) {
1651 /* Already registered */
1656 i
= rdev
->debugfs_count
+ 1;
1657 if (i
> RADEON_DEBUGFS_MAX_COMPONENTS
) {
1658 DRM_ERROR("Reached maximum number of debugfs components.\n");
1659 DRM_ERROR("Report so we increase "
1660 "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1663 rdev
->debugfs
[rdev
->debugfs_count
].files
= files
;
1664 rdev
->debugfs
[rdev
->debugfs_count
].num_files
= nfiles
;
1665 rdev
->debugfs_count
= i
;
1666 #if defined(CONFIG_DEBUG_FS)
1667 drm_debugfs_create_files(files
, nfiles
,
1668 rdev
->ddev
->control
->debugfs_root
,
1669 rdev
->ddev
->control
);
1670 drm_debugfs_create_files(files
, nfiles
,
1671 rdev
->ddev
->primary
->debugfs_root
,
1672 rdev
->ddev
->primary
);
1677 static void radeon_debugfs_remove_files(struct radeon_device
*rdev
)
1679 #if defined(CONFIG_DEBUG_FS)
1682 for (i
= 0; i
< rdev
->debugfs_count
; i
++) {
1683 drm_debugfs_remove_files(rdev
->debugfs
[i
].files
,
1684 rdev
->debugfs
[i
].num_files
,
1685 rdev
->ddev
->control
);
1686 drm_debugfs_remove_files(rdev
->debugfs
[i
].files
,
1687 rdev
->debugfs
[i
].num_files
,
1688 rdev
->ddev
->primary
);
1693 #if defined(CONFIG_DEBUG_FS)
1694 int radeon_debugfs_init(struct drm_minor
*minor
)
1699 void radeon_debugfs_cleanup(struct drm_minor
*minor
)