drivers/net/ixgbe/ixgbe.h

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #ifndef _IXGBE_H_
  29 #define _IXGBE_H_
  30
  31 #include <linux/bitops.h>
  32 #include <linux/types.h>
  33 #include <linux/pci.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/cpumask.h>
  36 #include <linux/aer.h>
  37 #include <linux/if_vlan.h>
  38
  39 #include "ixgbe_type.h"
  40 #include "ixgbe_common.h"
  41 #include "ixgbe_dcb.h"
  42 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
  43 #define IXGBE_FCOE
  44 #include "ixgbe_fcoe.h"
  45 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
  46 #ifdef CONFIG_IXGBE_DCA
  47 #include <linux/dca.h>
  48 #endif
  49
  50 /* common prefix used by pr_<> macros */
  51 #undef pr_fmt
  52 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  53
  54 /* TX/RX descriptor defines */
  55 #define IXGBE_DEFAULT_TXD                   512
  56 #define IXGBE_MAX_TXD                      4096
  57 #define IXGBE_MIN_TXD                        64
  58
  59 #define IXGBE_DEFAULT_RXD                   512
  60 #define IXGBE_MAX_RXD                      4096
  61 #define IXGBE_MIN_RXD                        64
  62
  63 /* flow control */
  64 #define IXGBE_DEFAULT_FCRTL             0x10000
  65 #define IXGBE_MIN_FCRTL                    0x40
  66 #define IXGBE_MAX_FCRTL                 0x7FF80
  67 #define IXGBE_DEFAULT_FCRTH             0x20000
  68 #define IXGBE_MIN_FCRTH                   0x600
  69 #define IXGBE_MAX_FCRTH                 0x7FFF0
  70 #define IXGBE_DEFAULT_FCPAUSE            0xFFFF
  71 #define IXGBE_MIN_FCPAUSE                     0
  72 #define IXGBE_MAX_FCPAUSE                0xFFFF
  73
  74 /* Supported Rx Buffer Sizes */
  75 #define IXGBE_RXBUFFER_512   512    /* Used for packet split */
  76 #define IXGBE_RXBUFFER_2048  2048
  77 #define IXGBE_RXBUFFER_4096  4096
  78 #define IXGBE_RXBUFFER_8192  8192
  79 #define IXGBE_MAX_RXBUFFER   16384  /* largest size for a single descriptor */
  80
  81 /*
  82  * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
  83  * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
  84  * this adds up to 512 bytes of extra data meaning the smallest allocation
  85  * we could have is 1K.
  86  * i.e. RXBUFFER_512 --> size-1024 slab
  87  */
  88 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
  89
  90 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
  91
  92 /* How many Rx Buffers do we bundle into one write to the hardware ? */
  93 #define IXGBE_RX_BUFFER_WRITE   16      /* Must be power of 2 */
  94
  95 #define IXGBE_TX_FLAGS_CSUM             (u32)(1)
  96 #define IXGBE_TX_FLAGS_VLAN             (u32)(1 << 1)
  97 #define IXGBE_TX_FLAGS_TSO              (u32)(1 << 2)
  98 #define IXGBE_TX_FLAGS_IPV4             (u32)(1 << 3)
  99 #define IXGBE_TX_FLAGS_FCOE             (u32)(1 << 4)
 100 #define IXGBE_TX_FLAGS_FSO              (u32)(1 << 5)
 101 #define IXGBE_TX_FLAGS_VLAN_MASK        0xffff0000
 102 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK   0x0000e000
 103 #define IXGBE_TX_FLAGS_VLAN_SHIFT       16
 104
 105 #define IXGBE_MAX_RSC_INT_RATE          162760
 106
 107 #define IXGBE_MAX_VF_MC_ENTRIES         30
 108 #define IXGBE_MAX_VF_FUNCTIONS          64
 109 #define IXGBE_MAX_VFTA_ENTRIES          128
 110 #define MAX_EMULATION_MAC_ADDRS         16
 111 #define VMDQ_P(p)   ((p) + adapter->num_vfs)
 112
 113 struct vf_data_storage {
 114         unsigned char vf_mac_addresses[ETH_ALEN];
 115         u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
 116         u16 num_vf_mc_hashes;
 117         u16 default_vf_vlan_id;
 118         u16 vlans_enabled;
 119         bool clear_to_send;
 120         bool pf_set_mac;
 121         u16 pf_vlan; /* When set, guest VLAN config not allowed. */
 122         u16 pf_qos;
 123 };
 124
 125 /* wrapper around a pointer to a socket buffer,
 126  * so a DMA handle can be stored along with the buffer */
 127 struct ixgbe_tx_buffer {
 128         struct sk_buff *skb;
 129         dma_addr_t dma;
 130         unsigned long time_stamp;
 131         u16 length;
 132         u16 next_to_watch;
 133         u16 mapped_as_page;
 134 };
 135
 136 struct ixgbe_rx_buffer {
 137         struct sk_buff *skb;
 138         dma_addr_t dma;
 139         struct page *page;
 140         dma_addr_t page_dma;
 141         unsigned int page_offset;
 142 };
 143
 144 struct ixgbe_queue_stats {
 145         u64 packets;
 146         u64 bytes;
 147 };
 148
 149 struct ixgbe_ring {
 150         void *desc;                     /* descriptor ring memory */
 151         union {
 152                 struct ixgbe_tx_buffer *tx_buffer_info;
 153                 struct ixgbe_rx_buffer *rx_buffer_info;
 154         };
 155         u8 atr_sample_rate;
 156         u8 atr_count;
 157         u16 count;                      /* amount of descriptors */
 158         u16 rx_buf_len;
 159         u16 next_to_use;
 160         u16 next_to_clean;
 161
 162         u8 queue_index; /* needed for multiqueue queue management */
 163
 164 #define IXGBE_RING_RX_PS_ENABLED                (u8)(1)
 165         u8 flags;                       /* per ring feature flags */
 166         u16 head;
 167         u16 tail;
 168
 169         unsigned int total_bytes;
 170         unsigned int total_packets;
 171
 172 #ifdef CONFIG_IXGBE_DCA
 173         /* cpu for tx queue */
 174         int cpu;
 175 #endif
 176
 177         u16 work_limit;                 /* max work per interrupt */
 178         u16 reg_idx;                    /* holds the special value that gets
 179                                          * the hardware register offset
 180                                          * associated with this ring, which is
 181                                          * different for DCB and RSS modes
 182                                          */
 183
 184         struct ixgbe_queue_stats stats;
 185         struct u64_stats_sync syncp;
 186         int numa_node;
 187         unsigned long reinit_state;
 188         u64 rsc_count;                  /* stat for coalesced packets */
 189         u64 rsc_flush;                  /* stats for flushed packets */
 190         u32 restart_queue;              /* track tx queue restarts */
 191         u32 non_eop_descs;              /* track hardware descriptor chaining */
 192
 193         unsigned int size;              /* length in bytes */
 194         dma_addr_t dma;                 /* phys. address of descriptor ring */
 195 } ____cacheline_internodealigned_in_smp;
 196
 197 enum ixgbe_ring_f_enum {
 198         RING_F_NONE = 0,
 199         RING_F_DCB,
 200         RING_F_VMDQ,  /* SR-IOV uses the same ring feature */
 201         RING_F_RSS,
 202         RING_F_FDIR,
 203 #ifdef IXGBE_FCOE
 204         RING_F_FCOE,
 205 #endif /* IXGBE_FCOE */
 206
 207         RING_F_ARRAY_SIZE      /* must be last in enum set */
 208 };
 209
 210 #define IXGBE_MAX_DCB_INDICES   8
 211 #define IXGBE_MAX_RSS_INDICES  16
 212 #define IXGBE_MAX_VMDQ_INDICES 64
 213 #define IXGBE_MAX_FDIR_INDICES 64
 214 #ifdef IXGBE_FCOE
 215 #define IXGBE_MAX_FCOE_INDICES  8
 216 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
 217 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
 218 #else
 219 #define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
 220 #define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
 221 #endif /* IXGBE_FCOE */
 222 struct ixgbe_ring_feature {
 223         int indices;
 224         int mask;
 225 } ____cacheline_internodealigned_in_smp;
 226
 227
 228 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
 229                               ? 8 : 1)
 230 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
 231
 232 /* MAX_MSIX_Q_VECTORS of these are allocated,
 233  * but we only use one per queue-specific vector.
 234  */
 235 struct ixgbe_q_vector {
 236         struct ixgbe_adapter *adapter;
 237         unsigned int v_idx; /* index of q_vector within array, also used for
 238                              * finding the bit in EICR and friends that
 239                              * represents the vector for this ring */
 240         struct napi_struct napi;
 241         DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
 242         DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
 243         u8 rxr_count;     /* Rx ring count assigned to this vector */
 244         u8 txr_count;     /* Tx ring count assigned to this vector */
 245         u8 tx_itr;
 246         u8 rx_itr;
 247         u32 eitr;
 248         cpumask_var_t affinity_mask;
 249 };
 250
 251 /* Helper macros to switch between ints/sec and what the register uses.
 252  * And yes, it's the same math going both ways.  The lowest value
 253  * supported by all of the ixgbe hardware is 8.
 254  */
 255 #define EITR_INTS_PER_SEC_TO_REG(_eitr) \
 256         ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
 257 #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
 258
 259 #define IXGBE_DESC_UNUSED(R) \
 260         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 261         (R)->next_to_clean - (R)->next_to_use - 1)
 262
 263 #define IXGBE_RX_DESC_ADV(R, i)     \
 264         (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
 265 #define IXGBE_TX_DESC_ADV(R, i)     \
 266         (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
 267 #define IXGBE_TX_CTXTDESC_ADV(R, i)         \
 268         (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
 269
 270 #define IXGBE_MAX_JUMBO_FRAME_SIZE        16128
 271 #ifdef IXGBE_FCOE
 272 /* Use 3K as the baby jumbo frame size for FCoE */
 273 #define IXGBE_FCOE_JUMBO_FRAME_SIZE       3072
 274 #endif /* IXGBE_FCOE */
 275
 276 #define OTHER_VECTOR 1
 277 #define NON_Q_VECTORS (OTHER_VECTOR)
 278
 279 #define MAX_MSIX_VECTORS_82599 64
 280 #define MAX_MSIX_Q_VECTORS_82599 64
 281 #define MAX_MSIX_VECTORS_82598 18
 282 #define MAX_MSIX_Q_VECTORS_82598 16
 283
 284 #define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
 285 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
 286
 287 #define MIN_MSIX_Q_VECTORS 2
 288 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
 289
 290 /* board specific private data structure */
 291 struct ixgbe_adapter {
 292         struct timer_list watchdog_timer;
 293         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 294         u16 bd_number;
 295         struct work_struct reset_task;
 296         struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
 297         char name[MAX_MSIX_COUNT][IFNAMSIZ + 9];
 298         struct ixgbe_dcb_config dcb_cfg;
 299         struct ixgbe_dcb_config temp_dcb_cfg;
 300         u8 dcb_set_bitmap;
 301         enum ixgbe_fc_mode last_lfc_mode;
 302
 303         /* Interrupt Throttle Rate */
 304         u32 rx_itr_setting;
 305         u32 tx_itr_setting;
 306         u16 eitr_low;
 307         u16 eitr_high;
 308
 309         /* TX */
 310         struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
 311         int num_tx_queues;
 312         u32 tx_timeout_count;
 313         bool detect_tx_hung;
 314
 315         u64 restart_queue;
 316         u64 lsc_int;
 317
 318         /* RX */
 319         struct ixgbe_ring *rx_ring[MAX_RX_QUEUES] ____cacheline_aligned_in_smp;
 320         int num_rx_queues;
 321         int num_rx_pools;               /* == num_rx_queues in 82598 */
 322         int num_rx_queues_per_pool;     /* 1 if 82598, can be many if 82599 */
 323         u64 hw_csum_rx_error;
 324         u64 hw_rx_no_dma_resources;
 325         u64 non_eop_descs;
 326         int num_msix_vectors;
 327         int max_msix_q_vectors;         /* true count of q_vectors for device */
 328         struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
 329         struct msix_entry *msix_entries;
 330
 331         u32 alloc_rx_page_failed;
 332         u32 alloc_rx_buff_failed;
 333
 334         /* Some features need tri-state capability,
 335          * thus the additional *_CAPABLE flags.
 336          */
 337         u32 flags;
 338 #define IXGBE_FLAG_RX_CSUM_ENABLED              (u32)(1)
 339 #define IXGBE_FLAG_MSI_CAPABLE                  (u32)(1 << 1)
 340 #define IXGBE_FLAG_MSI_ENABLED                  (u32)(1 << 2)
 341 #define IXGBE_FLAG_MSIX_CAPABLE                 (u32)(1 << 3)
 342 #define IXGBE_FLAG_MSIX_ENABLED                 (u32)(1 << 4)
 343 #define IXGBE_FLAG_RX_1BUF_CAPABLE              (u32)(1 << 6)
 344 #define IXGBE_FLAG_RX_PS_CAPABLE                (u32)(1 << 7)
 345 #define IXGBE_FLAG_RX_PS_ENABLED                (u32)(1 << 8)
 346 #define IXGBE_FLAG_IN_NETPOLL                   (u32)(1 << 9)
 347 #define IXGBE_FLAG_DCA_ENABLED                  (u32)(1 << 10)
 348 #define IXGBE_FLAG_DCA_CAPABLE                  (u32)(1 << 11)
 349 #define IXGBE_FLAG_IMIR_ENABLED                 (u32)(1 << 12)
 350 #define IXGBE_FLAG_MQ_CAPABLE                   (u32)(1 << 13)
 351 #define IXGBE_FLAG_DCB_ENABLED                  (u32)(1 << 14)
 352 #define IXGBE_FLAG_RSS_ENABLED                  (u32)(1 << 16)
 353 #define IXGBE_FLAG_RSS_CAPABLE                  (u32)(1 << 17)
 354 #define IXGBE_FLAG_VMDQ_CAPABLE                 (u32)(1 << 18)
 355 #define IXGBE_FLAG_VMDQ_ENABLED                 (u32)(1 << 19)
 356 #define IXGBE_FLAG_FAN_FAIL_CAPABLE             (u32)(1 << 20)
 357 #define IXGBE_FLAG_NEED_LINK_UPDATE             (u32)(1 << 22)
 358 #define IXGBE_FLAG_IN_SFP_LINK_TASK             (u32)(1 << 23)
 359 #define IXGBE_FLAG_IN_SFP_MOD_TASK              (u32)(1 << 24)
 360 #define IXGBE_FLAG_FDIR_HASH_CAPABLE            (u32)(1 << 25)
 361 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE         (u32)(1 << 26)
 362 #define IXGBE_FLAG_FCOE_CAPABLE                 (u32)(1 << 27)
 363 #define IXGBE_FLAG_FCOE_ENABLED                 (u32)(1 << 28)
 364 #define IXGBE_FLAG_SRIOV_CAPABLE                (u32)(1 << 29)
 365 #define IXGBE_FLAG_SRIOV_ENABLED                (u32)(1 << 30)
 366
 367         u32 flags2;
 368 #define IXGBE_FLAG2_RSC_CAPABLE                 (u32)(1)
 369 #define IXGBE_FLAG2_RSC_ENABLED                 (u32)(1 << 1)
 370 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE         (u32)(1 << 2)
 371 /* default to trying for four seconds */
 372 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
 373
 374         /* OS defined structs */
 375         struct net_device *netdev;
 376         struct pci_dev *pdev;
 377
 378         u32 test_icr;
 379         struct ixgbe_ring test_tx_ring;
 380         struct ixgbe_ring test_rx_ring;
 381
 382         /* structs defined in ixgbe_hw.h */
 383         struct ixgbe_hw hw;
 384         u16 msg_enable;
 385         struct ixgbe_hw_stats stats;
 386
 387         /* Interrupt Throttle Rate */
 388         u32 rx_eitr_param;
 389         u32 tx_eitr_param;
 390
 391         unsigned long state;
 392         u64 tx_busy;
 393         unsigned int tx_ring_count;
 394         unsigned int rx_ring_count;
 395
 396         u32 link_speed;
 397         bool link_up;
 398         unsigned long link_check_timeout;
 399
 400         struct work_struct watchdog_task;
 401         struct work_struct sfp_task;
 402         struct timer_list sfp_timer;
 403         struct work_struct multispeed_fiber_task;
 404         struct work_struct sfp_config_module_task;
 405         u32 fdir_pballoc;
 406         u32 atr_sample_rate;
 407         spinlock_t fdir_perfect_lock;
 408         struct work_struct fdir_reinit_task;
 409 #ifdef IXGBE_FCOE
 410         struct ixgbe_fcoe fcoe;
 411 #endif /* IXGBE_FCOE */
 412         u64 rsc_total_count;
 413         u64 rsc_total_flush;
 414         u32 wol;
 415         u16 eeprom_version;
 416
 417         int node;
 418         struct work_struct check_overtemp_task;
 419         u32 interrupt_event;
 420
 421         /* SR-IOV */
 422         DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
 423         unsigned int num_vfs;
 424         struct vf_data_storage *vfinfo;
 425 };
 426
 427 enum ixbge_state_t {
 428         __IXGBE_TESTING,
 429         __IXGBE_RESETTING,
 430         __IXGBE_DOWN,
 431         __IXGBE_FDIR_INIT_DONE,
 432         __IXGBE_SFP_MODULE_NOT_FOUND
 433 };
 434
 435 enum ixgbe_boards {
 436         board_82598,
 437         board_82599,
 438 };
 439
 440 extern struct ixgbe_info ixgbe_82598_info;
 441 extern struct ixgbe_info ixgbe_82599_info;
 442 #ifdef CONFIG_IXGBE_DCB
 443 extern const struct dcbnl_rtnl_ops dcbnl_ops;
 444 extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
 445                               struct ixgbe_dcb_config *dst_dcb_cfg,
 446                               int tc_max);
 447 #endif
 448
 449 extern char ixgbe_driver_name[];
 450 extern const char ixgbe_driver_version[];
 451
 452 extern int ixgbe_up(struct ixgbe_adapter *adapter);
 453 extern void ixgbe_down(struct ixgbe_adapter *adapter);
 454 extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
 455 extern void ixgbe_reset(struct ixgbe_adapter *adapter);
 456 extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
 457 extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
 458 extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
 459 extern void ixgbe_free_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
 460 extern void ixgbe_free_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
 461 extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
 462 extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
 463 extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
 464 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
 465 extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
 466 extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
 467                                          struct net_device *,
 468                                          struct ixgbe_adapter *,
 469                                          struct ixgbe_ring *);
 470 extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *,
 471                                              struct ixgbe_tx_buffer *);
 472 extern void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
 473                                    struct ixgbe_ring *rx_ring,
 474                                    int cleaned_count);
 475 extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
 476 extern int ethtool_ioctl(struct ifreq *ifr);
 477 extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
 478 extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc);
 479 extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc);
 480 extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
 481                                                  struct ixgbe_atr_input *input,
 482                                                  u8 queue);
 483 extern s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
 484                                       struct ixgbe_atr_input *input,
 485                                       struct ixgbe_atr_input_masks *input_masks,
 486                                       u16 soft_id, u8 queue);
 487 extern s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input,
 488                                        u16 vlan_id);
 489 extern s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input,
 490                                         u32 src_addr);
 491 extern s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input,
 492                                         u32 dst_addr);
 493 extern s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input,
 494                                         u16 src_port);
 495 extern s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input,
 496                                         u16 dst_port);
 497 extern s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input,
 498                                          u16 flex_byte);
 499 extern s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input,
 500                                       u8 l4type);
 501 extern void ixgbe_set_rx_mode(struct net_device *netdev);
 502 #ifdef IXGBE_FCOE
 503 extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
 504 extern int ixgbe_fso(struct ixgbe_adapter *adapter,
 505                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
 506                      u32 tx_flags, u8 *hdr_len);
 507 extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
 508 extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
 509                           union ixgbe_adv_rx_desc *rx_desc,
 510                           struct sk_buff *skb);
 511 extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
 512                               struct scatterlist *sgl, unsigned int sgc);
 513 extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
 514 extern int ixgbe_fcoe_enable(struct net_device *netdev);
 515 extern int ixgbe_fcoe_disable(struct net_device *netdev);
 516 #ifdef CONFIG_IXGBE_DCB
 517 extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
 518 extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
 519 #endif /* CONFIG_IXGBE_DCB */
 520 extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
 521 #endif /* IXGBE_FCOE */
 522
 523 #endif /* _IXGBE_H_ */