drivers/net/bnx2x/bnx2x_link.h

   1 /* Copyright 2008-2010 Broadcom Corporation
   2  *
   3  * Unless you and Broadcom execute a separate written software license
   4  * agreement governing use of this software, this software is licensed to you
   5  * under the terms of the GNU General Public License version 2, available
   6  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
   7  *
   8  * Notwithstanding the above, under no circumstances may you combine this
   9  * software in any way with any other Broadcom software provided under a
  10  * license other than the GPL, without Broadcom's express prior written
  11  * consent.
  12  *
  13  * Written by Yaniv Rosner
  14  *
  15  */
  16
  17 #ifndef BNX2X_LINK_H
  18 #define BNX2X_LINK_H
  19
  20
  21
  22 /***********************************************************/
  23 /*                         Defines                         */
  24 /***********************************************************/
  25 #define DEFAULT_PHY_DEV_ADDR    3
  26 #define E2_DEFAULT_PHY_DEV_ADDR 5
  27
  28
  29
  30 #define BNX2X_FLOW_CTRL_AUTO            PORT_FEATURE_FLOW_CONTROL_AUTO
  31 #define BNX2X_FLOW_CTRL_TX              PORT_FEATURE_FLOW_CONTROL_TX
  32 #define BNX2X_FLOW_CTRL_RX              PORT_FEATURE_FLOW_CONTROL_RX
  33 #define BNX2X_FLOW_CTRL_BOTH            PORT_FEATURE_FLOW_CONTROL_BOTH
  34 #define BNX2X_FLOW_CTRL_NONE            PORT_FEATURE_FLOW_CONTROL_NONE
  35
  36 #define SPEED_AUTO_NEG      0
  37 #define SPEED_12000             12000
  38 #define SPEED_12500             12500
  39 #define SPEED_13000             13000
  40 #define SPEED_15000             15000
  41 #define SPEED_16000             16000
  42
  43 #define SFP_EEPROM_VENDOR_NAME_ADDR             0x14
  44 #define SFP_EEPROM_VENDOR_NAME_SIZE             16
  45 #define SFP_EEPROM_VENDOR_OUI_ADDR              0x25
  46 #define SFP_EEPROM_VENDOR_OUI_SIZE              3
  47 #define SFP_EEPROM_PART_NO_ADDR                 0x28
  48 #define SFP_EEPROM_PART_NO_SIZE         16
  49 #define PWR_FLT_ERR_MSG_LEN                     250
  50
  51 #define XGXS_EXT_PHY_TYPE(ext_phy_config) \
  52                 ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
  53 #define XGXS_EXT_PHY_ADDR(ext_phy_config) \
  54                 (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
  55                  PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
  56 #define SERDES_EXT_PHY_TYPE(ext_phy_config) \
  57                 ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
  58
  59 /* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
  60 #define SINGLE_MEDIA_DIRECT(params)     (params->num_phys == 1)
  61 /* Single Media board contains single external phy */
  62 #define SINGLE_MEDIA(params)            (params->num_phys == 2)
  63 /* Dual Media board contains two external phy with different media */
  64 #define DUAL_MEDIA(params)              (params->num_phys == 3)
  65 #define FW_PARAM_MDIO_CTRL_OFFSET 16
  66 #define FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
  67         (phy_addr | phy_type | mdio_access << FW_PARAM_MDIO_CTRL_OFFSET)
  68 /***********************************************************/
  69 /*                         Structs                         */
  70 /***********************************************************/
  71 #define INT_PHY         0
  72 #define EXT_PHY1        1
  73 #define EXT_PHY2        2
  74 #define MAX_PHYS        3
  75
  76 /* Same configuration is shared between the XGXS and the first external phy */
  77 #define LINK_CONFIG_SIZE (MAX_PHYS - 1)
  78 #define LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == INT_PHY) ? \
  79                                          0 : (_phy_idx - 1))
  80 /***********************************************************/
  81 /*                      bnx2x_phy struct                     */
  82 /*  Defines the required arguments and function per phy    */
  83 /***********************************************************/
  84 struct link_vars;
  85 struct link_params;
  86 struct bnx2x_phy;
  87
  88 typedef u8 (*config_init_t)(struct bnx2x_phy *phy, struct link_params *params,
  89                             struct link_vars *vars);
  90 typedef u8 (*read_status_t)(struct bnx2x_phy *phy, struct link_params *params,
  91                             struct link_vars *vars);
  92 typedef void (*link_reset_t)(struct bnx2x_phy *phy,
  93                              struct link_params *params);
  94 typedef void (*config_loopback_t)(struct bnx2x_phy *phy,
  95                                   struct link_params *params);
  96 typedef u8 (*format_fw_ver_t)(u32 raw, u8 *str, u16 *len);
  97 typedef void (*hw_reset_t)(struct bnx2x_phy *phy, struct link_params *params);
  98 typedef void (*set_link_led_t)(struct bnx2x_phy *phy,
  99                                struct link_params *params, u8 mode);
 100 typedef void (*phy_specific_func_t)(struct bnx2x_phy *phy,
 101                                     struct link_params *params, u32 action);
 102
 103 struct bnx2x_phy {
 104         u32 type;
 105
 106         /* Loaded during init */
 107         u8 addr;
 108
 109         u8 flags;
 110         /* Require HW lock */
 111 #define FLAGS_HW_LOCK_REQUIRED          (1<<0)
 112         /* No Over-Current detection */
 113 #define FLAGS_NOC                       (1<<1)
 114         /* Fan failure detection required */
 115 #define FLAGS_FAN_FAILURE_DET_REQ       (1<<2)
 116         /* Initialize first the XGXS and only then the phy itself */
 117 #define FLAGS_INIT_XGXS_FIRST           (1<<3)
 118 #define FLAGS_REARM_LATCH_SIGNAL        (1<<6)
 119 #define FLAGS_SFP_NOT_APPROVED          (1<<7)
 120
 121         u8 def_md_devad;
 122         u8 reserved;
 123         /* preemphasis values for the rx side */
 124         u16 rx_preemphasis[4];
 125
 126         /* preemphasis values for the tx side */
 127         u16 tx_preemphasis[4];
 128
 129         /* EMAC address for access MDIO */
 130         u32 mdio_ctrl;
 131
 132         u32 supported;
 133
 134         u32 media_type;
 135 #define ETH_PHY_UNSPECIFIED 0x0
 136 #define ETH_PHY_SFP_FIBER   0x1
 137 #define ETH_PHY_XFP_FIBER   0x2
 138 #define ETH_PHY_DA_TWINAX   0x3
 139 #define ETH_PHY_BASE_T      0x4
 140 #define ETH_PHY_NOT_PRESENT 0xff
 141
 142         /* The address in which version is located*/
 143         u32 ver_addr;
 144
 145         u16 req_flow_ctrl;
 146
 147         u16 req_line_speed;
 148
 149         u32 speed_cap_mask;
 150
 151         u16 req_duplex;
 152         u16 rsrv;
 153         /* Called per phy/port init, and it configures LASI, speed, autoneg,
 154          duplex, flow control negotiation, etc. */
 155         config_init_t config_init;
 156
 157         /* Called due to interrupt. It determines the link, speed */
 158         read_status_t read_status;
 159
 160         /* Called when driver is unloading. Should reset the phy */
 161         link_reset_t link_reset;
 162
 163         /* Set the loopback configuration for the phy */
 164         config_loopback_t config_loopback;
 165
 166         /* Format the given raw number into str up to len */
 167         format_fw_ver_t format_fw_ver;
 168
 169         /* Reset the phy (both ports) */
 170         hw_reset_t hw_reset;
 171
 172         /* Set link led mode (on/off/oper)*/
 173         set_link_led_t set_link_led;
 174
 175         /* PHY Specific tasks */
 176         phy_specific_func_t phy_specific_func;
 177 #define DISABLE_TX      1
 178 #define ENABLE_TX       2
 179 };
 180
 181 /* Inputs parameters to the CLC */
 182 struct link_params {
 183
 184         u8 port;
 185
 186         /* Default / User Configuration */
 187         u8 loopback_mode;
 188 #define LOOPBACK_NONE   0
 189 #define LOOPBACK_EMAC   1
 190 #define LOOPBACK_BMAC   2
 191 #define LOOPBACK_XGXS           3
 192 #define LOOPBACK_EXT_PHY        4
 193 #define LOOPBACK_EXT    5
 194
 195         /* Device parameters */
 196         u8 mac_addr[6];
 197
 198         u16 req_duplex[LINK_CONFIG_SIZE];
 199         u16 req_flow_ctrl[LINK_CONFIG_SIZE];
 200
 201         u16 req_line_speed[LINK_CONFIG_SIZE]; /* Also determine AutoNeg */
 202
 203         /* shmem parameters */
 204         u32 shmem_base;
 205         u32 shmem2_base;
 206         u32 speed_cap_mask[LINK_CONFIG_SIZE];
 207         u32 switch_cfg;
 208 #define SWITCH_CFG_1G           PORT_FEATURE_CON_SWITCH_1G_SWITCH
 209 #define SWITCH_CFG_10G          PORT_FEATURE_CON_SWITCH_10G_SWITCH
 210 #define SWITCH_CFG_AUTO_DETECT  PORT_FEATURE_CON_SWITCH_AUTO_DETECT
 211
 212         u32 lane_config;
 213
 214         /* Phy register parameter */
 215         u32 chip_id;
 216
 217         u32 feature_config_flags;
 218 #define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
 219 #define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
 220 #define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY        (1<<3)
 221         /* Will be populated during common init */
 222         struct bnx2x_phy phy[MAX_PHYS];
 223
 224         /* Will be populated during common init */
 225         u8 num_phys;
 226
 227         u8 rsrv;
 228         u16 hw_led_mode; /* part of the hw_config read from the shmem */
 229         u32 multi_phy_config;
 230
 231         /* Device pointer passed to all callback functions */
 232         struct bnx2x *bp;
 233         u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
 234                                 req_flow_ctrl is set to AUTO */
 235 };
 236
 237 /* Output parameters */
 238 struct link_vars {
 239         u8 phy_flags;
 240
 241         u8 mac_type;
 242 #define MAC_TYPE_NONE           0
 243 #define MAC_TYPE_EMAC           1
 244 #define MAC_TYPE_BMAC           2
 245
 246         u8 phy_link_up; /* internal phy link indication */
 247         u8 link_up;
 248
 249         u16 line_speed;
 250         u16 duplex;
 251
 252         u16 flow_ctrl;
 253         u16 ieee_fc;
 254
 255         /* The same definitions as the shmem parameter */
 256         u32 link_status;
 257 };
 258
 259 /***********************************************************/
 260 /*                         Functions                       */
 261 /***********************************************************/
 262 u8 bnx2x_phy_init(struct link_params *input, struct link_vars *output);
 263
 264 /* Reset the link. Should be called when driver or interface goes down
 265    Before calling phy firmware upgrade, the reset_ext_phy should be set
 266    to 0 */
 267 u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
 268                   u8 reset_ext_phy);
 269
 270 /* bnx2x_link_update should be called upon link interrupt */
 271 u8 bnx2x_link_update(struct link_params *input, struct link_vars *output);
 272
 273 /* use the following phy functions to read/write from external_phy
 274   In order to use it to read/write internal phy registers, use
 275   DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
 276   the register */
 277 u8 bnx2x_phy_read(struct link_params *params, u8 phy_addr,
 278                   u8 devad, u16 reg, u16 *ret_val);
 279
 280 u8 bnx2x_phy_write(struct link_params *params, u8 phy_addr,
 281                    u8 devad, u16 reg, u16 val);
 282 /* Reads the link_status from the shmem,
 283    and update the link vars accordingly */
 284 void bnx2x_link_status_update(struct link_params *input,
 285                             struct link_vars *output);
 286 /* returns string representing the fw_version of the external phy */
 287 u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
 288                               u8 *version, u16 len);
 289
 290 /* Set/Unset the led
 291    Basically, the CLC takes care of the led for the link, but in case one needs
 292    to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to
 293    blink the led, and LED_MODE_OFF to set the led off.*/
 294 u8 bnx2x_set_led(struct link_params *params, struct link_vars *vars,
 295                  u8 mode, u32 speed);
 296 #define LED_MODE_OFF                    0
 297 #define LED_MODE_ON                     1
 298 #define LED_MODE_OPER                   2
 299 #define LED_MODE_FRONT_PANEL_OFF        3
 300
 301 /* bnx2x_handle_module_detect_int should be called upon module detection
 302    interrupt */
 303 void bnx2x_handle_module_detect_int(struct link_params *params);
 304
 305 /* Get the actual link status. In case it returns 0, link is up,
 306         otherwise link is down*/
 307 u8 bnx2x_test_link(struct link_params *input, struct link_vars *vars,
 308                    u8 is_serdes);
 309
 310 /* One-time initialization for external phy after power up */
 311 u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
 312                          u32 shmem2_base_path[], u32 chip_id);
 313
 314 /* Reset the external PHY using GPIO */
 315 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port);
 316
 317 /* Reset the external of SFX7101 */
 318 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy);
 319
 320 void bnx2x_hw_reset_phy(struct link_params *params);
 321
 322 /* Checks if HW lock is required for this phy/board type */
 323 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base,
 324                           u32 shmem2_base);
 325
 326 /* Check swap bit and adjust PHY order */
 327 u32 bnx2x_phy_selection(struct link_params *params);
 328
 329 /* Probe the phys on board, and populate them in "params" */
 330 u8 bnx2x_phy_probe(struct link_params *params);
 331 /* Checks if fan failure detection is required on one of the phys on board */
 332 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base,
 333                              u32 shmem2_base, u8 port);
 334
 335 #endif /* BNX2X_LINK_H */