2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
18 #include <linux/types.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/acpi.h>
24 #include <linux/kallsyms.h>
25 #include <linux/dmi.h>
28 int isa_dma_bridge_buggy
;
29 EXPORT_SYMBOL(isa_dma_bridge_buggy
);
31 EXPORT_SYMBOL(pci_pci_problems
);
33 EXPORT_SYMBOL(pcie_mch_quirk
);
35 #ifdef CONFIG_PCI_QUIRKS
36 /* The Mellanox Tavor device gives false positive parity errors
37 * Mark this device with a broken_parity_status, to allow
38 * PCI scanning code to "skip" this now blacklisted device.
40 static void __devinit
quirk_mellanox_tavor(struct pci_dev
*dev
)
42 dev
->broken_parity_status
= 1; /* This device gives false positives */
44 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX
,PCI_DEVICE_ID_MELLANOX_TAVOR
,quirk_mellanox_tavor
);
45 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX
,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE
,quirk_mellanox_tavor
);
47 /* Deal with broken BIOS'es that neglect to enable passive release,
48 which can cause problems in combination with the 82441FX/PPro MTRRs */
49 static void quirk_passive_release(struct pci_dev
*dev
)
51 struct pci_dev
*d
= NULL
;
54 /* We have to make sure a particular bit is set in the PIIX3
55 ISA bridge, so we have to go out and find it. */
56 while ((d
= pci_get_device(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_0
, d
))) {
57 pci_read_config_byte(d
, 0x82, &dlc
);
59 dev_err(&d
->dev
, "PIIX3: Enabling Passive Release\n");
61 pci_write_config_byte(d
, 0x82, dlc
);
65 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_passive_release
);
66 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_passive_release
);
68 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
69 but VIA don't answer queries. If you happen to have good contacts at VIA
70 ask them for me please -- Alan
72 This appears to be BIOS not version dependent. So presumably there is a
75 static void __devinit
quirk_isa_dma_hangs(struct pci_dev
*dev
)
77 if (!isa_dma_bridge_buggy
) {
78 isa_dma_bridge_buggy
=1;
79 dev_info(&dev
->dev
, "Activating ISA DMA hang workarounds\n");
83 * Its not totally clear which chipsets are the problematic ones
84 * We know 82C586 and 82C596 variants are affected.
86 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_0
, quirk_isa_dma_hangs
);
87 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C596
, quirk_isa_dma_hangs
);
88 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_0
, quirk_isa_dma_hangs
);
89 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1533
, quirk_isa_dma_hangs
);
90 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_1
, quirk_isa_dma_hangs
);
91 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_2
, quirk_isa_dma_hangs
);
92 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_3
, quirk_isa_dma_hangs
);
95 * Chipsets where PCI->PCI transfers vanish or hang
97 static void __devinit
quirk_nopcipci(struct pci_dev
*dev
)
99 if ((pci_pci_problems
& PCIPCI_FAIL
)==0) {
100 dev_info(&dev
->dev
, "Disabling direct PCI/PCI transfers\n");
101 pci_pci_problems
|= PCIPCI_FAIL
;
104 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_5597
, quirk_nopcipci
);
105 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_496
, quirk_nopcipci
);
107 static void __devinit
quirk_nopciamd(struct pci_dev
*dev
)
110 pci_read_config_byte(dev
, 0x08, &rev
);
113 dev_info(&dev
->dev
, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
114 pci_pci_problems
|= PCIAGP_FAIL
;
117 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8151_0
, quirk_nopciamd
);
120 * Triton requires workarounds to be used by the drivers
122 static void __devinit
quirk_triton(struct pci_dev
*dev
)
124 if ((pci_pci_problems
&PCIPCI_TRITON
)==0) {
125 dev_info(&dev
->dev
, "Limiting direct PCI/PCI transfers\n");
126 pci_pci_problems
|= PCIPCI_TRITON
;
129 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437
, quirk_triton
);
130 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437VX
, quirk_triton
);
131 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82439
, quirk_triton
);
132 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82439TX
, quirk_triton
);
135 * VIA Apollo KT133 needs PCI latency patch
136 * Made according to a windows driver based patch by George E. Breese
137 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
138 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
139 * the info on which Mr Breese based his work.
141 * Updated based on further information from the site and also on
142 * information provided by VIA
144 static void quirk_vialatency(struct pci_dev
*dev
)
148 /* Ok we have a potential problem chipset here. Now see if we have
149 a buggy southbridge */
151 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, NULL
);
153 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
154 /* Check for buggy part revisions */
155 if (p
->revision
< 0x40 || p
->revision
> 0x42)
158 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8231
, NULL
);
159 if (p
==NULL
) /* No problem parts */
161 /* Check for buggy part revisions */
162 if (p
->revision
< 0x10 || p
->revision
> 0x12)
167 * Ok we have the problem. Now set the PCI master grant to
168 * occur every master grant. The apparent bug is that under high
169 * PCI load (quite common in Linux of course) you can get data
170 * loss when the CPU is held off the bus for 3 bus master requests
171 * This happens to include the IDE controllers....
173 * VIA only apply this fix when an SB Live! is present but under
174 * both Linux and Windows this isnt enough, and we have seen
175 * corruption without SB Live! but with things like 3 UDMA IDE
176 * controllers. So we ignore that bit of the VIA recommendation..
179 pci_read_config_byte(dev
, 0x76, &busarb
);
180 /* Set bit 4 and bi 5 of byte 76 to 0x01
181 "Master priority rotation on every PCI master grant */
184 pci_write_config_byte(dev
, 0x76, busarb
);
185 dev_info(&dev
->dev
, "Applying VIA southbridge workaround\n");
189 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8363_0
, quirk_vialatency
);
190 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8371_1
, quirk_vialatency
);
191 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8361
, quirk_vialatency
);
192 /* Must restore this on a resume from RAM */
193 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8363_0
, quirk_vialatency
);
194 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8371_1
, quirk_vialatency
);
195 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8361
, quirk_vialatency
);
198 * VIA Apollo VP3 needs ETBF on BT848/878
200 static void __devinit
quirk_viaetbf(struct pci_dev
*dev
)
202 if ((pci_pci_problems
&PCIPCI_VIAETBF
)==0) {
203 dev_info(&dev
->dev
, "Limiting direct PCI/PCI transfers\n");
204 pci_pci_problems
|= PCIPCI_VIAETBF
;
207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C597_0
, quirk_viaetbf
);
209 static void __devinit
quirk_vsfx(struct pci_dev
*dev
)
211 if ((pci_pci_problems
&PCIPCI_VSFX
)==0) {
212 dev_info(&dev
->dev
, "Limiting direct PCI/PCI transfers\n");
213 pci_pci_problems
|= PCIPCI_VSFX
;
216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C576
, quirk_vsfx
);
219 * Ali Magik requires workarounds to be used by the drivers
220 * that DMA to AGP space. Latency must be set to 0xA and triton
221 * workaround applied too
222 * [Info kindly provided by ALi]
224 static void __init
quirk_alimagik(struct pci_dev
*dev
)
226 if ((pci_pci_problems
&PCIPCI_ALIMAGIK
)==0) {
227 dev_info(&dev
->dev
, "Limiting direct PCI/PCI transfers\n");
228 pci_pci_problems
|= PCIPCI_ALIMAGIK
|PCIPCI_TRITON
;
231 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1647
, quirk_alimagik
);
232 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1651
, quirk_alimagik
);
235 * Natoma has some interesting boundary conditions with Zoran stuff
238 static void __devinit
quirk_natoma(struct pci_dev
*dev
)
240 if ((pci_pci_problems
&PCIPCI_NATOMA
)==0) {
241 dev_info(&dev
->dev
, "Limiting direct PCI/PCI transfers\n");
242 pci_pci_problems
|= PCIPCI_NATOMA
;
245 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_natoma
);
246 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443LX_0
, quirk_natoma
);
247 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443LX_1
, quirk_natoma
);
248 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_0
, quirk_natoma
);
249 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_1
, quirk_natoma
);
250 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_2
, quirk_natoma
);
253 * This chip can cause PCI parity errors if config register 0xA0 is read
254 * while DMAs are occurring.
256 static void __devinit
quirk_citrine(struct pci_dev
*dev
)
258 dev
->cfg_size
= 0xA0;
260 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM
, PCI_DEVICE_ID_IBM_CITRINE
, quirk_citrine
);
263 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
264 * If it's needed, re-allocate the region.
266 static void __devinit
quirk_s3_64M(struct pci_dev
*dev
)
268 struct resource
*r
= &dev
->resource
[0];
270 if ((r
->start
& 0x3ffffff) || r
->end
!= r
->start
+ 0x3ffffff) {
275 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3
, PCI_DEVICE_ID_S3_868
, quirk_s3_64M
);
276 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3
, PCI_DEVICE_ID_S3_968
, quirk_s3_64M
);
278 static void __devinit
quirk_io_region(struct pci_dev
*dev
, unsigned region
,
279 unsigned size
, int nr
, const char *name
)
283 struct pci_bus_region bus_region
;
284 struct resource
*res
= dev
->resource
+ nr
;
286 res
->name
= pci_name(dev
);
288 res
->end
= region
+ size
- 1;
289 res
->flags
= IORESOURCE_IO
;
291 /* Convert from PCI bus to resource space. */
292 bus_region
.start
= res
->start
;
293 bus_region
.end
= res
->end
;
294 pcibios_bus_to_resource(dev
, res
, &bus_region
);
296 pci_claim_resource(dev
, nr
);
297 dev_info(&dev
->dev
, "quirk: region %04x-%04x claimed by %s\n", region
, region
+ size
- 1, name
);
302 * ATI Northbridge setups MCE the processor if you even
303 * read somewhere between 0x3b0->0x3bb or read 0x3d3
305 static void __devinit
quirk_ati_exploding_mce(struct pci_dev
*dev
)
307 dev_info(&dev
->dev
, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
308 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
309 request_region(0x3b0, 0x0C, "RadeonIGP");
310 request_region(0x3d3, 0x01, "RadeonIGP");
312 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS100
, quirk_ati_exploding_mce
);
315 * Let's make the southbridge information explicit instead
316 * of having to worry about people probing the ACPI areas,
317 * for example.. (Yes, it happens, and if you read the wrong
318 * ACPI register it will put the machine to sleep with no
319 * way of waking it up again. Bummer).
321 * ALI M7101: Two IO regions pointed to by words at
322 * 0xE0 (64 bytes of ACPI registers)
323 * 0xE2 (32 bytes of SMB registers)
325 static void __devinit
quirk_ali7101_acpi(struct pci_dev
*dev
)
329 pci_read_config_word(dev
, 0xE0, ®ion
);
330 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
, "ali7101 ACPI");
331 pci_read_config_word(dev
, 0xE2, ®ion
);
332 quirk_io_region(dev
, region
, 32, PCI_BRIDGE_RESOURCES
+1, "ali7101 SMB");
334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M7101
, quirk_ali7101_acpi
);
336 static void piix4_io_quirk(struct pci_dev
*dev
, const char *name
, unsigned int port
, unsigned int enable
)
339 u32 mask
, size
, base
;
341 pci_read_config_dword(dev
, port
, &devres
);
342 if ((devres
& enable
) != enable
)
344 mask
= (devres
>> 16) & 15;
345 base
= devres
& 0xffff;
348 unsigned bit
= size
>> 1;
349 if ((bit
& mask
) == bit
)
354 * For now we only print it out. Eventually we'll want to
355 * reserve it (at least if it's in the 0x1000+ range), but
356 * let's get enough confirmation reports first.
359 dev_info(&dev
->dev
, "%s PIO at %04x-%04x\n", name
, base
, base
+ size
- 1);
362 static void piix4_mem_quirk(struct pci_dev
*dev
, const char *name
, unsigned int port
, unsigned int enable
)
365 u32 mask
, size
, base
;
367 pci_read_config_dword(dev
, port
, &devres
);
368 if ((devres
& enable
) != enable
)
370 base
= devres
& 0xffff0000;
371 mask
= (devres
& 0x3f) << 16;
374 unsigned bit
= size
>> 1;
375 if ((bit
& mask
) == bit
)
380 * For now we only print it out. Eventually we'll want to
381 * reserve it, but let's get enough confirmation reports first.
384 dev_info(&dev
->dev
, "%s MMIO at %04x-%04x\n", name
, base
, base
+ size
- 1);
388 * PIIX4 ACPI: Two IO regions pointed to by longwords at
389 * 0x40 (64 bytes of ACPI registers)
390 * 0x90 (16 bytes of SMB registers)
391 * and a few strange programmable PIIX4 device resources.
393 static void __devinit
quirk_piix4_acpi(struct pci_dev
*dev
)
397 pci_read_config_dword(dev
, 0x40, ®ion
);
398 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
, "PIIX4 ACPI");
399 pci_read_config_dword(dev
, 0x90, ®ion
);
400 quirk_io_region(dev
, region
, 16, PCI_BRIDGE_RESOURCES
+1, "PIIX4 SMB");
402 /* Device resource A has enables for some of the other ones */
403 pci_read_config_dword(dev
, 0x5c, &res_a
);
405 piix4_io_quirk(dev
, "PIIX4 devres B", 0x60, 3 << 21);
406 piix4_io_quirk(dev
, "PIIX4 devres C", 0x64, 3 << 21);
408 /* Device resource D is just bitfields for static resources */
410 /* Device 12 enabled? */
411 if (res_a
& (1 << 29)) {
412 piix4_io_quirk(dev
, "PIIX4 devres E", 0x68, 1 << 20);
413 piix4_mem_quirk(dev
, "PIIX4 devres F", 0x6c, 1 << 7);
415 /* Device 13 enabled? */
416 if (res_a
& (1 << 30)) {
417 piix4_io_quirk(dev
, "PIIX4 devres G", 0x70, 1 << 20);
418 piix4_mem_quirk(dev
, "PIIX4 devres H", 0x74, 1 << 7);
420 piix4_io_quirk(dev
, "PIIX4 devres I", 0x78, 1 << 20);
421 piix4_io_quirk(dev
, "PIIX4 devres J", 0x7c, 1 << 20);
423 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371AB_3
, quirk_piix4_acpi
);
424 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443MX_3
, quirk_piix4_acpi
);
427 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
428 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
429 * 0x58 (64 bytes of GPIO I/O space)
431 static void __devinit
quirk_ich4_lpc_acpi(struct pci_dev
*dev
)
435 pci_read_config_dword(dev
, 0x40, ®ion
);
436 quirk_io_region(dev
, region
, 128, PCI_BRIDGE_RESOURCES
, "ICH4 ACPI/GPIO/TCO");
438 pci_read_config_dword(dev
, 0x58, ®ion
);
439 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
+1, "ICH4 GPIO");
441 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, quirk_ich4_lpc_acpi
);
442 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_0
, quirk_ich4_lpc_acpi
);
443 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, quirk_ich4_lpc_acpi
);
444 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_10
, quirk_ich4_lpc_acpi
);
445 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, quirk_ich4_lpc_acpi
);
446 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, quirk_ich4_lpc_acpi
);
447 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, quirk_ich4_lpc_acpi
);
448 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, quirk_ich4_lpc_acpi
);
449 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, quirk_ich4_lpc_acpi
);
450 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_1
, quirk_ich4_lpc_acpi
);
452 static void __devinit
quirk_ich6_lpc_acpi(struct pci_dev
*dev
)
456 pci_read_config_dword(dev
, 0x40, ®ion
);
457 quirk_io_region(dev
, region
, 128, PCI_BRIDGE_RESOURCES
, "ICH6 ACPI/GPIO/TCO");
459 pci_read_config_dword(dev
, 0x48, ®ion
);
460 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
+1, "ICH6 GPIO");
462 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_0
, quirk_ich6_lpc_acpi
);
463 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, quirk_ich6_lpc_acpi
);
464 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_0
, quirk_ich6_lpc_acpi
);
465 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_1
, quirk_ich6_lpc_acpi
);
466 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_31
, quirk_ich6_lpc_acpi
);
467 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_0
, quirk_ich6_lpc_acpi
);
468 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_2
, quirk_ich6_lpc_acpi
);
469 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_3
, quirk_ich6_lpc_acpi
);
470 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_1
, quirk_ich6_lpc_acpi
);
471 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_4
, quirk_ich6_lpc_acpi
);
472 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_2
, quirk_ich6_lpc_acpi
);
473 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_4
, quirk_ich6_lpc_acpi
);
474 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_7
, quirk_ich6_lpc_acpi
);
475 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_8
, quirk_ich6_lpc_acpi
);
478 * VIA ACPI: One IO region pointed to by longword at
479 * 0x48 or 0x20 (256 bytes of ACPI registers)
481 static void __devinit
quirk_vt82c586_acpi(struct pci_dev
*dev
)
485 if (dev
->revision
& 0x10) {
486 pci_read_config_dword(dev
, 0x48, ®ion
);
487 region
&= PCI_BASE_ADDRESS_IO_MASK
;
488 quirk_io_region(dev
, region
, 256, PCI_BRIDGE_RESOURCES
, "vt82c586 ACPI");
491 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_3
, quirk_vt82c586_acpi
);
494 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
495 * 0x48 (256 bytes of ACPI registers)
496 * 0x70 (128 bytes of hardware monitoring register)
497 * 0x90 (16 bytes of SMB registers)
499 static void __devinit
quirk_vt82c686_acpi(struct pci_dev
*dev
)
504 quirk_vt82c586_acpi(dev
);
506 pci_read_config_word(dev
, 0x70, &hm
);
507 hm
&= PCI_BASE_ADDRESS_IO_MASK
;
508 quirk_io_region(dev
, hm
, 128, PCI_BRIDGE_RESOURCES
+ 1, "vt82c686 HW-mon");
510 pci_read_config_dword(dev
, 0x90, &smb
);
511 smb
&= PCI_BASE_ADDRESS_IO_MASK
;
512 quirk_io_region(dev
, smb
, 16, PCI_BRIDGE_RESOURCES
+ 2, "vt82c686 SMB");
514 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_4
, quirk_vt82c686_acpi
);
517 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
518 * 0x88 (128 bytes of power management registers)
519 * 0xd0 (16 bytes of SMB registers)
521 static void __devinit
quirk_vt8235_acpi(struct pci_dev
*dev
)
525 pci_read_config_word(dev
, 0x88, &pm
);
526 pm
&= PCI_BASE_ADDRESS_IO_MASK
;
527 quirk_io_region(dev
, pm
, 128, PCI_BRIDGE_RESOURCES
, "vt8235 PM");
529 pci_read_config_word(dev
, 0xd0, &smb
);
530 smb
&= PCI_BASE_ADDRESS_IO_MASK
;
531 quirk_io_region(dev
, smb
, 16, PCI_BRIDGE_RESOURCES
+ 1, "vt8235 SMB");
533 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235
, quirk_vt8235_acpi
);
536 #ifdef CONFIG_X86_IO_APIC
538 #include <asm/io_apic.h>
541 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
542 * devices to the external APIC.
544 * TODO: When we have device-specific interrupt routers,
545 * this code will go away from quirks.
547 static void quirk_via_ioapic(struct pci_dev
*dev
)
552 tmp
= 0; /* nothing routed to external APIC */
554 tmp
= 0x1f; /* all known bits (4-0) routed to external APIC */
556 dev_info(&dev
->dev
, "%sbling VIA external APIC routing\n",
557 tmp
== 0 ? "Disa" : "Ena");
559 /* Offset 0x58: External APIC IRQ output control */
560 pci_write_config_byte (dev
, 0x58, tmp
);
562 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_ioapic
);
563 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_ioapic
);
566 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
567 * This leads to doubled level interrupt rates.
568 * Set this bit to get rid of cycle wastage.
569 * Otherwise uncritical.
571 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev
*dev
)
574 #define BYPASS_APIC_DEASSERT 8
576 pci_read_config_byte(dev
, 0x5B, &misc_control2
);
577 if (!(misc_control2
& BYPASS_APIC_DEASSERT
)) {
578 dev_info(&dev
->dev
, "Bypassing VIA 8237 APIC De-Assert Message\n");
579 pci_write_config_byte(dev
, 0x5B, misc_control2
|BYPASS_APIC_DEASSERT
);
582 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_vt8237_bypass_apic_deassert
);
583 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_vt8237_bypass_apic_deassert
);
586 * The AMD io apic can hang the box when an apic irq is masked.
587 * We check all revs >= B0 (yet not in the pre production!) as the bug
588 * is currently marked NoFix
590 * We have multiple reports of hangs with this chipset that went away with
591 * noapic specified. For the moment we assume it's the erratum. We may be wrong
592 * of course. However the advice is demonstrably good even if so..
594 static void __devinit
quirk_amd_ioapic(struct pci_dev
*dev
)
596 if (dev
->revision
>= 0x02) {
597 dev_warn(&dev
->dev
, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
598 dev_warn(&dev
->dev
, " : booting with the \"noapic\" option\n");
601 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_VIPER_7410
, quirk_amd_ioapic
);
603 static void __init
quirk_ioapic_rmw(struct pci_dev
*dev
)
605 if (dev
->devfn
== 0 && dev
->bus
->number
== 0)
608 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_ANY_ID
, quirk_ioapic_rmw
);
610 #define AMD8131_revA0 0x01
611 #define AMD8131_revB0 0x11
612 #define AMD8131_MISC 0x40
613 #define AMD8131_NIOAMODE_BIT 0
614 static void quirk_amd_8131_ioapic(struct pci_dev
*dev
)
621 if (dev
->revision
== AMD8131_revA0
|| dev
->revision
== AMD8131_revB0
) {
622 dev_info(&dev
->dev
, "Fixing up AMD8131 IOAPIC mode\n");
623 pci_read_config_byte( dev
, AMD8131_MISC
, &tmp
);
624 tmp
&= ~(1 << AMD8131_NIOAMODE_BIT
);
625 pci_write_config_byte( dev
, AMD8131_MISC
, tmp
);
628 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_amd_8131_ioapic
);
629 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_amd_8131_ioapic
);
630 #endif /* CONFIG_X86_IO_APIC */
633 * Some settings of MMRBC can lead to data corruption so block changes.
634 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
636 static void __init
quirk_amd_8131_mmrbc(struct pci_dev
*dev
)
638 if (dev
->subordinate
&& dev
->revision
<= 0x12) {
639 dev_info(&dev
->dev
, "AMD8131 rev %x detected; "
640 "disabling PCI-X MMRBC\n", dev
->revision
);
641 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MMRBC
;
644 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_amd_8131_mmrbc
);
647 * FIXME: it is questionable that quirk_via_acpi
648 * is needed. It shows up as an ISA bridge, and does not
649 * support the PCI_INTERRUPT_LINE register at all. Therefore
650 * it seems like setting the pci_dev's 'irq' to the
651 * value of the ACPI SCI interrupt is only done for convenience.
654 static void __devinit
quirk_via_acpi(struct pci_dev
*d
)
657 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
660 pci_read_config_byte(d
, 0x42, &irq
);
662 if (irq
&& (irq
!= 2))
665 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_3
, quirk_via_acpi
);
666 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_4
, quirk_via_acpi
);
670 * VIA bridges which have VLink
673 static int via_vlink_dev_lo
= -1, via_vlink_dev_hi
= 18;
675 static void quirk_via_bridge(struct pci_dev
*dev
)
677 /* See what bridge we have and find the device ranges */
678 switch (dev
->device
) {
679 case PCI_DEVICE_ID_VIA_82C686
:
680 /* The VT82C686 is special, it attaches to PCI and can have
681 any device number. All its subdevices are functions of
682 that single device. */
683 via_vlink_dev_lo
= PCI_SLOT(dev
->devfn
);
684 via_vlink_dev_hi
= PCI_SLOT(dev
->devfn
);
686 case PCI_DEVICE_ID_VIA_8237
:
687 case PCI_DEVICE_ID_VIA_8237A
:
688 via_vlink_dev_lo
= 15;
690 case PCI_DEVICE_ID_VIA_8235
:
691 via_vlink_dev_lo
= 16;
693 case PCI_DEVICE_ID_VIA_8231
:
694 case PCI_DEVICE_ID_VIA_8233_0
:
695 case PCI_DEVICE_ID_VIA_8233A
:
696 case PCI_DEVICE_ID_VIA_8233C_0
:
697 via_vlink_dev_lo
= 17;
701 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_bridge
);
702 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8231
, quirk_via_bridge
);
703 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8233_0
, quirk_via_bridge
);
704 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8233A
, quirk_via_bridge
);
705 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8233C_0
, quirk_via_bridge
);
706 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235
, quirk_via_bridge
);
707 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_bridge
);
708 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237A
, quirk_via_bridge
);
711 * quirk_via_vlink - VIA VLink IRQ number update
714 * If the device we are dealing with is on a PIC IRQ we need to
715 * ensure that the IRQ line register which usually is not relevant
716 * for PCI cards, is actually written so that interrupts get sent
717 * to the right place.
718 * We only do this on systems where a VIA south bridge was detected,
719 * and only for VIA devices on the motherboard (see quirk_via_bridge
723 static void quirk_via_vlink(struct pci_dev
*dev
)
727 /* Check if we have VLink at all */
728 if (via_vlink_dev_lo
== -1)
733 /* Don't quirk interrupts outside the legacy IRQ range */
734 if (!new_irq
|| new_irq
> 15)
737 /* Internal device ? */
738 if (dev
->bus
->number
!= 0 || PCI_SLOT(dev
->devfn
) > via_vlink_dev_hi
||
739 PCI_SLOT(dev
->devfn
) < via_vlink_dev_lo
)
742 /* This is an internal VLink device on a PIC interrupt. The BIOS
743 ought to have set this but may not have, so we redo it */
745 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
746 if (new_irq
!= irq
) {
747 dev_info(&dev
->dev
, "VIA VLink IRQ fixup, from %d to %d\n",
749 udelay(15); /* unknown if delay really needed */
750 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, new_irq
);
753 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA
, PCI_ANY_ID
, quirk_via_vlink
);
756 * VIA VT82C598 has its device ID settable and many BIOSes
757 * set it to the ID of VT82C597 for backward compatibility.
758 * We need to switch it off to be able to recognize the real
761 static void __devinit
quirk_vt82c598_id(struct pci_dev
*dev
)
763 pci_write_config_byte(dev
, 0xfc, 0);
764 pci_read_config_word(dev
, PCI_DEVICE_ID
, &dev
->device
);
766 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C597_0
, quirk_vt82c598_id
);
769 * CardBus controllers have a legacy base address that enables them
770 * to respond as i82365 pcmcia controllers. We don't want them to
771 * do this even if the Linux CardBus driver is not loaded, because
772 * the Linux i82365 driver does not (and should not) handle CardBus.
774 static void quirk_cardbus_legacy(struct pci_dev
*dev
)
776 if ((PCI_CLASS_BRIDGE_CARDBUS
<< 8) ^ dev
->class)
778 pci_write_config_dword(dev
, PCI_CB_LEGACY_MODE_BASE
, 0);
780 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID
, PCI_ANY_ID
, quirk_cardbus_legacy
);
781 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID
, PCI_ANY_ID
, quirk_cardbus_legacy
);
784 * Following the PCI ordering rules is optional on the AMD762. I'm not
785 * sure what the designers were smoking but let's not inhale...
787 * To be fair to AMD, it follows the spec by default, its BIOS people
790 static void quirk_amd_ordering(struct pci_dev
*dev
)
793 pci_read_config_dword(dev
, 0x4C, &pcic
);
796 dev_warn(&dev
->dev
, "BIOS failed to enable PCI standards compliance; fixing this error\n");
797 pci_write_config_dword(dev
, 0x4C, pcic
);
798 pci_read_config_dword(dev
, 0x84, &pcic
);
799 pcic
|= (1<<23); /* Required in this mode */
800 pci_write_config_dword(dev
, 0x84, pcic
);
803 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_FE_GATE_700C
, quirk_amd_ordering
);
804 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_FE_GATE_700C
, quirk_amd_ordering
);
807 * DreamWorks provided workaround for Dunord I-3000 problem
809 * This card decodes and responds to addresses not apparently
810 * assigned to it. We force a larger allocation to ensure that
811 * nothing gets put too close to it.
813 static void __devinit
quirk_dunord ( struct pci_dev
* dev
)
815 struct resource
*r
= &dev
->resource
[1];
819 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD
, PCI_DEVICE_ID_DUNORD_I3000
, quirk_dunord
);
822 * i82380FB mobile docking controller: its PCI-to-PCI bridge
823 * is subtractive decoding (transparent), and does indicate this
824 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
827 static void __devinit
quirk_transparent_bridge(struct pci_dev
*dev
)
829 dev
->transparent
= 1;
831 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82380FB
, quirk_transparent_bridge
);
832 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA
, 0x605, quirk_transparent_bridge
);
835 * Common misconfiguration of the MediaGX/Geode PCI master that will
836 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
837 * datasheets found at http://www.national.com/ds/GX for info on what
838 * these bits do. <christer@weinigel.se>
840 static void quirk_mediagx_master(struct pci_dev
*dev
)
843 pci_read_config_byte(dev
, 0x41, ®
);
846 dev_info(&dev
->dev
, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg
);
847 pci_write_config_byte(dev
, 0x41, reg
);
850 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX
, PCI_DEVICE_ID_CYRIX_PCI_MASTER
, quirk_mediagx_master
);
851 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX
, PCI_DEVICE_ID_CYRIX_PCI_MASTER
, quirk_mediagx_master
);
854 * Ensure C0 rev restreaming is off. This is normally done by
855 * the BIOS but in the odd case it is not the results are corruption
856 * hence the presence of a Linux check
858 static void quirk_disable_pxb(struct pci_dev
*pdev
)
862 if (pdev
->revision
!= 0x04) /* Only C0 requires this */
864 pci_read_config_word(pdev
, 0x40, &config
);
865 if (config
& (1<<6)) {
867 pci_write_config_word(pdev
, 0x40, config
);
868 dev_info(&pdev
->dev
, "C0 revision 450NX. Disabling PCI restreaming\n");
871 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, quirk_disable_pxb
);
872 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, quirk_disable_pxb
);
874 static void __devinit
quirk_amd_ide_mode(struct pci_dev
*pdev
)
876 /* set sb600/sb700/sb800 sata to ahci mode */
879 pci_read_config_byte(pdev
, PCI_CLASS_DEVICE
, &tmp
);
881 pci_read_config_byte(pdev
, 0x40, &tmp
);
882 pci_write_config_byte(pdev
, 0x40, tmp
|1);
883 pci_write_config_byte(pdev
, 0x9, 1);
884 pci_write_config_byte(pdev
, 0xa, 6);
885 pci_write_config_byte(pdev
, 0x40, tmp
);
887 pdev
->class = PCI_CLASS_STORAGE_SATA_AHCI
;
888 dev_info(&pdev
->dev
, "set SATA to AHCI mode\n");
891 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP600_SATA
, quirk_amd_ide_mode
);
892 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP600_SATA
, quirk_amd_ide_mode
);
893 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP700_SATA
, quirk_amd_ide_mode
);
894 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP700_SATA
, quirk_amd_ide_mode
);
897 * Serverworks CSB5 IDE does not fully support native mode
899 static void __devinit
quirk_svwks_csb5ide(struct pci_dev
*pdev
)
902 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
906 pci_write_config_byte(pdev
, PCI_CLASS_PROG
, prog
);
907 /* PCI layer will sort out resources */
910 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
, quirk_svwks_csb5ide
);
913 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
915 static void __init
quirk_ide_samemode(struct pci_dev
*pdev
)
919 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
921 if (((prog
& 1) && !(prog
& 4)) || ((prog
& 4) && !(prog
& 1))) {
922 dev_info(&pdev
->dev
, "IDE mode mismatch; forcing legacy mode\n");
925 pci_write_config_byte(pdev
, PCI_CLASS_PROG
, prog
);
928 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_10
, quirk_ide_samemode
);
931 * Some ATA devices break if put into D3
934 static void __devinit
quirk_no_ata_d3(struct pci_dev
*pdev
)
936 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
937 if ((pdev
->class >> 8) == PCI_CLASS_STORAGE_IDE
)
938 pdev
->dev_flags
|= PCI_DEV_FLAGS_NO_D3
;
940 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, PCI_ANY_ID
, quirk_no_ata_d3
);
941 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI
, PCI_ANY_ID
, quirk_no_ata_d3
);
943 /* This was originally an Alpha specific thing, but it really fits here.
944 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
946 static void __init
quirk_eisa_bridge(struct pci_dev
*dev
)
948 dev
->class = PCI_CLASS_BRIDGE_EISA
<< 8;
950 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82375
, quirk_eisa_bridge
);
954 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
955 * is not activated. The myth is that Asus said that they do not want the
956 * users to be irritated by just another PCI Device in the Win98 device
957 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
958 * package 2.7.0 for details)
960 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
961 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
962 * becomes necessary to do this tweak in two steps -- the chosen trigger
963 * is either the Host bridge (preferred) or on-board VGA controller.
965 * Note that we used to unhide the SMBus that way on Toshiba laptops
966 * (Satellite A40 and Tecra M2) but then found that the thermal management
967 * was done by SMM code, which could cause unsynchronized concurrent
968 * accesses to the SMBus registers, with potentially bad effects. Thus you
969 * should be very careful when adding new entries: if SMM is accessing the
970 * Intel SMBus, this is a very good reason to leave it hidden.
972 * Likewise, many recent laptops use ACPI for thermal management. If the
973 * ACPI DSDT code accesses the SMBus, then Linux should not access it
974 * natively, and keeping the SMBus hidden is the right thing to do. If you
975 * are about to add an entry in the table below, please first disassemble
976 * the DSDT and double-check that there is no code accessing the SMBus.
978 static int asus_hides_smbus
;
980 static void __init
asus_hides_smbus_hostbridge(struct pci_dev
*dev
)
982 if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_ASUSTEK
)) {
983 if (dev
->device
== PCI_DEVICE_ID_INTEL_82845_HB
)
984 switch(dev
->subsystem_device
) {
985 case 0x8025: /* P4B-LX */
986 case 0x8070: /* P4B */
987 case 0x8088: /* P4B533 */
988 case 0x1626: /* L3C notebook */
989 asus_hides_smbus
= 1;
991 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82845G_HB
)
992 switch(dev
->subsystem_device
) {
993 case 0x80b1: /* P4GE-V */
994 case 0x80b2: /* P4PE */
995 case 0x8093: /* P4B533-V */
996 asus_hides_smbus
= 1;
998 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82850_HB
)
999 switch(dev
->subsystem_device
) {
1000 case 0x8030: /* P4T533 */
1001 asus_hides_smbus
= 1;
1003 else if (dev
->device
== PCI_DEVICE_ID_INTEL_7205_0
)
1004 switch (dev
->subsystem_device
) {
1005 case 0x8070: /* P4G8X Deluxe */
1006 asus_hides_smbus
= 1;
1008 else if (dev
->device
== PCI_DEVICE_ID_INTEL_E7501_MCH
)
1009 switch (dev
->subsystem_device
) {
1010 case 0x80c9: /* PU-DLS */
1011 asus_hides_smbus
= 1;
1013 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82855GM_HB
)
1014 switch (dev
->subsystem_device
) {
1015 case 0x1751: /* M2N notebook */
1016 case 0x1821: /* M5N notebook */
1017 asus_hides_smbus
= 1;
1019 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1020 switch (dev
->subsystem_device
) {
1021 case 0x184b: /* W1N notebook */
1022 case 0x186a: /* M6Ne notebook */
1023 asus_hides_smbus
= 1;
1025 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82865_HB
)
1026 switch (dev
->subsystem_device
) {
1027 case 0x80f2: /* P4P800-X */
1028 asus_hides_smbus
= 1;
1030 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82915GM_HB
)
1031 switch (dev
->subsystem_device
) {
1032 case 0x1882: /* M6V notebook */
1033 case 0x1977: /* A6VA notebook */
1034 asus_hides_smbus
= 1;
1036 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_HP
)) {
1037 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1038 switch(dev
->subsystem_device
) {
1039 case 0x088C: /* HP Compaq nc8000 */
1040 case 0x0890: /* HP Compaq nc6000 */
1041 asus_hides_smbus
= 1;
1043 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82865_HB
)
1044 switch (dev
->subsystem_device
) {
1045 case 0x12bc: /* HP D330L */
1046 case 0x12bd: /* HP D530 */
1047 asus_hides_smbus
= 1;
1049 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82875_HB
)
1050 switch (dev
->subsystem_device
) {
1051 case 0x12bf: /* HP xw4100 */
1052 asus_hides_smbus
= 1;
1054 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_SAMSUNG
)) {
1055 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1056 switch(dev
->subsystem_device
) {
1057 case 0xC00C: /* Samsung P35 notebook */
1058 asus_hides_smbus
= 1;
1060 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_COMPAQ
)) {
1061 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1062 switch(dev
->subsystem_device
) {
1063 case 0x0058: /* Compaq Evo N620c */
1064 asus_hides_smbus
= 1;
1066 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82810_IG3
)
1067 switch(dev
->subsystem_device
) {
1068 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1069 /* Motherboard doesn't have Host bridge
1070 * subvendor/subdevice IDs, therefore checking
1071 * its on-board VGA controller */
1072 asus_hides_smbus
= 1;
1074 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82845G_IG
)
1075 switch(dev
->subsystem_device
) {
1076 case 0x00b8: /* Compaq Evo D510 CMT */
1077 case 0x00b9: /* Compaq Evo D510 SFF */
1078 asus_hides_smbus
= 1;
1080 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82815_CGC
)
1081 switch (dev
->subsystem_device
) {
1082 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1083 /* Motherboard doesn't have host bridge
1084 * subvendor/subdevice IDs, therefore checking
1085 * its on-board VGA controller */
1086 asus_hides_smbus
= 1;
1090 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82845_HB
, asus_hides_smbus_hostbridge
);
1091 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82845G_HB
, asus_hides_smbus_hostbridge
);
1092 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82850_HB
, asus_hides_smbus_hostbridge
);
1093 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82865_HB
, asus_hides_smbus_hostbridge
);
1094 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82875_HB
, asus_hides_smbus_hostbridge
);
1095 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_7205_0
, asus_hides_smbus_hostbridge
);
1096 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7501_MCH
, asus_hides_smbus_hostbridge
);
1097 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82855PM_HB
, asus_hides_smbus_hostbridge
);
1098 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82855GM_HB
, asus_hides_smbus_hostbridge
);
1099 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82915GM_HB
, asus_hides_smbus_hostbridge
);
1101 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82810_IG3
, asus_hides_smbus_hostbridge
);
1102 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82845G_IG
, asus_hides_smbus_hostbridge
);
1103 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82815_CGC
, asus_hides_smbus_hostbridge
);
1105 static void asus_hides_smbus_lpc(struct pci_dev
*dev
)
1109 if (likely(!asus_hides_smbus
))
1112 pci_read_config_word(dev
, 0xF2, &val
);
1114 pci_write_config_word(dev
, 0xF2, val
& (~0x8));
1115 pci_read_config_word(dev
, 0xF2, &val
);
1117 dev_info(&dev
->dev
, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val
);
1119 dev_info(&dev
->dev
, "Enabled i801 SMBus device\n");
1122 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, asus_hides_smbus_lpc
);
1123 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, asus_hides_smbus_lpc
);
1124 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, asus_hides_smbus_lpc
);
1125 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, asus_hides_smbus_lpc
);
1126 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, asus_hides_smbus_lpc
);
1127 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, asus_hides_smbus_lpc
);
1128 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, asus_hides_smbus_lpc
);
1129 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, asus_hides_smbus_lpc
);
1130 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, asus_hides_smbus_lpc
);
1131 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, asus_hides_smbus_lpc
);
1132 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, asus_hides_smbus_lpc
);
1133 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, asus_hides_smbus_lpc
);
1134 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, asus_hides_smbus_lpc
);
1135 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, asus_hides_smbus_lpc
);
1137 /* It appears we just have one such device. If not, we have a warning */
1138 static void __iomem
*asus_rcba_base
;
1139 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev
*dev
)
1143 if (likely(!asus_hides_smbus
))
1145 WARN_ON(asus_rcba_base
);
1147 pci_read_config_dword(dev
, 0xF0, &rcba
);
1148 /* use bits 31:14, 16 kB aligned */
1149 asus_rcba_base
= ioremap_nocache(rcba
& 0xFFFFC000, 0x4000);
1150 if (asus_rcba_base
== NULL
)
1154 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev
*dev
)
1158 if (likely(!asus_hides_smbus
|| !asus_rcba_base
))
1160 /* read the Function Disable register, dword mode only */
1161 val
= readl(asus_rcba_base
+ 0x3418);
1162 writel(val
& 0xFFFFFFF7, asus_rcba_base
+ 0x3418); /* enable the SMBus device */
1165 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev
*dev
)
1167 if (likely(!asus_hides_smbus
|| !asus_rcba_base
))
1169 iounmap(asus_rcba_base
);
1170 asus_rcba_base
= NULL
;
1171 dev_info(&dev
->dev
, "Enabled ICH6/i801 SMBus device\n");
1174 static void asus_hides_smbus_lpc_ich6(struct pci_dev
*dev
)
1176 asus_hides_smbus_lpc_ich6_suspend(dev
);
1177 asus_hides_smbus_lpc_ich6_resume_early(dev
);
1178 asus_hides_smbus_lpc_ich6_resume(dev
);
1180 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6
);
1181 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6_suspend
);
1182 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6_resume
);
1183 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6_resume_early
);
1186 * SiS 96x south bridge: BIOS typically hides SMBus device...
1188 static void quirk_sis_96x_smbus(struct pci_dev
*dev
)
1191 pci_read_config_byte(dev
, 0x77, &val
);
1193 dev_info(&dev
->dev
, "Enabling SiS 96x SMBus\n");
1194 pci_write_config_byte(dev
, 0x77, val
& ~0x10);
1197 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_961
, quirk_sis_96x_smbus
);
1198 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_962
, quirk_sis_96x_smbus
);
1199 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_963
, quirk_sis_96x_smbus
);
1200 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_LPC
, quirk_sis_96x_smbus
);
1201 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_961
, quirk_sis_96x_smbus
);
1202 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_962
, quirk_sis_96x_smbus
);
1203 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_963
, quirk_sis_96x_smbus
);
1204 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_LPC
, quirk_sis_96x_smbus
);
1207 * ... This is further complicated by the fact that some SiS96x south
1208 * bridges pretend to be 85C503/5513 instead. In that case see if we
1209 * spotted a compatible north bridge to make sure.
1210 * (pci_find_device doesn't work yet)
1212 * We can also enable the sis96x bit in the discovery register..
1214 #define SIS_DETECT_REGISTER 0x40
1216 static void quirk_sis_503(struct pci_dev
*dev
)
1221 pci_read_config_byte(dev
, SIS_DETECT_REGISTER
, ®
);
1222 pci_write_config_byte(dev
, SIS_DETECT_REGISTER
, reg
| (1 << 6));
1223 pci_read_config_word(dev
, PCI_DEVICE_ID
, &devid
);
1224 if (((devid
& 0xfff0) != 0x0960) && (devid
!= 0x0018)) {
1225 pci_write_config_byte(dev
, SIS_DETECT_REGISTER
, reg
);
1230 * Ok, it now shows up as a 96x.. run the 96x quirk by
1231 * hand in case it has already been processed.
1232 * (depends on link order, which is apparently not guaranteed)
1234 dev
->device
= devid
;
1235 quirk_sis_96x_smbus(dev
);
1237 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_503
, quirk_sis_503
);
1238 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_503
, quirk_sis_503
);
1242 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1243 * and MC97 modem controller are disabled when a second PCI soundcard is
1244 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1247 static void asus_hides_ac97_lpc(struct pci_dev
*dev
)
1250 int asus_hides_ac97
= 0;
1252 if (likely(dev
->subsystem_vendor
== PCI_VENDOR_ID_ASUSTEK
)) {
1253 if (dev
->device
== PCI_DEVICE_ID_VIA_8237
)
1254 asus_hides_ac97
= 1;
1257 if (!asus_hides_ac97
)
1260 pci_read_config_byte(dev
, 0x50, &val
);
1262 pci_write_config_byte(dev
, 0x50, val
& (~0xc0));
1263 pci_read_config_byte(dev
, 0x50, &val
);
1265 dev_info(&dev
->dev
, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val
);
1267 dev_info(&dev
->dev
, "Enabled onboard AC97/MC97 devices\n");
1270 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, asus_hides_ac97_lpc
);
1271 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, asus_hides_ac97_lpc
);
1273 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1276 * If we are using libata we can drive this chip properly but must
1277 * do this early on to make the additional device appear during
1280 static void quirk_jmicron_ata(struct pci_dev
*pdev
)
1282 u32 conf1
, conf5
, class;
1285 /* Only poke fn 0 */
1286 if (PCI_FUNC(pdev
->devfn
))
1289 pci_read_config_dword(pdev
, 0x40, &conf1
);
1290 pci_read_config_dword(pdev
, 0x80, &conf5
);
1292 conf1
&= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1293 conf5
&= ~(1 << 24); /* Clear bit 24 */
1295 switch (pdev
->device
) {
1296 case PCI_DEVICE_ID_JMICRON_JMB360
:
1297 /* The controller should be in single function ahci mode */
1298 conf1
|= 0x0002A100; /* Set 8, 13, 15, 17 */
1301 case PCI_DEVICE_ID_JMICRON_JMB365
:
1302 case PCI_DEVICE_ID_JMICRON_JMB366
:
1303 /* Redirect IDE second PATA port to the right spot */
1306 case PCI_DEVICE_ID_JMICRON_JMB361
:
1307 case PCI_DEVICE_ID_JMICRON_JMB363
:
1308 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1309 /* Set the class codes correctly and then direct IDE 0 */
1310 conf1
|= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1313 case PCI_DEVICE_ID_JMICRON_JMB368
:
1314 /* The controller should be in single function IDE mode */
1315 conf1
|= 0x00C00000; /* Set 22, 23 */
1319 pci_write_config_dword(pdev
, 0x40, conf1
);
1320 pci_write_config_dword(pdev
, 0x80, conf5
);
1322 /* Update pdev accordingly */
1323 pci_read_config_byte(pdev
, PCI_HEADER_TYPE
, &hdr
);
1324 pdev
->hdr_type
= hdr
& 0x7f;
1325 pdev
->multifunction
= !!(hdr
& 0x80);
1327 pci_read_config_dword(pdev
, PCI_CLASS_REVISION
, &class);
1328 pdev
->class = class >> 8;
1330 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB360
, quirk_jmicron_ata
);
1331 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB361
, quirk_jmicron_ata
);
1332 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB363
, quirk_jmicron_ata
);
1333 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB365
, quirk_jmicron_ata
);
1334 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB366
, quirk_jmicron_ata
);
1335 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB368
, quirk_jmicron_ata
);
1336 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB360
, quirk_jmicron_ata
);
1337 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB361
, quirk_jmicron_ata
);
1338 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB363
, quirk_jmicron_ata
);
1339 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB365
, quirk_jmicron_ata
);
1340 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB366
, quirk_jmicron_ata
);
1341 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB368
, quirk_jmicron_ata
);
1345 #ifdef CONFIG_X86_IO_APIC
1346 static void __init
quirk_alder_ioapic(struct pci_dev
*pdev
)
1350 if ((pdev
->class >> 8) != 0xff00)
1353 /* the first BAR is the location of the IO APIC...we must
1354 * not touch this (and it's already covered by the fixmap), so
1355 * forcibly insert it into the resource tree */
1356 if (pci_resource_start(pdev
, 0) && pci_resource_len(pdev
, 0))
1357 insert_resource(&iomem_resource
, &pdev
->resource
[0]);
1359 /* The next five BARs all seem to be rubbish, so just clean
1361 for (i
=1; i
< 6; i
++) {
1362 memset(&pdev
->resource
[i
], 0, sizeof(pdev
->resource
[i
]));
1366 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_EESSC
, quirk_alder_ioapic
);
1369 static void __devinit
quirk_pcie_mch(struct pci_dev
*pdev
)
1373 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7520_MCH
, quirk_pcie_mch
);
1374 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7320_MCH
, quirk_pcie_mch
);
1375 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7525_MCH
, quirk_pcie_mch
);
1379 * It's possible for the MSI to get corrupted if shpc and acpi
1380 * are used together on certain PXH-based systems.
1382 static void __devinit
quirk_pcie_pxh(struct pci_dev
*dev
)
1386 dev_warn(&dev
->dev
, "PXH quirk detected; SHPC device MSI disabled\n");
1388 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHD_0
, quirk_pcie_pxh
);
1389 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHD_1
, quirk_pcie_pxh
);
1390 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
, quirk_pcie_pxh
);
1391 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
, quirk_pcie_pxh
);
1392 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHV
, quirk_pcie_pxh
);
1395 * Some Intel PCI Express chipsets have trouble with downstream
1396 * device power management.
1398 static void quirk_intel_pcie_pm(struct pci_dev
* dev
)
1400 pci_pm_d3_delay
= 120;
1404 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e2, quirk_intel_pcie_pm
);
1405 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e3, quirk_intel_pcie_pm
);
1406 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e4, quirk_intel_pcie_pm
);
1407 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e5, quirk_intel_pcie_pm
);
1408 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e6, quirk_intel_pcie_pm
);
1409 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e7, quirk_intel_pcie_pm
);
1410 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f7, quirk_intel_pcie_pm
);
1411 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f8, quirk_intel_pcie_pm
);
1412 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f9, quirk_intel_pcie_pm
);
1413 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25fa, quirk_intel_pcie_pm
);
1414 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2601, quirk_intel_pcie_pm
);
1415 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2602, quirk_intel_pcie_pm
);
1416 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2603, quirk_intel_pcie_pm
);
1417 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2604, quirk_intel_pcie_pm
);
1418 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2605, quirk_intel_pcie_pm
);
1419 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2606, quirk_intel_pcie_pm
);
1420 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2607, quirk_intel_pcie_pm
);
1421 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2608, quirk_intel_pcie_pm
);
1422 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2609, quirk_intel_pcie_pm
);
1423 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x260a, quirk_intel_pcie_pm
);
1424 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x260b, quirk_intel_pcie_pm
);
1427 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1428 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1429 * Re-allocate the region if needed...
1431 static void __init
quirk_tc86c001_ide(struct pci_dev
*dev
)
1433 struct resource
*r
= &dev
->resource
[0];
1435 if (r
->start
& 0x8) {
1440 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2
,
1441 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE
,
1442 quirk_tc86c001_ide
);
1444 static void __devinit
quirk_netmos(struct pci_dev
*dev
)
1446 unsigned int num_parallel
= (dev
->subsystem_device
& 0xf0) >> 4;
1447 unsigned int num_serial
= dev
->subsystem_device
& 0xf;
1450 * These Netmos parts are multiport serial devices with optional
1451 * parallel ports. Even when parallel ports are present, they
1452 * are identified as class SERIAL, which means the serial driver
1453 * will claim them. To prevent this, mark them as class OTHER.
1454 * These combo devices should be claimed by parport_serial.
1456 * The subdevice ID is of the form 0x00PS, where <P> is the number
1457 * of parallel ports and <S> is the number of serial ports.
1459 switch (dev
->device
) {
1460 case PCI_DEVICE_ID_NETMOS_9735
:
1461 case PCI_DEVICE_ID_NETMOS_9745
:
1462 case PCI_DEVICE_ID_NETMOS_9835
:
1463 case PCI_DEVICE_ID_NETMOS_9845
:
1464 case PCI_DEVICE_ID_NETMOS_9855
:
1465 if ((dev
->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL
&&
1467 dev_info(&dev
->dev
, "Netmos %04x (%u parallel, "
1468 "%u serial); changing class SERIAL to OTHER "
1469 "(use parport_serial)\n",
1470 dev
->device
, num_parallel
, num_serial
);
1471 dev
->class = (PCI_CLASS_COMMUNICATION_OTHER
<< 8) |
1472 (dev
->class & 0xff);
1476 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS
, PCI_ANY_ID
, quirk_netmos
);
1478 static void __devinit
quirk_e100_interrupt(struct pci_dev
*dev
)
1485 switch (dev
->device
) {
1486 /* PCI IDs taken from drivers/net/e100.c */
1488 case 0x1030 ... 0x1034:
1489 case 0x1038 ... 0x103E:
1490 case 0x1050 ... 0x1057:
1492 case 0x1064 ... 0x106B:
1493 case 0x1091 ... 0x1095:
1506 * Some firmware hands off the e100 with interrupts enabled,
1507 * which can cause a flood of interrupts if packets are
1508 * received before the driver attaches to the device. So
1509 * disable all e100 interrupts here. The driver will
1510 * re-enable them when it's ready.
1512 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1514 if (!(command
& PCI_COMMAND_MEMORY
) || !pci_resource_start(dev
, 0))
1518 * Check that the device is in the D0 power state. If it's not,
1519 * there is no point to look any further.
1521 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
1523 pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &pmcsr
);
1524 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) != PCI_D0
)
1528 /* Convert from PCI bus to resource space. */
1529 csr
= ioremap(pci_resource_start(dev
, 0), 8);
1531 dev_warn(&dev
->dev
, "Can't map e100 registers\n");
1535 cmd_hi
= readb(csr
+ 3);
1537 dev_warn(&dev
->dev
, "Firmware left e100 interrupts enabled; "
1544 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
, quirk_e100_interrupt
);
1546 static void __devinit
fixup_rev1_53c810(struct pci_dev
* dev
)
1548 /* rev 1 ncr53c810 chips don't set the class at all which means
1549 * they don't get their resources remapped. Fix that here.
1552 if (dev
->class == PCI_CLASS_NOT_DEFINED
) {
1553 dev_info(&dev
->dev
, "NCR 53c810 rev 1 detected; setting PCI class\n");
1554 dev
->class = PCI_CLASS_STORAGE_SCSI
;
1557 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR
, PCI_DEVICE_ID_NCR_53C810
, fixup_rev1_53c810
);
1559 /* Enable 1k I/O space granularity on the Intel P64H2 */
1560 static void __devinit
quirk_p64h2_1k_io(struct pci_dev
*dev
)
1563 u8 io_base_lo
, io_limit_lo
;
1564 unsigned long base
, limit
;
1565 struct resource
*res
= dev
->resource
+ PCI_BRIDGE_RESOURCES
;
1567 pci_read_config_word(dev
, 0x40, &en1k
);
1570 dev_info(&dev
->dev
, "Enable I/O Space to 1KB granularity\n");
1572 pci_read_config_byte(dev
, PCI_IO_BASE
, &io_base_lo
);
1573 pci_read_config_byte(dev
, PCI_IO_LIMIT
, &io_limit_lo
);
1574 base
= (io_base_lo
& (PCI_IO_RANGE_MASK
| 0x0c)) << 8;
1575 limit
= (io_limit_lo
& (PCI_IO_RANGE_MASK
| 0x0c)) << 8;
1577 if (base
<= limit
) {
1579 res
->end
= limit
+ 0x3ff;
1583 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x1460, quirk_p64h2_1k_io
);
1585 /* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1586 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1587 * in drivers/pci/setup-bus.c
1589 static void __devinit
quirk_p64h2_1k_io_fix_iobl(struct pci_dev
*dev
)
1591 u16 en1k
, iobl_adr
, iobl_adr_1k
;
1592 struct resource
*res
= dev
->resource
+ PCI_BRIDGE_RESOURCES
;
1594 pci_read_config_word(dev
, 0x40, &en1k
);
1597 pci_read_config_word(dev
, PCI_IO_BASE
, &iobl_adr
);
1599 iobl_adr_1k
= iobl_adr
| (res
->start
>> 8) | (res
->end
& 0xfc00);
1601 if (iobl_adr
!= iobl_adr_1k
) {
1602 dev_info(&dev
->dev
, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
1603 iobl_adr
,iobl_adr_1k
);
1604 pci_write_config_word(dev
, PCI_IO_BASE
, iobl_adr_1k
);
1608 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1460, quirk_p64h2_1k_io_fix_iobl
);
1610 /* Under some circumstances, AER is not linked with extended capabilities.
1611 * Force it to be linked by setting the corresponding control bit in the
1614 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev
*dev
)
1617 if (pci_read_config_byte(dev
, 0xf41, &b
) == 0) {
1619 pci_write_config_byte(dev
, 0xf41, b
| 0x20);
1621 "Linking AER extended capability\n");
1625 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
1626 quirk_nvidia_ck804_pcie_aer_ext_cap
);
1627 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
1628 quirk_nvidia_ck804_pcie_aer_ext_cap
);
1630 static void __devinit
quirk_via_cx700_pci_parking_caching(struct pci_dev
*dev
)
1633 * Disable PCI Bus Parking and PCI Master read caching on CX700
1634 * which causes unspecified timing errors with a VT6212L on the PCI
1635 * bus leading to USB2.0 packet loss. The defaults are that these
1636 * features are turned off but some BIOSes turn them on.
1640 if (pci_read_config_byte(dev
, 0x76, &b
) == 0) {
1642 /* Turn off PCI Bus Parking */
1643 pci_write_config_byte(dev
, 0x76, b
^ 0x40);
1646 "Disabling VIA CX700 PCI parking\n");
1650 if (pci_read_config_byte(dev
, 0x72, &b
) == 0) {
1652 /* Turn off PCI Master read caching */
1653 pci_write_config_byte(dev
, 0x72, 0x0);
1655 /* Set PCI Master Bus time-out to "1x16 PCLK" */
1656 pci_write_config_byte(dev
, 0x75, 0x1);
1658 /* Disable "Read FIFO Timer" */
1659 pci_write_config_byte(dev
, 0x77, 0x0);
1662 "Disabling VIA CX700 PCI caching\n");
1666 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA
, 0x324e, quirk_via_cx700_pci_parking_caching
);
1669 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
1670 * VPD end tag will hang the device. This problem was initially
1671 * observed when a vpd entry was created in sysfs
1672 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
1673 * will dump 32k of data. Reading a full 32k will cause an access
1674 * beyond the VPD end tag causing the device to hang. Once the device
1675 * is hung, the bnx2 driver will not be able to reset the device.
1676 * We believe that it is legal to read beyond the end tag and
1677 * therefore the solution is to limit the read/write length.
1679 static void __devinit
quirk_brcm_570x_limit_vpd(struct pci_dev
*dev
)
1682 * Only disable the VPD capability for 5706, 5706S, 5708,
1683 * 5708S and 5709 rev. A
1685 if ((dev
->device
== PCI_DEVICE_ID_NX2_5706
) ||
1686 (dev
->device
== PCI_DEVICE_ID_NX2_5706S
) ||
1687 (dev
->device
== PCI_DEVICE_ID_NX2_5708
) ||
1688 (dev
->device
== PCI_DEVICE_ID_NX2_5708S
) ||
1689 ((dev
->device
== PCI_DEVICE_ID_NX2_5709
) &&
1690 (dev
->revision
& 0xf0) == 0x0)) {
1692 dev
->vpd
->len
= 0x80;
1696 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
1697 PCI_DEVICE_ID_NX2_5706
,
1698 quirk_brcm_570x_limit_vpd
);
1699 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
1700 PCI_DEVICE_ID_NX2_5706S
,
1701 quirk_brcm_570x_limit_vpd
);
1702 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
1703 PCI_DEVICE_ID_NX2_5708
,
1704 quirk_brcm_570x_limit_vpd
);
1705 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
1706 PCI_DEVICE_ID_NX2_5708S
,
1707 quirk_brcm_570x_limit_vpd
);
1708 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
1709 PCI_DEVICE_ID_NX2_5709
,
1710 quirk_brcm_570x_limit_vpd
);
1711 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
1712 PCI_DEVICE_ID_NX2_5709S
,
1713 quirk_brcm_570x_limit_vpd
);
1715 #ifdef CONFIG_PCI_MSI
1716 /* Some chipsets do not support MSI. We cannot easily rely on setting
1717 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
1718 * some other busses controlled by the chipset even if Linux is not
1719 * aware of it. Instead of setting the flag on all busses in the
1720 * machine, simply disable MSI globally.
1722 static void __init
quirk_disable_all_msi(struct pci_dev
*dev
)
1725 dev_warn(&dev
->dev
, "MSI quirk detected; MSI disabled\n");
1727 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE
, quirk_disable_all_msi
);
1728 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS400_200
, quirk_disable_all_msi
);
1729 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS480
, quirk_disable_all_msi
);
1730 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_VT3336
, quirk_disable_all_msi
);
1731 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_VT3351
, quirk_disable_all_msi
);
1733 /* Disable MSI on chipsets that are known to not support it */
1734 static void __devinit
quirk_disable_msi(struct pci_dev
*dev
)
1736 if (dev
->subordinate
) {
1737 dev_warn(&dev
->dev
, "MSI quirk detected; "
1738 "subordinate MSI disabled\n");
1739 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
1742 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_disable_msi
);
1744 /* Go through the list of Hypertransport capabilities and
1745 * return 1 if a HT MSI capability is found and enabled */
1746 static int __devinit
msi_ht_cap_enabled(struct pci_dev
*dev
)
1750 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
1751 while (pos
&& ttl
--) {
1754 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
1757 dev_info(&dev
->dev
, "Found %s HT MSI Mapping\n",
1758 flags
& HT_MSI_FLAGS_ENABLE
?
1759 "enabled" : "disabled");
1760 return (flags
& HT_MSI_FLAGS_ENABLE
) != 0;
1763 pos
= pci_find_next_ht_capability(dev
, pos
,
1764 HT_CAPTYPE_MSI_MAPPING
);
1769 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
1770 static void __devinit
quirk_msi_ht_cap(struct pci_dev
*dev
)
1772 if (dev
->subordinate
&& !msi_ht_cap_enabled(dev
)) {
1773 dev_warn(&dev
->dev
, "MSI quirk detected; "
1774 "subordinate MSI disabled\n");
1775 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
1778 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE
,
1782 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
1783 * MSI are supported if the MSI capability set in any of these mappings.
1785 static void __devinit
quirk_nvidia_ck804_msi_ht_cap(struct pci_dev
*dev
)
1787 struct pci_dev
*pdev
;
1789 if (!dev
->subordinate
)
1792 /* check HT MSI cap on this chipset and the root one.
1793 * a single one having MSI is enough to be sure that MSI are supported.
1795 pdev
= pci_get_slot(dev
->bus
, 0);
1798 if (!msi_ht_cap_enabled(dev
) && !msi_ht_cap_enabled(pdev
)) {
1799 dev_warn(&dev
->dev
, "MSI quirk detected; "
1800 "subordinate MSI disabled\n");
1801 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
1805 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
1806 quirk_nvidia_ck804_msi_ht_cap
);
1808 /* Force enable MSI mapping capability on HT bridges */
1809 static void __devinit
ht_enable_msi_mapping(struct pci_dev
*dev
)
1813 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
1814 while (pos
&& ttl
--) {
1817 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
1819 dev_info(&dev
->dev
, "Enabling HT MSI Mapping\n");
1821 pci_write_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
1822 flags
| HT_MSI_FLAGS_ENABLE
);
1824 pos
= pci_find_next_ht_capability(dev
, pos
,
1825 HT_CAPTYPE_MSI_MAPPING
);
1828 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS
,
1829 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB
,
1830 ht_enable_msi_mapping
);
1832 /* The P5N32-SLI Premium motherboard from Asus has a problem with msi
1833 * for the MCP55 NIC. It is not yet determined whether the msi problem
1834 * also affects other devices. As for now, turn off msi for this device.
1836 static void __devinit
nvenet_msi_disable(struct pci_dev
*dev
)
1838 if (dmi_name_in_vendors("P5N32-SLI PREMIUM")) {
1840 "Disabling msi for MCP55 NIC on P5N32-SLI Premium\n");
1844 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA
,
1845 PCI_DEVICE_ID_NVIDIA_NVENET_15
,
1846 nvenet_msi_disable
);
1848 static void __devinit
nv_msi_ht_cap_quirk(struct pci_dev
*dev
)
1850 struct pci_dev
*host_bridge
;
1854 * HT MSI mapping should be disabled on devices that are below
1855 * a non-Hypertransport host bridge. Locate the host bridge...
1857 host_bridge
= pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1858 if (host_bridge
== NULL
) {
1860 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
1864 pos
= pci_find_ht_capability(host_bridge
, HT_CAPTYPE_SLAVE
);
1866 /* Host bridge is to HT */
1867 ht_enable_msi_mapping(dev
);
1871 /* Host bridge is not to HT, disable HT MSI mapping on this device */
1872 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
1873 while (pos
&& ttl
--) {
1876 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
1878 dev_info(&dev
->dev
, "Disabling HT MSI mapping");
1879 pci_write_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
1880 flags
& ~HT_MSI_FLAGS_ENABLE
);
1882 pos
= pci_find_next_ht_capability(dev
, pos
,
1883 HT_CAPTYPE_MSI_MAPPING
);
1886 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
, nv_msi_ht_cap_quirk
);
1887 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_ANY_ID
, nv_msi_ht_cap_quirk
);
1889 static void __devinit
quirk_msi_intx_disable_bug(struct pci_dev
*dev
)
1891 dev
->dev_flags
|= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
;
1893 static void __devinit
quirk_msi_intx_disable_ati_bug(struct pci_dev
*dev
)
1897 /* SB700 MSI issue will be fixed at HW level from revision A21,
1898 * we need check PCI REVISION ID of SMBus controller to get SB700
1901 p
= pci_get_device(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_SBX00_SMBUS
,
1906 if ((p
->revision
< 0x3B) && (p
->revision
>= 0x30))
1907 dev
->dev_flags
|= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
;
1910 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
1911 PCI_DEVICE_ID_TIGON3_5780
,
1912 quirk_msi_intx_disable_bug
);
1913 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
1914 PCI_DEVICE_ID_TIGON3_5780S
,
1915 quirk_msi_intx_disable_bug
);
1916 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
1917 PCI_DEVICE_ID_TIGON3_5714
,
1918 quirk_msi_intx_disable_bug
);
1919 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
1920 PCI_DEVICE_ID_TIGON3_5714S
,
1921 quirk_msi_intx_disable_bug
);
1922 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
1923 PCI_DEVICE_ID_TIGON3_5715
,
1924 quirk_msi_intx_disable_bug
);
1925 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
1926 PCI_DEVICE_ID_TIGON3_5715S
,
1927 quirk_msi_intx_disable_bug
);
1929 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4390,
1930 quirk_msi_intx_disable_ati_bug
);
1931 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4391,
1932 quirk_msi_intx_disable_ati_bug
);
1933 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4392,
1934 quirk_msi_intx_disable_ati_bug
);
1935 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4393,
1936 quirk_msi_intx_disable_ati_bug
);
1937 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4394,
1938 quirk_msi_intx_disable_ati_bug
);
1940 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4373,
1941 quirk_msi_intx_disable_bug
);
1942 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4374,
1943 quirk_msi_intx_disable_bug
);
1944 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4375,
1945 quirk_msi_intx_disable_bug
);
1947 #endif /* CONFIG_PCI_MSI */
1949 static void pci_do_fixups(struct pci_dev
*dev
, struct pci_fixup
*f
, struct pci_fixup
*end
)
1952 if ((f
->vendor
== dev
->vendor
|| f
->vendor
== (u16
) PCI_ANY_ID
) &&
1953 (f
->device
== dev
->device
|| f
->device
== (u16
) PCI_ANY_ID
)) {
1954 dev_dbg(&dev
->dev
, "calling %pF\n", f
->hook
);
1961 extern struct pci_fixup __start_pci_fixups_early
[];
1962 extern struct pci_fixup __end_pci_fixups_early
[];
1963 extern struct pci_fixup __start_pci_fixups_header
[];
1964 extern struct pci_fixup __end_pci_fixups_header
[];
1965 extern struct pci_fixup __start_pci_fixups_final
[];
1966 extern struct pci_fixup __end_pci_fixups_final
[];
1967 extern struct pci_fixup __start_pci_fixups_enable
[];
1968 extern struct pci_fixup __end_pci_fixups_enable
[];
1969 extern struct pci_fixup __start_pci_fixups_resume
[];
1970 extern struct pci_fixup __end_pci_fixups_resume
[];
1971 extern struct pci_fixup __start_pci_fixups_resume_early
[];
1972 extern struct pci_fixup __end_pci_fixups_resume_early
[];
1973 extern struct pci_fixup __start_pci_fixups_suspend
[];
1974 extern struct pci_fixup __end_pci_fixups_suspend
[];
1977 void pci_fixup_device(enum pci_fixup_pass pass
, struct pci_dev
*dev
)
1979 struct pci_fixup
*start
, *end
;
1982 case pci_fixup_early
:
1983 start
= __start_pci_fixups_early
;
1984 end
= __end_pci_fixups_early
;
1987 case pci_fixup_header
:
1988 start
= __start_pci_fixups_header
;
1989 end
= __end_pci_fixups_header
;
1992 case pci_fixup_final
:
1993 start
= __start_pci_fixups_final
;
1994 end
= __end_pci_fixups_final
;
1997 case pci_fixup_enable
:
1998 start
= __start_pci_fixups_enable
;
1999 end
= __end_pci_fixups_enable
;
2002 case pci_fixup_resume
:
2003 start
= __start_pci_fixups_resume
;
2004 end
= __end_pci_fixups_resume
;
2007 case pci_fixup_resume_early
:
2008 start
= __start_pci_fixups_resume_early
;
2009 end
= __end_pci_fixups_resume_early
;
2012 case pci_fixup_suspend
:
2013 start
= __start_pci_fixups_suspend
;
2014 end
= __end_pci_fixups_suspend
;
2018 /* stupid compiler warning, you would think with an enum... */
2021 pci_do_fixups(dev
, start
, end
);
2024 void pci_fixup_device(enum pci_fixup_pass pass
, struct pci_dev
*dev
) {}
2026 EXPORT_SYMBOL(pci_fixup_device
);