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cnic: Fix rare race condition during iSCSI disconnect.
[linux-2.6.git] / drivers / net / ethernet / broadcom / cnic.c
blob091c60a9897cca06a08c709243aafd26a40256b0
1 /* cnic.c: Broadcom CNIC core network driver.
2 *
3 * Copyright (c) 2006-2012 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
10 * Modified and maintained by: Michael Chan <mchan@broadcom.com>
11 */
12
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15 #include <linux/module.h>
16
17 #include <linux/kernel.h>
18 #include <linux/errno.h>
19 #include <linux/list.h>
20 #include <linux/slab.h>
21 #include <linux/pci.h>
22 #include <linux/init.h>
23 #include <linux/netdevice.h>
24 #include <linux/uio_driver.h>
25 #include <linux/in.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/delay.h>
28 #include <linux/ethtool.h>
29 #include <linux/if_vlan.h>
30 #include <linux/prefetch.h>
31 #include <linux/random.h>
32 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
33 #define BCM_VLAN 1
34 #endif
35 #include <net/ip.h>
36 #include <net/tcp.h>
37 #include <net/route.h>
38 #include <net/ipv6.h>
39 #include <net/ip6_route.h>
40 #include <net/ip6_checksum.h>
41 #include <scsi/iscsi_if.h>
42
43 #include "cnic_if.h"
44 #include "bnx2.h"
45 #include "bnx2x/bnx2x_reg.h"
46 #include "bnx2x/bnx2x_fw_defs.h"
47 #include "bnx2x/bnx2x_hsi.h"
48 #include "../../../scsi/bnx2i/57xx_iscsi_constants.h"
49 #include "../../../scsi/bnx2i/57xx_iscsi_hsi.h"
50 #include "../../../scsi/bnx2fc/bnx2fc_constants.h"
51 #include "cnic.h"
52 #include "cnic_defs.h"
53
54 #define DRV_MODULE_NAME "cnic"
55
56 static char version[] =
57 "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
58
59 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
60 "Chen (zongxi@broadcom.com");
61 MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
62 MODULE_LICENSE("GPL");
63 MODULE_VERSION(CNIC_MODULE_VERSION);
64
65 /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
66 static LIST_HEAD(cnic_dev_list);
67 static LIST_HEAD(cnic_udev_list);
68 static DEFINE_RWLOCK(cnic_dev_lock);
69 static DEFINE_MUTEX(cnic_lock);
70
71 static struct cnic_ulp_ops __rcu *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
72
73 /* helper function, assuming cnic_lock is held */
74 static inline struct cnic_ulp_ops *cnic_ulp_tbl_prot(int type)
75 {
76 return rcu_dereference_protected(cnic_ulp_tbl[type],
77 lockdep_is_held(&cnic_lock));
78 }
79
80 static int cnic_service_bnx2(void *, void *);
81 static int cnic_service_bnx2x(void *, void *);
82 static int cnic_ctl(void *, struct cnic_ctl_info *);
83
84 static struct cnic_ops cnic_bnx2_ops = {
85 .cnic_owner = THIS_MODULE,
86 .cnic_handler = cnic_service_bnx2,
87 .cnic_ctl = cnic_ctl,
88 };
89
90 static struct cnic_ops cnic_bnx2x_ops = {
91 .cnic_owner = THIS_MODULE,
92 .cnic_handler = cnic_service_bnx2x,
93 .cnic_ctl = cnic_ctl,
94 };
95
96 static struct workqueue_struct *cnic_wq;
97
98 static void cnic_shutdown_rings(struct cnic_dev *);
99 static void cnic_init_rings(struct cnic_dev *);
100 static int cnic_cm_set_pg(struct cnic_sock *);
101
102 static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
103 {
104 struct cnic_uio_dev *udev = uinfo->priv;
105 struct cnic_dev *dev;
106
107 if (!capable(CAP_NET_ADMIN))
108 return -EPERM;
109
110 if (udev->uio_dev != -1)
111 return -EBUSY;
112
113 rtnl_lock();
114 dev = udev->dev;
115
116 if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
117 rtnl_unlock();
118 return -ENODEV;
119 }
120
121 udev->uio_dev = iminor(inode);
122
123 cnic_shutdown_rings(dev);
124 cnic_init_rings(dev);
125 rtnl_unlock();
126
127 return 0;
128 }
129
130 static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
131 {
132 struct cnic_uio_dev *udev = uinfo->priv;
133
134 udev->uio_dev = -1;
135 return 0;
136 }
137
138 static inline void cnic_hold(struct cnic_dev *dev)
139 {
140 atomic_inc(&dev->ref_count);
141 }
142
143 static inline void cnic_put(struct cnic_dev *dev)
144 {
145 atomic_dec(&dev->ref_count);
146 }
147
148 static inline void csk_hold(struct cnic_sock *csk)
149 {
150 atomic_inc(&csk->ref_count);
151 }
152
153 static inline void csk_put(struct cnic_sock *csk)
154 {
155 atomic_dec(&csk->ref_count);
156 }
157
158 static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
159 {
160 struct cnic_dev *cdev;
161
162 read_lock(&cnic_dev_lock);
163 list_for_each_entry(cdev, &cnic_dev_list, list) {
164 if (netdev == cdev->netdev) {
165 cnic_hold(cdev);
166 read_unlock(&cnic_dev_lock);
167 return cdev;
168 }
169 }
170 read_unlock(&cnic_dev_lock);
171 return NULL;
172 }
173
174 static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
175 {
176 atomic_inc(&ulp_ops->ref_count);
177 }
178
179 static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
180 {
181 atomic_dec(&ulp_ops->ref_count);
182 }
183
184 static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
185 {
186 struct cnic_local *cp = dev->cnic_priv;
187 struct cnic_eth_dev *ethdev = cp->ethdev;
188 struct drv_ctl_info info;
189 struct drv_ctl_io *io = &info.data.io;
190
191 info.cmd = DRV_CTL_CTX_WR_CMD;
192 io->cid_addr = cid_addr;
193 io->offset = off;
194 io->data = val;
195 ethdev->drv_ctl(dev->netdev, &info);
196 }
197
198 static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
199 {
200 struct cnic_local *cp = dev->cnic_priv;
201 struct cnic_eth_dev *ethdev = cp->ethdev;
202 struct drv_ctl_info info;
203 struct drv_ctl_io *io = &info.data.io;
204
205 info.cmd = DRV_CTL_CTXTBL_WR_CMD;
206 io->offset = off;
207 io->dma_addr = addr;
208 ethdev->drv_ctl(dev->netdev, &info);
209 }
210
211 static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
212 {
213 struct cnic_local *cp = dev->cnic_priv;
214 struct cnic_eth_dev *ethdev = cp->ethdev;
215 struct drv_ctl_info info;
216 struct drv_ctl_l2_ring *ring = &info.data.ring;
217
218 if (start)
219 info.cmd = DRV_CTL_START_L2_CMD;
220 else
221 info.cmd = DRV_CTL_STOP_L2_CMD;
222
223 ring->cid = cid;
224 ring->client_id = cl_id;
225 ethdev->drv_ctl(dev->netdev, &info);
226 }
227
228 static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
229 {
230 struct cnic_local *cp = dev->cnic_priv;
231 struct cnic_eth_dev *ethdev = cp->ethdev;
232 struct drv_ctl_info info;
233 struct drv_ctl_io *io = &info.data.io;
234
235 info.cmd = DRV_CTL_IO_WR_CMD;
236 io->offset = off;
237 io->data = val;
238 ethdev->drv_ctl(dev->netdev, &info);
239 }
240
241 static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
242 {
243 struct cnic_local *cp = dev->cnic_priv;
244 struct cnic_eth_dev *ethdev = cp->ethdev;
245 struct drv_ctl_info info;
246 struct drv_ctl_io *io = &info.data.io;
247
248 info.cmd = DRV_CTL_IO_RD_CMD;
249 io->offset = off;
250 ethdev->drv_ctl(dev->netdev, &info);
251 return io->data;
252 }
253
254 static void cnic_ulp_ctl(struct cnic_dev *dev, int ulp_type, bool reg)
255 {
256 struct cnic_local *cp = dev->cnic_priv;
257 struct cnic_eth_dev *ethdev = cp->ethdev;
258 struct drv_ctl_info info;
259 struct fcoe_capabilities *fcoe_cap =
260 &info.data.register_data.fcoe_features;
261
262 if (reg) {
263 info.cmd = DRV_CTL_ULP_REGISTER_CMD;
264 if (ulp_type == CNIC_ULP_FCOE && dev->fcoe_cap)
265 memcpy(fcoe_cap, dev->fcoe_cap, sizeof(*fcoe_cap));
266 } else {
267 info.cmd = DRV_CTL_ULP_UNREGISTER_CMD;
268 }
269
270 info.data.ulp_type = ulp_type;
271 ethdev->drv_ctl(dev->netdev, &info);
272 }
273
274 static int cnic_in_use(struct cnic_sock *csk)
275 {
276 return test_bit(SK_F_INUSE, &csk->flags);
277 }
278
279 static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
280 {
281 struct cnic_local *cp = dev->cnic_priv;
282 struct cnic_eth_dev *ethdev = cp->ethdev;
283 struct drv_ctl_info info;
284
285 info.cmd = cmd;
286 info.data.credit.credit_count = count;
287 ethdev->drv_ctl(dev->netdev, &info);
288 }
289
290 static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
291 {
292 u32 i;
293
294 if (!cp->ctx_tbl)
295 return -EINVAL;
296
297 for (i = 0; i < cp->max_cid_space; i++) {
298 if (cp->ctx_tbl[i].cid == cid) {
299 *l5_cid = i;
300 return 0;
301 }
302 }
303 return -EINVAL;
304 }
305
306 static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
307 struct cnic_sock *csk)
308 {
309 struct iscsi_path path_req;
310 char *buf = NULL;
311 u16 len = 0;
312 u32 msg_type = ISCSI_KEVENT_IF_DOWN;
313 struct cnic_ulp_ops *ulp_ops;
314 struct cnic_uio_dev *udev = cp->udev;
315 int rc = 0, retry = 0;
316
317 if (!udev || udev->uio_dev == -1)
318 return -ENODEV;
319
320 if (csk) {
321 len = sizeof(path_req);
322 buf = (char *) &path_req;
323 memset(&path_req, 0, len);
324
325 msg_type = ISCSI_KEVENT_PATH_REQ;
326 path_req.handle = (u64) csk->l5_cid;
327 if (test_bit(SK_F_IPV6, &csk->flags)) {
328 memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
329 sizeof(struct in6_addr));
330 path_req.ip_addr_len = 16;
331 } else {
332 memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
333 sizeof(struct in_addr));
334 path_req.ip_addr_len = 4;
335 }
336 path_req.vlan_id = csk->vlan_id;
337 path_req.pmtu = csk->mtu;
338 }
339
340 while (retry < 3) {
341 rc = 0;
342 rcu_read_lock();
343 ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
344 if (ulp_ops)
345 rc = ulp_ops->iscsi_nl_send_msg(
346 cp->ulp_handle[CNIC_ULP_ISCSI],
347 msg_type, buf, len);
348 rcu_read_unlock();
349 if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
350 break;
351
352 msleep(100);
353 retry++;
354 }
355 return rc;
356 }
357
358 static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
359
360 static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
361 char *buf, u16 len)
362 {
363 int rc = -EINVAL;
364
365 switch (msg_type) {
366 case ISCSI_UEVENT_PATH_UPDATE: {
367 struct cnic_local *cp;
368 u32 l5_cid;
369 struct cnic_sock *csk;
370 struct iscsi_path *path_resp;
371
372 if (len < sizeof(*path_resp))
373 break;
374
375 path_resp = (struct iscsi_path *) buf;
376 cp = dev->cnic_priv;
377 l5_cid = (u32) path_resp->handle;
378 if (l5_cid >= MAX_CM_SK_TBL_SZ)
379 break;
380
381 rcu_read_lock();
382 if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
383 rc = -ENODEV;
384 rcu_read_unlock();
385 break;
386 }
387 csk = &cp->csk_tbl[l5_cid];
388 csk_hold(csk);
389 if (cnic_in_use(csk) &&
390 test_bit(SK_F_CONNECT_START, &csk->flags)) {
391
392 csk->vlan_id = path_resp->vlan_id;
393
394 memcpy(csk->ha, path_resp->mac_addr, 6);
395 if (test_bit(SK_F_IPV6, &csk->flags))
396 memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
397 sizeof(struct in6_addr));
398 else
399 memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
400 sizeof(struct in_addr));
401
402 if (is_valid_ether_addr(csk->ha)) {
403 cnic_cm_set_pg(csk);
404 } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
405 !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
406
407 cnic_cm_upcall(cp, csk,
408 L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
409 clear_bit(SK_F_CONNECT_START, &csk->flags);
410 }
411 }
412 csk_put(csk);
413 rcu_read_unlock();
414 rc = 0;
415 }
416 }
417
418 return rc;
419 }
420
421 static int cnic_offld_prep(struct cnic_sock *csk)
422 {
423 if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
424 return 0;
425
426 if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
427 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
428 return 0;
429 }
430
431 return 1;
432 }
433
434 static int cnic_close_prep(struct cnic_sock *csk)
435 {
436 clear_bit(SK_F_CONNECT_START, &csk->flags);
437 smp_mb__after_clear_bit();
438
439 if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
440 while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
441 msleep(1);
442
443 return 1;
444 }
445 return 0;
446 }
447
448 static int cnic_abort_prep(struct cnic_sock *csk)
449 {
450 clear_bit(SK_F_CONNECT_START, &csk->flags);
451 smp_mb__after_clear_bit();
452
453 while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
454 msleep(1);
455
456 if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
457 csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
458 return 1;
459 }
460
461 return 0;
462 }
463
464 int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
465 {
466 struct cnic_dev *dev;
467
468 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
469 pr_err("%s: Bad type %d\n", __func__, ulp_type);
470 return -EINVAL;
471 }
472 mutex_lock(&cnic_lock);
473 if (cnic_ulp_tbl_prot(ulp_type)) {
474 pr_err("%s: Type %d has already been registered\n",
475 __func__, ulp_type);
476 mutex_unlock(&cnic_lock);
477 return -EBUSY;
478 }
479
480 read_lock(&cnic_dev_lock);
481 list_for_each_entry(dev, &cnic_dev_list, list) {
482 struct cnic_local *cp = dev->cnic_priv;
483
484 clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
485 }
486 read_unlock(&cnic_dev_lock);
487
488 atomic_set(&ulp_ops->ref_count, 0);
489 rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
490 mutex_unlock(&cnic_lock);
491
492 /* Prevent race conditions with netdev_event */
493 rtnl_lock();
494 list_for_each_entry(dev, &cnic_dev_list, list) {
495 struct cnic_local *cp = dev->cnic_priv;
496
497 if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
498 ulp_ops->cnic_init(dev);
499 }
500 rtnl_unlock();
501
502 return 0;
503 }
504
505 int cnic_unregister_driver(int ulp_type)
506 {
507 struct cnic_dev *dev;
508 struct cnic_ulp_ops *ulp_ops;
509 int i = 0;
510
511 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
512 pr_err("%s: Bad type %d\n", __func__, ulp_type);
513 return -EINVAL;
514 }
515 mutex_lock(&cnic_lock);
516 ulp_ops = cnic_ulp_tbl_prot(ulp_type);
517 if (!ulp_ops) {
518 pr_err("%s: Type %d has not been registered\n",
519 __func__, ulp_type);
520 goto out_unlock;
521 }
522 read_lock(&cnic_dev_lock);
523 list_for_each_entry(dev, &cnic_dev_list, list) {
524 struct cnic_local *cp = dev->cnic_priv;
525
526 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
527 pr_err("%s: Type %d still has devices registered\n",
528 __func__, ulp_type);
529 read_unlock(&cnic_dev_lock);
530 goto out_unlock;
531 }
532 }
533 read_unlock(&cnic_dev_lock);
534
535 RCU_INIT_POINTER(cnic_ulp_tbl[ulp_type], NULL);
536
537 mutex_unlock(&cnic_lock);
538 synchronize_rcu();
539 while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
540 msleep(100);
541 i++;
542 }
543
544 if (atomic_read(&ulp_ops->ref_count) != 0)
545 pr_warn("%s: Failed waiting for ref count to go to zero\n",
546 __func__);
547 return 0;
548
549 out_unlock:
550 mutex_unlock(&cnic_lock);
551 return -EINVAL;
552 }
553
554 static int cnic_start_hw(struct cnic_dev *);
555 static void cnic_stop_hw(struct cnic_dev *);
556
557 static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
558 void *ulp_ctx)
559 {
560 struct cnic_local *cp = dev->cnic_priv;
561 struct cnic_ulp_ops *ulp_ops;
562
563 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
564 pr_err("%s: Bad type %d\n", __func__, ulp_type);
565 return -EINVAL;
566 }
567 mutex_lock(&cnic_lock);
568 if (cnic_ulp_tbl_prot(ulp_type) == NULL) {
569 pr_err("%s: Driver with type %d has not been registered\n",
570 __func__, ulp_type);
571 mutex_unlock(&cnic_lock);
572 return -EAGAIN;
573 }
574 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
575 pr_err("%s: Type %d has already been registered to this device\n",
576 __func__, ulp_type);
577 mutex_unlock(&cnic_lock);
578 return -EBUSY;
579 }
580
581 clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
582 cp->ulp_handle[ulp_type] = ulp_ctx;
583 ulp_ops = cnic_ulp_tbl_prot(ulp_type);
584 rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
585 cnic_hold(dev);
586
587 if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
588 if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
589 ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
590
591 mutex_unlock(&cnic_lock);
592
593 cnic_ulp_ctl(dev, ulp_type, true);
594
595 return 0;
596
597 }
598 EXPORT_SYMBOL(cnic_register_driver);
599
600 static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
601 {
602 struct cnic_local *cp = dev->cnic_priv;
603 int i = 0;
604
605 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
606 pr_err("%s: Bad type %d\n", __func__, ulp_type);
607 return -EINVAL;
608 }
609 mutex_lock(&cnic_lock);
610 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
611 RCU_INIT_POINTER(cp->ulp_ops[ulp_type], NULL);
612 cnic_put(dev);
613 } else {
614 pr_err("%s: device not registered to this ulp type %d\n",
615 __func__, ulp_type);
616 mutex_unlock(&cnic_lock);
617 return -EINVAL;
618 }
619 mutex_unlock(&cnic_lock);
620
621 if (ulp_type == CNIC_ULP_ISCSI)
622 cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
623 else if (ulp_type == CNIC_ULP_FCOE)
624 dev->fcoe_cap = NULL;
625
626 synchronize_rcu();
627
628 while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
629 i < 20) {
630 msleep(100);
631 i++;
632 }
633 if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
634 netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
635
636 cnic_ulp_ctl(dev, ulp_type, false);
637
638 return 0;
639 }
640 EXPORT_SYMBOL(cnic_unregister_driver);
641
642 static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id,
643 u32 next)
644 {
645 id_tbl->start = start_id;
646 id_tbl->max = size;
647 id_tbl->next = next;
648 spin_lock_init(&id_tbl->lock);
649 id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
650 if (!id_tbl->table)
651 return -ENOMEM;
652
653 return 0;
654 }
655
656 static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
657 {
658 kfree(id_tbl->table);
659 id_tbl->table = NULL;
660 }
661
662 static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
663 {
664 int ret = -1;
665
666 id -= id_tbl->start;
667 if (id >= id_tbl->max)
668 return ret;
669
670 spin_lock(&id_tbl->lock);
671 if (!test_bit(id, id_tbl->table)) {
672 set_bit(id, id_tbl->table);
673 ret = 0;
674 }
675 spin_unlock(&id_tbl->lock);
676 return ret;
677 }
678
679 /* Returns -1 if not successful */
680 static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
681 {
682 u32 id;
683
684 spin_lock(&id_tbl->lock);
685 id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
686 if (id >= id_tbl->max) {
687 id = -1;
688 if (id_tbl->next != 0) {
689 id = find_first_zero_bit(id_tbl->table, id_tbl->next);
690 if (id >= id_tbl->next)
691 id = -1;
692 }
693 }
694
695 if (id < id_tbl->max) {
696 set_bit(id, id_tbl->table);
697 id_tbl->next = (id + 1) & (id_tbl->max - 1);
698 id += id_tbl->start;
699 }
700
701 spin_unlock(&id_tbl->lock);
702
703 return id;
704 }
705
706 static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
707 {
708 if (id == -1)
709 return;
710
711 id -= id_tbl->start;
712 if (id >= id_tbl->max)
713 return;
714
715 clear_bit(id, id_tbl->table);
716 }
717
718 static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
719 {
720 int i;
721
722 if (!dma->pg_arr)
723 return;
724
725 for (i = 0; i < dma->num_pages; i++) {
726 if (dma->pg_arr[i]) {
727 dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
728 dma->pg_arr[i], dma->pg_map_arr[i]);
729 dma->pg_arr[i] = NULL;
730 }
731 }
732 if (dma->pgtbl) {
733 dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
734 dma->pgtbl, dma->pgtbl_map);
735 dma->pgtbl = NULL;
736 }
737 kfree(dma->pg_arr);
738 dma->pg_arr = NULL;
739 dma->num_pages = 0;
740 }
741
742 static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
743 {
744 int i;
745 __le32 *page_table = (__le32 *) dma->pgtbl;
746
747 for (i = 0; i < dma->num_pages; i++) {
748 /* Each entry needs to be in big endian format. */
749 *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
750 page_table++;
751 *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
752 page_table++;
753 }
754 }
755
756 static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
757 {
758 int i;
759 __le32 *page_table = (__le32 *) dma->pgtbl;
760
761 for (i = 0; i < dma->num_pages; i++) {
762 /* Each entry needs to be in little endian format. */
763 *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
764 page_table++;
765 *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
766 page_table++;
767 }
768 }
769
770 static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
771 int pages, int use_pg_tbl)
772 {
773 int i, size;
774 struct cnic_local *cp = dev->cnic_priv;
775
776 size = pages * (sizeof(void *) + sizeof(dma_addr_t));
777 dma->pg_arr = kzalloc(size, GFP_ATOMIC);
778 if (dma->pg_arr == NULL)
779 return -ENOMEM;
780
781 dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
782 dma->num_pages = pages;
783
784 for (i = 0; i < pages; i++) {
785 dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
786 BCM_PAGE_SIZE,
787 &dma->pg_map_arr[i],
788 GFP_ATOMIC);
789 if (dma->pg_arr[i] == NULL)
790 goto error;
791 }
792 if (!use_pg_tbl)
793 return 0;
794
795 dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
796 ~(BCM_PAGE_SIZE - 1);
797 dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
798 &dma->pgtbl_map, GFP_ATOMIC);
799 if (dma->pgtbl == NULL)
800 goto error;
801
802 cp->setup_pgtbl(dev, dma);
803
804 return 0;
805
806 error:
807 cnic_free_dma(dev, dma);
808 return -ENOMEM;
809 }
810
811 static void cnic_free_context(struct cnic_dev *dev)
812 {
813 struct cnic_local *cp = dev->cnic_priv;
814 int i;
815
816 for (i = 0; i < cp->ctx_blks; i++) {
817 if (cp->ctx_arr[i].ctx) {
818 dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
819 cp->ctx_arr[i].ctx,
820 cp->ctx_arr[i].mapping);
821 cp->ctx_arr[i].ctx = NULL;
822 }
823 }
824 }
825
826 static void __cnic_free_uio_rings(struct cnic_uio_dev *udev)
827 {
828 if (udev->l2_buf) {
829 dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
830 udev->l2_buf, udev->l2_buf_map);
831 udev->l2_buf = NULL;
832 }
833
834 if (udev->l2_ring) {
835 dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
836 udev->l2_ring, udev->l2_ring_map);
837 udev->l2_ring = NULL;
838 }
839
840 }
841
842 static void __cnic_free_uio(struct cnic_uio_dev *udev)
843 {
844 uio_unregister_device(&udev->cnic_uinfo);
845
846 __cnic_free_uio_rings(udev);
847
848 pci_dev_put(udev->pdev);
849 kfree(udev);
850 }
851
852 static void cnic_free_uio(struct cnic_uio_dev *udev)
853 {
854 if (!udev)
855 return;
856
857 write_lock(&cnic_dev_lock);
858 list_del_init(&udev->list);
859 write_unlock(&cnic_dev_lock);
860 __cnic_free_uio(udev);
861 }
862
863 static void cnic_free_resc(struct cnic_dev *dev)
864 {
865 struct cnic_local *cp = dev->cnic_priv;
866 struct cnic_uio_dev *udev = cp->udev;
867
868 if (udev) {
869 udev->dev = NULL;
870 cp->udev = NULL;
871 if (udev->uio_dev == -1)
872 __cnic_free_uio_rings(udev);
873 }
874
875 cnic_free_context(dev);
876 kfree(cp->ctx_arr);
877 cp->ctx_arr = NULL;
878 cp->ctx_blks = 0;
879
880 cnic_free_dma(dev, &cp->gbl_buf_info);
881 cnic_free_dma(dev, &cp->kwq_info);
882 cnic_free_dma(dev, &cp->kwq_16_data_info);
883 cnic_free_dma(dev, &cp->kcq2.dma);
884 cnic_free_dma(dev, &cp->kcq1.dma);
885 kfree(cp->iscsi_tbl);
886 cp->iscsi_tbl = NULL;
887 kfree(cp->ctx_tbl);
888 cp->ctx_tbl = NULL;
889
890 cnic_free_id_tbl(&cp->fcoe_cid_tbl);
891 cnic_free_id_tbl(&cp->cid_tbl);
892 }
893
894 static int cnic_alloc_context(struct cnic_dev *dev)
895 {
896 struct cnic_local *cp = dev->cnic_priv;
897
898 if (CHIP_NUM(cp) == CHIP_NUM_5709) {
899 int i, k, arr_size;
900
901 cp->ctx_blk_size = BCM_PAGE_SIZE;
902 cp->cids_per_blk = BCM_PAGE_SIZE / 128;
903 arr_size = BNX2_MAX_CID / cp->cids_per_blk *
904 sizeof(struct cnic_ctx);
905 cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
906 if (cp->ctx_arr == NULL)
907 return -ENOMEM;
908
909 k = 0;
910 for (i = 0; i < 2; i++) {
911 u32 j, reg, off, lo, hi;
912
913 if (i == 0)
914 off = BNX2_PG_CTX_MAP;
915 else
916 off = BNX2_ISCSI_CTX_MAP;
917
918 reg = cnic_reg_rd_ind(dev, off);
919 lo = reg >> 16;
920 hi = reg & 0xffff;
921 for (j = lo; j < hi; j += cp->cids_per_blk, k++)
922 cp->ctx_arr[k].cid = j;
923 }
924
925 cp->ctx_blks = k;
926 if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
927 cp->ctx_blks = 0;
928 return -ENOMEM;
929 }
930
931 for (i = 0; i < cp->ctx_blks; i++) {
932 cp->ctx_arr[i].ctx =
933 dma_alloc_coherent(&dev->pcidev->dev,
934 BCM_PAGE_SIZE,
935 &cp->ctx_arr[i].mapping,
936 GFP_KERNEL);
937 if (cp->ctx_arr[i].ctx == NULL)
938 return -ENOMEM;
939 }
940 }
941 return 0;
942 }
943
944 static u16 cnic_bnx2_next_idx(u16 idx)
945 {
946 return idx + 1;
947 }
948
949 static u16 cnic_bnx2_hw_idx(u16 idx)
950 {
951 return idx;
952 }
953
954 static u16 cnic_bnx2x_next_idx(u16 idx)
955 {
956 idx++;
957 if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
958 idx++;
959
960 return idx;
961 }
962
963 static u16 cnic_bnx2x_hw_idx(u16 idx)
964 {
965 if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
966 idx++;
967 return idx;
968 }
969
970 static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info,
971 bool use_pg_tbl)
972 {
973 int err, i, use_page_tbl = 0;
974 struct kcqe **kcq;
975
976 if (use_pg_tbl)
977 use_page_tbl = 1;
978
979 err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, use_page_tbl);
980 if (err)
981 return err;
982
983 kcq = (struct kcqe **) info->dma.pg_arr;
984 info->kcq = kcq;
985
986 info->next_idx = cnic_bnx2_next_idx;
987 info->hw_idx = cnic_bnx2_hw_idx;
988 if (use_pg_tbl)
989 return 0;
990
991 info->next_idx = cnic_bnx2x_next_idx;
992 info->hw_idx = cnic_bnx2x_hw_idx;
993
994 for (i = 0; i < KCQ_PAGE_CNT; i++) {
995 struct bnx2x_bd_chain_next *next =
996 (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
997 int j = i + 1;
998
999 if (j >= KCQ_PAGE_CNT)
1000 j = 0;
1001 next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
1002 next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
1003 }
1004 return 0;
1005 }
1006
1007 static int __cnic_alloc_uio_rings(struct cnic_uio_dev *udev, int pages)
1008 {
1009 struct cnic_local *cp = udev->dev->cnic_priv;
1010
1011 if (udev->l2_ring)
1012 return 0;
1013
1014 udev->l2_ring_size = pages * BCM_PAGE_SIZE;
1015 udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
1016 &udev->l2_ring_map,
1017 GFP_KERNEL | __GFP_COMP);
1018 if (!udev->l2_ring)
1019 return -ENOMEM;
1020
1021 udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
1022 udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
1023 udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
1024 &udev->l2_buf_map,
1025 GFP_KERNEL | __GFP_COMP);
1026 if (!udev->l2_buf) {
1027 __cnic_free_uio_rings(udev);
1028 return -ENOMEM;
1029 }
1030
1031 return 0;
1032
1033 }
1034
1035 static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
1036 {
1037 struct cnic_local *cp = dev->cnic_priv;
1038 struct cnic_uio_dev *udev;
1039
1040 read_lock(&cnic_dev_lock);
1041 list_for_each_entry(udev, &cnic_udev_list, list) {
1042 if (udev->pdev == dev->pcidev) {
1043 udev->dev = dev;
1044 if (__cnic_alloc_uio_rings(udev, pages)) {
1045 udev->dev = NULL;
1046 read_unlock(&cnic_dev_lock);
1047 return -ENOMEM;
1048 }
1049 cp->udev = udev;
1050 read_unlock(&cnic_dev_lock);
1051 return 0;
1052 }
1053 }
1054 read_unlock(&cnic_dev_lock);
1055
1056 udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
1057 if (!udev)
1058 return -ENOMEM;
1059
1060 udev->uio_dev = -1;
1061
1062 udev->dev = dev;
1063 udev->pdev = dev->pcidev;
1064
1065 if (__cnic_alloc_uio_rings(udev, pages))
1066 goto err_udev;
1067
1068 write_lock(&cnic_dev_lock);
1069 list_add(&udev->list, &cnic_udev_list);
1070 write_unlock(&cnic_dev_lock);
1071
1072 pci_dev_get(udev->pdev);
1073
1074 cp->udev = udev;
1075
1076 return 0;
1077
1078 err_udev:
1079 kfree(udev);
1080 return -ENOMEM;
1081 }
1082
1083 static int cnic_init_uio(struct cnic_dev *dev)
1084 {
1085 struct cnic_local *cp = dev->cnic_priv;
1086 struct cnic_uio_dev *udev = cp->udev;
1087 struct uio_info *uinfo;
1088 int ret = 0;
1089
1090 if (!udev)
1091 return -ENOMEM;
1092
1093 uinfo = &udev->cnic_uinfo;
1094
1095 uinfo->mem[0].addr = pci_resource_start(dev->pcidev, 0);
1096 uinfo->mem[0].internal_addr = dev->regview;
1097 uinfo->mem[0].memtype = UIO_MEM_PHYS;
1098
1099 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
1100 uinfo->mem[0].size = MB_GET_CID_ADDR(TX_TSS_CID +
1101 TX_MAX_TSS_RINGS + 1);
1102 uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
1103 PAGE_MASK;
1104 if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
1105 uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
1106 else
1107 uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
1108
1109 uinfo->name = "bnx2_cnic";
1110 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
1111 uinfo->mem[0].size = pci_resource_len(dev->pcidev, 0);
1112
1113 uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
1114 PAGE_MASK;
1115 uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
1116
1117 uinfo->name = "bnx2x_cnic";
1118 }
1119
1120 uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
1121
1122 uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
1123 uinfo->mem[2].size = udev->l2_ring_size;
1124 uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
1125
1126 uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
1127 uinfo->mem[3].size = udev->l2_buf_size;
1128 uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
1129
1130 uinfo->version = CNIC_MODULE_VERSION;
1131 uinfo->irq = UIO_IRQ_CUSTOM;
1132
1133 uinfo->open = cnic_uio_open;
1134 uinfo->release = cnic_uio_close;
1135
1136 if (udev->uio_dev == -1) {
1137 if (!uinfo->priv) {
1138 uinfo->priv = udev;
1139
1140 ret = uio_register_device(&udev->pdev->dev, uinfo);
1141 }
1142 } else {
1143 cnic_init_rings(dev);
1144 }
1145
1146 return ret;
1147 }
1148
1149 static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
1150 {
1151 struct cnic_local *cp = dev->cnic_priv;
1152 int ret;
1153
1154 ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
1155 if (ret)
1156 goto error;
1157 cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
1158
1159 ret = cnic_alloc_kcq(dev, &cp->kcq1, true);
1160 if (ret)
1161 goto error;
1162
1163 ret = cnic_alloc_context(dev);
1164 if (ret)
1165 goto error;
1166
1167 ret = cnic_alloc_uio_rings(dev, 2);
1168 if (ret)
1169 goto error;
1170
1171 ret = cnic_init_uio(dev);
1172 if (ret)
1173 goto error;
1174
1175 return 0;
1176
1177 error:
1178 cnic_free_resc(dev);
1179 return ret;
1180 }
1181
1182 static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
1183 {
1184 struct cnic_local *cp = dev->cnic_priv;
1185 int ctx_blk_size = cp->ethdev->ctx_blk_size;
1186 int total_mem, blks, i;
1187
1188 total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
1189 blks = total_mem / ctx_blk_size;
1190 if (total_mem % ctx_blk_size)
1191 blks++;
1192
1193 if (blks > cp->ethdev->ctx_tbl_len)
1194 return -ENOMEM;
1195
1196 cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
1197 if (cp->ctx_arr == NULL)
1198 return -ENOMEM;
1199
1200 cp->ctx_blks = blks;
1201 cp->ctx_blk_size = ctx_blk_size;
1202 if (!BNX2X_CHIP_IS_57710(cp->chip_id))
1203 cp->ctx_align = 0;
1204 else
1205 cp->ctx_align = ctx_blk_size;
1206
1207 cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
1208
1209 for (i = 0; i < blks; i++) {
1210 cp->ctx_arr[i].ctx =
1211 dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
1212 &cp->ctx_arr[i].mapping,
1213 GFP_KERNEL);
1214 if (cp->ctx_arr[i].ctx == NULL)
1215 return -ENOMEM;
1216
1217 if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
1218 if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
1219 cnic_free_context(dev);
1220 cp->ctx_blk_size += cp->ctx_align;
1221 i = -1;
1222 continue;
1223 }
1224 }
1225 }
1226 return 0;
1227 }
1228
1229 static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
1230 {
1231 struct cnic_local *cp = dev->cnic_priv;
1232 struct cnic_eth_dev *ethdev = cp->ethdev;
1233 u32 start_cid = ethdev->starting_cid;
1234 int i, j, n, ret, pages;
1235 struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
1236
1237 cp->iro_arr = ethdev->iro_arr;
1238
1239 cp->max_cid_space = MAX_ISCSI_TBL_SZ;
1240 cp->iscsi_start_cid = start_cid;
1241 cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
1242
1243 if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
1244 cp->max_cid_space += dev->max_fcoe_conn;
1245 cp->fcoe_init_cid = ethdev->fcoe_init_cid;
1246 if (!cp->fcoe_init_cid)
1247 cp->fcoe_init_cid = 0x10;
1248 }
1249
1250 cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
1251 GFP_KERNEL);
1252 if (!cp->iscsi_tbl)
1253 goto error;
1254
1255 cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
1256 cp->max_cid_space, GFP_KERNEL);
1257 if (!cp->ctx_tbl)
1258 goto error;
1259
1260 for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
1261 cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
1262 cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
1263 }
1264
1265 for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
1266 cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
1267
1268 pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
1269 PAGE_SIZE;
1270
1271 ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
1272 if (ret)
1273 return -ENOMEM;
1274
1275 n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
1276 for (i = 0, j = 0; i < cp->max_cid_space; i++) {
1277 long off = CNIC_KWQ16_DATA_SIZE * (i % n);
1278
1279 cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
1280 cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
1281 off;
1282
1283 if ((i % n) == (n - 1))
1284 j++;
1285 }
1286
1287 ret = cnic_alloc_kcq(dev, &cp->kcq1, false);
1288 if (ret)
1289 goto error;
1290
1291 if (CNIC_SUPPORTS_FCOE(cp)) {
1292 ret = cnic_alloc_kcq(dev, &cp->kcq2, true);
1293 if (ret)
1294 goto error;
1295 }
1296
1297 pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
1298 ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
1299 if (ret)
1300 goto error;
1301
1302 ret = cnic_alloc_bnx2x_context(dev);
1303 if (ret)
1304 goto error;
1305
1306 if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
1307 return 0;
1308
1309 cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
1310
1311 cp->l2_rx_ring_size = 15;
1312
1313 ret = cnic_alloc_uio_rings(dev, 4);
1314 if (ret)
1315 goto error;
1316
1317 ret = cnic_init_uio(dev);
1318 if (ret)
1319 goto error;
1320
1321 return 0;
1322
1323 error:
1324 cnic_free_resc(dev);
1325 return -ENOMEM;
1326 }
1327
1328 static inline u32 cnic_kwq_avail(struct cnic_local *cp)
1329 {
1330 return cp->max_kwq_idx -
1331 ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
1332 }
1333
1334 static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
1335 u32 num_wqes)
1336 {
1337 struct cnic_local *cp = dev->cnic_priv;
1338 struct kwqe *prod_qe;
1339 u16 prod, sw_prod, i;
1340
1341 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
1342 return -EAGAIN; /* bnx2 is down */
1343
1344 spin_lock_bh(&cp->cnic_ulp_lock);
1345 if (num_wqes > cnic_kwq_avail(cp) &&
1346 !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
1347 spin_unlock_bh(&cp->cnic_ulp_lock);
1348 return -EAGAIN;
1349 }
1350
1351 clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
1352
1353 prod = cp->kwq_prod_idx;
1354 sw_prod = prod & MAX_KWQ_IDX;
1355 for (i = 0; i < num_wqes; i++) {
1356 prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
1357 memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
1358 prod++;
1359 sw_prod = prod & MAX_KWQ_IDX;
1360 }
1361 cp->kwq_prod_idx = prod;
1362
1363 CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
1364
1365 spin_unlock_bh(&cp->cnic_ulp_lock);
1366 return 0;
1367 }
1368
1369 static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
1370 union l5cm_specific_data *l5_data)
1371 {
1372 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1373 dma_addr_t map;
1374
1375 map = ctx->kwqe_data_mapping;
1376 l5_data->phy_address.lo = (u64) map & 0xffffffff;
1377 l5_data->phy_address.hi = (u64) map >> 32;
1378 return ctx->kwqe_data;
1379 }
1380
1381 static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
1382 u32 type, union l5cm_specific_data *l5_data)
1383 {
1384 struct cnic_local *cp = dev->cnic_priv;
1385 struct l5cm_spe kwqe;
1386 struct kwqe_16 *kwq[1];
1387 u16 type_16;
1388 int ret;
1389
1390 kwqe.hdr.conn_and_cmd_data =
1391 cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
1392 BNX2X_HW_CID(cp, cid)));
1393
1394 type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1395 type_16 |= (cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
1396 SPE_HDR_FUNCTION_ID;
1397
1398 kwqe.hdr.type = cpu_to_le16(type_16);
1399 kwqe.hdr.reserved1 = 0;
1400 kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
1401 kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
1402
1403 kwq[0] = (struct kwqe_16 *) &kwqe;
1404
1405 spin_lock_bh(&cp->cnic_ulp_lock);
1406 ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
1407 spin_unlock_bh(&cp->cnic_ulp_lock);
1408
1409 if (ret == 1)
1410 return 0;
1411
1412 return ret;
1413 }
1414
1415 static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
1416 struct kcqe *cqes[], u32 num_cqes)
1417 {
1418 struct cnic_local *cp = dev->cnic_priv;
1419 struct cnic_ulp_ops *ulp_ops;
1420
1421 rcu_read_lock();
1422 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
1423 if (likely(ulp_ops)) {
1424 ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
1425 cqes, num_cqes);
1426 }
1427 rcu_read_unlock();
1428 }
1429
1430 static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
1431 {
1432 struct cnic_local *cp = dev->cnic_priv;
1433 struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
1434 int hq_bds, pages;
1435 u32 pfid = cp->pfid;
1436
1437 cp->num_iscsi_tasks = req1->num_tasks_per_conn;
1438 cp->num_ccells = req1->num_ccells_per_conn;
1439 cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
1440 cp->num_iscsi_tasks;
1441 cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
1442 BNX2X_ISCSI_R2TQE_SIZE;
1443 cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
1444 pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
1445 hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
1446 cp->num_cqs = req1->num_cqs;
1447
1448 if (!dev->max_iscsi_conn)
1449 return 0;
1450
1451 /* init Tstorm RAM */
1452 CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
1453 req1->rq_num_wqes);
1454 CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1455 PAGE_SIZE);
1456 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1457 TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
1458 CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
1459 TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1460 req1->num_tasks_per_conn);
1461
1462 /* init Ustorm RAM */
1463 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1464 USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
1465 req1->rq_buffer_size);
1466 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1467 PAGE_SIZE);
1468 CNIC_WR8(dev, BAR_USTRORM_INTMEM +
1469 USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
1470 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1471 USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1472 req1->num_tasks_per_conn);
1473 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
1474 req1->rq_num_wqes);
1475 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
1476 req1->cq_num_wqes);
1477 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
1478 cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
1479
1480 /* init Xstorm RAM */
1481 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1482 PAGE_SIZE);
1483 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1484 XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
1485 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
1486 XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1487 req1->num_tasks_per_conn);
1488 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
1489 hq_bds);
1490 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
1491 req1->num_tasks_per_conn);
1492 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
1493 cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
1494
1495 /* init Cstorm RAM */
1496 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1497 PAGE_SIZE);
1498 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
1499 CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
1500 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
1501 CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1502 req1->num_tasks_per_conn);
1503 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
1504 req1->cq_num_wqes);
1505 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
1506 hq_bds);
1507
1508 return 0;
1509 }
1510
1511 static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
1512 {
1513 struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
1514 struct cnic_local *cp = dev->cnic_priv;
1515 u32 pfid = cp->pfid;
1516 struct iscsi_kcqe kcqe;
1517 struct kcqe *cqes[1];
1518
1519 memset(&kcqe, 0, sizeof(kcqe));
1520 if (!dev->max_iscsi_conn) {
1521 kcqe.completion_status =
1522 ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
1523 goto done;
1524 }
1525
1526 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
1527 TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
1528 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
1529 TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
1530 req2->error_bit_map[1]);
1531
1532 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1533 USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
1534 CNIC_WR(dev, BAR_USTRORM_INTMEM +
1535 USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
1536 CNIC_WR(dev, BAR_USTRORM_INTMEM +
1537 USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
1538 req2->error_bit_map[1]);
1539
1540 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
1541 CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
1542
1543 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1544
1545 done:
1546 kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
1547 cqes[0] = (struct kcqe *) &kcqe;
1548 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1549
1550 return 0;
1551 }
1552
1553 static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
1554 {
1555 struct cnic_local *cp = dev->cnic_priv;
1556 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1557
1558 if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
1559 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1560
1561 cnic_free_dma(dev, &iscsi->hq_info);
1562 cnic_free_dma(dev, &iscsi->r2tq_info);
1563 cnic_free_dma(dev, &iscsi->task_array_info);
1564 cnic_free_id(&cp->cid_tbl, ctx->cid);
1565 } else {
1566 cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
1567 }
1568
1569 ctx->cid = 0;
1570 }
1571
1572 static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
1573 {
1574 u32 cid;
1575 int ret, pages;
1576 struct cnic_local *cp = dev->cnic_priv;
1577 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1578 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1579
1580 if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
1581 cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
1582 if (cid == -1) {
1583 ret = -ENOMEM;
1584 goto error;
1585 }
1586 ctx->cid = cid;
1587 return 0;
1588 }
1589
1590 cid = cnic_alloc_new_id(&cp->cid_tbl);
1591 if (cid == -1) {
1592 ret = -ENOMEM;
1593 goto error;
1594 }
1595
1596 ctx->cid = cid;
1597 pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
1598
1599 ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
1600 if (ret)
1601 goto error;
1602
1603 pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
1604 ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
1605 if (ret)
1606 goto error;
1607
1608 pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
1609 ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
1610 if (ret)
1611 goto error;
1612
1613 return 0;
1614
1615 error:
1616 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1617 return ret;
1618 }
1619
1620 static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
1621 struct regpair *ctx_addr)
1622 {
1623 struct cnic_local *cp = dev->cnic_priv;
1624 struct cnic_eth_dev *ethdev = cp->ethdev;
1625 int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
1626 int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
1627 unsigned long align_off = 0;
1628 dma_addr_t ctx_map;
1629 void *ctx;
1630
1631 if (cp->ctx_align) {
1632 unsigned long mask = cp->ctx_align - 1;
1633
1634 if (cp->ctx_arr[blk].mapping & mask)
1635 align_off = cp->ctx_align -
1636 (cp->ctx_arr[blk].mapping & mask);
1637 }
1638 ctx_map = cp->ctx_arr[blk].mapping + align_off +
1639 (off * BNX2X_CONTEXT_MEM_SIZE);
1640 ctx = cp->ctx_arr[blk].ctx + align_off +
1641 (off * BNX2X_CONTEXT_MEM_SIZE);
1642 if (init)
1643 memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
1644
1645 ctx_addr->lo = ctx_map & 0xffffffff;
1646 ctx_addr->hi = (u64) ctx_map >> 32;
1647 return ctx;
1648 }
1649
1650 static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
1651 u32 num)
1652 {
1653 struct cnic_local *cp = dev->cnic_priv;
1654 struct iscsi_kwqe_conn_offload1 *req1 =
1655 (struct iscsi_kwqe_conn_offload1 *) wqes[0];
1656 struct iscsi_kwqe_conn_offload2 *req2 =
1657 (struct iscsi_kwqe_conn_offload2 *) wqes[1];
1658 struct iscsi_kwqe_conn_offload3 *req3;
1659 struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
1660 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1661 u32 cid = ctx->cid;
1662 u32 hw_cid = BNX2X_HW_CID(cp, cid);
1663 struct iscsi_context *ictx;
1664 struct regpair context_addr;
1665 int i, j, n = 2, n_max;
1666 u8 port = CNIC_PORT(cp);
1667
1668 ctx->ctx_flags = 0;
1669 if (!req2->num_additional_wqes)
1670 return -EINVAL;
1671
1672 n_max = req2->num_additional_wqes + 2;
1673
1674 ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
1675 if (ictx == NULL)
1676 return -ENOMEM;
1677
1678 req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
1679
1680 ictx->xstorm_ag_context.hq_prod = 1;
1681
1682 ictx->xstorm_st_context.iscsi.first_burst_length =
1683 ISCSI_DEF_FIRST_BURST_LEN;
1684 ictx->xstorm_st_context.iscsi.max_send_pdu_length =
1685 ISCSI_DEF_MAX_RECV_SEG_LEN;
1686 ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
1687 req1->sq_page_table_addr_lo;
1688 ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
1689 req1->sq_page_table_addr_hi;
1690 ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
1691 ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
1692 ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
1693 iscsi->hq_info.pgtbl_map & 0xffffffff;
1694 ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
1695 (u64) iscsi->hq_info.pgtbl_map >> 32;
1696 ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
1697 iscsi->hq_info.pgtbl[0];
1698 ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
1699 iscsi->hq_info.pgtbl[1];
1700 ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
1701 iscsi->r2tq_info.pgtbl_map & 0xffffffff;
1702 ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
1703 (u64) iscsi->r2tq_info.pgtbl_map >> 32;
1704 ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
1705 iscsi->r2tq_info.pgtbl[0];
1706 ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
1707 iscsi->r2tq_info.pgtbl[1];
1708 ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
1709 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1710 ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
1711 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1712 ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
1713 BNX2X_ISCSI_PBL_NOT_CACHED;
1714 ictx->xstorm_st_context.iscsi.flags.flags |=
1715 XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
1716 ictx->xstorm_st_context.iscsi.flags.flags |=
1717 XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
1718 ictx->xstorm_st_context.common.ethernet.reserved_vlan_type =
1719 ETH_P_8021Q;
1720 if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) &&
1721 cp->port_mode == CHIP_2_PORT_MODE) {
1722
1723 port = 0;
1724 }
1725 ictx->xstorm_st_context.common.flags =
1726 1 << XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT;
1727 ictx->xstorm_st_context.common.flags =
1728 port << XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT;
1729
1730 ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
1731 /* TSTORM requires the base address of RQ DB & not PTE */
1732 ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
1733 req2->rq_page_table_addr_lo & PAGE_MASK;
1734 ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
1735 req2->rq_page_table_addr_hi;
1736 ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
1737 ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
1738 ictx->tstorm_st_context.tcp.flags2 |=
1739 TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
1740 ictx->tstorm_st_context.tcp.ooo_support_mode =
1741 TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
1742
1743 ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
1744
1745 ictx->ustorm_st_context.ring.rq.pbl_base.lo =
1746 req2->rq_page_table_addr_lo;
1747 ictx->ustorm_st_context.ring.rq.pbl_base.hi =
1748 req2->rq_page_table_addr_hi;
1749 ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
1750 ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
1751 ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
1752 iscsi->r2tq_info.pgtbl_map & 0xffffffff;
1753 ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
1754 (u64) iscsi->r2tq_info.pgtbl_map >> 32;
1755 ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
1756 iscsi->r2tq_info.pgtbl[0];
1757 ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
1758 iscsi->r2tq_info.pgtbl[1];
1759 ictx->ustorm_st_context.ring.cq_pbl_base.lo =
1760 req1->cq_page_table_addr_lo;
1761 ictx->ustorm_st_context.ring.cq_pbl_base.hi =
1762 req1->cq_page_table_addr_hi;
1763 ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
1764 ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
1765 ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
1766 ictx->ustorm_st_context.task_pbe_cache_index =
1767 BNX2X_ISCSI_PBL_NOT_CACHED;
1768 ictx->ustorm_st_context.task_pdu_cache_index =
1769 BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
1770
1771 for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
1772 if (j == 3) {
1773 if (n >= n_max)
1774 break;
1775 req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
1776 j = 0;
1777 }
1778 ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
1779 ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
1780 req3->qp_first_pte[j].hi;
1781 ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
1782 req3->qp_first_pte[j].lo;
1783 }
1784
1785 ictx->ustorm_st_context.task_pbl_base.lo =
1786 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1787 ictx->ustorm_st_context.task_pbl_base.hi =
1788 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1789 ictx->ustorm_st_context.tce_phy_addr.lo =
1790 iscsi->task_array_info.pgtbl[0];
1791 ictx->ustorm_st_context.tce_phy_addr.hi =
1792 iscsi->task_array_info.pgtbl[1];
1793 ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
1794 ictx->ustorm_st_context.num_cqs = cp->num_cqs;
1795 ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
1796 ictx->ustorm_st_context.negotiated_rx_and_flags |=
1797 ISCSI_DEF_MAX_BURST_LEN;
1798 ictx->ustorm_st_context.negotiated_rx |=
1799 ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
1800 USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
1801
1802 ictx->cstorm_st_context.hq_pbl_base.lo =
1803 iscsi->hq_info.pgtbl_map & 0xffffffff;
1804 ictx->cstorm_st_context.hq_pbl_base.hi =
1805 (u64) iscsi->hq_info.pgtbl_map >> 32;
1806 ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
1807 ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
1808 ictx->cstorm_st_context.task_pbl_base.lo =
1809 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1810 ictx->cstorm_st_context.task_pbl_base.hi =
1811 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1812 /* CSTORM and USTORM initialization is different, CSTORM requires
1813 * CQ DB base & not PTE addr */
1814 ictx->cstorm_st_context.cq_db_base.lo =
1815 req1->cq_page_table_addr_lo & PAGE_MASK;
1816 ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
1817 ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
1818 ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
1819 for (i = 0; i < cp->num_cqs; i++) {
1820 ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
1821 ISCSI_INITIAL_SN;
1822 ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
1823 ISCSI_INITIAL_SN;
1824 }
1825
1826 ictx->xstorm_ag_context.cdu_reserved =
1827 CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
1828 ISCSI_CONNECTION_TYPE);
1829 ictx->ustorm_ag_context.cdu_usage =
1830 CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
1831 ISCSI_CONNECTION_TYPE);
1832 return 0;
1833
1834 }
1835
1836 static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
1837 u32 num, int *work)
1838 {
1839 struct iscsi_kwqe_conn_offload1 *req1;
1840 struct iscsi_kwqe_conn_offload2 *req2;
1841 struct cnic_local *cp = dev->cnic_priv;
1842 struct cnic_context *ctx;
1843 struct iscsi_kcqe kcqe;
1844 struct kcqe *cqes[1];
1845 u32 l5_cid;
1846 int ret = 0;
1847
1848 if (num < 2) {
1849 *work = num;
1850 return -EINVAL;
1851 }
1852
1853 req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
1854 req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
1855 if ((num - 2) < req2->num_additional_wqes) {
1856 *work = num;
1857 return -EINVAL;
1858 }
1859 *work = 2 + req2->num_additional_wqes;
1860
1861 l5_cid = req1->iscsi_conn_id;
1862 if (l5_cid >= MAX_ISCSI_TBL_SZ)
1863 return -EINVAL;
1864
1865 memset(&kcqe, 0, sizeof(kcqe));
1866 kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
1867 kcqe.iscsi_conn_id = l5_cid;
1868 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
1869
1870 ctx = &cp->ctx_tbl[l5_cid];
1871 if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
1872 kcqe.completion_status =
1873 ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
1874 goto done;
1875 }
1876
1877 if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
1878 atomic_dec(&cp->iscsi_conn);
1879 goto done;
1880 }
1881 ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
1882 if (ret) {
1883 atomic_dec(&cp->iscsi_conn);
1884 ret = 0;
1885 goto done;
1886 }
1887 ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
1888 if (ret < 0) {
1889 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1890 atomic_dec(&cp->iscsi_conn);
1891 goto done;
1892 }
1893
1894 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1895 kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
1896
1897 done:
1898 cqes[0] = (struct kcqe *) &kcqe;
1899 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1900 return 0;
1901 }
1902
1903
1904 static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
1905 {
1906 struct cnic_local *cp = dev->cnic_priv;
1907 struct iscsi_kwqe_conn_update *req =
1908 (struct iscsi_kwqe_conn_update *) kwqe;
1909 void *data;
1910 union l5cm_specific_data l5_data;
1911 u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
1912 int ret;
1913
1914 if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
1915 return -EINVAL;
1916
1917 data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
1918 if (!data)
1919 return -ENOMEM;
1920
1921 memcpy(data, kwqe, sizeof(struct kwqe));
1922
1923 ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
1924 req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
1925 return ret;
1926 }
1927
1928 static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
1929 {
1930 struct cnic_local *cp = dev->cnic_priv;
1931 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1932 union l5cm_specific_data l5_data;
1933 int ret;
1934 u32 hw_cid;
1935
1936 init_waitqueue_head(&ctx->waitq);
1937 ctx->wait_cond = 0;
1938 memset(&l5_data, 0, sizeof(l5_data));
1939 hw_cid = BNX2X_HW_CID(cp, ctx->cid);
1940
1941 ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
1942 hw_cid, NONE_CONNECTION_TYPE, &l5_data);
1943
1944 if (ret == 0) {
1945 wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
1946 if (unlikely(test_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags)))
1947 return -EBUSY;
1948 }
1949
1950 return 0;
1951 }
1952
1953 static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
1954 {
1955 struct cnic_local *cp = dev->cnic_priv;
1956 struct iscsi_kwqe_conn_destroy *req =
1957 (struct iscsi_kwqe_conn_destroy *) kwqe;
1958 u32 l5_cid = req->reserved0;
1959 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1960 int ret = 0;
1961 struct iscsi_kcqe kcqe;
1962 struct kcqe *cqes[1];
1963
1964 if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
1965 goto skip_cfc_delete;
1966
1967 if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
1968 unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
1969
1970 if (delta > (2 * HZ))
1971 delta = 0;
1972
1973 set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
1974 queue_delayed_work(cnic_wq, &cp->delete_task, delta);
1975 goto destroy_reply;
1976 }
1977
1978 ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
1979
1980 skip_cfc_delete:
1981 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1982
1983 if (!ret) {
1984 atomic_dec(&cp->iscsi_conn);
1985 clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
1986 }
1987
1988 destroy_reply:
1989 memset(&kcqe, 0, sizeof(kcqe));
1990 kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
1991 kcqe.iscsi_conn_id = l5_cid;
1992 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1993 kcqe.iscsi_conn_context_id = req->context_id;
1994
1995 cqes[0] = (struct kcqe *) &kcqe;
1996 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1997
1998 return 0;
1999 }
2000
2001 static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
2002 struct l4_kwq_connect_req1 *kwqe1,
2003 struct l4_kwq_connect_req3 *kwqe3,
2004 struct l5cm_active_conn_buffer *conn_buf)
2005 {
2006 struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
2007 struct l5cm_xstorm_conn_buffer *xstorm_buf =
2008 &conn_buf->xstorm_conn_buffer;
2009 struct l5cm_tstorm_conn_buffer *tstorm_buf =
2010 &conn_buf->tstorm_conn_buffer;
2011 struct regpair context_addr;
2012 u32 cid = BNX2X_SW_CID(kwqe1->cid);
2013 struct in6_addr src_ip, dst_ip;
2014 int i;
2015 u32 *addrp;
2016
2017 addrp = (u32 *) &conn_addr->local_ip_addr;
2018 for (i = 0; i < 4; i++, addrp++)
2019 src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
2020
2021 addrp = (u32 *) &conn_addr->remote_ip_addr;
2022 for (i = 0; i < 4; i++, addrp++)
2023 dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
2024
2025 cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
2026
2027 xstorm_buf->context_addr.hi = context_addr.hi;
2028 xstorm_buf->context_addr.lo = context_addr.lo;
2029 xstorm_buf->mss = 0xffff;
2030 xstorm_buf->rcv_buf = kwqe3->rcv_buf;
2031 if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
2032 xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
2033 xstorm_buf->pseudo_header_checksum =
2034 swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
2035
2036 if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
2037 tstorm_buf->params |=
2038 L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
2039 if (kwqe3->ka_timeout) {
2040 tstorm_buf->ka_enable = 1;
2041 tstorm_buf->ka_timeout = kwqe3->ka_timeout;
2042 tstorm_buf->ka_interval = kwqe3->ka_interval;
2043 tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
2044 }
2045 tstorm_buf->max_rt_time = 0xffffffff;
2046 }
2047
2048 static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
2049 {
2050 struct cnic_local *cp = dev->cnic_priv;
2051 u32 pfid = cp->pfid;
2052 u8 *mac = dev->mac_addr;
2053
2054 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
2055 XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
2056 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
2057 XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
2058 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
2059 XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
2060 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
2061 XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
2062 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
2063 XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
2064 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
2065 XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
2066
2067 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
2068 TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
2069 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
2070 TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
2071 mac[4]);
2072 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
2073 TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
2074 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
2075 TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
2076 mac[2]);
2077 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
2078 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[1]);
2079 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
2080 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
2081 mac[0]);
2082 }
2083
2084 static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
2085 {
2086 struct cnic_local *cp = dev->cnic_priv;
2087 u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
2088 u16 tstorm_flags = 0;
2089
2090 if (tcp_ts) {
2091 xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
2092 tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
2093 }
2094
2095 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
2096 XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
2097
2098 CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
2099 TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
2100 }
2101
2102 static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
2103 u32 num, int *work)
2104 {
2105 struct cnic_local *cp = dev->cnic_priv;
2106 struct l4_kwq_connect_req1 *kwqe1 =
2107 (struct l4_kwq_connect_req1 *) wqes[0];
2108 struct l4_kwq_connect_req3 *kwqe3;
2109 struct l5cm_active_conn_buffer *conn_buf;
2110 struct l5cm_conn_addr_params *conn_addr;
2111 union l5cm_specific_data l5_data;
2112 u32 l5_cid = kwqe1->pg_cid;
2113 struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
2114 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
2115 int ret;
2116
2117 if (num < 2) {
2118 *work = num;
2119 return -EINVAL;
2120 }
2121
2122 if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
2123 *work = 3;
2124 else
2125 *work = 2;
2126
2127 if (num < *work) {
2128 *work = num;
2129 return -EINVAL;
2130 }
2131
2132 if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
2133 netdev_err(dev->netdev, "conn_buf size too big\n");
2134 return -ENOMEM;
2135 }
2136 conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
2137 if (!conn_buf)
2138 return -ENOMEM;
2139
2140 memset(conn_buf, 0, sizeof(*conn_buf));
2141
2142 conn_addr = &conn_buf->conn_addr_buf;
2143 conn_addr->remote_addr_0 = csk->ha[0];
2144 conn_addr->remote_addr_1 = csk->ha[1];
2145 conn_addr->remote_addr_2 = csk->ha[2];
2146 conn_addr->remote_addr_3 = csk->ha[3];
2147 conn_addr->remote_addr_4 = csk->ha[4];
2148 conn_addr->remote_addr_5 = csk->ha[5];
2149
2150 if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
2151 struct l4_kwq_connect_req2 *kwqe2 =
2152 (struct l4_kwq_connect_req2 *) wqes[1];
2153
2154 conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
2155 conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
2156 conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
2157
2158 conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
2159 conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
2160 conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
2161 conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
2162 }
2163 kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
2164
2165 conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
2166 conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
2167 conn_addr->local_tcp_port = kwqe1->src_port;
2168 conn_addr->remote_tcp_port = kwqe1->dst_port;
2169
2170 conn_addr->pmtu = kwqe3->pmtu;
2171 cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
2172
2173 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
2174 XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
2175
2176 cnic_bnx2x_set_tcp_timestamp(dev,
2177 kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
2178
2179 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
2180 kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
2181 if (!ret)
2182 set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
2183
2184 return ret;
2185 }
2186
2187 static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
2188 {
2189 struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
2190 union l5cm_specific_data l5_data;
2191 int ret;
2192
2193 memset(&l5_data, 0, sizeof(l5_data));
2194 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
2195 req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
2196 return ret;
2197 }
2198
2199 static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
2200 {
2201 struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
2202 union l5cm_specific_data l5_data;
2203 int ret;
2204
2205 memset(&l5_data, 0, sizeof(l5_data));
2206 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
2207 req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
2208 return ret;
2209 }
2210 static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
2211 {
2212 struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
2213 struct l4_kcq kcqe;
2214 struct kcqe *cqes[1];
2215
2216 memset(&kcqe, 0, sizeof(kcqe));
2217 kcqe.pg_host_opaque = req->host_opaque;
2218 kcqe.pg_cid = req->host_opaque;
2219 kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
2220 cqes[0] = (struct kcqe *) &kcqe;
2221 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
2222 return 0;
2223 }
2224
2225 static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
2226 {
2227 struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
2228 struct l4_kcq kcqe;
2229 struct kcqe *cqes[1];
2230
2231 memset(&kcqe, 0, sizeof(kcqe));
2232 kcqe.pg_host_opaque = req->pg_host_opaque;
2233 kcqe.pg_cid = req->pg_cid;
2234 kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
2235 cqes[0] = (struct kcqe *) &kcqe;
2236 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
2237 return 0;
2238 }
2239
2240 static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
2241 {
2242 struct fcoe_kwqe_stat *req;
2243 struct fcoe_stat_ramrod_params *fcoe_stat;
2244 union l5cm_specific_data l5_data;
2245 struct cnic_local *cp = dev->cnic_priv;
2246 int ret;
2247 u32 cid;
2248
2249 req = (struct fcoe_kwqe_stat *) kwqe;
2250 cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
2251
2252 fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
2253 if (!fcoe_stat)
2254 return -ENOMEM;
2255
2256 memset(fcoe_stat, 0, sizeof(*fcoe_stat));
2257 memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
2258
2259 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT_FUNC, cid,
2260 FCOE_CONNECTION_TYPE, &l5_data);
2261 return ret;
2262 }
2263
2264 static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
2265 u32 num, int *work)
2266 {
2267 int ret;
2268 struct cnic_local *cp = dev->cnic_priv;
2269 u32 cid;
2270 struct fcoe_init_ramrod_params *fcoe_init;
2271 struct fcoe_kwqe_init1 *req1;
2272 struct fcoe_kwqe_init2 *req2;
2273 struct fcoe_kwqe_init3 *req3;
2274 union l5cm_specific_data l5_data;
2275
2276 if (num < 3) {
2277 *work = num;
2278 return -EINVAL;
2279 }
2280 req1 = (struct fcoe_kwqe_init1 *) wqes[0];
2281 req2 = (struct fcoe_kwqe_init2 *) wqes[1];
2282 req3 = (struct fcoe_kwqe_init3 *) wqes[2];
2283 if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
2284 *work = 1;
2285 return -EINVAL;
2286 }
2287 if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
2288 *work = 2;
2289 return -EINVAL;
2290 }
2291
2292 if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
2293 netdev_err(dev->netdev, "fcoe_init size too big\n");
2294 return -ENOMEM;
2295 }
2296 fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
2297 if (!fcoe_init)
2298 return -ENOMEM;
2299
2300 memset(fcoe_init, 0, sizeof(*fcoe_init));
2301 memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
2302 memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
2303 memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
2304 fcoe_init->eq_pbl_base.lo = cp->kcq2.dma.pgtbl_map & 0xffffffff;
2305 fcoe_init->eq_pbl_base.hi = (u64) cp->kcq2.dma.pgtbl_map >> 32;
2306 fcoe_init->eq_pbl_size = cp->kcq2.dma.num_pages;
2307
2308 fcoe_init->sb_num = cp->status_blk_num;
2309 fcoe_init->eq_prod = MAX_KCQ_IDX;
2310 fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
2311 cp->kcq2.sw_prod_idx = 0;
2312
2313 cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
2314 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT_FUNC, cid,
2315 FCOE_CONNECTION_TYPE, &l5_data);
2316 *work = 3;
2317 return ret;
2318 }
2319
2320 static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
2321 u32 num, int *work)
2322 {
2323 int ret = 0;
2324 u32 cid = -1, l5_cid;
2325 struct cnic_local *cp = dev->cnic_priv;
2326 struct fcoe_kwqe_conn_offload1 *req1;
2327 struct fcoe_kwqe_conn_offload2 *req2;
2328 struct fcoe_kwqe_conn_offload3 *req3;
2329 struct fcoe_kwqe_conn_offload4 *req4;
2330 struct fcoe_conn_offload_ramrod_params *fcoe_offload;
2331 struct cnic_context *ctx;
2332 struct fcoe_context *fctx;
2333 struct regpair ctx_addr;
2334 union l5cm_specific_data l5_data;
2335 struct fcoe_kcqe kcqe;
2336 struct kcqe *cqes[1];
2337
2338 if (num < 4) {
2339 *work = num;
2340 return -EINVAL;
2341 }
2342 req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
2343 req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
2344 req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
2345 req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
2346
2347 *work = 4;
2348
2349 l5_cid = req1->fcoe_conn_id;
2350 if (l5_cid >= dev->max_fcoe_conn)
2351 goto err_reply;
2352
2353 l5_cid += BNX2X_FCOE_L5_CID_BASE;
2354
2355 ctx = &cp->ctx_tbl[l5_cid];
2356 if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
2357 goto err_reply;
2358
2359 ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
2360 if (ret) {
2361 ret = 0;
2362 goto err_reply;
2363 }
2364 cid = ctx->cid;
2365
2366 fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
2367 if (fctx) {
2368 u32 hw_cid = BNX2X_HW_CID(cp, cid);
2369 u32 val;
2370
2371 val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
2372 FCOE_CONNECTION_TYPE);
2373 fctx->xstorm_ag_context.cdu_reserved = val;
2374 val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
2375 FCOE_CONNECTION_TYPE);
2376 fctx->ustorm_ag_context.cdu_usage = val;
2377 }
2378 if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
2379 netdev_err(dev->netdev, "fcoe_offload size too big\n");
2380 goto err_reply;
2381 }
2382 fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
2383 if (!fcoe_offload)
2384 goto err_reply;
2385
2386 memset(fcoe_offload, 0, sizeof(*fcoe_offload));
2387 memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
2388 memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
2389 memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
2390 memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
2391
2392 cid = BNX2X_HW_CID(cp, cid);
2393 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
2394 FCOE_CONNECTION_TYPE, &l5_data);
2395 if (!ret)
2396 set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
2397
2398 return ret;
2399
2400 err_reply:
2401 if (cid != -1)
2402 cnic_free_bnx2x_conn_resc(dev, l5_cid);
2403
2404 memset(&kcqe, 0, sizeof(kcqe));
2405 kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
2406 kcqe.fcoe_conn_id = req1->fcoe_conn_id;
2407 kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
2408
2409 cqes[0] = (struct kcqe *) &kcqe;
2410 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
2411 return ret;
2412 }
2413
2414 static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
2415 {
2416 struct fcoe_kwqe_conn_enable_disable *req;
2417 struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
2418 union l5cm_specific_data l5_data;
2419 int ret;
2420 u32 cid, l5_cid;
2421 struct cnic_local *cp = dev->cnic_priv;
2422
2423 req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
2424 cid = req->context_id;
2425 l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
2426
2427 if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
2428 netdev_err(dev->netdev, "fcoe_enable size too big\n");
2429 return -ENOMEM;
2430 }
2431 fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
2432 if (!fcoe_enable)
2433 return -ENOMEM;
2434
2435 memset(fcoe_enable, 0, sizeof(*fcoe_enable));
2436 memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
2437 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
2438 FCOE_CONNECTION_TYPE, &l5_data);
2439 return ret;
2440 }
2441
2442 static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
2443 {
2444 struct fcoe_kwqe_conn_enable_disable *req;
2445 struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
2446 union l5cm_specific_data l5_data;
2447 int ret;
2448 u32 cid, l5_cid;
2449 struct cnic_local *cp = dev->cnic_priv;
2450
2451 req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
2452 cid = req->context_id;
2453 l5_cid = req->conn_id;
2454 if (l5_cid >= dev->max_fcoe_conn)
2455 return -EINVAL;
2456
2457 l5_cid += BNX2X_FCOE_L5_CID_BASE;
2458
2459 if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
2460 netdev_err(dev->netdev, "fcoe_disable size too big\n");
2461 return -ENOMEM;
2462 }
2463 fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
2464 if (!fcoe_disable)
2465 return -ENOMEM;
2466
2467 memset(fcoe_disable, 0, sizeof(*fcoe_disable));
2468 memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
2469 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
2470 FCOE_CONNECTION_TYPE, &l5_data);
2471 return ret;
2472 }
2473
2474 static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
2475 {
2476 struct fcoe_kwqe_conn_destroy *req;
2477 union l5cm_specific_data l5_data;
2478 int ret;
2479 u32 cid, l5_cid;
2480 struct cnic_local *cp = dev->cnic_priv;
2481 struct cnic_context *ctx;
2482 struct fcoe_kcqe kcqe;
2483 struct kcqe *cqes[1];
2484
2485 req = (struct fcoe_kwqe_conn_destroy *) kwqe;
2486 cid = req->context_id;
2487 l5_cid = req->conn_id;
2488 if (l5_cid >= dev->max_fcoe_conn)
2489 return -EINVAL;
2490
2491 l5_cid += BNX2X_FCOE_L5_CID_BASE;
2492
2493 ctx = &cp->ctx_tbl[l5_cid];
2494
2495 init_waitqueue_head(&ctx->waitq);
2496 ctx->wait_cond = 0;
2497
2498 memset(&kcqe, 0, sizeof(kcqe));
2499 kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_ERROR;
2500 memset(&l5_data, 0, sizeof(l5_data));
2501 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
2502 FCOE_CONNECTION_TYPE, &l5_data);
2503 if (ret == 0) {
2504 wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
2505 if (ctx->wait_cond)
2506 kcqe.completion_status = 0;
2507 }
2508
2509 set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
2510 queue_delayed_work(cnic_wq, &cp->delete_task, msecs_to_jiffies(2000));
2511
2512 kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
2513 kcqe.fcoe_conn_id = req->conn_id;
2514 kcqe.fcoe_conn_context_id = cid;
2515
2516 cqes[0] = (struct kcqe *) &kcqe;
2517 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
2518 return ret;
2519 }
2520
2521 static void cnic_bnx2x_delete_wait(struct cnic_dev *dev, u32 start_cid)
2522 {
2523 struct cnic_local *cp = dev->cnic_priv;
2524 u32 i;
2525
2526 for (i = start_cid; i < cp->max_cid_space; i++) {
2527 struct cnic_context *ctx = &cp->ctx_tbl[i];
2528 int j;
2529
2530 while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
2531 msleep(10);
2532
2533 for (j = 0; j < 5; j++) {
2534 if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
2535 break;
2536 msleep(20);
2537 }
2538
2539 if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
2540 netdev_warn(dev->netdev, "CID %x not deleted\n",
2541 ctx->cid);
2542 }
2543 }
2544
2545 static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
2546 {
2547 struct fcoe_kwqe_destroy *req;
2548 union l5cm_specific_data l5_data;
2549 struct cnic_local *cp = dev->cnic_priv;
2550 int ret;
2551 u32 cid;
2552
2553 cnic_bnx2x_delete_wait(dev, MAX_ISCSI_TBL_SZ);
2554
2555 req = (struct fcoe_kwqe_destroy *) kwqe;
2556 cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
2557
2558 memset(&l5_data, 0, sizeof(l5_data));
2559 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY_FUNC, cid,
2560 FCOE_CONNECTION_TYPE, &l5_data);
2561 return ret;
2562 }
2563
2564 static void cnic_bnx2x_kwqe_err(struct cnic_dev *dev, struct kwqe *kwqe)
2565 {
2566 struct cnic_local *cp = dev->cnic_priv;
2567 struct kcqe kcqe;
2568 struct kcqe *cqes[1];
2569 u32 cid;
2570 u32 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
2571 u32 layer_code = kwqe->kwqe_op_flag & KWQE_LAYER_MASK;
2572 u32 kcqe_op;
2573 int ulp_type;
2574
2575 cid = kwqe->kwqe_info0;
2576 memset(&kcqe, 0, sizeof(kcqe));
2577
2578 if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_FCOE) {
2579 u32 l5_cid = 0;
2580
2581 ulp_type = CNIC_ULP_FCOE;
2582 if (opcode == FCOE_KWQE_OPCODE_DISABLE_CONN) {
2583 struct fcoe_kwqe_conn_enable_disable *req;
2584
2585 req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
2586 kcqe_op = FCOE_KCQE_OPCODE_DISABLE_CONN;
2587 cid = req->context_id;
2588 l5_cid = req->conn_id;
2589 } else if (opcode == FCOE_KWQE_OPCODE_DESTROY) {
2590 kcqe_op = FCOE_KCQE_OPCODE_DESTROY_FUNC;
2591 } else {
2592 return;
2593 }
2594 kcqe.kcqe_op_flag = kcqe_op << KCQE_FLAGS_OPCODE_SHIFT;
2595 kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_FCOE;
2596 kcqe.kcqe_info1 = FCOE_KCQE_COMPLETION_STATUS_PARITY_ERROR;
2597 kcqe.kcqe_info2 = cid;
2598 kcqe.kcqe_info0 = l5_cid;
2599
2600 } else if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_ISCSI) {
2601 ulp_type = CNIC_ULP_ISCSI;
2602 if (opcode == ISCSI_KWQE_OPCODE_UPDATE_CONN)
2603 cid = kwqe->kwqe_info1;
2604
2605 kcqe.kcqe_op_flag = (opcode + 0x10) << KCQE_FLAGS_OPCODE_SHIFT;
2606 kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_ISCSI;
2607 kcqe.kcqe_info1 = ISCSI_KCQE_COMPLETION_STATUS_PARITY_ERR;
2608 kcqe.kcqe_info2 = cid;
2609 cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &kcqe.kcqe_info0);
2610
2611 } else if (layer_code == KWQE_FLAGS_LAYER_MASK_L4) {
2612 struct l4_kcq *l4kcqe = (struct l4_kcq *) &kcqe;
2613
2614 ulp_type = CNIC_ULP_L4;
2615 if (opcode == L4_KWQE_OPCODE_VALUE_CONNECT1)
2616 kcqe_op = L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE;
2617 else if (opcode == L4_KWQE_OPCODE_VALUE_RESET)
2618 kcqe_op = L4_KCQE_OPCODE_VALUE_RESET_COMP;
2619 else if (opcode == L4_KWQE_OPCODE_VALUE_CLOSE)
2620 kcqe_op = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
2621 else
2622 return;
2623
2624 kcqe.kcqe_op_flag = (kcqe_op << KCQE_FLAGS_OPCODE_SHIFT) |
2625 KCQE_FLAGS_LAYER_MASK_L4;
2626 l4kcqe->status = L4_KCQE_COMPLETION_STATUS_PARITY_ERROR;
2627 l4kcqe->cid = cid;
2628 cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &l4kcqe->conn_id);
2629 } else {
2630 return;
2631 }
2632
2633 cqes[0] = &kcqe;
2634 cnic_reply_bnx2x_kcqes(dev, ulp_type, cqes, 1);
2635 }
2636
2637 static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
2638 struct kwqe *wqes[], u32 num_wqes)
2639 {
2640 int i, work, ret;
2641 u32 opcode;
2642 struct kwqe *kwqe;
2643
2644 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
2645 return -EAGAIN; /* bnx2 is down */
2646
2647 for (i = 0; i < num_wqes; ) {
2648 kwqe = wqes[i];
2649 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
2650 work = 1;
2651
2652 switch (opcode) {
2653 case ISCSI_KWQE_OPCODE_INIT1:
2654 ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
2655 break;
2656 case ISCSI_KWQE_OPCODE_INIT2:
2657 ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
2658 break;
2659 case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
2660 ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
2661 num_wqes - i, &work);
2662 break;
2663 case ISCSI_KWQE_OPCODE_UPDATE_CONN:
2664 ret = cnic_bnx2x_iscsi_update(dev, kwqe);
2665 break;
2666 case ISCSI_KWQE_OPCODE_DESTROY_CONN:
2667 ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
2668 break;
2669 case L4_KWQE_OPCODE_VALUE_CONNECT1:
2670 ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
2671 &work);
2672 break;
2673 case L4_KWQE_OPCODE_VALUE_CLOSE:
2674 ret = cnic_bnx2x_close(dev, kwqe);
2675 break;
2676 case L4_KWQE_OPCODE_VALUE_RESET:
2677 ret = cnic_bnx2x_reset(dev, kwqe);
2678 break;
2679 case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
2680 ret = cnic_bnx2x_offload_pg(dev, kwqe);
2681 break;
2682 case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
2683 ret = cnic_bnx2x_update_pg(dev, kwqe);
2684 break;
2685 case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
2686 ret = 0;
2687 break;
2688 default:
2689 ret = 0;
2690 netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
2691 opcode);
2692 break;
2693 }
2694 if (ret < 0) {
2695 netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
2696 opcode);
2697
2698 /* Possibly bnx2x parity error, send completion
2699 * to ulp drivers with error code to speed up
2700 * cleanup and reset recovery.
2701 */
2702 if (ret == -EIO || ret == -EAGAIN)
2703 cnic_bnx2x_kwqe_err(dev, kwqe);
2704 }
2705 i += work;
2706 }
2707 return 0;
2708 }
2709
2710 static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
2711 struct kwqe *wqes[], u32 num_wqes)
2712 {
2713 struct cnic_local *cp = dev->cnic_priv;
2714 int i, work, ret;
2715 u32 opcode;
2716 struct kwqe *kwqe;
2717
2718 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
2719 return -EAGAIN; /* bnx2 is down */
2720
2721 if (!BNX2X_CHIP_IS_E2_PLUS(cp->chip_id))
2722 return -EINVAL;
2723
2724 for (i = 0; i < num_wqes; ) {
2725 kwqe = wqes[i];
2726 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
2727 work = 1;
2728
2729 switch (opcode) {
2730 case FCOE_KWQE_OPCODE_INIT1:
2731 ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
2732 num_wqes - i, &work);
2733 break;
2734 case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
2735 ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
2736 num_wqes - i, &work);
2737 break;
2738 case FCOE_KWQE_OPCODE_ENABLE_CONN:
2739 ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
2740 break;
2741 case FCOE_KWQE_OPCODE_DISABLE_CONN:
2742 ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
2743 break;
2744 case FCOE_KWQE_OPCODE_DESTROY_CONN:
2745 ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
2746 break;
2747 case FCOE_KWQE_OPCODE_DESTROY:
2748 ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
2749 break;
2750 case FCOE_KWQE_OPCODE_STAT:
2751 ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
2752 break;
2753 default:
2754 ret = 0;
2755 netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
2756 opcode);
2757 break;
2758 }
2759 if (ret < 0) {
2760 netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
2761 opcode);
2762
2763 /* Possibly bnx2x parity error, send completion
2764 * to ulp drivers with error code to speed up
2765 * cleanup and reset recovery.
2766 */
2767 if (ret == -EIO || ret == -EAGAIN)
2768 cnic_bnx2x_kwqe_err(dev, kwqe);
2769 }
2770 i += work;
2771 }
2772 return 0;
2773 }
2774
2775 static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
2776 u32 num_wqes)
2777 {
2778 int ret = -EINVAL;
2779 u32 layer_code;
2780
2781 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
2782 return -EAGAIN; /* bnx2x is down */
2783
2784 if (!num_wqes)
2785 return 0;
2786
2787 layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
2788 switch (layer_code) {
2789 case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
2790 case KWQE_FLAGS_LAYER_MASK_L4:
2791 case KWQE_FLAGS_LAYER_MASK_L2:
2792 ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
2793 break;
2794
2795 case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
2796 ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
2797 break;
2798 }
2799 return ret;
2800 }
2801
2802 static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
2803 {
2804 if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
2805 return KCQE_FLAGS_LAYER_MASK_L4;
2806
2807 return opflag & KCQE_FLAGS_LAYER_MASK;
2808 }
2809
2810 static void service_kcqes(struct cnic_dev *dev, int num_cqes)
2811 {
2812 struct cnic_local *cp = dev->cnic_priv;
2813 int i, j, comp = 0;
2814
2815 i = 0;
2816 j = 1;
2817 while (num_cqes) {
2818 struct cnic_ulp_ops *ulp_ops;
2819 int ulp_type;
2820 u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
2821 u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
2822
2823 if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
2824 comp++;
2825
2826 while (j < num_cqes) {
2827 u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
2828
2829 if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
2830 break;
2831
2832 if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
2833 comp++;
2834 j++;
2835 }
2836
2837 if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
2838 ulp_type = CNIC_ULP_RDMA;
2839 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
2840 ulp_type = CNIC_ULP_ISCSI;
2841 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
2842 ulp_type = CNIC_ULP_FCOE;
2843 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
2844 ulp_type = CNIC_ULP_L4;
2845 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
2846 goto end;
2847 else {
2848 netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
2849 kcqe_op_flag);
2850 goto end;
2851 }
2852
2853 rcu_read_lock();
2854 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
2855 if (likely(ulp_ops)) {
2856 ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
2857 cp->completed_kcq + i, j);
2858 }
2859 rcu_read_unlock();
2860 end:
2861 num_cqes -= j;
2862 i += j;
2863 j = 1;
2864 }
2865 if (unlikely(comp))
2866 cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
2867 }
2868
2869 static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
2870 {
2871 struct cnic_local *cp = dev->cnic_priv;
2872 u16 i, ri, hw_prod, last;
2873 struct kcqe *kcqe;
2874 int kcqe_cnt = 0, last_cnt = 0;
2875
2876 i = ri = last = info->sw_prod_idx;
2877 ri &= MAX_KCQ_IDX;
2878 hw_prod = *info->hw_prod_idx_ptr;
2879 hw_prod = info->hw_idx(hw_prod);
2880
2881 while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
2882 kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
2883 cp->completed_kcq[kcqe_cnt++] = kcqe;
2884 i = info->next_idx(i);
2885 ri = i & MAX_KCQ_IDX;
2886 if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
2887 last_cnt = kcqe_cnt;
2888 last = i;
2889 }
2890 }
2891
2892 info->sw_prod_idx = last;
2893 return last_cnt;
2894 }
2895
2896 static int cnic_l2_completion(struct cnic_local *cp)
2897 {
2898 u16 hw_cons, sw_cons;
2899 struct cnic_uio_dev *udev = cp->udev;
2900 union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
2901 (udev->l2_ring + (2 * BCM_PAGE_SIZE));
2902 u32 cmd;
2903 int comp = 0;
2904
2905 if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
2906 return 0;
2907
2908 hw_cons = *cp->rx_cons_ptr;
2909 if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
2910 hw_cons++;
2911
2912 sw_cons = cp->rx_cons;
2913 while (sw_cons != hw_cons) {
2914 u8 cqe_fp_flags;
2915
2916 cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
2917 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2918 if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
2919 cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
2920 cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
2921 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
2922 cmd == RAMROD_CMD_ID_ETH_HALT)
2923 comp++;
2924 }
2925 sw_cons = BNX2X_NEXT_RCQE(sw_cons);
2926 }
2927 return comp;
2928 }
2929
2930 static void cnic_chk_pkt_rings(struct cnic_local *cp)
2931 {
2932 u16 rx_cons, tx_cons;
2933 int comp = 0;
2934
2935 if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
2936 return;
2937
2938 rx_cons = *cp->rx_cons_ptr;
2939 tx_cons = *cp->tx_cons_ptr;
2940 if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
2941 if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
2942 comp = cnic_l2_completion(cp);
2943
2944 cp->tx_cons = tx_cons;
2945 cp->rx_cons = rx_cons;
2946
2947 if (cp->udev)
2948 uio_event_notify(&cp->udev->cnic_uinfo);
2949 }
2950 if (comp)
2951 clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
2952 }
2953
2954 static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
2955 {
2956 struct cnic_local *cp = dev->cnic_priv;
2957 u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
2958 int kcqe_cnt;
2959
2960 /* status block index must be read before reading other fields */
2961 rmb();
2962 cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
2963
2964 while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
2965
2966 service_kcqes(dev, kcqe_cnt);
2967
2968 /* Tell compiler that status_blk fields can change. */
2969 barrier();
2970 status_idx = (u16) *cp->kcq1.status_idx_ptr;
2971 /* status block index must be read first */
2972 rmb();
2973 cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
2974 }
2975
2976 CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
2977
2978 cnic_chk_pkt_rings(cp);
2979
2980 return status_idx;
2981 }
2982
2983 static int cnic_service_bnx2(void *data, void *status_blk)
2984 {
2985 struct cnic_dev *dev = data;
2986
2987 if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
2988 struct status_block *sblk = status_blk;
2989
2990 return sblk->status_idx;
2991 }
2992
2993 return cnic_service_bnx2_queues(dev);
2994 }
2995
2996 static void cnic_service_bnx2_msix(unsigned long data)
2997 {
2998 struct cnic_dev *dev = (struct cnic_dev *) data;
2999 struct cnic_local *cp = dev->cnic_priv;
3000
3001 cp->last_status_idx = cnic_service_bnx2_queues(dev);
3002
3003 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
3004 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
3005 }
3006
3007 static void cnic_doirq(struct cnic_dev *dev)
3008 {
3009 struct cnic_local *cp = dev->cnic_priv;
3010
3011 if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
3012 u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
3013
3014 prefetch(cp->status_blk.gen);
3015 prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
3016
3017 tasklet_schedule(&cp->cnic_irq_task);
3018 }
3019 }
3020
3021 static irqreturn_t cnic_irq(int irq, void *dev_instance)
3022 {
3023 struct cnic_dev *dev = dev_instance;
3024 struct cnic_local *cp = dev->cnic_priv;
3025
3026 if (cp->ack_int)
3027 cp->ack_int(dev);
3028
3029 cnic_doirq(dev);
3030
3031 return IRQ_HANDLED;
3032 }
3033
3034 static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
3035 u16 index, u8 op, u8 update)
3036 {
3037 struct cnic_local *cp = dev->cnic_priv;
3038 u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
3039 COMMAND_REG_INT_ACK);
3040 struct igu_ack_register igu_ack;
3041
3042 igu_ack.status_block_index = index;
3043 igu_ack.sb_id_and_flags =
3044 ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
3045 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
3046 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
3047 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
3048
3049 CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
3050 }
3051
3052 static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
3053 u16 index, u8 op, u8 update)
3054 {
3055 struct igu_regular cmd_data;
3056 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
3057
3058 cmd_data.sb_id_and_flags =
3059 (index << IGU_REGULAR_SB_INDEX_SHIFT) |
3060 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
3061 (update << IGU_REGULAR_BUPDATE_SHIFT) |
3062 (op << IGU_REGULAR_ENABLE_INT_SHIFT);
3063
3064
3065 CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
3066 }
3067
3068 static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
3069 {
3070 struct cnic_local *cp = dev->cnic_priv;
3071
3072 cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
3073 IGU_INT_DISABLE, 0);
3074 }
3075
3076 static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
3077 {
3078 struct cnic_local *cp = dev->cnic_priv;
3079
3080 cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
3081 IGU_INT_DISABLE, 0);
3082 }
3083
3084 static void cnic_arm_bnx2x_msix(struct cnic_dev *dev, u32 idx)
3085 {
3086 struct cnic_local *cp = dev->cnic_priv;
3087
3088 cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, idx,
3089 IGU_INT_ENABLE, 1);
3090 }
3091
3092 static void cnic_arm_bnx2x_e2_msix(struct cnic_dev *dev, u32 idx)
3093 {
3094 struct cnic_local *cp = dev->cnic_priv;
3095
3096 cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, idx,
3097 IGU_INT_ENABLE, 1);
3098 }
3099
3100 static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
3101 {
3102 u32 last_status = *info->status_idx_ptr;
3103 int kcqe_cnt;
3104
3105 /* status block index must be read before reading the KCQ */
3106 rmb();
3107 while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
3108
3109 service_kcqes(dev, kcqe_cnt);
3110
3111 /* Tell compiler that sblk fields can change. */
3112 barrier();
3113
3114 last_status = *info->status_idx_ptr;
3115 /* status block index must be read before reading the KCQ */
3116 rmb();
3117 }
3118 return last_status;
3119 }
3120
3121 static void cnic_service_bnx2x_bh(unsigned long data)
3122 {
3123 struct cnic_dev *dev = (struct cnic_dev *) data;
3124 struct cnic_local *cp = dev->cnic_priv;
3125 u32 status_idx, new_status_idx;
3126
3127 if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
3128 return;
3129
3130 while (1) {
3131 status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
3132
3133 CNIC_WR16(dev, cp->kcq1.io_addr,
3134 cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
3135
3136 if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_FCOE) {
3137 cp->arm_int(dev, status_idx);
3138 break;
3139 }
3140
3141 new_status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
3142
3143 if (new_status_idx != status_idx)
3144 continue;
3145
3146 CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
3147 MAX_KCQ_IDX);
3148
3149 cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
3150 status_idx, IGU_INT_ENABLE, 1);
3151
3152 break;
3153 }
3154 }
3155
3156 static int cnic_service_bnx2x(void *data, void *status_blk)
3157 {
3158 struct cnic_dev *dev = data;
3159 struct cnic_local *cp = dev->cnic_priv;
3160
3161 if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
3162 cnic_doirq(dev);
3163
3164 cnic_chk_pkt_rings(cp);
3165
3166 return 0;
3167 }
3168
3169 static void cnic_ulp_stop_one(struct cnic_local *cp, int if_type)
3170 {
3171 struct cnic_ulp_ops *ulp_ops;
3172
3173 if (if_type == CNIC_ULP_ISCSI)
3174 cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
3175
3176 mutex_lock(&cnic_lock);
3177 ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
3178 lockdep_is_held(&cnic_lock));
3179 if (!ulp_ops) {
3180 mutex_unlock(&cnic_lock);
3181 return;
3182 }
3183 set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
3184 mutex_unlock(&cnic_lock);
3185
3186 if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
3187 ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
3188
3189 clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
3190 }
3191
3192 static void cnic_ulp_stop(struct cnic_dev *dev)
3193 {
3194 struct cnic_local *cp = dev->cnic_priv;
3195 int if_type;
3196
3197 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++)
3198 cnic_ulp_stop_one(cp, if_type);
3199 }
3200
3201 static void cnic_ulp_start(struct cnic_dev *dev)
3202 {
3203 struct cnic_local *cp = dev->cnic_priv;
3204 int if_type;
3205
3206 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
3207 struct cnic_ulp_ops *ulp_ops;
3208
3209 mutex_lock(&cnic_lock);
3210 ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
3211 lockdep_is_held(&cnic_lock));
3212 if (!ulp_ops || !ulp_ops->cnic_start) {
3213 mutex_unlock(&cnic_lock);
3214 continue;
3215 }
3216 set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
3217 mutex_unlock(&cnic_lock);
3218
3219 if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
3220 ulp_ops->cnic_start(cp->ulp_handle[if_type]);
3221
3222 clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
3223 }
3224 }
3225
3226 static int cnic_copy_ulp_stats(struct cnic_dev *dev, int ulp_type)
3227 {
3228 struct cnic_local *cp = dev->cnic_priv;
3229 struct cnic_ulp_ops *ulp_ops;
3230 int rc;
3231
3232 mutex_lock(&cnic_lock);
3233 ulp_ops = cnic_ulp_tbl_prot(ulp_type);
3234 if (ulp_ops && ulp_ops->cnic_get_stats)
3235 rc = ulp_ops->cnic_get_stats(cp->ulp_handle[ulp_type]);
3236 else
3237 rc = -ENODEV;
3238 mutex_unlock(&cnic_lock);
3239 return rc;
3240 }
3241
3242 static int cnic_ctl(void *data, struct cnic_ctl_info *info)
3243 {
3244 struct cnic_dev *dev = data;
3245 int ulp_type = CNIC_ULP_ISCSI;
3246
3247 switch (info->cmd) {
3248 case CNIC_CTL_STOP_CMD:
3249 cnic_hold(dev);
3250
3251 cnic_ulp_stop(dev);
3252 cnic_stop_hw(dev);
3253
3254 cnic_put(dev);
3255 break;
3256 case CNIC_CTL_START_CMD:
3257 cnic_hold(dev);
3258
3259 if (!cnic_start_hw(dev))
3260 cnic_ulp_start(dev);
3261
3262 cnic_put(dev);
3263 break;
3264 case CNIC_CTL_STOP_ISCSI_CMD: {
3265 struct cnic_local *cp = dev->cnic_priv;
3266 set_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags);
3267 queue_delayed_work(cnic_wq, &cp->delete_task, 0);
3268 break;
3269 }
3270 case CNIC_CTL_COMPLETION_CMD: {
3271 struct cnic_ctl_completion *comp = &info->data.comp;
3272 u32 cid = BNX2X_SW_CID(comp->cid);
3273 u32 l5_cid;
3274 struct cnic_local *cp = dev->cnic_priv;
3275
3276 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
3277 break;
3278
3279 if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
3280 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
3281
3282 if (unlikely(comp->error)) {
3283 set_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags);
3284 netdev_err(dev->netdev,
3285 "CID %x CFC delete comp error %x\n",
3286 cid, comp->error);
3287 }
3288
3289 ctx->wait_cond = 1;
3290 wake_up(&ctx->waitq);
3291 }
3292 break;
3293 }
3294 case CNIC_CTL_FCOE_STATS_GET_CMD:
3295 ulp_type = CNIC_ULP_FCOE;
3296 /* fall through */
3297 case CNIC_CTL_ISCSI_STATS_GET_CMD:
3298 cnic_hold(dev);
3299 cnic_copy_ulp_stats(dev, ulp_type);
3300 cnic_put(dev);
3301 break;
3302
3303 default:
3304 return -EINVAL;
3305 }
3306 return 0;
3307 }
3308
3309 static void cnic_ulp_init(struct cnic_dev *dev)
3310 {
3311 int i;
3312 struct cnic_local *cp = dev->cnic_priv;
3313
3314 for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
3315 struct cnic_ulp_ops *ulp_ops;
3316
3317 mutex_lock(&cnic_lock);
3318 ulp_ops = cnic_ulp_tbl_prot(i);
3319 if (!ulp_ops || !ulp_ops->cnic_init) {
3320 mutex_unlock(&cnic_lock);
3321 continue;
3322 }
3323 ulp_get(ulp_ops);
3324 mutex_unlock(&cnic_lock);
3325
3326 if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
3327 ulp_ops->cnic_init(dev);
3328
3329 ulp_put(ulp_ops);
3330 }
3331 }
3332
3333 static void cnic_ulp_exit(struct cnic_dev *dev)
3334 {
3335 int i;
3336 struct cnic_local *cp = dev->cnic_priv;
3337
3338 for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
3339 struct cnic_ulp_ops *ulp_ops;
3340
3341 mutex_lock(&cnic_lock);
3342 ulp_ops = cnic_ulp_tbl_prot(i);
3343 if (!ulp_ops || !ulp_ops->cnic_exit) {
3344 mutex_unlock(&cnic_lock);
3345 continue;
3346 }
3347 ulp_get(ulp_ops);
3348 mutex_unlock(&cnic_lock);
3349
3350 if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
3351 ulp_ops->cnic_exit(dev);
3352
3353 ulp_put(ulp_ops);
3354 }
3355 }
3356
3357 static int cnic_cm_offload_pg(struct cnic_sock *csk)
3358 {
3359 struct cnic_dev *dev = csk->dev;
3360 struct l4_kwq_offload_pg *l4kwqe;
3361 struct kwqe *wqes[1];
3362
3363 l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
3364 memset(l4kwqe, 0, sizeof(*l4kwqe));
3365 wqes[0] = (struct kwqe *) l4kwqe;
3366
3367 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
3368 l4kwqe->flags =
3369 L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
3370 l4kwqe->l2hdr_nbytes = ETH_HLEN;
3371
3372 l4kwqe->da0 = csk->ha[0];
3373 l4kwqe->da1 = csk->ha[1];
3374 l4kwqe->da2 = csk->ha[2];
3375 l4kwqe->da3 = csk->ha[3];
3376 l4kwqe->da4 = csk->ha[4];
3377 l4kwqe->da5 = csk->ha[5];
3378
3379 l4kwqe->sa0 = dev->mac_addr[0];
3380 l4kwqe->sa1 = dev->mac_addr[1];
3381 l4kwqe->sa2 = dev->mac_addr[2];
3382 l4kwqe->sa3 = dev->mac_addr[3];
3383 l4kwqe->sa4 = dev->mac_addr[4];
3384 l4kwqe->sa5 = dev->mac_addr[5];
3385
3386 l4kwqe->etype = ETH_P_IP;
3387 l4kwqe->ipid_start = DEF_IPID_START;
3388 l4kwqe->host_opaque = csk->l5_cid;
3389
3390 if (csk->vlan_id) {
3391 l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
3392 l4kwqe->vlan_tag = csk->vlan_id;
3393 l4kwqe->l2hdr_nbytes += 4;
3394 }
3395
3396 return dev->submit_kwqes(dev, wqes, 1);
3397 }
3398
3399 static int cnic_cm_update_pg(struct cnic_sock *csk)
3400 {
3401 struct cnic_dev *dev = csk->dev;
3402 struct l4_kwq_update_pg *l4kwqe;
3403 struct kwqe *wqes[1];
3404
3405 l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
3406 memset(l4kwqe, 0, sizeof(*l4kwqe));
3407 wqes[0] = (struct kwqe *) l4kwqe;
3408
3409 l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
3410 l4kwqe->flags =
3411 L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
3412 l4kwqe->pg_cid = csk->pg_cid;
3413
3414 l4kwqe->da0 = csk->ha[0];
3415 l4kwqe->da1 = csk->ha[1];
3416 l4kwqe->da2 = csk->ha[2];
3417 l4kwqe->da3 = csk->ha[3];
3418 l4kwqe->da4 = csk->ha[4];
3419 l4kwqe->da5 = csk->ha[5];
3420
3421 l4kwqe->pg_host_opaque = csk->l5_cid;
3422 l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
3423
3424 return dev->submit_kwqes(dev, wqes, 1);
3425 }
3426
3427 static int cnic_cm_upload_pg(struct cnic_sock *csk)
3428 {
3429 struct cnic_dev *dev = csk->dev;
3430 struct l4_kwq_upload *l4kwqe;
3431 struct kwqe *wqes[1];
3432
3433 l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
3434 memset(l4kwqe, 0, sizeof(*l4kwqe));
3435 wqes[0] = (struct kwqe *) l4kwqe;
3436
3437 l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
3438 l4kwqe->flags =
3439 L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
3440 l4kwqe->cid = csk->pg_cid;
3441
3442 return dev->submit_kwqes(dev, wqes, 1);
3443 }
3444
3445 static int cnic_cm_conn_req(struct cnic_sock *csk)
3446 {
3447 struct cnic_dev *dev = csk->dev;
3448 struct l4_kwq_connect_req1 *l4kwqe1;
3449 struct l4_kwq_connect_req2 *l4kwqe2;
3450 struct l4_kwq_connect_req3 *l4kwqe3;
3451 struct kwqe *wqes[3];
3452 u8 tcp_flags = 0;
3453 int num_wqes = 2;
3454
3455 l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
3456 l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
3457 l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
3458 memset(l4kwqe1, 0, sizeof(*l4kwqe1));
3459 memset(l4kwqe2, 0, sizeof(*l4kwqe2));
3460 memset(l4kwqe3, 0, sizeof(*l4kwqe3));
3461
3462 l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
3463 l4kwqe3->flags =
3464 L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
3465 l4kwqe3->ka_timeout = csk->ka_timeout;
3466 l4kwqe3->ka_interval = csk->ka_interval;
3467 l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
3468 l4kwqe3->tos = csk->tos;
3469 l4kwqe3->ttl = csk->ttl;
3470 l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
3471 l4kwqe3->pmtu = csk->mtu;
3472 l4kwqe3->rcv_buf = csk->rcv_buf;
3473 l4kwqe3->snd_buf = csk->snd_buf;
3474 l4kwqe3->seed = csk->seed;
3475
3476 wqes[0] = (struct kwqe *) l4kwqe1;
3477 if (test_bit(SK_F_IPV6, &csk->flags)) {
3478 wqes[1] = (struct kwqe *) l4kwqe2;
3479 wqes[2] = (struct kwqe *) l4kwqe3;
3480 num_wqes = 3;
3481
3482 l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
3483 l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
3484 l4kwqe2->flags =
3485 L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
3486 L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
3487 l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
3488 l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
3489 l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
3490 l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
3491 l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
3492 l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
3493 l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
3494 sizeof(struct tcphdr);
3495 } else {
3496 wqes[1] = (struct kwqe *) l4kwqe3;
3497 l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
3498 sizeof(struct tcphdr);
3499 }
3500
3501 l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
3502 l4kwqe1->flags =
3503 (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
3504 L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
3505 l4kwqe1->cid = csk->cid;
3506 l4kwqe1->pg_cid = csk->pg_cid;
3507 l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
3508 l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
3509 l4kwqe1->src_port = be16_to_cpu(csk->src_port);
3510 l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
3511 if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
3512 tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
3513 if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
3514 tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
3515 if (csk->tcp_flags & SK_TCP_NAGLE)
3516 tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
3517 if (csk->tcp_flags & SK_TCP_TIMESTAMP)
3518 tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
3519 if (csk->tcp_flags & SK_TCP_SACK)
3520 tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
3521 if (csk->tcp_flags & SK_TCP_SEG_SCALING)
3522 tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
3523
3524 l4kwqe1->tcp_flags = tcp_flags;
3525
3526 return dev->submit_kwqes(dev, wqes, num_wqes);
3527 }
3528
3529 static int cnic_cm_close_req(struct cnic_sock *csk)
3530 {
3531 struct cnic_dev *dev = csk->dev;
3532 struct l4_kwq_close_req *l4kwqe;
3533 struct kwqe *wqes[1];
3534
3535 l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
3536 memset(l4kwqe, 0, sizeof(*l4kwqe));
3537 wqes[0] = (struct kwqe *) l4kwqe;
3538
3539 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
3540 l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
3541 l4kwqe->cid = csk->cid;
3542
3543 return dev->submit_kwqes(dev, wqes, 1);
3544 }
3545
3546 static int cnic_cm_abort_req(struct cnic_sock *csk)
3547 {
3548 struct cnic_dev *dev = csk->dev;
3549 struct l4_kwq_reset_req *l4kwqe;
3550 struct kwqe *wqes[1];
3551
3552 l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
3553 memset(l4kwqe, 0, sizeof(*l4kwqe));
3554 wqes[0] = (struct kwqe *) l4kwqe;
3555
3556 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
3557 l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
3558 l4kwqe->cid = csk->cid;
3559
3560 return dev->submit_kwqes(dev, wqes, 1);
3561 }
3562
3563 static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
3564 u32 l5_cid, struct cnic_sock **csk, void *context)
3565 {
3566 struct cnic_local *cp = dev->cnic_priv;
3567 struct cnic_sock *csk1;
3568
3569 if (l5_cid >= MAX_CM_SK_TBL_SZ)
3570 return -EINVAL;
3571
3572 if (cp->ctx_tbl) {
3573 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
3574
3575 if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
3576 return -EAGAIN;
3577 }
3578
3579 csk1 = &cp->csk_tbl[l5_cid];
3580 if (atomic_read(&csk1->ref_count))
3581 return -EAGAIN;
3582
3583 if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
3584 return -EBUSY;
3585
3586 csk1->dev = dev;
3587 csk1->cid = cid;
3588 csk1->l5_cid = l5_cid;
3589 csk1->ulp_type = ulp_type;
3590 csk1->context = context;
3591
3592 csk1->ka_timeout = DEF_KA_TIMEOUT;
3593 csk1->ka_interval = DEF_KA_INTERVAL;
3594 csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
3595 csk1->tos = DEF_TOS;
3596 csk1->ttl = DEF_TTL;
3597 csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
3598 csk1->rcv_buf = DEF_RCV_BUF;
3599 csk1->snd_buf = DEF_SND_BUF;
3600 csk1->seed = DEF_SEED;
3601
3602 *csk = csk1;
3603 return 0;
3604 }
3605
3606 static void cnic_cm_cleanup(struct cnic_sock *csk)
3607 {
3608 if (csk->src_port) {
3609 struct cnic_dev *dev = csk->dev;
3610 struct cnic_local *cp = dev->cnic_priv;
3611
3612 cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
3613 csk->src_port = 0;
3614 }
3615 }
3616
3617 static void cnic_close_conn(struct cnic_sock *csk)
3618 {
3619 if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
3620 cnic_cm_upload_pg(csk);
3621 clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
3622 }
3623 cnic_cm_cleanup(csk);
3624 }
3625
3626 static int cnic_cm_destroy(struct cnic_sock *csk)
3627 {
3628 if (!cnic_in_use(csk))
3629 return -EINVAL;
3630
3631 csk_hold(csk);
3632 clear_bit(SK_F_INUSE, &csk->flags);
3633 smp_mb__after_clear_bit();
3634 while (atomic_read(&csk->ref_count) != 1)
3635 msleep(1);
3636 cnic_cm_cleanup(csk);
3637
3638 csk->flags = 0;
3639 csk_put(csk);
3640 return 0;
3641 }
3642
3643 static inline u16 cnic_get_vlan(struct net_device *dev,
3644 struct net_device **vlan_dev)
3645 {
3646 if (dev->priv_flags & IFF_802_1Q_VLAN) {
3647 *vlan_dev = vlan_dev_real_dev(dev);
3648 return vlan_dev_vlan_id(dev);
3649 }
3650 *vlan_dev = dev;
3651 return 0;
3652 }
3653
3654 static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
3655 struct dst_entry **dst)
3656 {
3657 #if defined(CONFIG_INET)
3658 struct rtable *rt;
3659
3660 rt = ip_route_output(&init_net, dst_addr->sin_addr.s_addr, 0, 0, 0);
3661 if (!IS_ERR(rt)) {
3662 *dst = &rt->dst;
3663 return 0;
3664 }
3665 return PTR_ERR(rt);
3666 #else
3667 return -ENETUNREACH;
3668 #endif
3669 }
3670
3671 static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
3672 struct dst_entry **dst)
3673 {
3674 #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
3675 struct flowi6 fl6;
3676
3677 memset(&fl6, 0, sizeof(fl6));
3678 fl6.daddr = dst_addr->sin6_addr;
3679 if (ipv6_addr_type(&fl6.daddr) & IPV6_ADDR_LINKLOCAL)
3680 fl6.flowi6_oif = dst_addr->sin6_scope_id;
3681
3682 *dst = ip6_route_output(&init_net, NULL, &fl6);
3683 if ((*dst)->error) {
3684 dst_release(*dst);
3685 *dst = NULL;
3686 return -ENETUNREACH;
3687 } else
3688 return 0;
3689 #endif
3690
3691 return -ENETUNREACH;
3692 }
3693
3694 static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
3695 int ulp_type)
3696 {
3697 struct cnic_dev *dev = NULL;
3698 struct dst_entry *dst;
3699 struct net_device *netdev = NULL;
3700 int err = -ENETUNREACH;
3701
3702 if (dst_addr->sin_family == AF_INET)
3703 err = cnic_get_v4_route(dst_addr, &dst);
3704 else if (dst_addr->sin_family == AF_INET6) {
3705 struct sockaddr_in6 *dst_addr6 =
3706 (struct sockaddr_in6 *) dst_addr;
3707
3708 err = cnic_get_v6_route(dst_addr6, &dst);
3709 } else
3710 return NULL;
3711
3712 if (err)
3713 return NULL;
3714
3715 if (!dst->dev)
3716 goto done;
3717
3718 cnic_get_vlan(dst->dev, &netdev);
3719
3720 dev = cnic_from_netdev(netdev);
3721
3722 done:
3723 dst_release(dst);
3724 if (dev)
3725 cnic_put(dev);
3726 return dev;
3727 }
3728
3729 static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
3730 {
3731 struct cnic_dev *dev = csk->dev;
3732 struct cnic_local *cp = dev->cnic_priv;
3733
3734 return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
3735 }
3736
3737 static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
3738 {
3739 struct cnic_dev *dev = csk->dev;
3740 struct cnic_local *cp = dev->cnic_priv;
3741 int is_v6, rc = 0;
3742 struct dst_entry *dst = NULL;
3743 struct net_device *realdev;
3744 __be16 local_port;
3745 u32 port_id;
3746
3747 if (saddr->local.v6.sin6_family == AF_INET6 &&
3748 saddr->remote.v6.sin6_family == AF_INET6)
3749 is_v6 = 1;
3750 else if (saddr->local.v4.sin_family == AF_INET &&
3751 saddr->remote.v4.sin_family == AF_INET)
3752 is_v6 = 0;
3753 else
3754 return -EINVAL;
3755
3756 clear_bit(SK_F_IPV6, &csk->flags);
3757
3758 if (is_v6) {
3759 set_bit(SK_F_IPV6, &csk->flags);
3760 cnic_get_v6_route(&saddr->remote.v6, &dst);
3761
3762 memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
3763 sizeof(struct in6_addr));
3764 csk->dst_port = saddr->remote.v6.sin6_port;
3765 local_port = saddr->local.v6.sin6_port;
3766
3767 } else {
3768 cnic_get_v4_route(&saddr->remote.v4, &dst);
3769
3770 csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
3771 csk->dst_port = saddr->remote.v4.sin_port;
3772 local_port = saddr->local.v4.sin_port;
3773 }
3774
3775 csk->vlan_id = 0;
3776 csk->mtu = dev->netdev->mtu;
3777 if (dst && dst->dev) {
3778 u16 vlan = cnic_get_vlan(dst->dev, &realdev);
3779 if (realdev == dev->netdev) {
3780 csk->vlan_id = vlan;
3781 csk->mtu = dst_mtu(dst);
3782 }
3783 }
3784
3785 port_id = be16_to_cpu(local_port);
3786 if (port_id >= CNIC_LOCAL_PORT_MIN &&
3787 port_id < CNIC_LOCAL_PORT_MAX) {
3788 if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
3789 port_id = 0;
3790 } else
3791 port_id = 0;
3792
3793 if (!port_id) {
3794 port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
3795 if (port_id == -1) {
3796 rc = -ENOMEM;
3797 goto err_out;
3798 }
3799 local_port = cpu_to_be16(port_id);
3800 }
3801 csk->src_port = local_port;
3802
3803 err_out:
3804 dst_release(dst);
3805 return rc;
3806 }
3807
3808 static void cnic_init_csk_state(struct cnic_sock *csk)
3809 {
3810 csk->state = 0;
3811 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3812 clear_bit(SK_F_CLOSING, &csk->flags);
3813 }
3814
3815 static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
3816 {
3817 struct cnic_local *cp = csk->dev->cnic_priv;
3818 int err = 0;
3819
3820 if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
3821 return -EOPNOTSUPP;
3822
3823 if (!cnic_in_use(csk))
3824 return -EINVAL;
3825
3826 if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
3827 return -EINVAL;
3828
3829 cnic_init_csk_state(csk);
3830
3831 err = cnic_get_route(csk, saddr);
3832 if (err)
3833 goto err_out;
3834
3835 err = cnic_resolve_addr(csk, saddr);
3836 if (!err)
3837 return 0;
3838
3839 err_out:
3840 clear_bit(SK_F_CONNECT_START, &csk->flags);
3841 return err;
3842 }
3843
3844 static int cnic_cm_abort(struct cnic_sock *csk)
3845 {
3846 struct cnic_local *cp = csk->dev->cnic_priv;
3847 u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
3848
3849 if (!cnic_in_use(csk))
3850 return -EINVAL;
3851
3852 if (cnic_abort_prep(csk))
3853 return cnic_cm_abort_req(csk);
3854
3855 /* Getting here means that we haven't started connect, or
3856 * connect was not successful, or it has been reset by the target.
3857 */
3858
3859 cp->close_conn(csk, opcode);
3860 if (csk->state != opcode) {
3861 /* Wait for remote reset sequence to complete */
3862 while (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
3863 msleep(1);
3864
3865 return -EALREADY;
3866 }
3867
3868 return 0;
3869 }
3870
3871 static int cnic_cm_close(struct cnic_sock *csk)
3872 {
3873 if (!cnic_in_use(csk))
3874 return -EINVAL;
3875
3876 if (cnic_close_prep(csk)) {
3877 csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
3878 return cnic_cm_close_req(csk);
3879 } else {
3880 /* Wait for remote reset sequence to complete */
3881 while (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
3882 msleep(1);
3883
3884 return -EALREADY;
3885 }
3886 return 0;
3887 }
3888
3889 static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
3890 u8 opcode)
3891 {
3892 struct cnic_ulp_ops *ulp_ops;
3893 int ulp_type = csk->ulp_type;
3894
3895 rcu_read_lock();
3896 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
3897 if (ulp_ops) {
3898 if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
3899 ulp_ops->cm_connect_complete(csk);
3900 else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
3901 ulp_ops->cm_close_complete(csk);
3902 else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
3903 ulp_ops->cm_remote_abort(csk);
3904 else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
3905 ulp_ops->cm_abort_complete(csk);
3906 else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
3907 ulp_ops->cm_remote_close(csk);
3908 }
3909 rcu_read_unlock();
3910 }
3911
3912 static int cnic_cm_set_pg(struct cnic_sock *csk)
3913 {
3914 if (cnic_offld_prep(csk)) {
3915 if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
3916 cnic_cm_update_pg(csk);
3917 else
3918 cnic_cm_offload_pg(csk);
3919 }
3920 return 0;
3921 }
3922
3923 static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
3924 {
3925 struct cnic_local *cp = dev->cnic_priv;
3926 u32 l5_cid = kcqe->pg_host_opaque;
3927 u8 opcode = kcqe->op_code;
3928 struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
3929
3930 csk_hold(csk);
3931 if (!cnic_in_use(csk))
3932 goto done;
3933
3934 if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
3935 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3936 goto done;
3937 }
3938 /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
3939 if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
3940 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3941 cnic_cm_upcall(cp, csk,
3942 L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
3943 goto done;
3944 }
3945
3946 csk->pg_cid = kcqe->pg_cid;
3947 set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
3948 cnic_cm_conn_req(csk);
3949
3950 done:
3951 csk_put(csk);
3952 }
3953
3954 static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
3955 {
3956 struct cnic_local *cp = dev->cnic_priv;
3957 struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
3958 u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
3959 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
3960
3961 ctx->timestamp = jiffies;
3962 ctx->wait_cond = 1;
3963 wake_up(&ctx->waitq);
3964 }
3965
3966 static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
3967 {
3968 struct cnic_local *cp = dev->cnic_priv;
3969 struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
3970 u8 opcode = l4kcqe->op_code;
3971 u32 l5_cid;
3972 struct cnic_sock *csk;
3973
3974 if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
3975 cnic_process_fcoe_term_conn(dev, kcqe);
3976 return;
3977 }
3978 if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
3979 opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
3980 cnic_cm_process_offld_pg(dev, l4kcqe);
3981 return;
3982 }
3983
3984 l5_cid = l4kcqe->conn_id;
3985 if (opcode & 0x80)
3986 l5_cid = l4kcqe->cid;
3987 if (l5_cid >= MAX_CM_SK_TBL_SZ)
3988 return;
3989
3990 csk = &cp->csk_tbl[l5_cid];
3991 csk_hold(csk);
3992
3993 if (!cnic_in_use(csk)) {
3994 csk_put(csk);
3995 return;
3996 }
3997
3998 switch (opcode) {
3999 case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
4000 if (l4kcqe->status != 0) {
4001 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
4002 cnic_cm_upcall(cp, csk,
4003 L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
4004 }
4005 break;
4006 case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
4007 if (l4kcqe->status == 0)
4008 set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
4009 else if (l4kcqe->status ==
4010 L4_KCQE_COMPLETION_STATUS_PARITY_ERROR)
4011 set_bit(SK_F_HW_ERR, &csk->flags);
4012
4013 smp_mb__before_clear_bit();
4014 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
4015 cnic_cm_upcall(cp, csk, opcode);
4016 break;
4017
4018 case L5CM_RAMROD_CMD_ID_CLOSE:
4019 if (l4kcqe->status != 0) {
4020 netdev_warn(dev->netdev, "RAMROD CLOSE compl with "
4021 "status 0x%x\n", l4kcqe->status);
4022 opcode = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
4023 /* Fall through */
4024 } else {
4025 break;
4026 }
4027 case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
4028 case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
4029 case L4_KCQE_OPCODE_VALUE_RESET_COMP:
4030 case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
4031 case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
4032 if (l4kcqe->status == L4_KCQE_COMPLETION_STATUS_PARITY_ERROR)
4033 set_bit(SK_F_HW_ERR, &csk->flags);
4034
4035 cp->close_conn(csk, opcode);
4036 break;
4037
4038 case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
4039 /* after we already sent CLOSE_REQ */
4040 if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags) &&
4041 !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags) &&
4042 csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
4043 cp->close_conn(csk, L4_KCQE_OPCODE_VALUE_RESET_COMP);
4044 else
4045 cnic_cm_upcall(cp, csk, opcode);
4046 break;
4047 }
4048 csk_put(csk);
4049 }
4050
4051 static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
4052 {
4053 struct cnic_dev *dev = data;
4054 int i;
4055
4056 for (i = 0; i < num; i++)
4057 cnic_cm_process_kcqe(dev, kcqe[i]);
4058 }
4059
4060 static struct cnic_ulp_ops cm_ulp_ops = {
4061 .indicate_kcqes = cnic_cm_indicate_kcqe,
4062 };
4063
4064 static void cnic_cm_free_mem(struct cnic_dev *dev)
4065 {
4066 struct cnic_local *cp = dev->cnic_priv;
4067
4068 kfree(cp->csk_tbl);
4069 cp->csk_tbl = NULL;
4070 cnic_free_id_tbl(&cp->csk_port_tbl);
4071 }
4072
4073 static int cnic_cm_alloc_mem(struct cnic_dev *dev)
4074 {
4075 struct cnic_local *cp = dev->cnic_priv;
4076 u32 port_id;
4077
4078 cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
4079 GFP_KERNEL);
4080 if (!cp->csk_tbl)
4081 return -ENOMEM;
4082
4083 port_id = random32();
4084 port_id %= CNIC_LOCAL_PORT_RANGE;
4085 if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
4086 CNIC_LOCAL_PORT_MIN, port_id)) {
4087 cnic_cm_free_mem(dev);
4088 return -ENOMEM;
4089 }
4090 return 0;
4091 }
4092
4093 static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
4094 {
4095 if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
4096 /* Unsolicited RESET_COMP or RESET_RECEIVED */
4097 opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
4098 csk->state = opcode;
4099 }
4100
4101 /* 1. If event opcode matches the expected event in csk->state
4102 * 2. If the expected event is CLOSE_COMP or RESET_COMP, we accept any
4103 * event
4104 * 3. If the expected event is 0, meaning the connection was never
4105 * never established, we accept the opcode from cm_abort.
4106 */
4107 if (opcode == csk->state || csk->state == 0 ||
4108 csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP ||
4109 csk->state == L4_KCQE_OPCODE_VALUE_RESET_COMP) {
4110 if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
4111 if (csk->state == 0)
4112 csk->state = opcode;
4113 return 1;
4114 }
4115 }
4116 return 0;
4117 }
4118
4119 static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
4120 {
4121 struct cnic_dev *dev = csk->dev;
4122 struct cnic_local *cp = dev->cnic_priv;
4123
4124 if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
4125 cnic_cm_upcall(cp, csk, opcode);
4126 return;
4127 }
4128
4129 clear_bit(SK_F_CONNECT_START, &csk->flags);
4130 cnic_close_conn(csk);
4131 csk->state = opcode;
4132 cnic_cm_upcall(cp, csk, opcode);
4133 }
4134
4135 static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
4136 {
4137 }
4138
4139 static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
4140 {
4141 u32 seed;
4142
4143 seed = random32();
4144 cnic_ctx_wr(dev, 45, 0, seed);
4145 return 0;
4146 }
4147
4148 static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
4149 {
4150 struct cnic_dev *dev = csk->dev;
4151 struct cnic_local *cp = dev->cnic_priv;
4152 struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
4153 union l5cm_specific_data l5_data;
4154 u32 cmd = 0;
4155 int close_complete = 0;
4156
4157 switch (opcode) {
4158 case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
4159 case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
4160 case L4_KCQE_OPCODE_VALUE_RESET_COMP:
4161 if (cnic_ready_to_close(csk, opcode)) {
4162 if (test_bit(SK_F_HW_ERR, &csk->flags))
4163 close_complete = 1;
4164 else if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
4165 cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
4166 else
4167 close_complete = 1;
4168 }
4169 break;
4170 case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
4171 cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
4172 break;
4173 case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
4174 close_complete = 1;
4175 break;
4176 }
4177 if (cmd) {
4178 memset(&l5_data, 0, sizeof(l5_data));
4179
4180 cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
4181 &l5_data);
4182 } else if (close_complete) {
4183 ctx->timestamp = jiffies;
4184 cnic_close_conn(csk);
4185 cnic_cm_upcall(cp, csk, csk->state);
4186 }
4187 }
4188
4189 static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
4190 {
4191 struct cnic_local *cp = dev->cnic_priv;
4192
4193 if (!cp->ctx_tbl)
4194 return;
4195
4196 if (!netif_running(dev->netdev))
4197 return;
4198
4199 cnic_bnx2x_delete_wait(dev, 0);
4200
4201 cancel_delayed_work(&cp->delete_task);
4202 flush_workqueue(cnic_wq);
4203
4204 if (atomic_read(&cp->iscsi_conn) != 0)
4205 netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
4206 atomic_read(&cp->iscsi_conn));
4207 }
4208
4209 static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
4210 {
4211 struct cnic_local *cp = dev->cnic_priv;
4212 u32 pfid = cp->pfid;
4213 u32 port = CNIC_PORT(cp);
4214
4215 cnic_init_bnx2x_mac(dev);
4216 cnic_bnx2x_set_tcp_timestamp(dev, 1);
4217
4218 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
4219 XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
4220
4221 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
4222 XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
4223 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
4224 XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
4225 DEF_MAX_DA_COUNT);
4226
4227 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
4228 XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
4229 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
4230 XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
4231 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
4232 XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
4233 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
4234 XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
4235
4236 CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
4237 DEF_MAX_CWND);
4238 return 0;
4239 }
4240
4241 static void cnic_delete_task(struct work_struct *work)
4242 {
4243 struct cnic_local *cp;
4244 struct cnic_dev *dev;
4245 u32 i;
4246 int need_resched = 0;
4247
4248 cp = container_of(work, struct cnic_local, delete_task.work);
4249 dev = cp->dev;
4250
4251 if (test_and_clear_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags)) {
4252 struct drv_ctl_info info;
4253
4254 cnic_ulp_stop_one(cp, CNIC_ULP_ISCSI);
4255
4256 info.cmd = DRV_CTL_ISCSI_STOPPED_CMD;
4257 cp->ethdev->drv_ctl(dev->netdev, &info);
4258 }
4259
4260 for (i = 0; i < cp->max_cid_space; i++) {
4261 struct cnic_context *ctx = &cp->ctx_tbl[i];
4262 int err;
4263
4264 if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
4265 !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
4266 continue;
4267
4268 if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
4269 need_resched = 1;
4270 continue;
4271 }
4272
4273 if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
4274 continue;
4275
4276 err = cnic_bnx2x_destroy_ramrod(dev, i);
4277
4278 cnic_free_bnx2x_conn_resc(dev, i);
4279 if (!err) {
4280 if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
4281 atomic_dec(&cp->iscsi_conn);
4282
4283 clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
4284 }
4285 }
4286
4287 if (need_resched)
4288 queue_delayed_work(cnic_wq, &cp->delete_task,
4289 msecs_to_jiffies(10));
4290
4291 }
4292
4293 static int cnic_cm_open(struct cnic_dev *dev)
4294 {
4295 struct cnic_local *cp = dev->cnic_priv;
4296 int err;
4297
4298 err = cnic_cm_alloc_mem(dev);
4299 if (err)
4300 return err;
4301
4302 err = cp->start_cm(dev);
4303
4304 if (err)
4305 goto err_out;
4306
4307 INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
4308
4309 dev->cm_create = cnic_cm_create;
4310 dev->cm_destroy = cnic_cm_destroy;
4311 dev->cm_connect = cnic_cm_connect;
4312 dev->cm_abort = cnic_cm_abort;
4313 dev->cm_close = cnic_cm_close;
4314 dev->cm_select_dev = cnic_cm_select_dev;
4315
4316 cp->ulp_handle[CNIC_ULP_L4] = dev;
4317 rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
4318 return 0;
4319
4320 err_out:
4321 cnic_cm_free_mem(dev);
4322 return err;
4323 }
4324
4325 static int cnic_cm_shutdown(struct cnic_dev *dev)
4326 {
4327 struct cnic_local *cp = dev->cnic_priv;
4328 int i;
4329
4330 if (!cp->csk_tbl)
4331 return 0;
4332
4333 for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
4334 struct cnic_sock *csk = &cp->csk_tbl[i];
4335
4336 clear_bit(SK_F_INUSE, &csk->flags);
4337 cnic_cm_cleanup(csk);
4338 }
4339 cnic_cm_free_mem(dev);
4340
4341 return 0;
4342 }
4343
4344 static void cnic_init_context(struct cnic_dev *dev, u32 cid)
4345 {
4346 u32 cid_addr;
4347 int i;
4348
4349 cid_addr = GET_CID_ADDR(cid);
4350
4351 for (i = 0; i < CTX_SIZE; i += 4)
4352 cnic_ctx_wr(dev, cid_addr, i, 0);
4353 }
4354
4355 static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
4356 {
4357 struct cnic_local *cp = dev->cnic_priv;
4358 int ret = 0, i;
4359 u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
4360
4361 if (CHIP_NUM(cp) != CHIP_NUM_5709)
4362 return 0;
4363
4364 for (i = 0; i < cp->ctx_blks; i++) {
4365 int j;
4366 u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
4367 u32 val;
4368
4369 memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
4370
4371 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
4372 (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
4373 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
4374 (u64) cp->ctx_arr[i].mapping >> 32);
4375 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
4376 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
4377 for (j = 0; j < 10; j++) {
4378
4379 val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
4380 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
4381 break;
4382 udelay(5);
4383 }
4384 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
4385 ret = -EBUSY;
4386 break;
4387 }
4388 }
4389 return ret;
4390 }
4391
4392 static void cnic_free_irq(struct cnic_dev *dev)
4393 {
4394 struct cnic_local *cp = dev->cnic_priv;
4395 struct cnic_eth_dev *ethdev = cp->ethdev;
4396
4397 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4398 cp->disable_int_sync(dev);
4399 tasklet_kill(&cp->cnic_irq_task);
4400 free_irq(ethdev->irq_arr[0].vector, dev);
4401 }
4402 }
4403
4404 static int cnic_request_irq(struct cnic_dev *dev)
4405 {
4406 struct cnic_local *cp = dev->cnic_priv;
4407 struct cnic_eth_dev *ethdev = cp->ethdev;
4408 int err;
4409
4410 err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
4411 if (err)
4412 tasklet_disable(&cp->cnic_irq_task);
4413
4414 return err;
4415 }
4416
4417 static int cnic_init_bnx2_irq(struct cnic_dev *dev)
4418 {
4419 struct cnic_local *cp = dev->cnic_priv;
4420 struct cnic_eth_dev *ethdev = cp->ethdev;
4421
4422 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4423 int err, i = 0;
4424 int sblk_num = cp->status_blk_num;
4425 u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4426 BNX2_HC_SB_CONFIG_1;
4427
4428 CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4429
4430 CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
4431 CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
4432 CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
4433
4434 cp->last_status_idx = cp->status_blk.bnx2->status_idx;
4435 tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
4436 (unsigned long) dev);
4437 err = cnic_request_irq(dev);
4438 if (err)
4439 return err;
4440
4441 while (cp->status_blk.bnx2->status_completion_producer_index &&
4442 i < 10) {
4443 CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
4444 1 << (11 + sblk_num));
4445 udelay(10);
4446 i++;
4447 barrier();
4448 }
4449 if (cp->status_blk.bnx2->status_completion_producer_index) {
4450 cnic_free_irq(dev);
4451 goto failed;
4452 }
4453
4454 } else {
4455 struct status_block *sblk = cp->status_blk.gen;
4456 u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
4457 int i = 0;
4458
4459 while (sblk->status_completion_producer_index && i < 10) {
4460 CNIC_WR(dev, BNX2_HC_COMMAND,
4461 hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
4462 udelay(10);
4463 i++;
4464 barrier();
4465 }
4466 if (sblk->status_completion_producer_index)
4467 goto failed;
4468
4469 }
4470 return 0;
4471
4472 failed:
4473 netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
4474 return -EBUSY;
4475 }
4476
4477 static void cnic_enable_bnx2_int(struct cnic_dev *dev)
4478 {
4479 struct cnic_local *cp = dev->cnic_priv;
4480 struct cnic_eth_dev *ethdev = cp->ethdev;
4481
4482 if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
4483 return;
4484
4485 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
4486 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
4487 }
4488
4489 static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
4490 {
4491 struct cnic_local *cp = dev->cnic_priv;
4492 struct cnic_eth_dev *ethdev = cp->ethdev;
4493
4494 if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
4495 return;
4496
4497 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
4498 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4499 CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
4500 synchronize_irq(ethdev->irq_arr[0].vector);
4501 }
4502
4503 static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
4504 {
4505 struct cnic_local *cp = dev->cnic_priv;
4506 struct cnic_eth_dev *ethdev = cp->ethdev;
4507 struct cnic_uio_dev *udev = cp->udev;
4508 u32 cid_addr, tx_cid, sb_id;
4509 u32 val, offset0, offset1, offset2, offset3;
4510 int i;
4511 struct tx_bd *txbd;
4512 dma_addr_t buf_map, ring_map = udev->l2_ring_map;
4513 struct status_block *s_blk = cp->status_blk.gen;
4514
4515 sb_id = cp->status_blk_num;
4516 tx_cid = 20;
4517 cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
4518 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4519 struct status_block_msix *sblk = cp->status_blk.bnx2;
4520
4521 tx_cid = TX_TSS_CID + sb_id - 1;
4522 CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
4523 (TX_TSS_CID << 7));
4524 cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
4525 }
4526 cp->tx_cons = *cp->tx_cons_ptr;
4527
4528 cid_addr = GET_CID_ADDR(tx_cid);
4529 if (CHIP_NUM(cp) == CHIP_NUM_5709) {
4530 u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
4531
4532 for (i = 0; i < PHY_CTX_SIZE; i += 4)
4533 cnic_ctx_wr(dev, cid_addr2, i, 0);
4534
4535 offset0 = BNX2_L2CTX_TYPE_XI;
4536 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4537 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4538 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4539 } else {
4540 cnic_init_context(dev, tx_cid);
4541 cnic_init_context(dev, tx_cid + 1);
4542
4543 offset0 = BNX2_L2CTX_TYPE;
4544 offset1 = BNX2_L2CTX_CMD_TYPE;
4545 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4546 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4547 }
4548 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
4549 cnic_ctx_wr(dev, cid_addr, offset0, val);
4550
4551 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4552 cnic_ctx_wr(dev, cid_addr, offset1, val);
4553
4554 txbd = udev->l2_ring;
4555
4556 buf_map = udev->l2_buf_map;
4557 for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
4558 txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
4559 txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
4560 }
4561 val = (u64) ring_map >> 32;
4562 cnic_ctx_wr(dev, cid_addr, offset2, val);
4563 txbd->tx_bd_haddr_hi = val;
4564
4565 val = (u64) ring_map & 0xffffffff;
4566 cnic_ctx_wr(dev, cid_addr, offset3, val);
4567 txbd->tx_bd_haddr_lo = val;
4568 }
4569
4570 static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
4571 {
4572 struct cnic_local *cp = dev->cnic_priv;
4573 struct cnic_eth_dev *ethdev = cp->ethdev;
4574 struct cnic_uio_dev *udev = cp->udev;
4575 u32 cid_addr, sb_id, val, coal_reg, coal_val;
4576 int i;
4577 struct rx_bd *rxbd;
4578 struct status_block *s_blk = cp->status_blk.gen;
4579 dma_addr_t ring_map = udev->l2_ring_map;
4580
4581 sb_id = cp->status_blk_num;
4582 cnic_init_context(dev, 2);
4583 cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
4584 coal_reg = BNX2_HC_COMMAND;
4585 coal_val = CNIC_RD(dev, coal_reg);
4586 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4587 struct status_block_msix *sblk = cp->status_blk.bnx2;
4588
4589 cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
4590 coal_reg = BNX2_HC_COALESCE_NOW;
4591 coal_val = 1 << (11 + sb_id);
4592 }
4593 i = 0;
4594 while (!(*cp->rx_cons_ptr != 0) && i < 10) {
4595 CNIC_WR(dev, coal_reg, coal_val);
4596 udelay(10);
4597 i++;
4598 barrier();
4599 }
4600 cp->rx_cons = *cp->rx_cons_ptr;
4601
4602 cid_addr = GET_CID_ADDR(2);
4603 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
4604 BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
4605 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
4606
4607 if (sb_id == 0)
4608 val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
4609 else
4610 val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
4611 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
4612
4613 rxbd = udev->l2_ring + BCM_PAGE_SIZE;
4614 for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
4615 dma_addr_t buf_map;
4616 int n = (i % cp->l2_rx_ring_size) + 1;
4617
4618 buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
4619 rxbd->rx_bd_len = cp->l2_single_buf_size;
4620 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4621 rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
4622 rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
4623 }
4624 val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
4625 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
4626 rxbd->rx_bd_haddr_hi = val;
4627
4628 val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
4629 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
4630 rxbd->rx_bd_haddr_lo = val;
4631
4632 val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
4633 cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
4634 }
4635
4636 static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
4637 {
4638 struct kwqe *wqes[1], l2kwqe;
4639
4640 memset(&l2kwqe, 0, sizeof(l2kwqe));
4641 wqes[0] = &l2kwqe;
4642 l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
4643 (L2_KWQE_OPCODE_VALUE_FLUSH <<
4644 KWQE_OPCODE_SHIFT) | 2;
4645 dev->submit_kwqes(dev, wqes, 1);
4646 }
4647
4648 static void cnic_set_bnx2_mac(struct cnic_dev *dev)
4649 {
4650 struct cnic_local *cp = dev->cnic_priv;
4651 u32 val;
4652
4653 val = cp->func << 2;
4654
4655 cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
4656
4657 val = cnic_reg_rd_ind(dev, cp->shmem_base +
4658 BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
4659 dev->mac_addr[0] = (u8) (val >> 8);
4660 dev->mac_addr[1] = (u8) val;
4661
4662 CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
4663
4664 val = cnic_reg_rd_ind(dev, cp->shmem_base +
4665 BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
4666 dev->mac_addr[2] = (u8) (val >> 24);
4667 dev->mac_addr[3] = (u8) (val >> 16);
4668 dev->mac_addr[4] = (u8) (val >> 8);
4669 dev->mac_addr[5] = (u8) val;
4670
4671 CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
4672
4673 val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
4674 if (CHIP_NUM(cp) != CHIP_NUM_5709)
4675 val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
4676
4677 CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
4678 CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
4679 CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
4680 }
4681
4682 static int cnic_start_bnx2_hw(struct cnic_dev *dev)
4683 {
4684 struct cnic_local *cp = dev->cnic_priv;
4685 struct cnic_eth_dev *ethdev = cp->ethdev;
4686 struct status_block *sblk = cp->status_blk.gen;
4687 u32 val, kcq_cid_addr, kwq_cid_addr;
4688 int err;
4689
4690 cnic_set_bnx2_mac(dev);
4691
4692 val = CNIC_RD(dev, BNX2_MQ_CONFIG);
4693 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4694 if (BCM_PAGE_BITS > 12)
4695 val |= (12 - 8) << 4;
4696 else
4697 val |= (BCM_PAGE_BITS - 8) << 4;
4698
4699 CNIC_WR(dev, BNX2_MQ_CONFIG, val);
4700
4701 CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
4702 CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
4703 CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
4704
4705 err = cnic_setup_5709_context(dev, 1);
4706 if (err)
4707 return err;
4708
4709 cnic_init_context(dev, KWQ_CID);
4710 cnic_init_context(dev, KCQ_CID);
4711
4712 kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
4713 cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
4714
4715 cp->max_kwq_idx = MAX_KWQ_IDX;
4716 cp->kwq_prod_idx = 0;
4717 cp->kwq_con_idx = 0;
4718 set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
4719
4720 if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
4721 cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
4722 else
4723 cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
4724
4725 /* Initialize the kernel work queue context. */
4726 val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
4727 (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
4728 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
4729
4730 val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
4731 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
4732
4733 val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
4734 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
4735
4736 val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
4737 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
4738
4739 val = (u32) cp->kwq_info.pgtbl_map;
4740 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
4741
4742 kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
4743 cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
4744
4745 cp->kcq1.sw_prod_idx = 0;
4746 cp->kcq1.hw_prod_idx_ptr =
4747 &sblk->status_completion_producer_index;
4748
4749 cp->kcq1.status_idx_ptr = &sblk->status_idx;
4750
4751 /* Initialize the kernel complete queue context. */
4752 val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
4753 (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
4754 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
4755
4756 val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
4757 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
4758
4759 val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
4760 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
4761
4762 val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
4763 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
4764
4765 val = (u32) cp->kcq1.dma.pgtbl_map;
4766 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
4767
4768 cp->int_num = 0;
4769 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4770 struct status_block_msix *msblk = cp->status_blk.bnx2;
4771 u32 sb_id = cp->status_blk_num;
4772 u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
4773
4774 cp->kcq1.hw_prod_idx_ptr =
4775 &msblk->status_completion_producer_index;
4776 cp->kcq1.status_idx_ptr = &msblk->status_idx;
4777 cp->kwq_con_idx_ptr = &msblk->status_cmd_consumer_index;
4778 cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
4779 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
4780 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
4781 }
4782
4783 /* Enable Commnad Scheduler notification when we write to the
4784 * host producer index of the kernel contexts. */
4785 CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
4786
4787 /* Enable Command Scheduler notification when we write to either
4788 * the Send Queue or Receive Queue producer indexes of the kernel
4789 * bypass contexts. */
4790 CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
4791 CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
4792
4793 /* Notify COM when the driver post an application buffer. */
4794 CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
4795
4796 /* Set the CP and COM doorbells. These two processors polls the
4797 * doorbell for a non zero value before running. This must be done
4798 * after setting up the kernel queue contexts. */
4799 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
4800 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
4801
4802 cnic_init_bnx2_tx_ring(dev);
4803 cnic_init_bnx2_rx_ring(dev);
4804
4805 err = cnic_init_bnx2_irq(dev);
4806 if (err) {
4807 netdev_err(dev->netdev, "cnic_init_irq failed\n");
4808 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
4809 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
4810 return err;
4811 }
4812
4813 return 0;
4814 }
4815
4816 static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
4817 {
4818 struct cnic_local *cp = dev->cnic_priv;
4819 struct cnic_eth_dev *ethdev = cp->ethdev;
4820 u32 start_offset = ethdev->ctx_tbl_offset;
4821 int i;
4822
4823 for (i = 0; i < cp->ctx_blks; i++) {
4824 struct cnic_ctx *ctx = &cp->ctx_arr[i];
4825 dma_addr_t map = ctx->mapping;
4826
4827 if (cp->ctx_align) {
4828 unsigned long mask = cp->ctx_align - 1;
4829
4830 map = (map + mask) & ~mask;
4831 }
4832
4833 cnic_ctx_tbl_wr(dev, start_offset + i, map);
4834 }
4835 }
4836
4837 static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
4838 {
4839 struct cnic_local *cp = dev->cnic_priv;
4840 struct cnic_eth_dev *ethdev = cp->ethdev;
4841 int err = 0;
4842
4843 tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
4844 (unsigned long) dev);
4845 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
4846 err = cnic_request_irq(dev);
4847
4848 return err;
4849 }
4850
4851 static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
4852 u16 sb_id, u8 sb_index,
4853 u8 disable)
4854 {
4855
4856 u32 addr = BAR_CSTRORM_INTMEM +
4857 CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
4858 offsetof(struct hc_status_block_data_e1x, index_data) +
4859 sizeof(struct hc_index_data)*sb_index +
4860 offsetof(struct hc_index_data, flags);
4861 u16 flags = CNIC_RD16(dev, addr);
4862 /* clear and set */
4863 flags &= ~HC_INDEX_DATA_HC_ENABLED;
4864 flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
4865 HC_INDEX_DATA_HC_ENABLED);
4866 CNIC_WR16(dev, addr, flags);
4867 }
4868
4869 static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
4870 {
4871 struct cnic_local *cp = dev->cnic_priv;
4872 u8 sb_id = cp->status_blk_num;
4873
4874 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
4875 CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
4876 offsetof(struct hc_status_block_data_e1x, index_data) +
4877 sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
4878 offsetof(struct hc_index_data, timeout), 64 / 4);
4879 cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
4880 }
4881
4882 static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
4883 {
4884 }
4885
4886 static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
4887 struct client_init_ramrod_data *data)
4888 {
4889 struct cnic_local *cp = dev->cnic_priv;
4890 struct cnic_uio_dev *udev = cp->udev;
4891 union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
4892 dma_addr_t buf_map, ring_map = udev->l2_ring_map;
4893 struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
4894 int i;
4895 u32 cli = cp->ethdev->iscsi_l2_client_id;
4896 u32 val;
4897
4898 memset(txbd, 0, BCM_PAGE_SIZE);
4899
4900 buf_map = udev->l2_buf_map;
4901 for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
4902 struct eth_tx_start_bd *start_bd = &txbd->start_bd;
4903 struct eth_tx_parse_bd_e1x *pbd_e1x =
4904 &((txbd + 1)->parse_bd_e1x);
4905 struct eth_tx_parse_bd_e2 *pbd_e2 = &((txbd + 1)->parse_bd_e2);
4906 struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
4907
4908 start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
4909 start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
4910 reg_bd->addr_hi = start_bd->addr_hi;
4911 reg_bd->addr_lo = start_bd->addr_lo + 0x10;
4912 start_bd->nbytes = cpu_to_le16(0x10);
4913 start_bd->nbd = cpu_to_le16(3);
4914 start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
4915 start_bd->general_data &= ~ETH_TX_START_BD_PARSE_NBDS;
4916 start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
4917
4918 if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id))
4919 pbd_e2->parsing_data = (UNICAST_ADDRESS <<
4920 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
4921 else
4922 pbd_e1x->global_data = (UNICAST_ADDRESS <<
4923 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT);
4924 }
4925
4926 val = (u64) ring_map >> 32;
4927 txbd->next_bd.addr_hi = cpu_to_le32(val);
4928
4929 data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
4930
4931 val = (u64) ring_map & 0xffffffff;
4932 txbd->next_bd.addr_lo = cpu_to_le32(val);
4933
4934 data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
4935
4936 /* Other ramrod params */
4937 data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
4938 data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
4939
4940 /* reset xstorm per client statistics */
4941 if (cli < MAX_STAT_COUNTER_ID) {
4942 data->general.statistics_zero_flg = 1;
4943 data->general.statistics_en_flg = 1;
4944 data->general.statistics_counter_id = cli;
4945 }
4946
4947 cp->tx_cons_ptr =
4948 &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
4949 }
4950
4951 static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
4952 struct client_init_ramrod_data *data)
4953 {
4954 struct cnic_local *cp = dev->cnic_priv;
4955 struct cnic_uio_dev *udev = cp->udev;
4956 struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
4957 BCM_PAGE_SIZE);
4958 struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
4959 (udev->l2_ring + (2 * BCM_PAGE_SIZE));
4960 struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
4961 int i;
4962 u32 cli = cp->ethdev->iscsi_l2_client_id;
4963 int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
4964 u32 val;
4965 dma_addr_t ring_map = udev->l2_ring_map;
4966
4967 /* General data */
4968 data->general.client_id = cli;
4969 data->general.activate_flg = 1;
4970 data->general.sp_client_id = cli;
4971 data->general.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
4972 data->general.func_id = cp->pfid;
4973
4974 for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
4975 dma_addr_t buf_map;
4976 int n = (i % cp->l2_rx_ring_size) + 1;
4977
4978 buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
4979 rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
4980 rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
4981 }
4982
4983 val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
4984 rxbd->addr_hi = cpu_to_le32(val);
4985 data->rx.bd_page_base.hi = cpu_to_le32(val);
4986
4987 val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
4988 rxbd->addr_lo = cpu_to_le32(val);
4989 data->rx.bd_page_base.lo = cpu_to_le32(val);
4990
4991 rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
4992 val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
4993 rxcqe->addr_hi = cpu_to_le32(val);
4994 data->rx.cqe_page_base.hi = cpu_to_le32(val);
4995
4996 val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
4997 rxcqe->addr_lo = cpu_to_le32(val);
4998 data->rx.cqe_page_base.lo = cpu_to_le32(val);
4999
5000 /* Other ramrod params */
5001 data->rx.client_qzone_id = cl_qzone_id;
5002 data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
5003 data->rx.status_block_id = BNX2X_DEF_SB_ID;
5004
5005 data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
5006
5007 data->rx.max_bytes_on_bd = cpu_to_le16(cp->l2_single_buf_size);
5008 data->rx.outer_vlan_removal_enable_flg = 1;
5009 data->rx.silent_vlan_removal_flg = 1;
5010 data->rx.silent_vlan_value = 0;
5011 data->rx.silent_vlan_mask = 0xffff;
5012
5013 cp->rx_cons_ptr =
5014 &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
5015 cp->rx_cons = *cp->rx_cons_ptr;
5016 }
5017
5018 static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
5019 {
5020 struct cnic_local *cp = dev->cnic_priv;
5021 u32 pfid = cp->pfid;
5022
5023 cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
5024 CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
5025 cp->kcq1.sw_prod_idx = 0;
5026
5027 if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
5028 struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
5029
5030 cp->kcq1.hw_prod_idx_ptr =
5031 &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
5032 cp->kcq1.status_idx_ptr =
5033 &sb->sb.running_index[SM_RX_ID];
5034 } else {
5035 struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
5036
5037 cp->kcq1.hw_prod_idx_ptr =
5038 &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
5039 cp->kcq1.status_idx_ptr =
5040 &sb->sb.running_index[SM_RX_ID];
5041 }
5042
5043 if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
5044 struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
5045
5046 cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
5047 USTORM_FCOE_EQ_PROD_OFFSET(pfid);
5048 cp->kcq2.sw_prod_idx = 0;
5049 cp->kcq2.hw_prod_idx_ptr =
5050 &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
5051 cp->kcq2.status_idx_ptr =
5052 &sb->sb.running_index[SM_RX_ID];
5053 }
5054 }
5055
5056 static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
5057 {
5058 struct cnic_local *cp = dev->cnic_priv;
5059 struct cnic_eth_dev *ethdev = cp->ethdev;
5060 int func = CNIC_FUNC(cp), ret;
5061 u32 pfid;
5062
5063 dev->stats_addr = ethdev->addr_drv_info_to_mcp;
5064 cp->port_mode = CHIP_PORT_MODE_NONE;
5065
5066 if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
5067 u32 val;
5068
5069 pci_read_config_dword(dev->pcidev, PCICFG_ME_REGISTER, &val);
5070 cp->func = (u8) ((val & ME_REG_ABS_PF_NUM) >>
5071 ME_REG_ABS_PF_NUM_SHIFT);
5072 func = CNIC_FUNC(cp);
5073
5074 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN_OVWR);
5075 if (!(val & 1))
5076 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN);
5077 else
5078 val = (val >> 1) & 1;
5079
5080 if (val) {
5081 cp->port_mode = CHIP_4_PORT_MODE;
5082 cp->pfid = func >> 1;
5083 } else {
5084 cp->port_mode = CHIP_2_PORT_MODE;
5085 cp->pfid = func & 0x6;
5086 }
5087 } else {
5088 cp->pfid = func;
5089 }
5090 pfid = cp->pfid;
5091
5092 ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
5093 cp->iscsi_start_cid, 0);
5094
5095 if (ret)
5096 return -ENOMEM;
5097
5098 if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
5099 ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl, dev->max_fcoe_conn,
5100 cp->fcoe_start_cid, 0);
5101
5102 if (ret)
5103 return -ENOMEM;
5104 }
5105
5106 cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
5107
5108 cnic_init_bnx2x_kcq(dev);
5109
5110 /* Only 1 EQ */
5111 CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
5112 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
5113 CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
5114 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
5115 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
5116 cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
5117 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
5118 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
5119 (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
5120 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
5121 CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
5122 cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
5123 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
5124 CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
5125 (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
5126 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
5127 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
5128 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
5129 CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
5130 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
5131 CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
5132 HC_INDEX_ISCSI_EQ_CONS);
5133
5134 CNIC_WR(dev, BAR_USTRORM_INTMEM +
5135 USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
5136 cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
5137 CNIC_WR(dev, BAR_USTRORM_INTMEM +
5138 USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
5139 (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
5140
5141 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
5142 TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
5143
5144 cnic_setup_bnx2x_context(dev);
5145
5146 ret = cnic_init_bnx2x_irq(dev);
5147 if (ret)
5148 return ret;
5149
5150 return 0;
5151 }
5152
5153 static void cnic_init_rings(struct cnic_dev *dev)
5154 {
5155 struct cnic_local *cp = dev->cnic_priv;
5156 struct cnic_uio_dev *udev = cp->udev;
5157
5158 if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
5159 return;
5160
5161 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
5162 cnic_init_bnx2_tx_ring(dev);
5163 cnic_init_bnx2_rx_ring(dev);
5164 set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
5165 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
5166 u32 cli = cp->ethdev->iscsi_l2_client_id;
5167 u32 cid = cp->ethdev->iscsi_l2_cid;
5168 u32 cl_qzone_id;
5169 struct client_init_ramrod_data *data;
5170 union l5cm_specific_data l5_data;
5171 struct ustorm_eth_rx_producers rx_prods = {0};
5172 u32 off, i, *cid_ptr;
5173
5174 rx_prods.bd_prod = 0;
5175 rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
5176 barrier();
5177
5178 cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
5179
5180 off = BAR_USTRORM_INTMEM +
5181 (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) ?
5182 USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
5183 USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli));
5184
5185 for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
5186 CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
5187
5188 set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
5189
5190 data = udev->l2_buf;
5191 cid_ptr = udev->l2_buf + 12;
5192
5193 memset(data, 0, sizeof(*data));
5194
5195 cnic_init_bnx2x_tx_ring(dev, data);
5196 cnic_init_bnx2x_rx_ring(dev, data);
5197
5198 l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
5199 l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
5200
5201 set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
5202
5203 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
5204 cid, ETH_CONNECTION_TYPE, &l5_data);
5205
5206 i = 0;
5207 while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
5208 ++i < 10)
5209 msleep(1);
5210
5211 if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
5212 netdev_err(dev->netdev,
5213 "iSCSI CLIENT_SETUP did not complete\n");
5214 cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
5215 cnic_ring_ctl(dev, cid, cli, 1);
5216 *cid_ptr = cid;
5217 }
5218 }
5219
5220 static void cnic_shutdown_rings(struct cnic_dev *dev)
5221 {
5222 struct cnic_local *cp = dev->cnic_priv;
5223 struct cnic_uio_dev *udev = cp->udev;
5224 void *rx_ring;
5225
5226 if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
5227 return;
5228
5229 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
5230 cnic_shutdown_bnx2_rx_ring(dev);
5231 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
5232 u32 cli = cp->ethdev->iscsi_l2_client_id;
5233 u32 cid = cp->ethdev->iscsi_l2_cid;
5234 union l5cm_specific_data l5_data;
5235 int i;
5236
5237 cnic_ring_ctl(dev, cid, cli, 0);
5238
5239 set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
5240
5241 l5_data.phy_address.lo = cli;
5242 l5_data.phy_address.hi = 0;
5243 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
5244 cid, ETH_CONNECTION_TYPE, &l5_data);
5245 i = 0;
5246 while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
5247 ++i < 10)
5248 msleep(1);
5249
5250 if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
5251 netdev_err(dev->netdev,
5252 "iSCSI CLIENT_HALT did not complete\n");
5253 cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
5254
5255 memset(&l5_data, 0, sizeof(l5_data));
5256 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
5257 cid, NONE_CONNECTION_TYPE, &l5_data);
5258 msleep(10);
5259 }
5260 clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
5261 rx_ring = udev->l2_ring + BCM_PAGE_SIZE;
5262 memset(rx_ring, 0, BCM_PAGE_SIZE);
5263 }
5264
5265 static int cnic_register_netdev(struct cnic_dev *dev)
5266 {
5267 struct cnic_local *cp = dev->cnic_priv;
5268 struct cnic_eth_dev *ethdev = cp->ethdev;
5269 int err;
5270
5271 if (!ethdev)
5272 return -ENODEV;
5273
5274 if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
5275 return 0;
5276
5277 err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
5278 if (err)
5279 netdev_err(dev->netdev, "register_cnic failed\n");
5280
5281 return err;
5282 }
5283
5284 static void cnic_unregister_netdev(struct cnic_dev *dev)
5285 {
5286 struct cnic_local *cp = dev->cnic_priv;
5287 struct cnic_eth_dev *ethdev = cp->ethdev;
5288
5289 if (!ethdev)
5290 return;
5291
5292 ethdev->drv_unregister_cnic(dev->netdev);
5293 }
5294
5295 static int cnic_start_hw(struct cnic_dev *dev)
5296 {
5297 struct cnic_local *cp = dev->cnic_priv;
5298 struct cnic_eth_dev *ethdev = cp->ethdev;
5299 int err;
5300
5301 if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
5302 return -EALREADY;
5303
5304 dev->regview = ethdev->io_base;
5305 pci_dev_get(dev->pcidev);
5306 cp->func = PCI_FUNC(dev->pcidev->devfn);
5307 cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
5308 cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
5309
5310 err = cp->alloc_resc(dev);
5311 if (err) {
5312 netdev_err(dev->netdev, "allocate resource failure\n");
5313 goto err1;
5314 }
5315
5316 err = cp->start_hw(dev);
5317 if (err)
5318 goto err1;
5319
5320 err = cnic_cm_open(dev);
5321 if (err)
5322 goto err1;
5323
5324 set_bit(CNIC_F_CNIC_UP, &dev->flags);
5325
5326 cp->enable_int(dev);
5327
5328 return 0;
5329
5330 err1:
5331 cp->free_resc(dev);
5332 pci_dev_put(dev->pcidev);
5333 return err;
5334 }
5335
5336 static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
5337 {
5338 cnic_disable_bnx2_int_sync(dev);
5339
5340 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
5341 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
5342
5343 cnic_init_context(dev, KWQ_CID);
5344 cnic_init_context(dev, KCQ_CID);
5345
5346 cnic_setup_5709_context(dev, 0);
5347 cnic_free_irq(dev);
5348
5349 cnic_free_resc(dev);
5350 }
5351
5352
5353 static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
5354 {
5355 struct cnic_local *cp = dev->cnic_priv;
5356 u32 hc_index = HC_INDEX_ISCSI_EQ_CONS;
5357 u32 sb_id = cp->status_blk_num;
5358 u32 idx_off, syn_off;
5359
5360 cnic_free_irq(dev);
5361
5362 if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
5363 idx_off = offsetof(struct hc_status_block_e2, index_values) +
5364 (hc_index * sizeof(u16));
5365
5366 syn_off = CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hc_index, sb_id);
5367 } else {
5368 idx_off = offsetof(struct hc_status_block_e1x, index_values) +
5369 (hc_index * sizeof(u16));
5370
5371 syn_off = CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hc_index, sb_id);
5372 }
5373 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + syn_off, 0);
5374 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(sb_id) +
5375 idx_off, 0);
5376
5377 *cp->kcq1.hw_prod_idx_ptr = 0;
5378 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
5379 CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
5380 CNIC_WR16(dev, cp->kcq1.io_addr, 0);
5381 cnic_free_resc(dev);
5382 }
5383
5384 static void cnic_stop_hw(struct cnic_dev *dev)
5385 {
5386 if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
5387 struct cnic_local *cp = dev->cnic_priv;
5388 int i = 0;
5389
5390 /* Need to wait for the ring shutdown event to complete
5391 * before clearing the CNIC_UP flag.
5392 */
5393 while (cp->udev && cp->udev->uio_dev != -1 && i < 15) {
5394 msleep(100);
5395 i++;
5396 }
5397 cnic_shutdown_rings(dev);
5398 cp->stop_cm(dev);
5399 clear_bit(CNIC_F_CNIC_UP, &dev->flags);
5400 RCU_INIT_POINTER(cp->ulp_ops[CNIC_ULP_L4], NULL);
5401 synchronize_rcu();
5402 cnic_cm_shutdown(dev);
5403 cp->stop_hw(dev);
5404 pci_dev_put(dev->pcidev);
5405 }
5406 }
5407
5408 static void cnic_free_dev(struct cnic_dev *dev)
5409 {
5410 int i = 0;
5411
5412 while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
5413 msleep(100);
5414 i++;
5415 }
5416 if (atomic_read(&dev->ref_count) != 0)
5417 netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
5418
5419 netdev_info(dev->netdev, "Removed CNIC device\n");
5420 dev_put(dev->netdev);
5421 kfree(dev);
5422 }
5423
5424 static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
5425 struct pci_dev *pdev)
5426 {
5427 struct cnic_dev *cdev;
5428 struct cnic_local *cp;
5429 int alloc_size;
5430
5431 alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
5432
5433 cdev = kzalloc(alloc_size , GFP_KERNEL);
5434 if (cdev == NULL) {
5435 netdev_err(dev, "allocate dev struct failure\n");
5436 return NULL;
5437 }
5438
5439 cdev->netdev = dev;
5440 cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
5441 cdev->register_device = cnic_register_device;
5442 cdev->unregister_device = cnic_unregister_device;
5443 cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
5444
5445 cp = cdev->cnic_priv;
5446 cp->dev = cdev;
5447 cp->l2_single_buf_size = 0x400;
5448 cp->l2_rx_ring_size = 3;
5449
5450 spin_lock_init(&cp->cnic_ulp_lock);
5451
5452 netdev_info(dev, "Added CNIC device\n");
5453
5454 return cdev;
5455 }
5456
5457 static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
5458 {
5459 struct pci_dev *pdev;
5460 struct cnic_dev *cdev;
5461 struct cnic_local *cp;
5462 struct cnic_eth_dev *ethdev = NULL;
5463 struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
5464
5465 probe = symbol_get(bnx2_cnic_probe);
5466 if (probe) {
5467 ethdev = (*probe)(dev);
5468 symbol_put(bnx2_cnic_probe);
5469 }
5470 if (!ethdev)
5471 return NULL;
5472
5473 pdev = ethdev->pdev;
5474 if (!pdev)
5475 return NULL;
5476
5477 dev_hold(dev);
5478 pci_dev_get(pdev);
5479 if ((pdev->device == PCI_DEVICE_ID_NX2_5709 ||
5480 pdev->device == PCI_DEVICE_ID_NX2_5709S) &&
5481 (pdev->revision < 0x10)) {
5482 pci_dev_put(pdev);
5483 goto cnic_err;
5484 }
5485 pci_dev_put(pdev);
5486
5487 cdev = cnic_alloc_dev(dev, pdev);
5488 if (cdev == NULL)
5489 goto cnic_err;
5490
5491 set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
5492 cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
5493
5494 cp = cdev->cnic_priv;
5495 cp->ethdev = ethdev;
5496 cdev->pcidev = pdev;
5497 cp->chip_id = ethdev->chip_id;
5498
5499 cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
5500
5501 cp->cnic_ops = &cnic_bnx2_ops;
5502 cp->start_hw = cnic_start_bnx2_hw;
5503 cp->stop_hw = cnic_stop_bnx2_hw;
5504 cp->setup_pgtbl = cnic_setup_page_tbl;
5505 cp->alloc_resc = cnic_alloc_bnx2_resc;
5506 cp->free_resc = cnic_free_resc;
5507 cp->start_cm = cnic_cm_init_bnx2_hw;
5508 cp->stop_cm = cnic_cm_stop_bnx2_hw;
5509 cp->enable_int = cnic_enable_bnx2_int;
5510 cp->disable_int_sync = cnic_disable_bnx2_int_sync;
5511 cp->close_conn = cnic_close_bnx2_conn;
5512 return cdev;
5513
5514 cnic_err:
5515 dev_put(dev);
5516 return NULL;
5517 }
5518
5519 static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
5520 {
5521 struct pci_dev *pdev;
5522 struct cnic_dev *cdev;
5523 struct cnic_local *cp;
5524 struct cnic_eth_dev *ethdev = NULL;
5525 struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
5526
5527 probe = symbol_get(bnx2x_cnic_probe);
5528 if (probe) {
5529 ethdev = (*probe)(dev);
5530 symbol_put(bnx2x_cnic_probe);
5531 }
5532 if (!ethdev)
5533 return NULL;
5534
5535 pdev = ethdev->pdev;
5536 if (!pdev)
5537 return NULL;
5538
5539 dev_hold(dev);
5540 cdev = cnic_alloc_dev(dev, pdev);
5541 if (cdev == NULL) {
5542 dev_put(dev);
5543 return NULL;
5544 }
5545
5546 set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
5547 cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
5548
5549 cp = cdev->cnic_priv;
5550 cp->ethdev = ethdev;
5551 cdev->pcidev = pdev;
5552 cp->chip_id = ethdev->chip_id;
5553
5554 cdev->stats_addr = ethdev->addr_drv_info_to_mcp;
5555
5556 if (!(ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI))
5557 cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
5558 if (CNIC_SUPPORTS_FCOE(cp))
5559 cdev->max_fcoe_conn = ethdev->max_fcoe_conn;
5560
5561 if (cdev->max_fcoe_conn > BNX2X_FCOE_NUM_CONNECTIONS)
5562 cdev->max_fcoe_conn = BNX2X_FCOE_NUM_CONNECTIONS;
5563
5564 memcpy(cdev->mac_addr, ethdev->iscsi_mac, 6);
5565
5566 cp->cnic_ops = &cnic_bnx2x_ops;
5567 cp->start_hw = cnic_start_bnx2x_hw;
5568 cp->stop_hw = cnic_stop_bnx2x_hw;
5569 cp->setup_pgtbl = cnic_setup_page_tbl_le;
5570 cp->alloc_resc = cnic_alloc_bnx2x_resc;
5571 cp->free_resc = cnic_free_resc;
5572 cp->start_cm = cnic_cm_init_bnx2x_hw;
5573 cp->stop_cm = cnic_cm_stop_bnx2x_hw;
5574 cp->enable_int = cnic_enable_bnx2x_int;
5575 cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
5576 if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
5577 cp->ack_int = cnic_ack_bnx2x_e2_msix;
5578 cp->arm_int = cnic_arm_bnx2x_e2_msix;
5579 } else {
5580 cp->ack_int = cnic_ack_bnx2x_msix;
5581 cp->arm_int = cnic_arm_bnx2x_msix;
5582 }
5583 cp->close_conn = cnic_close_bnx2x_conn;
5584 return cdev;
5585 }
5586
5587 static struct cnic_dev *is_cnic_dev(struct net_device *dev)
5588 {
5589 struct ethtool_drvinfo drvinfo;
5590 struct cnic_dev *cdev = NULL;
5591
5592 if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
5593 memset(&drvinfo, 0, sizeof(drvinfo));
5594 dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
5595
5596 if (!strcmp(drvinfo.driver, "bnx2"))
5597 cdev = init_bnx2_cnic(dev);
5598 if (!strcmp(drvinfo.driver, "bnx2x"))
5599 cdev = init_bnx2x_cnic(dev);
5600 if (cdev) {
5601 write_lock(&cnic_dev_lock);
5602 list_add(&cdev->list, &cnic_dev_list);
5603 write_unlock(&cnic_dev_lock);
5604 }
5605 }
5606 return cdev;
5607 }
5608
5609 static void cnic_rcv_netevent(struct cnic_local *cp, unsigned long event,
5610 u16 vlan_id)
5611 {
5612 int if_type;
5613
5614 rcu_read_lock();
5615 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
5616 struct cnic_ulp_ops *ulp_ops;
5617 void *ctx;
5618
5619 ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
5620 if (!ulp_ops || !ulp_ops->indicate_netevent)
5621 continue;
5622
5623 ctx = cp->ulp_handle[if_type];
5624
5625 ulp_ops->indicate_netevent(ctx, event, vlan_id);
5626 }
5627 rcu_read_unlock();
5628 }
5629
5630 /* netdev event handler */
5631 static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
5632 void *ptr)
5633 {
5634 struct net_device *netdev = ptr;
5635 struct cnic_dev *dev;
5636 int new_dev = 0;
5637
5638 dev = cnic_from_netdev(netdev);
5639
5640 if (!dev && (event == NETDEV_REGISTER || netif_running(netdev))) {
5641 /* Check for the hot-plug device */
5642 dev = is_cnic_dev(netdev);
5643 if (dev) {
5644 new_dev = 1;
5645 cnic_hold(dev);
5646 }
5647 }
5648 if (dev) {
5649 struct cnic_local *cp = dev->cnic_priv;
5650
5651 if (new_dev)
5652 cnic_ulp_init(dev);
5653 else if (event == NETDEV_UNREGISTER)
5654 cnic_ulp_exit(dev);
5655
5656 if (event == NETDEV_UP || (new_dev && netif_running(netdev))) {
5657 if (cnic_register_netdev(dev) != 0) {
5658 cnic_put(dev);
5659 goto done;
5660 }
5661 if (!cnic_start_hw(dev))
5662 cnic_ulp_start(dev);
5663 }
5664
5665 cnic_rcv_netevent(cp, event, 0);
5666
5667 if (event == NETDEV_GOING_DOWN) {
5668 cnic_ulp_stop(dev);
5669 cnic_stop_hw(dev);
5670 cnic_unregister_netdev(dev);
5671 } else if (event == NETDEV_UNREGISTER) {
5672 write_lock(&cnic_dev_lock);
5673 list_del_init(&dev->list);
5674 write_unlock(&cnic_dev_lock);
5675
5676 cnic_put(dev);
5677 cnic_free_dev(dev);
5678 goto done;
5679 }
5680 cnic_put(dev);
5681 } else {
5682 struct net_device *realdev;
5683 u16 vid;
5684
5685 vid = cnic_get_vlan(netdev, &realdev);
5686 if (realdev) {
5687 dev = cnic_from_netdev(realdev);
5688 if (dev) {
5689 vid |= VLAN_TAG_PRESENT;
5690 cnic_rcv_netevent(dev->cnic_priv, event, vid);
5691 cnic_put(dev);
5692 }
5693 }
5694 }
5695 done:
5696 return NOTIFY_DONE;
5697 }
5698
5699 static struct notifier_block cnic_netdev_notifier = {
5700 .notifier_call = cnic_netdev_event
5701 };
5702
5703 static void cnic_release(void)
5704 {
5705 struct cnic_dev *dev;
5706 struct cnic_uio_dev *udev;
5707
5708 while (!list_empty(&cnic_dev_list)) {
5709 dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
5710 if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
5711 cnic_ulp_stop(dev);
5712 cnic_stop_hw(dev);
5713 }
5714
5715 cnic_ulp_exit(dev);
5716 cnic_unregister_netdev(dev);
5717 list_del_init(&dev->list);
5718 cnic_free_dev(dev);
5719 }
5720 while (!list_empty(&cnic_udev_list)) {
5721 udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
5722 list);
5723 cnic_free_uio(udev);
5724 }
5725 }
5726
5727 static int __init cnic_init(void)
5728 {
5729 int rc = 0;
5730
5731 pr_info("%s", version);
5732
5733 rc = register_netdevice_notifier(&cnic_netdev_notifier);
5734 if (rc) {
5735 cnic_release();
5736 return rc;
5737 }
5738
5739 cnic_wq = create_singlethread_workqueue("cnic_wq");
5740 if (!cnic_wq) {
5741 cnic_release();
5742 unregister_netdevice_notifier(&cnic_netdev_notifier);
5743 return -ENOMEM;
5744 }
5745
5746 return 0;
5747 }
5748
5749 static void __exit cnic_exit(void)
5750 {
5751 unregister_netdevice_notifier(&cnic_netdev_notifier);
5752 cnic_release();
5753 destroy_workqueue(cnic_wq);
5754 }
5755
5756 module_init(cnic_init);
5757 module_exit(cnic_exit);
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