2 * arch/m68k/q40/config.c
4 * Copyright (C) 1999 Richard Zidlicky
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file README.legal in the main directory of this archive
15 #include <linux/config.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
19 #include <linux/tty.h>
20 #include <linux/console.h>
21 #include <linux/linkage.h>
22 #include <linux/init.h>
23 #include <linux/major.h>
24 #include <linux/serial_reg.h>
25 #include <linux/rtc.h>
26 #include <linux/vt_kern.h>
30 #include <asm/bootinfo.h>
31 #include <asm/system.h>
32 #include <asm/pgtable.h>
33 #include <asm/setup.h>
35 #include <asm/traps.h>
36 #include <asm/machdep.h>
37 #include <asm/q40_master.h>
39 extern irqreturn_t
q40_process_int (int level
, struct pt_regs
*regs
);
40 extern void q40_init_IRQ (void);
41 static void q40_get_model(char *model
);
42 static int q40_get_hardware_list(char *buffer
);
43 extern void q40_sched_init(irqreturn_t (*handler
)(int, void *, struct pt_regs
*));
45 extern unsigned long q40_gettimeoffset (void);
46 extern int q40_hwclk (int, struct rtc_time
*);
47 extern unsigned int q40_get_ss (void);
48 extern int q40_set_clock_mmss (unsigned long);
49 static int q40_get_rtc_pll(struct rtc_pll_info
*pll
);
50 static int q40_set_rtc_pll(struct rtc_pll_info
*pll
);
51 extern void q40_reset (void);
53 extern void q40_waitbut(void);
54 void q40_set_vectors (void);
56 extern void q40_mksound(unsigned int /*freq*/, unsigned int /*ticks*/ );
58 extern char m68k_debug_device
[];
59 static void q40_mem_console_write(struct console
*co
, const char *b
,
64 static struct console q40_console_driver
= {
66 .flags
= CON_PRINTBUFFER
,
71 /* early debugging function:*/
72 extern char *q40_mem_cptr
; /*=(char *)0xff020000;*/
75 static void q40_mem_console_write(struct console
*co
, const char *s
,
88 void printq40(char *str
)
93 while (l
-- >0 && _cpleft
-- >0)
104 #ifdef CONFIG_HEARTBEAT
105 static void q40_heartbeat(int on
)
119 printk ("\n\n*******************************************\n"
120 "Called q40_reset : press the RESET button!! \n"
121 "*******************************************\n");
128 printk ("\n\n*******************\n"
130 "*******************\n");
135 static void q40_get_model(char *model
)
137 sprintf(model
, "Q40");
140 /* No hardware options on Q40? */
142 static int q40_get_hardware_list(char *buffer
)
148 static unsigned int serports
[]={0x3f8,0x2f8,0x3e8,0x2e8,0};
149 void q40_disable_irqs(void)
154 while((i
=serports
[j
++])) outb(0,i
+UART_IER
);
155 master_outb(0,EXT_ENABLE_REG
);
156 master_outb(0,KEY_IRQ_ENABLE_REG
);
159 void __init
config_q40(void)
161 mach_sched_init
= q40_sched_init
;
163 mach_init_IRQ
= q40_init_IRQ
;
164 mach_gettimeoffset
= q40_gettimeoffset
;
165 mach_hwclk
= q40_hwclk
;
166 mach_get_ss
= q40_get_ss
;
167 mach_get_rtc_pll
= q40_get_rtc_pll
;
168 mach_set_rtc_pll
= q40_set_rtc_pll
;
169 mach_set_clock_mmss
= q40_set_clock_mmss
;
171 mach_reset
= q40_reset
;
172 mach_get_model
= q40_get_model
;
173 mach_get_hardware_list
= q40_get_hardware_list
;
175 #if defined(CONFIG_INPUT_M68K_BEEP) || defined(CONFIG_INPUT_M68K_BEEP_MODULE)
176 mach_beep
= q40_mksound
;
178 #ifdef CONFIG_HEARTBEAT
179 mach_heartbeat
= q40_heartbeat
;
181 mach_halt
= q40_halt
;
183 /* disable a few things that SMSQ might have left enabled */
186 /* no DMA at all, but ide-scsi requires it.. make sure
187 * all physical RAM fits into the boundary - otherwise
188 * allocator may play costly and useless tricks */
189 mach_max_dma_address
= 1024*1024*1024;
191 /* useful for early debugging stages - writes kernel messages into SRAM */
192 if (!strncmp( m68k_debug_device
,"mem",3 ))
194 /*printk("using NVRAM debug, q40_mem_cptr=%p\n",q40_mem_cptr);*/
195 _cpleft
=2000-((long)q40_mem_cptr
-0xff020000)/4;
196 q40_console_driver
.write
= q40_mem_console_write
;
197 register_console(&q40_console_driver
);
202 int q40_parse_bootinfo(const struct bi_record
*rec
)
208 static inline unsigned char bcd2bin (unsigned char b
)
210 return ((b
>>4)*10 + (b
&15));
213 static inline unsigned char bin2bcd (unsigned char b
)
215 return (((b
/10)*16) + (b
%10));
219 unsigned long q40_gettimeoffset (void)
221 return 5000*(ql_ticks
!=0);
226 * Looks like op is non-zero for setting the clock, and zero for
229 * struct hwclk_time {
230 * unsigned sec; 0..59
231 * unsigned min; 0..59
232 * unsigned hour; 0..23
233 * unsigned day; 1..31
234 * unsigned mon; 0..11
235 * unsigned year; 00...
236 * int wday; 0..6, 0 is Sunday, -1 means unknown/don't set
240 int q40_hwclk(int op
, struct rtc_time
*t
)
244 Q40_RTC_CTRL
|= Q40_RTC_WRITE
;
246 Q40_RTC_SECS
= bin2bcd(t
->tm_sec
);
247 Q40_RTC_MINS
= bin2bcd(t
->tm_min
);
248 Q40_RTC_HOUR
= bin2bcd(t
->tm_hour
);
249 Q40_RTC_DATE
= bin2bcd(t
->tm_mday
);
250 Q40_RTC_MNTH
= bin2bcd(t
->tm_mon
+ 1);
251 Q40_RTC_YEAR
= bin2bcd(t
->tm_year
%100);
253 Q40_RTC_DOW
= bin2bcd(t
->tm_wday
+1);
255 Q40_RTC_CTRL
&= ~(Q40_RTC_WRITE
);
259 Q40_RTC_CTRL
|= Q40_RTC_READ
;
261 t
->tm_year
= bcd2bin (Q40_RTC_YEAR
);
262 t
->tm_mon
= bcd2bin (Q40_RTC_MNTH
)-1;
263 t
->tm_mday
= bcd2bin (Q40_RTC_DATE
);
264 t
->tm_hour
= bcd2bin (Q40_RTC_HOUR
);
265 t
->tm_min
= bcd2bin (Q40_RTC_MINS
);
266 t
->tm_sec
= bcd2bin (Q40_RTC_SECS
);
268 Q40_RTC_CTRL
&= ~(Q40_RTC_READ
);
272 t
->tm_wday
= bcd2bin(Q40_RTC_DOW
)-1;
279 unsigned int q40_get_ss(void)
281 return bcd2bin(Q40_RTC_SECS
);
285 * Set the minutes and seconds from seconds value 'nowtime'. Fail if
286 * clock is out by > 30 minutes. Logic lifted from atari code.
289 int q40_set_clock_mmss (unsigned long nowtime
)
292 short real_seconds
= nowtime
% 60, real_minutes
= (nowtime
/ 60) % 60;
297 rtc_minutes
= bcd2bin (Q40_RTC_MINS
);
299 if ((rtc_minutes
< real_minutes
300 ? real_minutes
- rtc_minutes
301 : rtc_minutes
- real_minutes
) < 30)
303 Q40_RTC_CTRL
|= Q40_RTC_WRITE
;
304 Q40_RTC_MINS
= bin2bcd(real_minutes
);
305 Q40_RTC_SECS
= bin2bcd(real_seconds
);
306 Q40_RTC_CTRL
&= ~(Q40_RTC_WRITE
);
316 /* get and set PLL calibration of RTC clock */
317 #define Q40_RTC_PLL_MASK ((1<<5)-1)
318 #define Q40_RTC_PLL_SIGN (1<<5)
320 static int q40_get_rtc_pll(struct rtc_pll_info
*pll
)
322 int tmp
=Q40_RTC_CTRL
;
323 pll
->pll_value
= tmp
& Q40_RTC_PLL_MASK
;
324 if (tmp
& Q40_RTC_PLL_SIGN
)
325 pll
->pll_value
= -pll
->pll_value
;
328 pll
->pll_posmult
=512;
329 pll
->pll_negmult
=256;
330 pll
->pll_clock
=125829120;
334 static int q40_set_rtc_pll(struct rtc_pll_info
*pll
)
337 /* the docs are a bit unclear so I am doublesetting */
338 /* RTC_WRITE here ... */
339 int tmp
= (pll
->pll_value
& 31) | (pll
->pll_value
<0 ? 32 : 0) |
341 Q40_RTC_CTRL
|= Q40_RTC_WRITE
;
343 Q40_RTC_CTRL
&= ~(Q40_RTC_WRITE
);