2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
13 #include <asm-generic/pci-bridge.h>
16 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
17 #define CARDBUS_RESERVE_BUSNR 3
19 struct resource busn_resource
= {
23 .flags
= IORESOURCE_BUS
,
26 /* Ugh. Need to stop exporting this to modules. */
27 LIST_HEAD(pci_root_buses
);
28 EXPORT_SYMBOL(pci_root_buses
);
30 static LIST_HEAD(pci_domain_busn_res_list
);
32 struct pci_domain_busn_res
{
33 struct list_head list
;
38 static struct resource
*get_pci_domain_busn_res(int domain_nr
)
40 struct pci_domain_busn_res
*r
;
42 list_for_each_entry(r
, &pci_domain_busn_res_list
, list
)
43 if (r
->domain_nr
== domain_nr
)
46 r
= kzalloc(sizeof(*r
), GFP_KERNEL
);
50 r
->domain_nr
= domain_nr
;
53 r
->res
.flags
= IORESOURCE_BUS
| IORESOURCE_PCI_FIXED
;
55 list_add_tail(&r
->list
, &pci_domain_busn_res_list
);
60 static int find_anything(struct device
*dev
, void *data
)
66 * Some device drivers need know if pci is initiated.
67 * Basically, we think pci is not initiated when there
68 * is no device to be found on the pci_bus_type.
70 int no_pci_devices(void)
75 dev
= bus_find_device(&pci_bus_type
, NULL
, NULL
, find_anything
);
76 no_devices
= (dev
== NULL
);
80 EXPORT_SYMBOL(no_pci_devices
);
85 static void release_pcibus_dev(struct device
*dev
)
87 struct pci_bus
*pci_bus
= to_pci_bus(dev
);
90 put_device(pci_bus
->bridge
);
91 pci_bus_remove_resources(pci_bus
);
92 pci_release_bus_of_node(pci_bus
);
96 static struct class pcibus_class
= {
98 .dev_release
= &release_pcibus_dev
,
99 .dev_attrs
= pcibus_dev_attrs
,
102 static int __init
pcibus_class_init(void)
104 return class_register(&pcibus_class
);
106 postcore_initcall(pcibus_class_init
);
108 static u64
pci_size(u64 base
, u64 maxbase
, u64 mask
)
110 u64 size
= mask
& maxbase
; /* Find the significant bits */
114 /* Get the lowest of them to find the decode size, and
115 from that the extent. */
116 size
= (size
& ~(size
-1)) - 1;
118 /* base == maxbase can be valid only if the BAR has
119 already been programmed with all 1s. */
120 if (base
== maxbase
&& ((base
| size
) & mask
) != mask
)
126 static inline unsigned long decode_bar(struct pci_dev
*dev
, u32 bar
)
131 if ((bar
& PCI_BASE_ADDRESS_SPACE
) == PCI_BASE_ADDRESS_SPACE_IO
) {
132 flags
= bar
& ~PCI_BASE_ADDRESS_IO_MASK
;
133 flags
|= IORESOURCE_IO
;
137 flags
= bar
& ~PCI_BASE_ADDRESS_MEM_MASK
;
138 flags
|= IORESOURCE_MEM
;
139 if (flags
& PCI_BASE_ADDRESS_MEM_PREFETCH
)
140 flags
|= IORESOURCE_PREFETCH
;
142 mem_type
= bar
& PCI_BASE_ADDRESS_MEM_TYPE_MASK
;
144 case PCI_BASE_ADDRESS_MEM_TYPE_32
:
146 case PCI_BASE_ADDRESS_MEM_TYPE_1M
:
147 /* 1M mem BAR treated as 32-bit BAR */
149 case PCI_BASE_ADDRESS_MEM_TYPE_64
:
150 flags
|= IORESOURCE_MEM_64
;
153 /* mem unknown type treated as 32-bit BAR */
160 * pci_read_base - read a PCI BAR
161 * @dev: the PCI device
162 * @type: type of the BAR
163 * @res: resource buffer to be filled in
164 * @pos: BAR position in the config space
166 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
168 int __pci_read_base(struct pci_dev
*dev
, enum pci_bar_type type
,
169 struct resource
*res
, unsigned int pos
)
173 struct pci_bus_region region
, inverted_region
;
174 bool bar_too_big
= false, bar_disabled
= false;
176 mask
= type
? PCI_ROM_ADDRESS_MASK
: ~0;
178 /* No printks while decoding is disabled! */
179 if (!dev
->mmio_always_on
) {
180 pci_read_config_word(dev
, PCI_COMMAND
, &orig_cmd
);
181 pci_write_config_word(dev
, PCI_COMMAND
,
182 orig_cmd
& ~(PCI_COMMAND_MEMORY
| PCI_COMMAND_IO
));
185 res
->name
= pci_name(dev
);
187 pci_read_config_dword(dev
, pos
, &l
);
188 pci_write_config_dword(dev
, pos
, l
| mask
);
189 pci_read_config_dword(dev
, pos
, &sz
);
190 pci_write_config_dword(dev
, pos
, l
);
193 * All bits set in sz means the device isn't working properly.
194 * If the BAR isn't implemented, all bits must be 0. If it's a
195 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
198 if (!sz
|| sz
== 0xffffffff)
202 * I don't know how l can have all bits set. Copied from old code.
203 * Maybe it fixes a bug on some ancient platform.
208 if (type
== pci_bar_unknown
) {
209 res
->flags
= decode_bar(dev
, l
);
210 res
->flags
|= IORESOURCE_SIZEALIGN
;
211 if (res
->flags
& IORESOURCE_IO
) {
212 l
&= PCI_BASE_ADDRESS_IO_MASK
;
213 mask
= PCI_BASE_ADDRESS_IO_MASK
& (u32
) IO_SPACE_LIMIT
;
215 l
&= PCI_BASE_ADDRESS_MEM_MASK
;
216 mask
= (u32
)PCI_BASE_ADDRESS_MEM_MASK
;
219 res
->flags
|= (l
& IORESOURCE_ROM_ENABLE
);
220 l
&= PCI_ROM_ADDRESS_MASK
;
221 mask
= (u32
)PCI_ROM_ADDRESS_MASK
;
224 if (res
->flags
& IORESOURCE_MEM_64
) {
227 u64 mask64
= mask
| (u64
)~0 << 32;
229 pci_read_config_dword(dev
, pos
+ 4, &l
);
230 pci_write_config_dword(dev
, pos
+ 4, ~0);
231 pci_read_config_dword(dev
, pos
+ 4, &sz
);
232 pci_write_config_dword(dev
, pos
+ 4, l
);
234 l64
|= ((u64
)l
<< 32);
235 sz64
|= ((u64
)sz
<< 32);
237 sz64
= pci_size(l64
, sz64
, mask64
);
242 if ((sizeof(resource_size_t
) < 8) && (sz64
> 0x100000000ULL
)) {
247 if ((sizeof(resource_size_t
) < 8) && l
) {
248 /* Address above 32-bit boundary; disable the BAR */
249 pci_write_config_dword(dev
, pos
, 0);
250 pci_write_config_dword(dev
, pos
+ 4, 0);
256 region
.end
= l64
+ sz64
;
259 sz
= pci_size(l
, sz
, mask
);
268 pcibios_bus_to_resource(dev
, res
, ®ion
);
269 pcibios_resource_to_bus(dev
, &inverted_region
, res
);
272 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
273 * the corresponding resource address (the physical address used by
274 * the CPU. Converting that resource address back to a bus address
275 * should yield the original BAR value:
277 * resource_to_bus(bus_to_resource(A)) == A
279 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
280 * be claimed by the device.
282 if (inverted_region
.start
!= region
.start
) {
283 dev_info(&dev
->dev
, "reg 0x%x: initial BAR value %pa invalid; forcing reassignment\n",
285 res
->flags
|= IORESOURCE_UNSET
;
286 res
->end
-= res
->start
;
296 if (!dev
->mmio_always_on
)
297 pci_write_config_word(dev
, PCI_COMMAND
, orig_cmd
);
300 dev_err(&dev
->dev
, "reg 0x%x: can't handle 64-bit BAR\n", pos
);
301 if (res
->flags
&& !bar_disabled
)
302 dev_printk(KERN_DEBUG
, &dev
->dev
, "reg 0x%x: %pR\n", pos
, res
);
304 return (res
->flags
& IORESOURCE_MEM_64
) ? 1 : 0;
307 static void pci_read_bases(struct pci_dev
*dev
, unsigned int howmany
, int rom
)
309 unsigned int pos
, reg
;
311 for (pos
= 0; pos
< howmany
; pos
++) {
312 struct resource
*res
= &dev
->resource
[pos
];
313 reg
= PCI_BASE_ADDRESS_0
+ (pos
<< 2);
314 pos
+= __pci_read_base(dev
, pci_bar_unknown
, res
, reg
);
318 struct resource
*res
= &dev
->resource
[PCI_ROM_RESOURCE
];
319 dev
->rom_base_reg
= rom
;
320 res
->flags
= IORESOURCE_MEM
| IORESOURCE_PREFETCH
|
321 IORESOURCE_READONLY
| IORESOURCE_CACHEABLE
|
322 IORESOURCE_SIZEALIGN
;
323 __pci_read_base(dev
, pci_bar_mem32
, res
, rom
);
327 static void pci_read_bridge_io(struct pci_bus
*child
)
329 struct pci_dev
*dev
= child
->self
;
330 u8 io_base_lo
, io_limit_lo
;
331 unsigned long io_mask
, io_granularity
, base
, limit
;
332 struct pci_bus_region region
;
333 struct resource
*res
;
335 io_mask
= PCI_IO_RANGE_MASK
;
336 io_granularity
= 0x1000;
337 if (dev
->io_window_1k
) {
338 /* Support 1K I/O space granularity */
339 io_mask
= PCI_IO_1K_RANGE_MASK
;
340 io_granularity
= 0x400;
343 res
= child
->resource
[0];
344 pci_read_config_byte(dev
, PCI_IO_BASE
, &io_base_lo
);
345 pci_read_config_byte(dev
, PCI_IO_LIMIT
, &io_limit_lo
);
346 base
= (io_base_lo
& io_mask
) << 8;
347 limit
= (io_limit_lo
& io_mask
) << 8;
349 if ((io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) == PCI_IO_RANGE_TYPE_32
) {
350 u16 io_base_hi
, io_limit_hi
;
352 pci_read_config_word(dev
, PCI_IO_BASE_UPPER16
, &io_base_hi
);
353 pci_read_config_word(dev
, PCI_IO_LIMIT_UPPER16
, &io_limit_hi
);
354 base
|= ((unsigned long) io_base_hi
<< 16);
355 limit
|= ((unsigned long) io_limit_hi
<< 16);
359 res
->flags
= (io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) | IORESOURCE_IO
;
361 region
.end
= limit
+ io_granularity
- 1;
362 pcibios_bus_to_resource(dev
, res
, ®ion
);
363 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
367 static void pci_read_bridge_mmio(struct pci_bus
*child
)
369 struct pci_dev
*dev
= child
->self
;
370 u16 mem_base_lo
, mem_limit_lo
;
371 unsigned long base
, limit
;
372 struct pci_bus_region region
;
373 struct resource
*res
;
375 res
= child
->resource
[1];
376 pci_read_config_word(dev
, PCI_MEMORY_BASE
, &mem_base_lo
);
377 pci_read_config_word(dev
, PCI_MEMORY_LIMIT
, &mem_limit_lo
);
378 base
= ((unsigned long) mem_base_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
379 limit
= ((unsigned long) mem_limit_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
381 res
->flags
= (mem_base_lo
& PCI_MEMORY_RANGE_TYPE_MASK
) | IORESOURCE_MEM
;
383 region
.end
= limit
+ 0xfffff;
384 pcibios_bus_to_resource(dev
, res
, ®ion
);
385 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
389 static void pci_read_bridge_mmio_pref(struct pci_bus
*child
)
391 struct pci_dev
*dev
= child
->self
;
392 u16 mem_base_lo
, mem_limit_lo
;
393 unsigned long base
, limit
;
394 struct pci_bus_region region
;
395 struct resource
*res
;
397 res
= child
->resource
[2];
398 pci_read_config_word(dev
, PCI_PREF_MEMORY_BASE
, &mem_base_lo
);
399 pci_read_config_word(dev
, PCI_PREF_MEMORY_LIMIT
, &mem_limit_lo
);
400 base
= ((unsigned long) mem_base_lo
& PCI_PREF_RANGE_MASK
) << 16;
401 limit
= ((unsigned long) mem_limit_lo
& PCI_PREF_RANGE_MASK
) << 16;
403 if ((mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) == PCI_PREF_RANGE_TYPE_64
) {
404 u32 mem_base_hi
, mem_limit_hi
;
406 pci_read_config_dword(dev
, PCI_PREF_BASE_UPPER32
, &mem_base_hi
);
407 pci_read_config_dword(dev
, PCI_PREF_LIMIT_UPPER32
, &mem_limit_hi
);
410 * Some bridges set the base > limit by default, and some
411 * (broken) BIOSes do not initialize them. If we find
412 * this, just assume they are not being used.
414 if (mem_base_hi
<= mem_limit_hi
) {
415 #if BITS_PER_LONG == 64
416 base
|= ((unsigned long) mem_base_hi
) << 32;
417 limit
|= ((unsigned long) mem_limit_hi
) << 32;
419 if (mem_base_hi
|| mem_limit_hi
) {
420 dev_err(&dev
->dev
, "can't handle 64-bit "
421 "address space for bridge\n");
428 res
->flags
= (mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) |
429 IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
430 if (res
->flags
& PCI_PREF_RANGE_TYPE_64
)
431 res
->flags
|= IORESOURCE_MEM_64
;
433 region
.end
= limit
+ 0xfffff;
434 pcibios_bus_to_resource(dev
, res
, ®ion
);
435 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
439 void pci_read_bridge_bases(struct pci_bus
*child
)
441 struct pci_dev
*dev
= child
->self
;
442 struct resource
*res
;
445 if (pci_is_root_bus(child
)) /* It's a host bus, nothing to read */
448 dev_info(&dev
->dev
, "PCI bridge to %pR%s\n",
450 dev
->transparent
? " (subtractive decode)" : "");
452 pci_bus_remove_resources(child
);
453 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++)
454 child
->resource
[i
] = &dev
->resource
[PCI_BRIDGE_RESOURCES
+i
];
456 pci_read_bridge_io(child
);
457 pci_read_bridge_mmio(child
);
458 pci_read_bridge_mmio_pref(child
);
460 if (dev
->transparent
) {
461 pci_bus_for_each_resource(child
->parent
, res
, i
) {
463 pci_bus_add_resource(child
, res
,
464 PCI_SUBTRACTIVE_DECODE
);
465 dev_printk(KERN_DEBUG
, &dev
->dev
,
466 " bridge window %pR (subtractive decode)\n",
473 static struct pci_bus
*pci_alloc_bus(void)
477 b
= kzalloc(sizeof(*b
), GFP_KERNEL
);
481 INIT_LIST_HEAD(&b
->node
);
482 INIT_LIST_HEAD(&b
->children
);
483 INIT_LIST_HEAD(&b
->devices
);
484 INIT_LIST_HEAD(&b
->slots
);
485 INIT_LIST_HEAD(&b
->resources
);
486 b
->max_bus_speed
= PCI_SPEED_UNKNOWN
;
487 b
->cur_bus_speed
= PCI_SPEED_UNKNOWN
;
491 static void pci_release_host_bridge_dev(struct device
*dev
)
493 struct pci_host_bridge
*bridge
= to_pci_host_bridge(dev
);
495 if (bridge
->release_fn
)
496 bridge
->release_fn(bridge
);
498 pci_free_resource_list(&bridge
->windows
);
503 static struct pci_host_bridge
*pci_alloc_host_bridge(struct pci_bus
*b
)
505 struct pci_host_bridge
*bridge
;
507 bridge
= kzalloc(sizeof(*bridge
), GFP_KERNEL
);
511 INIT_LIST_HEAD(&bridge
->windows
);
516 static unsigned char pcix_bus_speed
[] = {
517 PCI_SPEED_UNKNOWN
, /* 0 */
518 PCI_SPEED_66MHz_PCIX
, /* 1 */
519 PCI_SPEED_100MHz_PCIX
, /* 2 */
520 PCI_SPEED_133MHz_PCIX
, /* 3 */
521 PCI_SPEED_UNKNOWN
, /* 4 */
522 PCI_SPEED_66MHz_PCIX_ECC
, /* 5 */
523 PCI_SPEED_100MHz_PCIX_ECC
, /* 6 */
524 PCI_SPEED_133MHz_PCIX_ECC
, /* 7 */
525 PCI_SPEED_UNKNOWN
, /* 8 */
526 PCI_SPEED_66MHz_PCIX_266
, /* 9 */
527 PCI_SPEED_100MHz_PCIX_266
, /* A */
528 PCI_SPEED_133MHz_PCIX_266
, /* B */
529 PCI_SPEED_UNKNOWN
, /* C */
530 PCI_SPEED_66MHz_PCIX_533
, /* D */
531 PCI_SPEED_100MHz_PCIX_533
, /* E */
532 PCI_SPEED_133MHz_PCIX_533
/* F */
535 static unsigned char pcie_link_speed
[] = {
536 PCI_SPEED_UNKNOWN
, /* 0 */
537 PCIE_SPEED_2_5GT
, /* 1 */
538 PCIE_SPEED_5_0GT
, /* 2 */
539 PCIE_SPEED_8_0GT
, /* 3 */
540 PCI_SPEED_UNKNOWN
, /* 4 */
541 PCI_SPEED_UNKNOWN
, /* 5 */
542 PCI_SPEED_UNKNOWN
, /* 6 */
543 PCI_SPEED_UNKNOWN
, /* 7 */
544 PCI_SPEED_UNKNOWN
, /* 8 */
545 PCI_SPEED_UNKNOWN
, /* 9 */
546 PCI_SPEED_UNKNOWN
, /* A */
547 PCI_SPEED_UNKNOWN
, /* B */
548 PCI_SPEED_UNKNOWN
, /* C */
549 PCI_SPEED_UNKNOWN
, /* D */
550 PCI_SPEED_UNKNOWN
, /* E */
551 PCI_SPEED_UNKNOWN
/* F */
554 void pcie_update_link_speed(struct pci_bus
*bus
, u16 linksta
)
556 bus
->cur_bus_speed
= pcie_link_speed
[linksta
& PCI_EXP_LNKSTA_CLS
];
558 EXPORT_SYMBOL_GPL(pcie_update_link_speed
);
560 static unsigned char agp_speeds
[] = {
568 static enum pci_bus_speed
agp_speed(int agp3
, int agpstat
)
574 else if (agpstat
& 2)
576 else if (agpstat
& 1)
588 return agp_speeds
[index
];
592 static void pci_set_bus_speed(struct pci_bus
*bus
)
594 struct pci_dev
*bridge
= bus
->self
;
597 pos
= pci_find_capability(bridge
, PCI_CAP_ID_AGP
);
599 pos
= pci_find_capability(bridge
, PCI_CAP_ID_AGP3
);
603 pci_read_config_dword(bridge
, pos
+ PCI_AGP_STATUS
, &agpstat
);
604 bus
->max_bus_speed
= agp_speed(agpstat
& 8, agpstat
& 7);
606 pci_read_config_dword(bridge
, pos
+ PCI_AGP_COMMAND
, &agpcmd
);
607 bus
->cur_bus_speed
= agp_speed(agpstat
& 8, agpcmd
& 7);
610 pos
= pci_find_capability(bridge
, PCI_CAP_ID_PCIX
);
613 enum pci_bus_speed max
;
615 pci_read_config_word(bridge
, pos
+ PCI_X_BRIDGE_SSTATUS
,
618 if (status
& PCI_X_SSTATUS_533MHZ
) {
619 max
= PCI_SPEED_133MHz_PCIX_533
;
620 } else if (status
& PCI_X_SSTATUS_266MHZ
) {
621 max
= PCI_SPEED_133MHz_PCIX_266
;
622 } else if (status
& PCI_X_SSTATUS_133MHZ
) {
623 if ((status
& PCI_X_SSTATUS_VERS
) == PCI_X_SSTATUS_V2
) {
624 max
= PCI_SPEED_133MHz_PCIX_ECC
;
626 max
= PCI_SPEED_133MHz_PCIX
;
629 max
= PCI_SPEED_66MHz_PCIX
;
632 bus
->max_bus_speed
= max
;
633 bus
->cur_bus_speed
= pcix_bus_speed
[
634 (status
& PCI_X_SSTATUS_FREQ
) >> 6];
639 pos
= pci_find_capability(bridge
, PCI_CAP_ID_EXP
);
644 pcie_capability_read_dword(bridge
, PCI_EXP_LNKCAP
, &linkcap
);
645 bus
->max_bus_speed
= pcie_link_speed
[linkcap
& PCI_EXP_LNKCAP_SLS
];
647 pcie_capability_read_word(bridge
, PCI_EXP_LNKSTA
, &linksta
);
648 pcie_update_link_speed(bus
, linksta
);
653 static struct pci_bus
*pci_alloc_child_bus(struct pci_bus
*parent
,
654 struct pci_dev
*bridge
, int busnr
)
656 struct pci_bus
*child
;
661 * Allocate a new bus, and inherit stuff from the parent..
663 child
= pci_alloc_bus();
667 child
->parent
= parent
;
668 child
->ops
= parent
->ops
;
669 child
->msi
= parent
->msi
;
670 child
->sysdata
= parent
->sysdata
;
671 child
->bus_flags
= parent
->bus_flags
;
673 /* initialize some portions of the bus device, but don't register it
674 * now as the parent is not properly set up yet.
676 child
->dev
.class = &pcibus_class
;
677 dev_set_name(&child
->dev
, "%04x:%02x", pci_domain_nr(child
), busnr
);
680 * Set up the primary, secondary and subordinate
683 child
->number
= child
->busn_res
.start
= busnr
;
684 child
->primary
= parent
->busn_res
.start
;
685 child
->busn_res
.end
= 0xff;
688 child
->dev
.parent
= parent
->bridge
;
692 child
->self
= bridge
;
693 child
->bridge
= get_device(&bridge
->dev
);
694 child
->dev
.parent
= child
->bridge
;
695 pci_set_bus_of_node(child
);
696 pci_set_bus_speed(child
);
698 /* Set up default resource pointers and names.. */
699 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++) {
700 child
->resource
[i
] = &bridge
->resource
[PCI_BRIDGE_RESOURCES
+i
];
701 child
->resource
[i
]->name
= child
->name
;
703 bridge
->subordinate
= child
;
706 ret
= device_register(&child
->dev
);
709 pcibios_add_bus(child
);
711 /* Create legacy_io and legacy_mem files for this bus */
712 pci_create_legacy_files(child
);
717 struct pci_bus
*__ref
pci_add_new_bus(struct pci_bus
*parent
, struct pci_dev
*dev
, int busnr
)
719 struct pci_bus
*child
;
721 child
= pci_alloc_child_bus(parent
, dev
, busnr
);
723 down_write(&pci_bus_sem
);
724 list_add_tail(&child
->node
, &parent
->children
);
725 up_write(&pci_bus_sem
);
730 static void pci_fixup_parent_subordinate_busnr(struct pci_bus
*child
, int max
)
732 struct pci_bus
*parent
= child
->parent
;
734 /* Attempts to fix that up are really dangerous unless
735 we're going to re-assign all bus numbers. */
736 if (!pcibios_assign_all_busses())
739 while (parent
->parent
&& parent
->busn_res
.end
< max
) {
740 parent
->busn_res
.end
= max
;
741 pci_write_config_byte(parent
->self
, PCI_SUBORDINATE_BUS
, max
);
742 parent
= parent
->parent
;
747 * If it's a bridge, configure it and scan the bus behind it.
748 * For CardBus bridges, we don't scan behind as the devices will
749 * be handled by the bridge driver itself.
751 * We need to process bridges in two passes -- first we scan those
752 * already configured by the BIOS and after we are done with all of
753 * them, we proceed to assigning numbers to the remaining buses in
754 * order to avoid overlaps between old and new bus numbers.
756 int pci_scan_bridge(struct pci_bus
*bus
, struct pci_dev
*dev
, int max
, int pass
)
758 struct pci_bus
*child
;
759 int is_cardbus
= (dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
);
762 u8 primary
, secondary
, subordinate
;
765 pci_read_config_dword(dev
, PCI_PRIMARY_BUS
, &buses
);
766 primary
= buses
& 0xFF;
767 secondary
= (buses
>> 8) & 0xFF;
768 subordinate
= (buses
>> 16) & 0xFF;
770 dev_dbg(&dev
->dev
, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
771 secondary
, subordinate
, pass
);
773 if (!primary
&& (primary
!= bus
->number
) && secondary
&& subordinate
) {
774 dev_warn(&dev
->dev
, "Primary bus is hard wired to 0\n");
775 primary
= bus
->number
;
778 /* Check if setup is sensible at all */
780 (primary
!= bus
->number
|| secondary
<= bus
->number
||
781 secondary
> subordinate
)) {
782 dev_info(&dev
->dev
, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
783 secondary
, subordinate
);
787 /* Disable MasterAbortMode during probing to avoid reporting
788 of bus errors (in some architectures) */
789 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &bctl
);
790 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
,
791 bctl
& ~PCI_BRIDGE_CTL_MASTER_ABORT
);
793 if ((secondary
|| subordinate
) && !pcibios_assign_all_busses() &&
794 !is_cardbus
&& !broken
) {
797 * Bus already configured by firmware, process it in the first
798 * pass and just note the configuration.
804 * If we already got to this bus through a different bridge,
805 * don't re-add it. This can happen with the i450NX chipset.
807 * However, we continue to descend down the hierarchy and
808 * scan remaining child buses.
810 child
= pci_find_bus(pci_domain_nr(bus
), secondary
);
812 child
= pci_add_new_bus(bus
, dev
, secondary
);
815 child
->primary
= primary
;
816 pci_bus_insert_busn_res(child
, secondary
, subordinate
);
817 child
->bridge_ctl
= bctl
;
820 cmax
= pci_scan_child_bus(child
);
823 if (child
->busn_res
.end
> max
)
824 max
= child
->busn_res
.end
;
827 * We need to assign a number to this bus which we always
828 * do in the second pass.
831 if (pcibios_assign_all_busses() || broken
)
832 /* Temporarily disable forwarding of the
833 configuration cycles on all bridges in
834 this bus segment to avoid possible
835 conflicts in the second pass between two
836 bridges programmed with overlapping
838 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
,
844 pci_write_config_word(dev
, PCI_STATUS
, 0xffff);
846 /* Prevent assigning a bus number that already exists.
847 * This can happen when a bridge is hot-plugged, so in
848 * this case we only re-scan this bus. */
849 child
= pci_find_bus(pci_domain_nr(bus
), max
+1);
851 child
= pci_add_new_bus(bus
, dev
, ++max
);
854 pci_bus_insert_busn_res(child
, max
, 0xff);
856 buses
= (buses
& 0xff000000)
857 | ((unsigned int)(child
->primary
) << 0)
858 | ((unsigned int)(child
->busn_res
.start
) << 8)
859 | ((unsigned int)(child
->busn_res
.end
) << 16);
862 * yenta.c forces a secondary latency timer of 176.
863 * Copy that behaviour here.
866 buses
&= ~0xff000000;
867 buses
|= CARDBUS_LATENCY_TIMER
<< 24;
871 * We need to blast all three values with a single write.
873 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
, buses
);
876 child
->bridge_ctl
= bctl
;
878 * Adjust subordinate busnr in parent buses.
879 * We do this before scanning for children because
880 * some devices may not be detected if the bios
883 pci_fixup_parent_subordinate_busnr(child
, max
);
884 /* Now we can scan all subordinate buses... */
885 max
= pci_scan_child_bus(child
);
887 * now fix it up again since we have found
888 * the real value of max.
890 pci_fixup_parent_subordinate_busnr(child
, max
);
893 * For CardBus bridges, we leave 4 bus numbers
894 * as cards with a PCI-to-PCI bridge can be
897 for (i
=0; i
<CARDBUS_RESERVE_BUSNR
; i
++) {
898 struct pci_bus
*parent
= bus
;
899 if (pci_find_bus(pci_domain_nr(bus
),
902 while (parent
->parent
) {
903 if ((!pcibios_assign_all_busses()) &&
904 (parent
->busn_res
.end
> max
) &&
905 (parent
->busn_res
.end
<= max
+i
)) {
908 parent
= parent
->parent
;
912 * Often, there are two cardbus bridges
913 * -- try to leave one valid bus number
921 pci_fixup_parent_subordinate_busnr(child
, max
);
924 * Set the subordinate bus number to its real value.
926 pci_bus_update_busn_res_end(child
, max
);
927 pci_write_config_byte(dev
, PCI_SUBORDINATE_BUS
, max
);
931 (is_cardbus
? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
932 pci_domain_nr(bus
), child
->number
);
934 /* Has only triggered on CardBus, fixup is in yenta_socket */
935 while (bus
->parent
) {
936 if ((child
->busn_res
.end
> bus
->busn_res
.end
) ||
937 (child
->number
> bus
->busn_res
.end
) ||
938 (child
->number
< bus
->number
) ||
939 (child
->busn_res
.end
< bus
->number
)) {
940 dev_info(&child
->dev
, "%pR %s "
941 "hidden behind%s bridge %s %pR\n",
943 (bus
->number
> child
->busn_res
.end
&&
944 bus
->busn_res
.end
< child
->number
) ?
945 "wholly" : "partially",
946 bus
->self
->transparent
? " transparent" : "",
954 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, bctl
);
960 * Read interrupt line and base address registers.
961 * The architecture-dependent code can tweak these, of course.
963 static void pci_read_irq(struct pci_dev
*dev
)
967 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &irq
);
970 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
974 void set_pcie_port_type(struct pci_dev
*pdev
)
979 pos
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
983 pdev
->pcie_cap
= pos
;
984 pci_read_config_word(pdev
, pos
+ PCI_EXP_FLAGS
, ®16
);
985 pdev
->pcie_flags_reg
= reg16
;
986 pci_read_config_word(pdev
, pos
+ PCI_EXP_DEVCAP
, ®16
);
987 pdev
->pcie_mpss
= reg16
& PCI_EXP_DEVCAP_PAYLOAD
;
990 void set_pcie_hotplug_bridge(struct pci_dev
*pdev
)
994 pcie_capability_read_dword(pdev
, PCI_EXP_SLTCAP
, ®32
);
995 if (reg32
& PCI_EXP_SLTCAP_HPC
)
996 pdev
->is_hotplug_bridge
= 1;
999 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1002 * pci_setup_device - fill in class and map information of a device
1003 * @dev: the device structure to fill
1005 * Initialize the device structure with information about the device's
1006 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1007 * Called at initialisation of the PCI subsystem and by CardBus services.
1008 * Returns 0 on success and negative if unknown type of device (not normal,
1009 * bridge or CardBus).
1011 int pci_setup_device(struct pci_dev
*dev
)
1015 struct pci_slot
*slot
;
1017 struct pci_bus_region region
;
1018 struct resource
*res
;
1020 if (pci_read_config_byte(dev
, PCI_HEADER_TYPE
, &hdr_type
))
1023 dev
->sysdata
= dev
->bus
->sysdata
;
1024 dev
->dev
.parent
= dev
->bus
->bridge
;
1025 dev
->dev
.bus
= &pci_bus_type
;
1026 dev
->hdr_type
= hdr_type
& 0x7f;
1027 dev
->multifunction
= !!(hdr_type
& 0x80);
1028 dev
->error_state
= pci_channel_io_normal
;
1029 set_pcie_port_type(dev
);
1031 list_for_each_entry(slot
, &dev
->bus
->slots
, list
)
1032 if (PCI_SLOT(dev
->devfn
) == slot
->number
)
1035 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1036 set this higher, assuming the system even supports it. */
1037 dev
->dma_mask
= 0xffffffff;
1039 dev_set_name(&dev
->dev
, "%04x:%02x:%02x.%d", pci_domain_nr(dev
->bus
),
1040 dev
->bus
->number
, PCI_SLOT(dev
->devfn
),
1041 PCI_FUNC(dev
->devfn
));
1043 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class);
1044 dev
->revision
= class & 0xff;
1045 dev
->class = class >> 8; /* upper 3 bytes */
1047 dev_printk(KERN_DEBUG
, &dev
->dev
, "[%04x:%04x] type %02x class %#08x\n",
1048 dev
->vendor
, dev
->device
, dev
->hdr_type
, dev
->class);
1050 /* need to have dev->class ready */
1051 dev
->cfg_size
= pci_cfg_space_size(dev
);
1053 /* "Unknown power state" */
1054 dev
->current_state
= PCI_UNKNOWN
;
1056 /* Early fixups, before probing the BARs */
1057 pci_fixup_device(pci_fixup_early
, dev
);
1058 /* device class may be changed after fixup */
1059 class = dev
->class >> 8;
1061 switch (dev
->hdr_type
) { /* header type */
1062 case PCI_HEADER_TYPE_NORMAL
: /* standard header */
1063 if (class == PCI_CLASS_BRIDGE_PCI
)
1066 pci_read_bases(dev
, 6, PCI_ROM_ADDRESS
);
1067 pci_read_config_word(dev
, PCI_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
1068 pci_read_config_word(dev
, PCI_SUBSYSTEM_ID
, &dev
->subsystem_device
);
1071 * Do the ugly legacy mode stuff here rather than broken chip
1072 * quirk code. Legacy mode ATA controllers have fixed
1073 * addresses. These are not always echoed in BAR0-3, and
1074 * BAR0-3 in a few cases contain junk!
1076 if (class == PCI_CLASS_STORAGE_IDE
) {
1078 pci_read_config_byte(dev
, PCI_CLASS_PROG
, &progif
);
1079 if ((progif
& 1) == 0) {
1080 region
.start
= 0x1F0;
1082 res
= &dev
->resource
[0];
1083 res
->flags
= LEGACY_IO_RESOURCE
;
1084 pcibios_bus_to_resource(dev
, res
, ®ion
);
1085 region
.start
= 0x3F6;
1087 res
= &dev
->resource
[1];
1088 res
->flags
= LEGACY_IO_RESOURCE
;
1089 pcibios_bus_to_resource(dev
, res
, ®ion
);
1091 if ((progif
& 4) == 0) {
1092 region
.start
= 0x170;
1094 res
= &dev
->resource
[2];
1095 res
->flags
= LEGACY_IO_RESOURCE
;
1096 pcibios_bus_to_resource(dev
, res
, ®ion
);
1097 region
.start
= 0x376;
1099 res
= &dev
->resource
[3];
1100 res
->flags
= LEGACY_IO_RESOURCE
;
1101 pcibios_bus_to_resource(dev
, res
, ®ion
);
1106 case PCI_HEADER_TYPE_BRIDGE
: /* bridge header */
1107 if (class != PCI_CLASS_BRIDGE_PCI
)
1109 /* The PCI-to-PCI bridge spec requires that subtractive
1110 decoding (i.e. transparent) bridge must have programming
1111 interface code of 0x01. */
1113 dev
->transparent
= ((dev
->class & 0xff) == 1);
1114 pci_read_bases(dev
, 2, PCI_ROM_ADDRESS1
);
1115 set_pcie_hotplug_bridge(dev
);
1116 pos
= pci_find_capability(dev
, PCI_CAP_ID_SSVID
);
1118 pci_read_config_word(dev
, pos
+ PCI_SSVID_VENDOR_ID
, &dev
->subsystem_vendor
);
1119 pci_read_config_word(dev
, pos
+ PCI_SSVID_DEVICE_ID
, &dev
->subsystem_device
);
1123 case PCI_HEADER_TYPE_CARDBUS
: /* CardBus bridge header */
1124 if (class != PCI_CLASS_BRIDGE_CARDBUS
)
1127 pci_read_bases(dev
, 1, 0);
1128 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
1129 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_ID
, &dev
->subsystem_device
);
1132 default: /* unknown header */
1133 dev_err(&dev
->dev
, "unknown header type %02x, "
1134 "ignoring device\n", dev
->hdr_type
);
1138 dev_err(&dev
->dev
, "ignoring class %#08x (doesn't match header "
1139 "type %02x)\n", dev
->class, dev
->hdr_type
);
1140 dev
->class = PCI_CLASS_NOT_DEFINED
;
1143 /* We found a fine healthy device, go go go... */
1147 static void pci_release_capabilities(struct pci_dev
*dev
)
1149 pci_vpd_release(dev
);
1150 pci_iov_release(dev
);
1151 pci_free_cap_save_buffers(dev
);
1155 * pci_release_dev - free a pci device structure when all users of it are finished.
1156 * @dev: device that's been disconnected
1158 * Will be called only by the device core when all users of this pci device are
1161 static void pci_release_dev(struct device
*dev
)
1163 struct pci_dev
*pci_dev
;
1165 pci_dev
= to_pci_dev(dev
);
1166 pci_release_capabilities(pci_dev
);
1167 pci_release_of_node(pci_dev
);
1168 pcibios_release_device(pci_dev
);
1169 pci_bus_put(pci_dev
->bus
);
1174 * pci_cfg_space_size - get the configuration space size of the PCI device.
1177 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1178 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1179 * access it. Maybe we don't have a way to generate extended config space
1180 * accesses, or the device is behind a reverse Express bridge. So we try
1181 * reading the dword at 0x100 which must either be 0 or a valid extended
1182 * capability header.
1184 int pci_cfg_space_size_ext(struct pci_dev
*dev
)
1187 int pos
= PCI_CFG_SPACE_SIZE
;
1189 if (pci_read_config_dword(dev
, pos
, &status
) != PCIBIOS_SUCCESSFUL
)
1191 if (status
== 0xffffffff)
1194 return PCI_CFG_SPACE_EXP_SIZE
;
1197 return PCI_CFG_SPACE_SIZE
;
1200 int pci_cfg_space_size(struct pci_dev
*dev
)
1206 class = dev
->class >> 8;
1207 if (class == PCI_CLASS_BRIDGE_HOST
)
1208 return pci_cfg_space_size_ext(dev
);
1210 if (!pci_is_pcie(dev
)) {
1211 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1215 pci_read_config_dword(dev
, pos
+ PCI_X_STATUS
, &status
);
1216 if (!(status
& (PCI_X_STATUS_266MHZ
| PCI_X_STATUS_533MHZ
)))
1220 return pci_cfg_space_size_ext(dev
);
1223 return PCI_CFG_SPACE_SIZE
;
1226 struct pci_dev
*pci_alloc_dev(struct pci_bus
*bus
)
1228 struct pci_dev
*dev
;
1230 dev
= kzalloc(sizeof(struct pci_dev
), GFP_KERNEL
);
1234 INIT_LIST_HEAD(&dev
->bus_list
);
1235 dev
->dev
.type
= &pci_dev_type
;
1236 dev
->bus
= pci_bus_get(bus
);
1240 EXPORT_SYMBOL(pci_alloc_dev
);
1242 struct pci_dev
*alloc_pci_dev(void)
1244 return pci_alloc_dev(NULL
);
1246 EXPORT_SYMBOL(alloc_pci_dev
);
1248 bool pci_bus_read_dev_vendor_id(struct pci_bus
*bus
, int devfn
, u32
*l
,
1253 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, l
))
1256 /* some broken boards return 0 or ~0 if a slot is empty: */
1257 if (*l
== 0xffffffff || *l
== 0x00000000 ||
1258 *l
== 0x0000ffff || *l
== 0xffff0000)
1261 /* Configuration request Retry Status */
1262 while (*l
== 0xffff0001) {
1268 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, l
))
1270 /* Card hasn't responded in 60 seconds? Must be stuck. */
1271 if (delay
> crs_timeout
) {
1272 printk(KERN_WARNING
"pci %04x:%02x:%02x.%d: not "
1273 "responding\n", pci_domain_nr(bus
),
1274 bus
->number
, PCI_SLOT(devfn
),
1282 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id
);
1285 * Read the config data for a PCI device, sanity-check it
1286 * and fill in the dev structure...
1288 static struct pci_dev
*pci_scan_device(struct pci_bus
*bus
, int devfn
)
1290 struct pci_dev
*dev
;
1293 if (!pci_bus_read_dev_vendor_id(bus
, devfn
, &l
, 60*1000))
1296 dev
= pci_alloc_dev(bus
);
1301 dev
->vendor
= l
& 0xffff;
1302 dev
->device
= (l
>> 16) & 0xffff;
1304 pci_set_of_node(dev
);
1306 if (pci_setup_device(dev
)) {
1307 pci_bus_put(dev
->bus
);
1315 static void pci_init_capabilities(struct pci_dev
*dev
)
1317 /* MSI/MSI-X list */
1318 pci_msi_init_pci_dev(dev
);
1320 /* Buffers for saving PCIe and PCI-X capabilities */
1321 pci_allocate_cap_save_buffers(dev
);
1323 /* Power Management */
1326 /* Vital Product Data */
1327 pci_vpd_pci22_init(dev
);
1329 /* Alternative Routing-ID Forwarding */
1330 pci_configure_ari(dev
);
1332 /* Single Root I/O Virtualization */
1335 /* Enable ACS P2P upstream forwarding */
1336 pci_enable_acs(dev
);
1339 void pci_device_add(struct pci_dev
*dev
, struct pci_bus
*bus
)
1343 device_initialize(&dev
->dev
);
1344 dev
->dev
.release
= pci_release_dev
;
1346 set_dev_node(&dev
->dev
, pcibus_to_node(bus
));
1347 dev
->dev
.dma_mask
= &dev
->dma_mask
;
1348 dev
->dev
.dma_parms
= &dev
->dma_parms
;
1349 dev
->dev
.coherent_dma_mask
= 0xffffffffull
;
1351 pci_set_dma_max_seg_size(dev
, 65536);
1352 pci_set_dma_seg_boundary(dev
, 0xffffffff);
1354 /* Fix up broken headers */
1355 pci_fixup_device(pci_fixup_header
, dev
);
1357 /* moved out from quirk header fixup code */
1358 pci_reassigndev_resource_alignment(dev
);
1360 /* Clear the state_saved flag. */
1361 dev
->state_saved
= false;
1363 /* Initialize various capabilities */
1364 pci_init_capabilities(dev
);
1367 * Add the device to our list of discovered devices
1368 * and the bus list for fixup functions, etc.
1370 down_write(&pci_bus_sem
);
1371 list_add_tail(&dev
->bus_list
, &bus
->devices
);
1372 up_write(&pci_bus_sem
);
1374 ret
= pcibios_add_device(dev
);
1377 /* Notifier could use PCI capabilities */
1378 dev
->match_driver
= false;
1379 ret
= device_add(&dev
->dev
);
1382 pci_proc_attach_device(dev
);
1385 struct pci_dev
*__ref
pci_scan_single_device(struct pci_bus
*bus
, int devfn
)
1387 struct pci_dev
*dev
;
1389 dev
= pci_get_slot(bus
, devfn
);
1395 dev
= pci_scan_device(bus
, devfn
);
1399 pci_device_add(dev
, bus
);
1403 EXPORT_SYMBOL(pci_scan_single_device
);
1405 static unsigned next_fn(struct pci_bus
*bus
, struct pci_dev
*dev
, unsigned fn
)
1411 if (pci_ari_enabled(bus
)) {
1414 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
);
1418 pci_read_config_word(dev
, pos
+ PCI_ARI_CAP
, &cap
);
1419 next_fn
= PCI_ARI_CAP_NFN(cap
);
1421 return 0; /* protect against malformed list */
1426 /* dev may be NULL for non-contiguous multifunction devices */
1427 if (!dev
|| dev
->multifunction
)
1428 return (fn
+ 1) % 8;
1433 static int only_one_child(struct pci_bus
*bus
)
1435 struct pci_dev
*parent
= bus
->self
;
1437 if (!parent
|| !pci_is_pcie(parent
))
1439 if (pci_pcie_type(parent
) == PCI_EXP_TYPE_ROOT_PORT
)
1441 if (pci_pcie_type(parent
) == PCI_EXP_TYPE_DOWNSTREAM
&&
1442 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS
))
1448 * pci_scan_slot - scan a PCI slot on a bus for devices.
1449 * @bus: PCI bus to scan
1450 * @devfn: slot number to scan (must have zero function.)
1452 * Scan a PCI slot on the specified PCI bus for devices, adding
1453 * discovered devices to the @bus->devices list. New devices
1454 * will not have is_added set.
1456 * Returns the number of new devices found.
1458 int pci_scan_slot(struct pci_bus
*bus
, int devfn
)
1460 unsigned fn
, nr
= 0;
1461 struct pci_dev
*dev
;
1463 if (only_one_child(bus
) && (devfn
> 0))
1464 return 0; /* Already scanned the entire slot */
1466 dev
= pci_scan_single_device(bus
, devfn
);
1472 for (fn
= next_fn(bus
, dev
, 0); fn
> 0; fn
= next_fn(bus
, dev
, fn
)) {
1473 dev
= pci_scan_single_device(bus
, devfn
+ fn
);
1477 dev
->multifunction
= 1;
1481 /* only one slot has pcie device */
1482 if (bus
->self
&& nr
)
1483 pcie_aspm_init_link_state(bus
->self
);
1488 static int pcie_find_smpss(struct pci_dev
*dev
, void *data
)
1492 if (!pci_is_pcie(dev
))
1495 /* For PCIE hotplug enabled slots not connected directly to a
1496 * PCI-E root port, there can be problems when hotplugging
1497 * devices. This is due to the possibility of hotplugging a
1498 * device into the fabric with a smaller MPS that the devices
1499 * currently running have configured. Modifying the MPS on the
1500 * running devices could cause a fatal bus error due to an
1501 * incoming frame being larger than the newly configured MPS.
1502 * To work around this, the MPS for the entire fabric must be
1503 * set to the minimum size. Any devices hotplugged into this
1504 * fabric will have the minimum MPS set. If the PCI hotplug
1505 * slot is directly connected to the root port and there are not
1506 * other devices on the fabric (which seems to be the most
1507 * common case), then this is not an issue and MPS discovery
1508 * will occur as normal.
1510 if (dev
->is_hotplug_bridge
&& (!list_is_singular(&dev
->bus
->devices
) ||
1512 pci_pcie_type(dev
->bus
->self
) != PCI_EXP_TYPE_ROOT_PORT
)))
1515 if (*smpss
> dev
->pcie_mpss
)
1516 *smpss
= dev
->pcie_mpss
;
1521 static void pcie_write_mps(struct pci_dev
*dev
, int mps
)
1525 if (pcie_bus_config
== PCIE_BUS_PERFORMANCE
) {
1526 mps
= 128 << dev
->pcie_mpss
;
1528 if (pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
&&
1530 /* For "Performance", the assumption is made that
1531 * downstream communication will never be larger than
1532 * the MRRS. So, the MPS only needs to be configured
1533 * for the upstream communication. This being the case,
1534 * walk from the top down and set the MPS of the child
1535 * to that of the parent bus.
1537 * Configure the device MPS with the smaller of the
1538 * device MPSS or the bridge MPS (which is assumed to be
1539 * properly configured at this point to the largest
1540 * allowable MPS based on its parent bus).
1542 mps
= min(mps
, pcie_get_mps(dev
->bus
->self
));
1545 rc
= pcie_set_mps(dev
, mps
);
1547 dev_err(&dev
->dev
, "Failed attempting to set the MPS\n");
1550 static void pcie_write_mrrs(struct pci_dev
*dev
)
1554 /* In the "safe" case, do not configure the MRRS. There appear to be
1555 * issues with setting MRRS to 0 on a number of devices.
1557 if (pcie_bus_config
!= PCIE_BUS_PERFORMANCE
)
1560 /* For Max performance, the MRRS must be set to the largest supported
1561 * value. However, it cannot be configured larger than the MPS the
1562 * device or the bus can support. This should already be properly
1563 * configured by a prior call to pcie_write_mps.
1565 mrrs
= pcie_get_mps(dev
);
1567 /* MRRS is a R/W register. Invalid values can be written, but a
1568 * subsequent read will verify if the value is acceptable or not.
1569 * If the MRRS value provided is not acceptable (e.g., too large),
1570 * shrink the value until it is acceptable to the HW.
1572 while (mrrs
!= pcie_get_readrq(dev
) && mrrs
>= 128) {
1573 rc
= pcie_set_readrq(dev
, mrrs
);
1577 dev_warn(&dev
->dev
, "Failed attempting to set the MRRS\n");
1582 dev_err(&dev
->dev
, "MRRS was unable to be configured with a "
1583 "safe value. If problems are experienced, try running "
1584 "with pci=pcie_bus_safe.\n");
1587 static int pcie_bus_configure_set(struct pci_dev
*dev
, void *data
)
1591 if (!pci_is_pcie(dev
))
1594 mps
= 128 << *(u8
*)data
;
1595 orig_mps
= pcie_get_mps(dev
);
1597 pcie_write_mps(dev
, mps
);
1598 pcie_write_mrrs(dev
);
1600 dev_info(&dev
->dev
, "PCI-E Max Payload Size set to %4d/%4d (was %4d), "
1601 "Max Read Rq %4d\n", pcie_get_mps(dev
), 128 << dev
->pcie_mpss
,
1602 orig_mps
, pcie_get_readrq(dev
));
1607 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
1608 * parents then children fashion. If this changes, then this code will not
1611 void pcie_bus_configure_settings(struct pci_bus
*bus
, u8 mpss
)
1615 if (!pci_is_pcie(bus
->self
))
1618 if (pcie_bus_config
== PCIE_BUS_TUNE_OFF
)
1621 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1622 * to be aware to the MPS of the destination. To work around this,
1623 * simply force the MPS of the entire system to the smallest possible.
1625 if (pcie_bus_config
== PCIE_BUS_PEER2PEER
)
1628 if (pcie_bus_config
== PCIE_BUS_SAFE
) {
1631 pcie_find_smpss(bus
->self
, &smpss
);
1632 pci_walk_bus(bus
, pcie_find_smpss
, &smpss
);
1635 pcie_bus_configure_set(bus
->self
, &smpss
);
1636 pci_walk_bus(bus
, pcie_bus_configure_set
, &smpss
);
1638 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings
);
1640 unsigned int pci_scan_child_bus(struct pci_bus
*bus
)
1642 unsigned int devfn
, pass
, max
= bus
->busn_res
.start
;
1643 struct pci_dev
*dev
;
1645 dev_dbg(&bus
->dev
, "scanning bus\n");
1647 /* Go find them, Rover! */
1648 for (devfn
= 0; devfn
< 0x100; devfn
+= 8)
1649 pci_scan_slot(bus
, devfn
);
1651 /* Reserve buses for SR-IOV capability. */
1652 max
+= pci_iov_bus_range(bus
);
1655 * After performing arch-dependent fixup of the bus, look behind
1656 * all PCI-to-PCI bridges on this bus.
1658 if (!bus
->is_added
) {
1659 dev_dbg(&bus
->dev
, "fixups for bus\n");
1660 pcibios_fixup_bus(bus
);
1664 for (pass
=0; pass
< 2; pass
++)
1665 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1666 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
1667 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
)
1668 max
= pci_scan_bridge(bus
, dev
, max
, pass
);
1672 * We've scanned the bus and so we know all about what's on
1673 * the other side of any bridges that may be on this bus plus
1676 * Return how far we've got finding sub-buses.
1678 dev_dbg(&bus
->dev
, "bus scan returning with max=%02x\n", max
);
1683 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
1684 * @bridge: Host bridge to set up.
1686 * Default empty implementation. Replace with an architecture-specific setup
1687 * routine, if necessary.
1689 int __weak
pcibios_root_bridge_prepare(struct pci_host_bridge
*bridge
)
1694 void __weak
pcibios_add_bus(struct pci_bus
*bus
)
1698 void __weak
pcibios_remove_bus(struct pci_bus
*bus
)
1702 struct pci_bus
*pci_create_root_bus(struct device
*parent
, int bus
,
1703 struct pci_ops
*ops
, void *sysdata
, struct list_head
*resources
)
1706 struct pci_host_bridge
*bridge
;
1707 struct pci_bus
*b
, *b2
;
1708 struct pci_host_bridge_window
*window
, *n
;
1709 struct resource
*res
;
1710 resource_size_t offset
;
1714 b
= pci_alloc_bus();
1718 b
->sysdata
= sysdata
;
1720 b
->number
= b
->busn_res
.start
= bus
;
1721 b2
= pci_find_bus(pci_domain_nr(b
), bus
);
1723 /* If we already got to this bus through a different bridge, ignore it */
1724 dev_dbg(&b2
->dev
, "bus already known\n");
1728 bridge
= pci_alloc_host_bridge(b
);
1732 bridge
->dev
.parent
= parent
;
1733 bridge
->dev
.release
= pci_release_host_bridge_dev
;
1734 dev_set_name(&bridge
->dev
, "pci%04x:%02x", pci_domain_nr(b
), bus
);
1735 error
= pcibios_root_bridge_prepare(bridge
);
1741 error
= device_register(&bridge
->dev
);
1743 put_device(&bridge
->dev
);
1746 b
->bridge
= get_device(&bridge
->dev
);
1747 device_enable_async_suspend(b
->bridge
);
1748 pci_set_bus_of_node(b
);
1751 set_dev_node(b
->bridge
, pcibus_to_node(b
));
1753 b
->dev
.class = &pcibus_class
;
1754 b
->dev
.parent
= b
->bridge
;
1755 dev_set_name(&b
->dev
, "%04x:%02x", pci_domain_nr(b
), bus
);
1756 error
= device_register(&b
->dev
);
1758 goto class_dev_reg_err
;
1762 /* Create legacy_io and legacy_mem files for this bus */
1763 pci_create_legacy_files(b
);
1766 dev_info(parent
, "PCI host bridge to bus %s\n", dev_name(&b
->dev
));
1768 printk(KERN_INFO
"PCI host bridge to bus %s\n", dev_name(&b
->dev
));
1770 /* Add initial resources to the bus */
1771 list_for_each_entry_safe(window
, n
, resources
, list
) {
1772 list_move_tail(&window
->list
, &bridge
->windows
);
1774 offset
= window
->offset
;
1775 if (res
->flags
& IORESOURCE_BUS
)
1776 pci_bus_insert_busn_res(b
, bus
, res
->end
);
1778 pci_bus_add_resource(b
, res
, 0);
1780 if (resource_type(res
) == IORESOURCE_IO
)
1781 fmt
= " (bus address [%#06llx-%#06llx])";
1783 fmt
= " (bus address [%#010llx-%#010llx])";
1784 snprintf(bus_addr
, sizeof(bus_addr
), fmt
,
1785 (unsigned long long) (res
->start
- offset
),
1786 (unsigned long long) (res
->end
- offset
));
1789 dev_info(&b
->dev
, "root bus resource %pR%s\n", res
, bus_addr
);
1792 down_write(&pci_bus_sem
);
1793 list_add_tail(&b
->node
, &pci_root_buses
);
1794 up_write(&pci_bus_sem
);
1799 put_device(&bridge
->dev
);
1800 device_unregister(&bridge
->dev
);
1806 int pci_bus_insert_busn_res(struct pci_bus
*b
, int bus
, int bus_max
)
1808 struct resource
*res
= &b
->busn_res
;
1809 struct resource
*parent_res
, *conflict
;
1813 res
->flags
= IORESOURCE_BUS
;
1815 if (!pci_is_root_bus(b
))
1816 parent_res
= &b
->parent
->busn_res
;
1818 parent_res
= get_pci_domain_busn_res(pci_domain_nr(b
));
1819 res
->flags
|= IORESOURCE_PCI_FIXED
;
1822 conflict
= insert_resource_conflict(parent_res
, res
);
1825 dev_printk(KERN_DEBUG
, &b
->dev
,
1826 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
1827 res
, pci_is_root_bus(b
) ? "domain " : "",
1828 parent_res
, conflict
->name
, conflict
);
1830 return conflict
== NULL
;
1833 int pci_bus_update_busn_res_end(struct pci_bus
*b
, int bus_max
)
1835 struct resource
*res
= &b
->busn_res
;
1836 struct resource old_res
= *res
;
1837 resource_size_t size
;
1840 if (res
->start
> bus_max
)
1843 size
= bus_max
- res
->start
+ 1;
1844 ret
= adjust_resource(res
, res
->start
, size
);
1845 dev_printk(KERN_DEBUG
, &b
->dev
,
1846 "busn_res: %pR end %s updated to %02x\n",
1847 &old_res
, ret
? "can not be" : "is", bus_max
);
1849 if (!ret
&& !res
->parent
)
1850 pci_bus_insert_busn_res(b
, res
->start
, res
->end
);
1855 void pci_bus_release_busn_res(struct pci_bus
*b
)
1857 struct resource
*res
= &b
->busn_res
;
1860 if (!res
->flags
|| !res
->parent
)
1863 ret
= release_resource(res
);
1864 dev_printk(KERN_DEBUG
, &b
->dev
,
1865 "busn_res: %pR %s released\n",
1866 res
, ret
? "can not be" : "is");
1869 struct pci_bus
*pci_scan_root_bus(struct device
*parent
, int bus
,
1870 struct pci_ops
*ops
, void *sysdata
, struct list_head
*resources
)
1872 struct pci_host_bridge_window
*window
;
1877 list_for_each_entry(window
, resources
, list
)
1878 if (window
->res
->flags
& IORESOURCE_BUS
) {
1883 b
= pci_create_root_bus(parent
, bus
, ops
, sysdata
, resources
);
1889 "No busn resource found for root bus, will use [bus %02x-ff]\n",
1891 pci_bus_insert_busn_res(b
, bus
, 255);
1894 max
= pci_scan_child_bus(b
);
1897 pci_bus_update_busn_res_end(b
, max
);
1899 pci_bus_add_devices(b
);
1902 EXPORT_SYMBOL(pci_scan_root_bus
);
1904 /* Deprecated; use pci_scan_root_bus() instead */
1905 struct pci_bus
*pci_scan_bus_parented(struct device
*parent
,
1906 int bus
, struct pci_ops
*ops
, void *sysdata
)
1908 LIST_HEAD(resources
);
1911 pci_add_resource(&resources
, &ioport_resource
);
1912 pci_add_resource(&resources
, &iomem_resource
);
1913 pci_add_resource(&resources
, &busn_resource
);
1914 b
= pci_create_root_bus(parent
, bus
, ops
, sysdata
, &resources
);
1916 pci_scan_child_bus(b
);
1918 pci_free_resource_list(&resources
);
1921 EXPORT_SYMBOL(pci_scan_bus_parented
);
1923 struct pci_bus
*pci_scan_bus(int bus
, struct pci_ops
*ops
,
1926 LIST_HEAD(resources
);
1929 pci_add_resource(&resources
, &ioport_resource
);
1930 pci_add_resource(&resources
, &iomem_resource
);
1931 pci_add_resource(&resources
, &busn_resource
);
1932 b
= pci_create_root_bus(NULL
, bus
, ops
, sysdata
, &resources
);
1934 pci_scan_child_bus(b
);
1935 pci_bus_add_devices(b
);
1937 pci_free_resource_list(&resources
);
1941 EXPORT_SYMBOL(pci_scan_bus
);
1944 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
1945 * @bridge: PCI bridge for the bus to scan
1947 * Scan a PCI bus and child buses for new devices, add them,
1948 * and enable them, resizing bridge mmio/io resource if necessary
1949 * and possible. The caller must ensure the child devices are already
1950 * removed for resizing to occur.
1952 * Returns the max number of subordinate bus discovered.
1954 unsigned int __ref
pci_rescan_bus_bridge_resize(struct pci_dev
*bridge
)
1957 struct pci_bus
*bus
= bridge
->subordinate
;
1959 max
= pci_scan_child_bus(bus
);
1961 pci_assign_unassigned_bridge_resources(bridge
);
1963 pci_bus_add_devices(bus
);
1969 * pci_rescan_bus - scan a PCI bus for devices.
1970 * @bus: PCI bus to scan
1972 * Scan a PCI bus and child buses for new devices, adds them,
1975 * Returns the max number of subordinate bus discovered.
1977 unsigned int __ref
pci_rescan_bus(struct pci_bus
*bus
)
1981 max
= pci_scan_child_bus(bus
);
1982 pci_assign_unassigned_bus_resources(bus
);
1983 pci_enable_bridges(bus
);
1984 pci_bus_add_devices(bus
);
1988 EXPORT_SYMBOL_GPL(pci_rescan_bus
);
1990 EXPORT_SYMBOL(pci_add_new_bus
);
1991 EXPORT_SYMBOL(pci_scan_slot
);
1992 EXPORT_SYMBOL(pci_scan_bridge
);
1993 EXPORT_SYMBOL_GPL(pci_scan_child_bus
);
1995 static int __init
pci_sort_bf_cmp(const struct device
*d_a
, const struct device
*d_b
)
1997 const struct pci_dev
*a
= to_pci_dev(d_a
);
1998 const struct pci_dev
*b
= to_pci_dev(d_b
);
2000 if (pci_domain_nr(a
->bus
) < pci_domain_nr(b
->bus
)) return -1;
2001 else if (pci_domain_nr(a
->bus
) > pci_domain_nr(b
->bus
)) return 1;
2003 if (a
->bus
->number
< b
->bus
->number
) return -1;
2004 else if (a
->bus
->number
> b
->bus
->number
) return 1;
2006 if (a
->devfn
< b
->devfn
) return -1;
2007 else if (a
->devfn
> b
->devfn
) return 1;
2012 void __init
pci_sort_breadthfirst(void)
2014 bus_sort_breadthfirst(&pci_bus_type
, &pci_sort_bf_cmp
);