?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
PCI: Introduce new MSI chip infrastructure
[linux-2.6.git] / drivers / pci / probe.c
blobb8eaa81678490921493213f796faf923324e961d
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
13 #include <asm-generic/pci-bridge.h>
14 #include "pci.h"
15
16 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
17 #define CARDBUS_RESERVE_BUSNR 3
18
19 struct resource busn_resource = {
20 .name = "PCI busn",
21 .start = 0,
22 .end = 255,
23 .flags = IORESOURCE_BUS,
24 };
25
26 /* Ugh. Need to stop exporting this to modules. */
27 LIST_HEAD(pci_root_buses);
28 EXPORT_SYMBOL(pci_root_buses);
29
30 static LIST_HEAD(pci_domain_busn_res_list);
31
32 struct pci_domain_busn_res {
33 struct list_head list;
34 struct resource res;
35 int domain_nr;
36 };
37
38 static struct resource *get_pci_domain_busn_res(int domain_nr)
39 {
40 struct pci_domain_busn_res *r;
41
42 list_for_each_entry(r, &pci_domain_busn_res_list, list)
43 if (r->domain_nr == domain_nr)
44 return &r->res;
45
46 r = kzalloc(sizeof(*r), GFP_KERNEL);
47 if (!r)
48 return NULL;
49
50 r->domain_nr = domain_nr;
51 r->res.start = 0;
52 r->res.end = 0xff;
53 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
54
55 list_add_tail(&r->list, &pci_domain_busn_res_list);
56
57 return &r->res;
58 }
59
60 static int find_anything(struct device *dev, void *data)
61 {
62 return 1;
63 }
64
65 /*
66 * Some device drivers need know if pci is initiated.
67 * Basically, we think pci is not initiated when there
68 * is no device to be found on the pci_bus_type.
69 */
70 int no_pci_devices(void)
71 {
72 struct device *dev;
73 int no_devices;
74
75 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
76 no_devices = (dev == NULL);
77 put_device(dev);
78 return no_devices;
79 }
80 EXPORT_SYMBOL(no_pci_devices);
81
82 /*
83 * PCI Bus Class
84 */
85 static void release_pcibus_dev(struct device *dev)
86 {
87 struct pci_bus *pci_bus = to_pci_bus(dev);
88
89 if (pci_bus->bridge)
90 put_device(pci_bus->bridge);
91 pci_bus_remove_resources(pci_bus);
92 pci_release_bus_of_node(pci_bus);
93 kfree(pci_bus);
94 }
95
96 static struct class pcibus_class = {
97 .name = "pci_bus",
98 .dev_release = &release_pcibus_dev,
99 .dev_attrs = pcibus_dev_attrs,
100 };
101
102 static int __init pcibus_class_init(void)
103 {
104 return class_register(&pcibus_class);
105 }
106 postcore_initcall(pcibus_class_init);
107
108 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
109 {
110 u64 size = mask & maxbase; /* Find the significant bits */
111 if (!size)
112 return 0;
113
114 /* Get the lowest of them to find the decode size, and
115 from that the extent. */
116 size = (size & ~(size-1)) - 1;
117
118 /* base == maxbase can be valid only if the BAR has
119 already been programmed with all 1s. */
120 if (base == maxbase && ((base | size) & mask) != mask)
121 return 0;
122
123 return size;
124 }
125
126 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
127 {
128 u32 mem_type;
129 unsigned long flags;
130
131 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
132 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
133 flags |= IORESOURCE_IO;
134 return flags;
135 }
136
137 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
138 flags |= IORESOURCE_MEM;
139 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
140 flags |= IORESOURCE_PREFETCH;
141
142 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
143 switch (mem_type) {
144 case PCI_BASE_ADDRESS_MEM_TYPE_32:
145 break;
146 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
147 /* 1M mem BAR treated as 32-bit BAR */
148 break;
149 case PCI_BASE_ADDRESS_MEM_TYPE_64:
150 flags |= IORESOURCE_MEM_64;
151 break;
152 default:
153 /* mem unknown type treated as 32-bit BAR */
154 break;
155 }
156 return flags;
157 }
158
159 /**
160 * pci_read_base - read a PCI BAR
161 * @dev: the PCI device
162 * @type: type of the BAR
163 * @res: resource buffer to be filled in
164 * @pos: BAR position in the config space
165 *
166 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
167 */
168 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
169 struct resource *res, unsigned int pos)
170 {
171 u32 l, sz, mask;
172 u16 orig_cmd;
173 struct pci_bus_region region, inverted_region;
174 bool bar_too_big = false, bar_disabled = false;
175
176 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
177
178 /* No printks while decoding is disabled! */
179 if (!dev->mmio_always_on) {
180 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
181 pci_write_config_word(dev, PCI_COMMAND,
182 orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
183 }
184
185 res->name = pci_name(dev);
186
187 pci_read_config_dword(dev, pos, &l);
188 pci_write_config_dword(dev, pos, l | mask);
189 pci_read_config_dword(dev, pos, &sz);
190 pci_write_config_dword(dev, pos, l);
191
192 /*
193 * All bits set in sz means the device isn't working properly.
194 * If the BAR isn't implemented, all bits must be 0. If it's a
195 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
196 * 1 must be clear.
197 */
198 if (!sz || sz == 0xffffffff)
199 goto fail;
200
201 /*
202 * I don't know how l can have all bits set. Copied from old code.
203 * Maybe it fixes a bug on some ancient platform.
204 */
205 if (l == 0xffffffff)
206 l = 0;
207
208 if (type == pci_bar_unknown) {
209 res->flags = decode_bar(dev, l);
210 res->flags |= IORESOURCE_SIZEALIGN;
211 if (res->flags & IORESOURCE_IO) {
212 l &= PCI_BASE_ADDRESS_IO_MASK;
213 mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT;
214 } else {
215 l &= PCI_BASE_ADDRESS_MEM_MASK;
216 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
217 }
218 } else {
219 res->flags |= (l & IORESOURCE_ROM_ENABLE);
220 l &= PCI_ROM_ADDRESS_MASK;
221 mask = (u32)PCI_ROM_ADDRESS_MASK;
222 }
223
224 if (res->flags & IORESOURCE_MEM_64) {
225 u64 l64 = l;
226 u64 sz64 = sz;
227 u64 mask64 = mask | (u64)~0 << 32;
228
229 pci_read_config_dword(dev, pos + 4, &l);
230 pci_write_config_dword(dev, pos + 4, ~0);
231 pci_read_config_dword(dev, pos + 4, &sz);
232 pci_write_config_dword(dev, pos + 4, l);
233
234 l64 |= ((u64)l << 32);
235 sz64 |= ((u64)sz << 32);
236
237 sz64 = pci_size(l64, sz64, mask64);
238
239 if (!sz64)
240 goto fail;
241
242 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
243 bar_too_big = true;
244 goto fail;
245 }
246
247 if ((sizeof(resource_size_t) < 8) && l) {
248 /* Address above 32-bit boundary; disable the BAR */
249 pci_write_config_dword(dev, pos, 0);
250 pci_write_config_dword(dev, pos + 4, 0);
251 region.start = 0;
252 region.end = sz64;
253 bar_disabled = true;
254 } else {
255 region.start = l64;
256 region.end = l64 + sz64;
257 }
258 } else {
259 sz = pci_size(l, sz, mask);
260
261 if (!sz)
262 goto fail;
263
264 region.start = l;
265 region.end = l + sz;
266 }
267
268 pcibios_bus_to_resource(dev, res, &region);
269 pcibios_resource_to_bus(dev, &inverted_region, res);
270
271 /*
272 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
273 * the corresponding resource address (the physical address used by
274 * the CPU. Converting that resource address back to a bus address
275 * should yield the original BAR value:
276 *
277 * resource_to_bus(bus_to_resource(A)) == A
278 *
279 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
280 * be claimed by the device.
281 */
282 if (inverted_region.start != region.start) {
283 dev_info(&dev->dev, "reg 0x%x: initial BAR value %pa invalid; forcing reassignment\n",
284 pos, &region.start);
285 res->flags |= IORESOURCE_UNSET;
286 res->end -= res->start;
287 res->start = 0;
288 }
289
290 goto out;
291
292
293 fail:
294 res->flags = 0;
295 out:
296 if (!dev->mmio_always_on)
297 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
298
299 if (bar_too_big)
300 dev_err(&dev->dev, "reg 0x%x: can't handle 64-bit BAR\n", pos);
301 if (res->flags && !bar_disabled)
302 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
303
304 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
305 }
306
307 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
308 {
309 unsigned int pos, reg;
310
311 for (pos = 0; pos < howmany; pos++) {
312 struct resource *res = &dev->resource[pos];
313 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
314 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
315 }
316
317 if (rom) {
318 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
319 dev->rom_base_reg = rom;
320 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
321 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
322 IORESOURCE_SIZEALIGN;
323 __pci_read_base(dev, pci_bar_mem32, res, rom);
324 }
325 }
326
327 static void pci_read_bridge_io(struct pci_bus *child)
328 {
329 struct pci_dev *dev = child->self;
330 u8 io_base_lo, io_limit_lo;
331 unsigned long io_mask, io_granularity, base, limit;
332 struct pci_bus_region region;
333 struct resource *res;
334
335 io_mask = PCI_IO_RANGE_MASK;
336 io_granularity = 0x1000;
337 if (dev->io_window_1k) {
338 /* Support 1K I/O space granularity */
339 io_mask = PCI_IO_1K_RANGE_MASK;
340 io_granularity = 0x400;
341 }
342
343 res = child->resource[0];
344 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
345 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
346 base = (io_base_lo & io_mask) << 8;
347 limit = (io_limit_lo & io_mask) << 8;
348
349 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
350 u16 io_base_hi, io_limit_hi;
351
352 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
353 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
354 base |= ((unsigned long) io_base_hi << 16);
355 limit |= ((unsigned long) io_limit_hi << 16);
356 }
357
358 if (base <= limit) {
359 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
360 region.start = base;
361 region.end = limit + io_granularity - 1;
362 pcibios_bus_to_resource(dev, res, &region);
363 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
364 }
365 }
366
367 static void pci_read_bridge_mmio(struct pci_bus *child)
368 {
369 struct pci_dev *dev = child->self;
370 u16 mem_base_lo, mem_limit_lo;
371 unsigned long base, limit;
372 struct pci_bus_region region;
373 struct resource *res;
374
375 res = child->resource[1];
376 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
377 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
378 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
379 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
380 if (base <= limit) {
381 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
382 region.start = base;
383 region.end = limit + 0xfffff;
384 pcibios_bus_to_resource(dev, res, &region);
385 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
386 }
387 }
388
389 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
390 {
391 struct pci_dev *dev = child->self;
392 u16 mem_base_lo, mem_limit_lo;
393 unsigned long base, limit;
394 struct pci_bus_region region;
395 struct resource *res;
396
397 res = child->resource[2];
398 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
399 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
400 base = ((unsigned long) mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
401 limit = ((unsigned long) mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
402
403 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
404 u32 mem_base_hi, mem_limit_hi;
405
406 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
407 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
408
409 /*
410 * Some bridges set the base > limit by default, and some
411 * (broken) BIOSes do not initialize them. If we find
412 * this, just assume they are not being used.
413 */
414 if (mem_base_hi <= mem_limit_hi) {
415 #if BITS_PER_LONG == 64
416 base |= ((unsigned long) mem_base_hi) << 32;
417 limit |= ((unsigned long) mem_limit_hi) << 32;
418 #else
419 if (mem_base_hi || mem_limit_hi) {
420 dev_err(&dev->dev, "can't handle 64-bit "
421 "address space for bridge\n");
422 return;
423 }
424 #endif
425 }
426 }
427 if (base <= limit) {
428 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
429 IORESOURCE_MEM | IORESOURCE_PREFETCH;
430 if (res->flags & PCI_PREF_RANGE_TYPE_64)
431 res->flags |= IORESOURCE_MEM_64;
432 region.start = base;
433 region.end = limit + 0xfffff;
434 pcibios_bus_to_resource(dev, res, &region);
435 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
436 }
437 }
438
439 void pci_read_bridge_bases(struct pci_bus *child)
440 {
441 struct pci_dev *dev = child->self;
442 struct resource *res;
443 int i;
444
445 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
446 return;
447
448 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
449 &child->busn_res,
450 dev->transparent ? " (subtractive decode)" : "");
451
452 pci_bus_remove_resources(child);
453 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
454 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
455
456 pci_read_bridge_io(child);
457 pci_read_bridge_mmio(child);
458 pci_read_bridge_mmio_pref(child);
459
460 if (dev->transparent) {
461 pci_bus_for_each_resource(child->parent, res, i) {
462 if (res) {
463 pci_bus_add_resource(child, res,
464 PCI_SUBTRACTIVE_DECODE);
465 dev_printk(KERN_DEBUG, &dev->dev,
466 " bridge window %pR (subtractive decode)\n",
467 res);
468 }
469 }
470 }
471 }
472
473 static struct pci_bus *pci_alloc_bus(void)
474 {
475 struct pci_bus *b;
476
477 b = kzalloc(sizeof(*b), GFP_KERNEL);
478 if (!b)
479 return NULL;
480
481 INIT_LIST_HEAD(&b->node);
482 INIT_LIST_HEAD(&b->children);
483 INIT_LIST_HEAD(&b->devices);
484 INIT_LIST_HEAD(&b->slots);
485 INIT_LIST_HEAD(&b->resources);
486 b->max_bus_speed = PCI_SPEED_UNKNOWN;
487 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
488 return b;
489 }
490
491 static void pci_release_host_bridge_dev(struct device *dev)
492 {
493 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
494
495 if (bridge->release_fn)
496 bridge->release_fn(bridge);
497
498 pci_free_resource_list(&bridge->windows);
499
500 kfree(bridge);
501 }
502
503 static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
504 {
505 struct pci_host_bridge *bridge;
506
507 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
508 if (!bridge)
509 return NULL;
510
511 INIT_LIST_HEAD(&bridge->windows);
512 bridge->bus = b;
513 return bridge;
514 }
515
516 static unsigned char pcix_bus_speed[] = {
517 PCI_SPEED_UNKNOWN, /* 0 */
518 PCI_SPEED_66MHz_PCIX, /* 1 */
519 PCI_SPEED_100MHz_PCIX, /* 2 */
520 PCI_SPEED_133MHz_PCIX, /* 3 */
521 PCI_SPEED_UNKNOWN, /* 4 */
522 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
523 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
524 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
525 PCI_SPEED_UNKNOWN, /* 8 */
526 PCI_SPEED_66MHz_PCIX_266, /* 9 */
527 PCI_SPEED_100MHz_PCIX_266, /* A */
528 PCI_SPEED_133MHz_PCIX_266, /* B */
529 PCI_SPEED_UNKNOWN, /* C */
530 PCI_SPEED_66MHz_PCIX_533, /* D */
531 PCI_SPEED_100MHz_PCIX_533, /* E */
532 PCI_SPEED_133MHz_PCIX_533 /* F */
533 };
534
535 static unsigned char pcie_link_speed[] = {
536 PCI_SPEED_UNKNOWN, /* 0 */
537 PCIE_SPEED_2_5GT, /* 1 */
538 PCIE_SPEED_5_0GT, /* 2 */
539 PCIE_SPEED_8_0GT, /* 3 */
540 PCI_SPEED_UNKNOWN, /* 4 */
541 PCI_SPEED_UNKNOWN, /* 5 */
542 PCI_SPEED_UNKNOWN, /* 6 */
543 PCI_SPEED_UNKNOWN, /* 7 */
544 PCI_SPEED_UNKNOWN, /* 8 */
545 PCI_SPEED_UNKNOWN, /* 9 */
546 PCI_SPEED_UNKNOWN, /* A */
547 PCI_SPEED_UNKNOWN, /* B */
548 PCI_SPEED_UNKNOWN, /* C */
549 PCI_SPEED_UNKNOWN, /* D */
550 PCI_SPEED_UNKNOWN, /* E */
551 PCI_SPEED_UNKNOWN /* F */
552 };
553
554 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
555 {
556 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
557 }
558 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
559
560 static unsigned char agp_speeds[] = {
561 AGP_UNKNOWN,
562 AGP_1X,
563 AGP_2X,
564 AGP_4X,
565 AGP_8X
566 };
567
568 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
569 {
570 int index = 0;
571
572 if (agpstat & 4)
573 index = 3;
574 else if (agpstat & 2)
575 index = 2;
576 else if (agpstat & 1)
577 index = 1;
578 else
579 goto out;
580
581 if (agp3) {
582 index += 2;
583 if (index == 5)
584 index = 0;
585 }
586
587 out:
588 return agp_speeds[index];
589 }
590
591
592 static void pci_set_bus_speed(struct pci_bus *bus)
593 {
594 struct pci_dev *bridge = bus->self;
595 int pos;
596
597 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
598 if (!pos)
599 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
600 if (pos) {
601 u32 agpstat, agpcmd;
602
603 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
604 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
605
606 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
607 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
608 }
609
610 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
611 if (pos) {
612 u16 status;
613 enum pci_bus_speed max;
614
615 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
616 &status);
617
618 if (status & PCI_X_SSTATUS_533MHZ) {
619 max = PCI_SPEED_133MHz_PCIX_533;
620 } else if (status & PCI_X_SSTATUS_266MHZ) {
621 max = PCI_SPEED_133MHz_PCIX_266;
622 } else if (status & PCI_X_SSTATUS_133MHZ) {
623 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) {
624 max = PCI_SPEED_133MHz_PCIX_ECC;
625 } else {
626 max = PCI_SPEED_133MHz_PCIX;
627 }
628 } else {
629 max = PCI_SPEED_66MHz_PCIX;
630 }
631
632 bus->max_bus_speed = max;
633 bus->cur_bus_speed = pcix_bus_speed[
634 (status & PCI_X_SSTATUS_FREQ) >> 6];
635
636 return;
637 }
638
639 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
640 if (pos) {
641 u32 linkcap;
642 u16 linksta;
643
644 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
645 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
646
647 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
648 pcie_update_link_speed(bus, linksta);
649 }
650 }
651
652
653 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
654 struct pci_dev *bridge, int busnr)
655 {
656 struct pci_bus *child;
657 int i;
658 int ret;
659
660 /*
661 * Allocate a new bus, and inherit stuff from the parent..
662 */
663 child = pci_alloc_bus();
664 if (!child)
665 return NULL;
666
667 child->parent = parent;
668 child->ops = parent->ops;
669 child->msi = parent->msi;
670 child->sysdata = parent->sysdata;
671 child->bus_flags = parent->bus_flags;
672
673 /* initialize some portions of the bus device, but don't register it
674 * now as the parent is not properly set up yet.
675 */
676 child->dev.class = &pcibus_class;
677 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
678
679 /*
680 * Set up the primary, secondary and subordinate
681 * bus numbers.
682 */
683 child->number = child->busn_res.start = busnr;
684 child->primary = parent->busn_res.start;
685 child->busn_res.end = 0xff;
686
687 if (!bridge) {
688 child->dev.parent = parent->bridge;
689 goto add_dev;
690 }
691
692 child->self = bridge;
693 child->bridge = get_device(&bridge->dev);
694 child->dev.parent = child->bridge;
695 pci_set_bus_of_node(child);
696 pci_set_bus_speed(child);
697
698 /* Set up default resource pointers and names.. */
699 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
700 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
701 child->resource[i]->name = child->name;
702 }
703 bridge->subordinate = child;
704
705 add_dev:
706 ret = device_register(&child->dev);
707 WARN_ON(ret < 0);
708
709 pcibios_add_bus(child);
710
711 /* Create legacy_io and legacy_mem files for this bus */
712 pci_create_legacy_files(child);
713
714 return child;
715 }
716
717 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
718 {
719 struct pci_bus *child;
720
721 child = pci_alloc_child_bus(parent, dev, busnr);
722 if (child) {
723 down_write(&pci_bus_sem);
724 list_add_tail(&child->node, &parent->children);
725 up_write(&pci_bus_sem);
726 }
727 return child;
728 }
729
730 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
731 {
732 struct pci_bus *parent = child->parent;
733
734 /* Attempts to fix that up are really dangerous unless
735 we're going to re-assign all bus numbers. */
736 if (!pcibios_assign_all_busses())
737 return;
738
739 while (parent->parent && parent->busn_res.end < max) {
740 parent->busn_res.end = max;
741 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
742 parent = parent->parent;
743 }
744 }
745
746 /*
747 * If it's a bridge, configure it and scan the bus behind it.
748 * For CardBus bridges, we don't scan behind as the devices will
749 * be handled by the bridge driver itself.
750 *
751 * We need to process bridges in two passes -- first we scan those
752 * already configured by the BIOS and after we are done with all of
753 * them, we proceed to assigning numbers to the remaining buses in
754 * order to avoid overlaps between old and new bus numbers.
755 */
756 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
757 {
758 struct pci_bus *child;
759 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
760 u32 buses, i, j = 0;
761 u16 bctl;
762 u8 primary, secondary, subordinate;
763 int broken = 0;
764
765 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
766 primary = buses & 0xFF;
767 secondary = (buses >> 8) & 0xFF;
768 subordinate = (buses >> 16) & 0xFF;
769
770 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
771 secondary, subordinate, pass);
772
773 if (!primary && (primary != bus->number) && secondary && subordinate) {
774 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
775 primary = bus->number;
776 }
777
778 /* Check if setup is sensible at all */
779 if (!pass &&
780 (primary != bus->number || secondary <= bus->number ||
781 secondary > subordinate)) {
782 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
783 secondary, subordinate);
784 broken = 1;
785 }
786
787 /* Disable MasterAbortMode during probing to avoid reporting
788 of bus errors (in some architectures) */
789 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
790 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
791 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
792
793 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
794 !is_cardbus && !broken) {
795 unsigned int cmax;
796 /*
797 * Bus already configured by firmware, process it in the first
798 * pass and just note the configuration.
799 */
800 if (pass)
801 goto out;
802
803 /*
804 * If we already got to this bus through a different bridge,
805 * don't re-add it. This can happen with the i450NX chipset.
806 *
807 * However, we continue to descend down the hierarchy and
808 * scan remaining child buses.
809 */
810 child = pci_find_bus(pci_domain_nr(bus), secondary);
811 if (!child) {
812 child = pci_add_new_bus(bus, dev, secondary);
813 if (!child)
814 goto out;
815 child->primary = primary;
816 pci_bus_insert_busn_res(child, secondary, subordinate);
817 child->bridge_ctl = bctl;
818 }
819
820 cmax = pci_scan_child_bus(child);
821 if (cmax > max)
822 max = cmax;
823 if (child->busn_res.end > max)
824 max = child->busn_res.end;
825 } else {
826 /*
827 * We need to assign a number to this bus which we always
828 * do in the second pass.
829 */
830 if (!pass) {
831 if (pcibios_assign_all_busses() || broken)
832 /* Temporarily disable forwarding of the
833 configuration cycles on all bridges in
834 this bus segment to avoid possible
835 conflicts in the second pass between two
836 bridges programmed with overlapping
837 bus ranges. */
838 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
839 buses & ~0xffffff);
840 goto out;
841 }
842
843 /* Clear errors */
844 pci_write_config_word(dev, PCI_STATUS, 0xffff);
845
846 /* Prevent assigning a bus number that already exists.
847 * This can happen when a bridge is hot-plugged, so in
848 * this case we only re-scan this bus. */
849 child = pci_find_bus(pci_domain_nr(bus), max+1);
850 if (!child) {
851 child = pci_add_new_bus(bus, dev, ++max);
852 if (!child)
853 goto out;
854 pci_bus_insert_busn_res(child, max, 0xff);
855 }
856 buses = (buses & 0xff000000)
857 | ((unsigned int)(child->primary) << 0)
858 | ((unsigned int)(child->busn_res.start) << 8)
859 | ((unsigned int)(child->busn_res.end) << 16);
860
861 /*
862 * yenta.c forces a secondary latency timer of 176.
863 * Copy that behaviour here.
864 */
865 if (is_cardbus) {
866 buses &= ~0xff000000;
867 buses |= CARDBUS_LATENCY_TIMER << 24;
868 }
869
870 /*
871 * We need to blast all three values with a single write.
872 */
873 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
874
875 if (!is_cardbus) {
876 child->bridge_ctl = bctl;
877 /*
878 * Adjust subordinate busnr in parent buses.
879 * We do this before scanning for children because
880 * some devices may not be detected if the bios
881 * was lazy.
882 */
883 pci_fixup_parent_subordinate_busnr(child, max);
884 /* Now we can scan all subordinate buses... */
885 max = pci_scan_child_bus(child);
886 /*
887 * now fix it up again since we have found
888 * the real value of max.
889 */
890 pci_fixup_parent_subordinate_busnr(child, max);
891 } else {
892 /*
893 * For CardBus bridges, we leave 4 bus numbers
894 * as cards with a PCI-to-PCI bridge can be
895 * inserted later.
896 */
897 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
898 struct pci_bus *parent = bus;
899 if (pci_find_bus(pci_domain_nr(bus),
900 max+i+1))
901 break;
902 while (parent->parent) {
903 if ((!pcibios_assign_all_busses()) &&
904 (parent->busn_res.end > max) &&
905 (parent->busn_res.end <= max+i)) {
906 j = 1;
907 }
908 parent = parent->parent;
909 }
910 if (j) {
911 /*
912 * Often, there are two cardbus bridges
913 * -- try to leave one valid bus number
914 * for each one.
915 */
916 i /= 2;
917 break;
918 }
919 }
920 max += i;
921 pci_fixup_parent_subordinate_busnr(child, max);
922 }
923 /*
924 * Set the subordinate bus number to its real value.
925 */
926 pci_bus_update_busn_res_end(child, max);
927 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
928 }
929
930 sprintf(child->name,
931 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
932 pci_domain_nr(bus), child->number);
933
934 /* Has only triggered on CardBus, fixup is in yenta_socket */
935 while (bus->parent) {
936 if ((child->busn_res.end > bus->busn_res.end) ||
937 (child->number > bus->busn_res.end) ||
938 (child->number < bus->number) ||
939 (child->busn_res.end < bus->number)) {
940 dev_info(&child->dev, "%pR %s "
941 "hidden behind%s bridge %s %pR\n",
942 &child->busn_res,
943 (bus->number > child->busn_res.end &&
944 bus->busn_res.end < child->number) ?
945 "wholly" : "partially",
946 bus->self->transparent ? " transparent" : "",
947 dev_name(&bus->dev),
948 &bus->busn_res);
949 }
950 bus = bus->parent;
951 }
952
953 out:
954 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
955
956 return max;
957 }
958
959 /*
960 * Read interrupt line and base address registers.
961 * The architecture-dependent code can tweak these, of course.
962 */
963 static void pci_read_irq(struct pci_dev *dev)
964 {
965 unsigned char irq;
966
967 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
968 dev->pin = irq;
969 if (irq)
970 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
971 dev->irq = irq;
972 }
973
974 void set_pcie_port_type(struct pci_dev *pdev)
975 {
976 int pos;
977 u16 reg16;
978
979 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
980 if (!pos)
981 return;
982 pdev->is_pcie = 1;
983 pdev->pcie_cap = pos;
984 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
985 pdev->pcie_flags_reg = reg16;
986 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
987 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
988 }
989
990 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
991 {
992 u32 reg32;
993
994 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &reg32);
995 if (reg32 & PCI_EXP_SLTCAP_HPC)
996 pdev->is_hotplug_bridge = 1;
997 }
998
999 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1000
1001 /**
1002 * pci_setup_device - fill in class and map information of a device
1003 * @dev: the device structure to fill
1004 *
1005 * Initialize the device structure with information about the device's
1006 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1007 * Called at initialisation of the PCI subsystem and by CardBus services.
1008 * Returns 0 on success and negative if unknown type of device (not normal,
1009 * bridge or CardBus).
1010 */
1011 int pci_setup_device(struct pci_dev *dev)
1012 {
1013 u32 class;
1014 u8 hdr_type;
1015 struct pci_slot *slot;
1016 int pos = 0;
1017 struct pci_bus_region region;
1018 struct resource *res;
1019
1020 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1021 return -EIO;
1022
1023 dev->sysdata = dev->bus->sysdata;
1024 dev->dev.parent = dev->bus->bridge;
1025 dev->dev.bus = &pci_bus_type;
1026 dev->hdr_type = hdr_type & 0x7f;
1027 dev->multifunction = !!(hdr_type & 0x80);
1028 dev->error_state = pci_channel_io_normal;
1029 set_pcie_port_type(dev);
1030
1031 list_for_each_entry(slot, &dev->bus->slots, list)
1032 if (PCI_SLOT(dev->devfn) == slot->number)
1033 dev->slot = slot;
1034
1035 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1036 set this higher, assuming the system even supports it. */
1037 dev->dma_mask = 0xffffffff;
1038
1039 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1040 dev->bus->number, PCI_SLOT(dev->devfn),
1041 PCI_FUNC(dev->devfn));
1042
1043 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1044 dev->revision = class & 0xff;
1045 dev->class = class >> 8; /* upper 3 bytes */
1046
1047 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1048 dev->vendor, dev->device, dev->hdr_type, dev->class);
1049
1050 /* need to have dev->class ready */
1051 dev->cfg_size = pci_cfg_space_size(dev);
1052
1053 /* "Unknown power state" */
1054 dev->current_state = PCI_UNKNOWN;
1055
1056 /* Early fixups, before probing the BARs */
1057 pci_fixup_device(pci_fixup_early, dev);
1058 /* device class may be changed after fixup */
1059 class = dev->class >> 8;
1060
1061 switch (dev->hdr_type) { /* header type */
1062 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1063 if (class == PCI_CLASS_BRIDGE_PCI)
1064 goto bad;
1065 pci_read_irq(dev);
1066 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1067 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1068 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1069
1070 /*
1071 * Do the ugly legacy mode stuff here rather than broken chip
1072 * quirk code. Legacy mode ATA controllers have fixed
1073 * addresses. These are not always echoed in BAR0-3, and
1074 * BAR0-3 in a few cases contain junk!
1075 */
1076 if (class == PCI_CLASS_STORAGE_IDE) {
1077 u8 progif;
1078 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1079 if ((progif & 1) == 0) {
1080 region.start = 0x1F0;
1081 region.end = 0x1F7;
1082 res = &dev->resource[0];
1083 res->flags = LEGACY_IO_RESOURCE;
1084 pcibios_bus_to_resource(dev, res, &region);
1085 region.start = 0x3F6;
1086 region.end = 0x3F6;
1087 res = &dev->resource[1];
1088 res->flags = LEGACY_IO_RESOURCE;
1089 pcibios_bus_to_resource(dev, res, &region);
1090 }
1091 if ((progif & 4) == 0) {
1092 region.start = 0x170;
1093 region.end = 0x177;
1094 res = &dev->resource[2];
1095 res->flags = LEGACY_IO_RESOURCE;
1096 pcibios_bus_to_resource(dev, res, &region);
1097 region.start = 0x376;
1098 region.end = 0x376;
1099 res = &dev->resource[3];
1100 res->flags = LEGACY_IO_RESOURCE;
1101 pcibios_bus_to_resource(dev, res, &region);
1102 }
1103 }
1104 break;
1105
1106 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1107 if (class != PCI_CLASS_BRIDGE_PCI)
1108 goto bad;
1109 /* The PCI-to-PCI bridge spec requires that subtractive
1110 decoding (i.e. transparent) bridge must have programming
1111 interface code of 0x01. */
1112 pci_read_irq(dev);
1113 dev->transparent = ((dev->class & 0xff) == 1);
1114 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1115 set_pcie_hotplug_bridge(dev);
1116 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1117 if (pos) {
1118 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1119 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1120 }
1121 break;
1122
1123 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1124 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1125 goto bad;
1126 pci_read_irq(dev);
1127 pci_read_bases(dev, 1, 0);
1128 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1129 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1130 break;
1131
1132 default: /* unknown header */
1133 dev_err(&dev->dev, "unknown header type %02x, "
1134 "ignoring device\n", dev->hdr_type);
1135 return -EIO;
1136
1137 bad:
1138 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header "
1139 "type %02x)\n", dev->class, dev->hdr_type);
1140 dev->class = PCI_CLASS_NOT_DEFINED;
1141 }
1142
1143 /* We found a fine healthy device, go go go... */
1144 return 0;
1145 }
1146
1147 static void pci_release_capabilities(struct pci_dev *dev)
1148 {
1149 pci_vpd_release(dev);
1150 pci_iov_release(dev);
1151 pci_free_cap_save_buffers(dev);
1152 }
1153
1154 /**
1155 * pci_release_dev - free a pci device structure when all users of it are finished.
1156 * @dev: device that's been disconnected
1157 *
1158 * Will be called only by the device core when all users of this pci device are
1159 * done.
1160 */
1161 static void pci_release_dev(struct device *dev)
1162 {
1163 struct pci_dev *pci_dev;
1164
1165 pci_dev = to_pci_dev(dev);
1166 pci_release_capabilities(pci_dev);
1167 pci_release_of_node(pci_dev);
1168 pcibios_release_device(pci_dev);
1169 pci_bus_put(pci_dev->bus);
1170 kfree(pci_dev);
1171 }
1172
1173 /**
1174 * pci_cfg_space_size - get the configuration space size of the PCI device.
1175 * @dev: PCI device
1176 *
1177 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1178 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1179 * access it. Maybe we don't have a way to generate extended config space
1180 * accesses, or the device is behind a reverse Express bridge. So we try
1181 * reading the dword at 0x100 which must either be 0 or a valid extended
1182 * capability header.
1183 */
1184 int pci_cfg_space_size_ext(struct pci_dev *dev)
1185 {
1186 u32 status;
1187 int pos = PCI_CFG_SPACE_SIZE;
1188
1189 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1190 goto fail;
1191 if (status == 0xffffffff)
1192 goto fail;
1193
1194 return PCI_CFG_SPACE_EXP_SIZE;
1195
1196 fail:
1197 return PCI_CFG_SPACE_SIZE;
1198 }
1199
1200 int pci_cfg_space_size(struct pci_dev *dev)
1201 {
1202 int pos;
1203 u32 status;
1204 u16 class;
1205
1206 class = dev->class >> 8;
1207 if (class == PCI_CLASS_BRIDGE_HOST)
1208 return pci_cfg_space_size_ext(dev);
1209
1210 if (!pci_is_pcie(dev)) {
1211 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1212 if (!pos)
1213 goto fail;
1214
1215 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1216 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1217 goto fail;
1218 }
1219
1220 return pci_cfg_space_size_ext(dev);
1221
1222 fail:
1223 return PCI_CFG_SPACE_SIZE;
1224 }
1225
1226 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
1227 {
1228 struct pci_dev *dev;
1229
1230 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1231 if (!dev)
1232 return NULL;
1233
1234 INIT_LIST_HEAD(&dev->bus_list);
1235 dev->dev.type = &pci_dev_type;
1236 dev->bus = pci_bus_get(bus);
1237
1238 return dev;
1239 }
1240 EXPORT_SYMBOL(pci_alloc_dev);
1241
1242 struct pci_dev *alloc_pci_dev(void)
1243 {
1244 return pci_alloc_dev(NULL);
1245 }
1246 EXPORT_SYMBOL(alloc_pci_dev);
1247
1248 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1249 int crs_timeout)
1250 {
1251 int delay = 1;
1252
1253 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1254 return false;
1255
1256 /* some broken boards return 0 or ~0 if a slot is empty: */
1257 if (*l == 0xffffffff || *l == 0x00000000 ||
1258 *l == 0x0000ffff || *l == 0xffff0000)
1259 return false;
1260
1261 /* Configuration request Retry Status */
1262 while (*l == 0xffff0001) {
1263 if (!crs_timeout)
1264 return false;
1265
1266 msleep(delay);
1267 delay *= 2;
1268 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1269 return false;
1270 /* Card hasn't responded in 60 seconds? Must be stuck. */
1271 if (delay > crs_timeout) {
1272 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
1273 "responding\n", pci_domain_nr(bus),
1274 bus->number, PCI_SLOT(devfn),
1275 PCI_FUNC(devfn));
1276 return false;
1277 }
1278 }
1279
1280 return true;
1281 }
1282 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1283
1284 /*
1285 * Read the config data for a PCI device, sanity-check it
1286 * and fill in the dev structure...
1287 */
1288 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1289 {
1290 struct pci_dev *dev;
1291 u32 l;
1292
1293 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1294 return NULL;
1295
1296 dev = pci_alloc_dev(bus);
1297 if (!dev)
1298 return NULL;
1299
1300 dev->devfn = devfn;
1301 dev->vendor = l & 0xffff;
1302 dev->device = (l >> 16) & 0xffff;
1303
1304 pci_set_of_node(dev);
1305
1306 if (pci_setup_device(dev)) {
1307 pci_bus_put(dev->bus);
1308 kfree(dev);
1309 return NULL;
1310 }
1311
1312 return dev;
1313 }
1314
1315 static void pci_init_capabilities(struct pci_dev *dev)
1316 {
1317 /* MSI/MSI-X list */
1318 pci_msi_init_pci_dev(dev);
1319
1320 /* Buffers for saving PCIe and PCI-X capabilities */
1321 pci_allocate_cap_save_buffers(dev);
1322
1323 /* Power Management */
1324 pci_pm_init(dev);
1325
1326 /* Vital Product Data */
1327 pci_vpd_pci22_init(dev);
1328
1329 /* Alternative Routing-ID Forwarding */
1330 pci_configure_ari(dev);
1331
1332 /* Single Root I/O Virtualization */
1333 pci_iov_init(dev);
1334
1335 /* Enable ACS P2P upstream forwarding */
1336 pci_enable_acs(dev);
1337 }
1338
1339 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1340 {
1341 int ret;
1342
1343 device_initialize(&dev->dev);
1344 dev->dev.release = pci_release_dev;
1345
1346 set_dev_node(&dev->dev, pcibus_to_node(bus));
1347 dev->dev.dma_mask = &dev->dma_mask;
1348 dev->dev.dma_parms = &dev->dma_parms;
1349 dev->dev.coherent_dma_mask = 0xffffffffull;
1350
1351 pci_set_dma_max_seg_size(dev, 65536);
1352 pci_set_dma_seg_boundary(dev, 0xffffffff);
1353
1354 /* Fix up broken headers */
1355 pci_fixup_device(pci_fixup_header, dev);
1356
1357 /* moved out from quirk header fixup code */
1358 pci_reassigndev_resource_alignment(dev);
1359
1360 /* Clear the state_saved flag. */
1361 dev->state_saved = false;
1362
1363 /* Initialize various capabilities */
1364 pci_init_capabilities(dev);
1365
1366 /*
1367 * Add the device to our list of discovered devices
1368 * and the bus list for fixup functions, etc.
1369 */
1370 down_write(&pci_bus_sem);
1371 list_add_tail(&dev->bus_list, &bus->devices);
1372 up_write(&pci_bus_sem);
1373
1374 ret = pcibios_add_device(dev);
1375 WARN_ON(ret < 0);
1376
1377 /* Notifier could use PCI capabilities */
1378 dev->match_driver = false;
1379 ret = device_add(&dev->dev);
1380 WARN_ON(ret < 0);
1381
1382 pci_proc_attach_device(dev);
1383 }
1384
1385 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
1386 {
1387 struct pci_dev *dev;
1388
1389 dev = pci_get_slot(bus, devfn);
1390 if (dev) {
1391 pci_dev_put(dev);
1392 return dev;
1393 }
1394
1395 dev = pci_scan_device(bus, devfn);
1396 if (!dev)
1397 return NULL;
1398
1399 pci_device_add(dev, bus);
1400
1401 return dev;
1402 }
1403 EXPORT_SYMBOL(pci_scan_single_device);
1404
1405 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
1406 {
1407 int pos;
1408 u16 cap = 0;
1409 unsigned next_fn;
1410
1411 if (pci_ari_enabled(bus)) {
1412 if (!dev)
1413 return 0;
1414 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1415 if (!pos)
1416 return 0;
1417
1418 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
1419 next_fn = PCI_ARI_CAP_NFN(cap);
1420 if (next_fn <= fn)
1421 return 0; /* protect against malformed list */
1422
1423 return next_fn;
1424 }
1425
1426 /* dev may be NULL for non-contiguous multifunction devices */
1427 if (!dev || dev->multifunction)
1428 return (fn + 1) % 8;
1429
1430 return 0;
1431 }
1432
1433 static int only_one_child(struct pci_bus *bus)
1434 {
1435 struct pci_dev *parent = bus->self;
1436
1437 if (!parent || !pci_is_pcie(parent))
1438 return 0;
1439 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
1440 return 1;
1441 if (pci_pcie_type(parent) == PCI_EXP_TYPE_DOWNSTREAM &&
1442 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
1443 return 1;
1444 return 0;
1445 }
1446
1447 /**
1448 * pci_scan_slot - scan a PCI slot on a bus for devices.
1449 * @bus: PCI bus to scan
1450 * @devfn: slot number to scan (must have zero function.)
1451 *
1452 * Scan a PCI slot on the specified PCI bus for devices, adding
1453 * discovered devices to the @bus->devices list. New devices
1454 * will not have is_added set.
1455 *
1456 * Returns the number of new devices found.
1457 */
1458 int pci_scan_slot(struct pci_bus *bus, int devfn)
1459 {
1460 unsigned fn, nr = 0;
1461 struct pci_dev *dev;
1462
1463 if (only_one_child(bus) && (devfn > 0))
1464 return 0; /* Already scanned the entire slot */
1465
1466 dev = pci_scan_single_device(bus, devfn);
1467 if (!dev)
1468 return 0;
1469 if (!dev->is_added)
1470 nr++;
1471
1472 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
1473 dev = pci_scan_single_device(bus, devfn + fn);
1474 if (dev) {
1475 if (!dev->is_added)
1476 nr++;
1477 dev->multifunction = 1;
1478 }
1479 }
1480
1481 /* only one slot has pcie device */
1482 if (bus->self && nr)
1483 pcie_aspm_init_link_state(bus->self);
1484
1485 return nr;
1486 }
1487
1488 static int pcie_find_smpss(struct pci_dev *dev, void *data)
1489 {
1490 u8 *smpss = data;
1491
1492 if (!pci_is_pcie(dev))
1493 return 0;
1494
1495 /* For PCIE hotplug enabled slots not connected directly to a
1496 * PCI-E root port, there can be problems when hotplugging
1497 * devices. This is due to the possibility of hotplugging a
1498 * device into the fabric with a smaller MPS that the devices
1499 * currently running have configured. Modifying the MPS on the
1500 * running devices could cause a fatal bus error due to an
1501 * incoming frame being larger than the newly configured MPS.
1502 * To work around this, the MPS for the entire fabric must be
1503 * set to the minimum size. Any devices hotplugged into this
1504 * fabric will have the minimum MPS set. If the PCI hotplug
1505 * slot is directly connected to the root port and there are not
1506 * other devices on the fabric (which seems to be the most
1507 * common case), then this is not an issue and MPS discovery
1508 * will occur as normal.
1509 */
1510 if (dev->is_hotplug_bridge && (!list_is_singular(&dev->bus->devices) ||
1511 (dev->bus->self &&
1512 pci_pcie_type(dev->bus->self) != PCI_EXP_TYPE_ROOT_PORT)))
1513 *smpss = 0;
1514
1515 if (*smpss > dev->pcie_mpss)
1516 *smpss = dev->pcie_mpss;
1517
1518 return 0;
1519 }
1520
1521 static void pcie_write_mps(struct pci_dev *dev, int mps)
1522 {
1523 int rc;
1524
1525 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1526 mps = 128 << dev->pcie_mpss;
1527
1528 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
1529 dev->bus->self)
1530 /* For "Performance", the assumption is made that
1531 * downstream communication will never be larger than
1532 * the MRRS. So, the MPS only needs to be configured
1533 * for the upstream communication. This being the case,
1534 * walk from the top down and set the MPS of the child
1535 * to that of the parent bus.
1536 *
1537 * Configure the device MPS with the smaller of the
1538 * device MPSS or the bridge MPS (which is assumed to be
1539 * properly configured at this point to the largest
1540 * allowable MPS based on its parent bus).
1541 */
1542 mps = min(mps, pcie_get_mps(dev->bus->self));
1543 }
1544
1545 rc = pcie_set_mps(dev, mps);
1546 if (rc)
1547 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1548 }
1549
1550 static void pcie_write_mrrs(struct pci_dev *dev)
1551 {
1552 int rc, mrrs;
1553
1554 /* In the "safe" case, do not configure the MRRS. There appear to be
1555 * issues with setting MRRS to 0 on a number of devices.
1556 */
1557 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1558 return;
1559
1560 /* For Max performance, the MRRS must be set to the largest supported
1561 * value. However, it cannot be configured larger than the MPS the
1562 * device or the bus can support. This should already be properly
1563 * configured by a prior call to pcie_write_mps.
1564 */
1565 mrrs = pcie_get_mps(dev);
1566
1567 /* MRRS is a R/W register. Invalid values can be written, but a
1568 * subsequent read will verify if the value is acceptable or not.
1569 * If the MRRS value provided is not acceptable (e.g., too large),
1570 * shrink the value until it is acceptable to the HW.
1571 */
1572 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1573 rc = pcie_set_readrq(dev, mrrs);
1574 if (!rc)
1575 break;
1576
1577 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
1578 mrrs /= 2;
1579 }
1580
1581 if (mrrs < 128)
1582 dev_err(&dev->dev, "MRRS was unable to be configured with a "
1583 "safe value. If problems are experienced, try running "
1584 "with pci=pcie_bus_safe.\n");
1585 }
1586
1587 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1588 {
1589 int mps, orig_mps;
1590
1591 if (!pci_is_pcie(dev))
1592 return 0;
1593
1594 mps = 128 << *(u8 *)data;
1595 orig_mps = pcie_get_mps(dev);
1596
1597 pcie_write_mps(dev, mps);
1598 pcie_write_mrrs(dev);
1599
1600 dev_info(&dev->dev, "PCI-E Max Payload Size set to %4d/%4d (was %4d), "
1601 "Max Read Rq %4d\n", pcie_get_mps(dev), 128 << dev->pcie_mpss,
1602 orig_mps, pcie_get_readrq(dev));
1603
1604 return 0;
1605 }
1606
1607 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
1608 * parents then children fashion. If this changes, then this code will not
1609 * work as designed.
1610 */
1611 void pcie_bus_configure_settings(struct pci_bus *bus, u8 mpss)
1612 {
1613 u8 smpss;
1614
1615 if (!pci_is_pcie(bus->self))
1616 return;
1617
1618 if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
1619 return;
1620
1621 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1622 * to be aware to the MPS of the destination. To work around this,
1623 * simply force the MPS of the entire system to the smallest possible.
1624 */
1625 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1626 smpss = 0;
1627
1628 if (pcie_bus_config == PCIE_BUS_SAFE) {
1629 smpss = mpss;
1630
1631 pcie_find_smpss(bus->self, &smpss);
1632 pci_walk_bus(bus, pcie_find_smpss, &smpss);
1633 }
1634
1635 pcie_bus_configure_set(bus->self, &smpss);
1636 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
1637 }
1638 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
1639
1640 unsigned int pci_scan_child_bus(struct pci_bus *bus)
1641 {
1642 unsigned int devfn, pass, max = bus->busn_res.start;
1643 struct pci_dev *dev;
1644
1645 dev_dbg(&bus->dev, "scanning bus\n");
1646
1647 /* Go find them, Rover! */
1648 for (devfn = 0; devfn < 0x100; devfn += 8)
1649 pci_scan_slot(bus, devfn);
1650
1651 /* Reserve buses for SR-IOV capability. */
1652 max += pci_iov_bus_range(bus);
1653
1654 /*
1655 * After performing arch-dependent fixup of the bus, look behind
1656 * all PCI-to-PCI bridges on this bus.
1657 */
1658 if (!bus->is_added) {
1659 dev_dbg(&bus->dev, "fixups for bus\n");
1660 pcibios_fixup_bus(bus);
1661 bus->is_added = 1;
1662 }
1663
1664 for (pass=0; pass < 2; pass++)
1665 list_for_each_entry(dev, &bus->devices, bus_list) {
1666 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1667 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1668 max = pci_scan_bridge(bus, dev, max, pass);
1669 }
1670
1671 /*
1672 * We've scanned the bus and so we know all about what's on
1673 * the other side of any bridges that may be on this bus plus
1674 * any devices.
1675 *
1676 * Return how far we've got finding sub-buses.
1677 */
1678 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
1679 return max;
1680 }
1681
1682 /**
1683 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
1684 * @bridge: Host bridge to set up.
1685 *
1686 * Default empty implementation. Replace with an architecture-specific setup
1687 * routine, if necessary.
1688 */
1689 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
1690 {
1691 return 0;
1692 }
1693
1694 void __weak pcibios_add_bus(struct pci_bus *bus)
1695 {
1696 }
1697
1698 void __weak pcibios_remove_bus(struct pci_bus *bus)
1699 {
1700 }
1701
1702 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1703 struct pci_ops *ops, void *sysdata, struct list_head *resources)
1704 {
1705 int error;
1706 struct pci_host_bridge *bridge;
1707 struct pci_bus *b, *b2;
1708 struct pci_host_bridge_window *window, *n;
1709 struct resource *res;
1710 resource_size_t offset;
1711 char bus_addr[64];
1712 char *fmt;
1713
1714 b = pci_alloc_bus();
1715 if (!b)
1716 return NULL;
1717
1718 b->sysdata = sysdata;
1719 b->ops = ops;
1720 b->number = b->busn_res.start = bus;
1721 b2 = pci_find_bus(pci_domain_nr(b), bus);
1722 if (b2) {
1723 /* If we already got to this bus through a different bridge, ignore it */
1724 dev_dbg(&b2->dev, "bus already known\n");
1725 goto err_out;
1726 }
1727
1728 bridge = pci_alloc_host_bridge(b);
1729 if (!bridge)
1730 goto err_out;
1731
1732 bridge->dev.parent = parent;
1733 bridge->dev.release = pci_release_host_bridge_dev;
1734 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus);
1735 error = pcibios_root_bridge_prepare(bridge);
1736 if (error) {
1737 kfree(bridge);
1738 goto err_out;
1739 }
1740
1741 error = device_register(&bridge->dev);
1742 if (error) {
1743 put_device(&bridge->dev);
1744 goto err_out;
1745 }
1746 b->bridge = get_device(&bridge->dev);
1747 device_enable_async_suspend(b->bridge);
1748 pci_set_bus_of_node(b);
1749
1750 if (!parent)
1751 set_dev_node(b->bridge, pcibus_to_node(b));
1752
1753 b->dev.class = &pcibus_class;
1754 b->dev.parent = b->bridge;
1755 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
1756 error = device_register(&b->dev);
1757 if (error)
1758 goto class_dev_reg_err;
1759
1760 pcibios_add_bus(b);
1761
1762 /* Create legacy_io and legacy_mem files for this bus */
1763 pci_create_legacy_files(b);
1764
1765 if (parent)
1766 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
1767 else
1768 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
1769
1770 /* Add initial resources to the bus */
1771 list_for_each_entry_safe(window, n, resources, list) {
1772 list_move_tail(&window->list, &bridge->windows);
1773 res = window->res;
1774 offset = window->offset;
1775 if (res->flags & IORESOURCE_BUS)
1776 pci_bus_insert_busn_res(b, bus, res->end);
1777 else
1778 pci_bus_add_resource(b, res, 0);
1779 if (offset) {
1780 if (resource_type(res) == IORESOURCE_IO)
1781 fmt = " (bus address [%#06llx-%#06llx])";
1782 else
1783 fmt = " (bus address [%#010llx-%#010llx])";
1784 snprintf(bus_addr, sizeof(bus_addr), fmt,
1785 (unsigned long long) (res->start - offset),
1786 (unsigned long long) (res->end - offset));
1787 } else
1788 bus_addr[0] = '\0';
1789 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
1790 }
1791
1792 down_write(&pci_bus_sem);
1793 list_add_tail(&b->node, &pci_root_buses);
1794 up_write(&pci_bus_sem);
1795
1796 return b;
1797
1798 class_dev_reg_err:
1799 put_device(&bridge->dev);
1800 device_unregister(&bridge->dev);
1801 err_out:
1802 kfree(b);
1803 return NULL;
1804 }
1805
1806 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
1807 {
1808 struct resource *res = &b->busn_res;
1809 struct resource *parent_res, *conflict;
1810
1811 res->start = bus;
1812 res->end = bus_max;
1813 res->flags = IORESOURCE_BUS;
1814
1815 if (!pci_is_root_bus(b))
1816 parent_res = &b->parent->busn_res;
1817 else {
1818 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
1819 res->flags |= IORESOURCE_PCI_FIXED;
1820 }
1821
1822 conflict = insert_resource_conflict(parent_res, res);
1823
1824 if (conflict)
1825 dev_printk(KERN_DEBUG, &b->dev,
1826 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
1827 res, pci_is_root_bus(b) ? "domain " : "",
1828 parent_res, conflict->name, conflict);
1829
1830 return conflict == NULL;
1831 }
1832
1833 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
1834 {
1835 struct resource *res = &b->busn_res;
1836 struct resource old_res = *res;
1837 resource_size_t size;
1838 int ret;
1839
1840 if (res->start > bus_max)
1841 return -EINVAL;
1842
1843 size = bus_max - res->start + 1;
1844 ret = adjust_resource(res, res->start, size);
1845 dev_printk(KERN_DEBUG, &b->dev,
1846 "busn_res: %pR end %s updated to %02x\n",
1847 &old_res, ret ? "can not be" : "is", bus_max);
1848
1849 if (!ret && !res->parent)
1850 pci_bus_insert_busn_res(b, res->start, res->end);
1851
1852 return ret;
1853 }
1854
1855 void pci_bus_release_busn_res(struct pci_bus *b)
1856 {
1857 struct resource *res = &b->busn_res;
1858 int ret;
1859
1860 if (!res->flags || !res->parent)
1861 return;
1862
1863 ret = release_resource(res);
1864 dev_printk(KERN_DEBUG, &b->dev,
1865 "busn_res: %pR %s released\n",
1866 res, ret ? "can not be" : "is");
1867 }
1868
1869 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1870 struct pci_ops *ops, void *sysdata, struct list_head *resources)
1871 {
1872 struct pci_host_bridge_window *window;
1873 bool found = false;
1874 struct pci_bus *b;
1875 int max;
1876
1877 list_for_each_entry(window, resources, list)
1878 if (window->res->flags & IORESOURCE_BUS) {
1879 found = true;
1880 break;
1881 }
1882
1883 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
1884 if (!b)
1885 return NULL;
1886
1887 if (!found) {
1888 dev_info(&b->dev,
1889 "No busn resource found for root bus, will use [bus %02x-ff]\n",
1890 bus);
1891 pci_bus_insert_busn_res(b, bus, 255);
1892 }
1893
1894 max = pci_scan_child_bus(b);
1895
1896 if (!found)
1897 pci_bus_update_busn_res_end(b, max);
1898
1899 pci_bus_add_devices(b);
1900 return b;
1901 }
1902 EXPORT_SYMBOL(pci_scan_root_bus);
1903
1904 /* Deprecated; use pci_scan_root_bus() instead */
1905 struct pci_bus *pci_scan_bus_parented(struct device *parent,
1906 int bus, struct pci_ops *ops, void *sysdata)
1907 {
1908 LIST_HEAD(resources);
1909 struct pci_bus *b;
1910
1911 pci_add_resource(&resources, &ioport_resource);
1912 pci_add_resource(&resources, &iomem_resource);
1913 pci_add_resource(&resources, &busn_resource);
1914 b = pci_create_root_bus(parent, bus, ops, sysdata, &resources);
1915 if (b)
1916 pci_scan_child_bus(b);
1917 else
1918 pci_free_resource_list(&resources);
1919 return b;
1920 }
1921 EXPORT_SYMBOL(pci_scan_bus_parented);
1922
1923 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
1924 void *sysdata)
1925 {
1926 LIST_HEAD(resources);
1927 struct pci_bus *b;
1928
1929 pci_add_resource(&resources, &ioport_resource);
1930 pci_add_resource(&resources, &iomem_resource);
1931 pci_add_resource(&resources, &busn_resource);
1932 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
1933 if (b) {
1934 pci_scan_child_bus(b);
1935 pci_bus_add_devices(b);
1936 } else {
1937 pci_free_resource_list(&resources);
1938 }
1939 return b;
1940 }
1941 EXPORT_SYMBOL(pci_scan_bus);
1942
1943 /**
1944 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
1945 * @bridge: PCI bridge for the bus to scan
1946 *
1947 * Scan a PCI bus and child buses for new devices, add them,
1948 * and enable them, resizing bridge mmio/io resource if necessary
1949 * and possible. The caller must ensure the child devices are already
1950 * removed for resizing to occur.
1951 *
1952 * Returns the max number of subordinate bus discovered.
1953 */
1954 unsigned int __ref pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
1955 {
1956 unsigned int max;
1957 struct pci_bus *bus = bridge->subordinate;
1958
1959 max = pci_scan_child_bus(bus);
1960
1961 pci_assign_unassigned_bridge_resources(bridge);
1962
1963 pci_bus_add_devices(bus);
1964
1965 return max;
1966 }
1967
1968 /**
1969 * pci_rescan_bus - scan a PCI bus for devices.
1970 * @bus: PCI bus to scan
1971 *
1972 * Scan a PCI bus and child buses for new devices, adds them,
1973 * and enables them.
1974 *
1975 * Returns the max number of subordinate bus discovered.
1976 */
1977 unsigned int __ref pci_rescan_bus(struct pci_bus *bus)
1978 {
1979 unsigned int max;
1980
1981 max = pci_scan_child_bus(bus);
1982 pci_assign_unassigned_bus_resources(bus);
1983 pci_enable_bridges(bus);
1984 pci_bus_add_devices(bus);
1985
1986 return max;
1987 }
1988 EXPORT_SYMBOL_GPL(pci_rescan_bus);
1989
1990 EXPORT_SYMBOL(pci_add_new_bus);
1991 EXPORT_SYMBOL(pci_scan_slot);
1992 EXPORT_SYMBOL(pci_scan_bridge);
1993 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1994
1995 static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
1996 {
1997 const struct pci_dev *a = to_pci_dev(d_a);
1998 const struct pci_dev *b = to_pci_dev(d_b);
1999
2000 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2001 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2002
2003 if (a->bus->number < b->bus->number) return -1;
2004 else if (a->bus->number > b->bus->number) return 1;
2005
2006 if (a->devfn < b->devfn) return -1;
2007 else if (a->devfn > b->devfn) return 1;
2008
2009 return 0;
2010 }
2011
2012 void __init pci_sort_breadthfirst(void)
2013 {
2014 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
2015 }
Linus' kernel tree