2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
4 * Author: Thomas Abraham <thomas.ab@samsung.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Common Clock Framework support for Exynos5250 SoC.
13 #include <linux/clk.h>
14 #include <linux/clkdev.h>
15 #include <linux/clk-provider.h>
17 #include <linux/of_address.h>
23 #define DIV_CPU0 0x500
24 #define SRC_CORE1 0x4204
25 #define SRC_TOP0 0x10210
26 #define SRC_TOP2 0x10218
27 #define SRC_GSCL 0x10220
28 #define SRC_DISP1_0 0x1022c
29 #define SRC_MAU 0x10240
30 #define SRC_FSYS 0x10244
31 #define SRC_GEN 0x10248
32 #define SRC_PERIC0 0x10250
33 #define SRC_PERIC1 0x10254
34 #define SRC_MASK_GSCL 0x10320
35 #define SRC_MASK_DISP1_0 0x1032c
36 #define SRC_MASK_MAU 0x10334
37 #define SRC_MASK_FSYS 0x10340
38 #define SRC_MASK_GEN 0x10344
39 #define SRC_MASK_PERIC0 0x10350
40 #define SRC_MASK_PERIC1 0x10354
41 #define DIV_TOP0 0x10510
42 #define DIV_TOP1 0x10514
43 #define DIV_GSCL 0x10520
44 #define DIV_DISP1_0 0x1052c
45 #define DIV_GEN 0x1053c
46 #define DIV_MAU 0x10544
47 #define DIV_FSYS0 0x10548
48 #define DIV_FSYS1 0x1054c
49 #define DIV_FSYS2 0x10550
50 #define DIV_PERIC0 0x10558
51 #define DIV_PERIC1 0x1055c
52 #define DIV_PERIC2 0x10560
53 #define DIV_PERIC3 0x10564
54 #define DIV_PERIC4 0x10568
55 #define DIV_PERIC5 0x1056c
56 #define GATE_IP_GSCL 0x10920
57 #define GATE_IP_MFC 0x1092c
58 #define GATE_IP_GEN 0x10934
59 #define GATE_IP_FSYS 0x10944
60 #define GATE_IP_PERIC 0x10950
61 #define GATE_IP_PERIS 0x10960
62 #define SRC_CDREX 0x20200
63 #define PLL_DIV2_SEL 0x20a24
64 #define GATE_IP_DISP1 0x10928
67 * Let each supported clock get a unique id. This id is used to lookup the clock
68 * for device tree based platforms. The clocks are categorized into three
69 * sections: core, sclk gate and bus interface gate clocks.
71 * When adding a new clock to this list, it is advised to choose a clock
72 * category and add it to the end of that category. That is because the the
73 * device tree source file is referring to these ids and any change in the
74 * sequence number of existing clocks will require corresponding change in the
75 * device tree files. This limitation would go away when pre-processor support
76 * for dtc would be available.
78 enum exynos5250_clks
{
84 /* gate for special clocks (sclk) */
85 sclk_cam_bayer
= 128, sclk_cam0
, sclk_cam1
, sclk_gscl_wa
, sclk_gscl_wb
,
86 sclk_fimd1
, sclk_mipi1
, sclk_dp
, sclk_hdmi
, sclk_pixel
, sclk_audio0
,
87 sclk_mmc0
, sclk_mmc1
, sclk_mmc2
, sclk_mmc3
, sclk_sata
, sclk_usb3
,
88 sclk_jpeg
, sclk_uart0
, sclk_uart1
, sclk_uart2
, sclk_uart3
, sclk_pwm
,
89 sclk_audio1
, sclk_audio2
, sclk_spdif
, sclk_spi0
, sclk_spi1
, sclk_spi2
,
93 gscl0
= 256, gscl1
, gscl2
, gscl3
, gscl_wa
, gscl_wb
, smmu_gscl0
,
94 smmu_gscl1
, smmu_gscl2
, smmu_gscl3
, mfc
, smmu_mfcl
, smmu_mfcr
, rotator
,
95 jpeg
, mdma1
, smmu_rotator
, smmu_jpeg
, smmu_mdma1
, pdma0
, pdma1
, sata
,
96 usbotg
, mipi_hsi
, sdmmc0
, sdmmc1
, sdmmc2
, sdmmc3
, sromc
, usb2
, usb3
,
97 sata_phyctrl
, sata_phyi2c
, uart0
, uart1
, uart2
, uart3
, uart4
, i2c0
,
98 i2c1
, i2c2
, i2c3
, i2c4
, i2c5
, i2c6
, i2c7
, i2c_hdmi
, adc
, spi0
, spi1
,
99 spi2
, i2s1
, i2s2
, pcm1
, pcm2
, pwm
, spdif
, ac97
, hsi2c0
, hsi2c1
, hsi2c2
,
100 hsi2c3
, chipid
, sysreg
, pmu
, cmu_top
, cmu_core
, cmu_mem
, tzpc0
, tzpc1
,
101 tzpc2
, tzpc3
, tzpc4
, tzpc5
, tzpc6
, tzpc7
, tzpc8
, tzpc9
, hdmi_cec
, mct
,
102 wdt
, rtc
, tmu
, fimd1
, mie1
, dsim0
, dp
, mixer
, hdmi
,
108 * list of controller registers to be saved and restored during a
109 * suspend/resume cycle.
111 static __initdata
unsigned long exynos5250_clk_regs
[] = {
157 /* list of all parent clock list */
158 PNAME(mout_apll_p
) = { "fin_pll", "fout_apll", };
159 PNAME(mout_cpu_p
) = { "mout_apll", "sclk_mpll", };
160 PNAME(mout_mpll_fout_p
) = { "fout_mplldiv2", "fout_mpll" };
161 PNAME(mout_mpll_p
) = { "fin_pll", "mout_mpll_fout" };
162 PNAME(mout_bpll_fout_p
) = { "fout_bplldiv2", "fout_bpll" };
163 PNAME(mout_bpll_p
) = { "fin_pll", "mout_bpll_fout" };
164 PNAME(mout_vpllsrc_p
) = { "fin_pll", "sclk_hdmi27m" };
165 PNAME(mout_vpll_p
) = { "mout_vpllsrc", "fout_vpll" };
166 PNAME(mout_cpll_p
) = { "fin_pll", "fout_cpll" };
167 PNAME(mout_epll_p
) = { "fin_pll", "fout_epll" };
168 PNAME(mout_mpll_user_p
) = { "fin_pll", "sclk_mpll" };
169 PNAME(mout_bpll_user_p
) = { "fin_pll", "sclk_bpll" };
170 PNAME(mout_aclk166_p
) = { "sclk_cpll", "sclk_mpll_user" };
171 PNAME(mout_aclk200_p
) = { "sclk_mpll_user", "sclk_bpll_user" };
172 PNAME(mout_hdmi_p
) = { "div_hdmi_pixel", "sclk_hdmiphy" };
173 PNAME(mout_usb3_p
) = { "sclk_mpll_user", "sclk_cpll" };
174 PNAME(mout_group1_p
) = { "fin_pll", "fin_pll", "sclk_hdmi27m",
175 "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy",
176 "sclk_mpll_user", "sclk_epll", "sclk_vpll",
178 PNAME(mout_audio0_p
) = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
179 "sclk_uhostphy", "sclk_hdmiphy",
180 "sclk_mpll_user", "sclk_epll", "sclk_vpll",
182 PNAME(mout_audio1_p
) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
183 "sclk_uhostphy", "sclk_hdmiphy",
184 "sclk_mpll_user", "sclk_epll", "sclk_vpll",
186 PNAME(mout_audio2_p
) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
187 "sclk_uhostphy", "sclk_hdmiphy",
188 "sclk_mpll_user", "sclk_epll", "sclk_vpll",
190 PNAME(mout_spdif_p
) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
193 /* fixed rate clocks generated outside the soc */
194 struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks
[] __initdata
= {
195 FRATE(fin_pll
, "fin_pll", NULL
, CLK_IS_ROOT
, 0),
198 /* fixed rate clocks generated inside the soc */
199 struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks
[] __initdata
= {
200 FRATE(none
, "sclk_hdmiphy", NULL
, CLK_IS_ROOT
, 24000000),
201 FRATE(none
, "sclk_hdmi27m", NULL
, CLK_IS_ROOT
, 27000000),
202 FRATE(none
, "sclk_dptxphy", NULL
, CLK_IS_ROOT
, 24000000),
203 FRATE(none
, "sclk_uhostphy", NULL
, CLK_IS_ROOT
, 48000000),
206 struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks
[] __initdata
= {
207 FFACTOR(none
, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
208 FFACTOR(none
, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
211 struct samsung_mux_clock exynos5250_mux_clks
[] __initdata
= {
212 MUX_A(none
, "mout_apll", mout_apll_p
, SRC_CPU
, 0, 1, "mout_apll"),
213 MUX_A(none
, "mout_cpu", mout_cpu_p
, SRC_CPU
, 16, 1, "mout_cpu"),
214 MUX(none
, "mout_mpll_fout", mout_mpll_fout_p
, PLL_DIV2_SEL
, 4, 1),
215 MUX_A(none
, "sclk_mpll", mout_mpll_p
, SRC_CORE1
, 8, 1, "mout_mpll"),
216 MUX(none
, "mout_bpll_fout", mout_bpll_fout_p
, PLL_DIV2_SEL
, 0, 1),
217 MUX(none
, "sclk_bpll", mout_bpll_p
, SRC_CDREX
, 0, 1),
218 MUX(none
, "mout_vpllsrc", mout_vpllsrc_p
, SRC_TOP2
, 0, 1),
219 MUX(none
, "sclk_vpll", mout_vpll_p
, SRC_TOP2
, 16, 1),
220 MUX(none
, "sclk_epll", mout_epll_p
, SRC_TOP2
, 12, 1),
221 MUX(none
, "sclk_cpll", mout_cpll_p
, SRC_TOP2
, 8, 1),
222 MUX(none
, "sclk_mpll_user", mout_mpll_user_p
, SRC_TOP2
, 20, 1),
223 MUX(none
, "sclk_bpll_user", mout_bpll_user_p
, SRC_TOP2
, 24, 1),
224 MUX(none
, "mout_aclk166", mout_aclk166_p
, SRC_TOP0
, 8, 1),
225 MUX(none
, "mout_aclk333", mout_aclk166_p
, SRC_TOP0
, 16, 1),
226 MUX(none
, "mout_aclk200", mout_aclk200_p
, SRC_TOP0
, 12, 1),
227 MUX(none
, "mout_cam_bayer", mout_group1_p
, SRC_GSCL
, 12, 4),
228 MUX(none
, "mout_cam0", mout_group1_p
, SRC_GSCL
, 16, 4),
229 MUX(none
, "mout_cam1", mout_group1_p
, SRC_GSCL
, 20, 4),
230 MUX(none
, "mout_gscl_wa", mout_group1_p
, SRC_GSCL
, 24, 4),
231 MUX(none
, "mout_gscl_wb", mout_group1_p
, SRC_GSCL
, 28, 4),
232 MUX(none
, "mout_fimd1", mout_group1_p
, SRC_DISP1_0
, 0, 4),
233 MUX(none
, "mout_mipi1", mout_group1_p
, SRC_DISP1_0
, 12, 4),
234 MUX(none
, "mout_dp", mout_group1_p
, SRC_DISP1_0
, 16, 4),
235 MUX(none
, "mout_hdmi", mout_hdmi_p
, SRC_DISP1_0
, 20, 1),
236 MUX(none
, "mout_audio0", mout_audio0_p
, SRC_MAU
, 0, 4),
237 MUX(none
, "mout_mmc0", mout_group1_p
, SRC_FSYS
, 0, 4),
238 MUX(none
, "mout_mmc1", mout_group1_p
, SRC_FSYS
, 4, 4),
239 MUX(none
, "mout_mmc2", mout_group1_p
, SRC_FSYS
, 8, 4),
240 MUX(none
, "mout_mmc3", mout_group1_p
, SRC_FSYS
, 12, 4),
241 MUX(none
, "mout_sata", mout_aclk200_p
, SRC_FSYS
, 24, 1),
242 MUX(none
, "mout_usb3", mout_usb3_p
, SRC_FSYS
, 28, 1),
243 MUX(none
, "mout_jpeg", mout_group1_p
, SRC_GEN
, 0, 4),
244 MUX(none
, "mout_uart0", mout_group1_p
, SRC_PERIC0
, 0, 4),
245 MUX(none
, "mout_uart1", mout_group1_p
, SRC_PERIC0
, 4, 4),
246 MUX(none
, "mout_uart2", mout_group1_p
, SRC_PERIC0
, 8, 4),
247 MUX(none
, "mout_uart3", mout_group1_p
, SRC_PERIC0
, 12, 4),
248 MUX(none
, "mout_pwm", mout_group1_p
, SRC_PERIC0
, 24, 4),
249 MUX(none
, "mout_audio1", mout_audio1_p
, SRC_PERIC1
, 0, 4),
250 MUX(none
, "mout_audio2", mout_audio2_p
, SRC_PERIC1
, 4, 4),
251 MUX(none
, "mout_spdif", mout_spdif_p
, SRC_PERIC1
, 8, 2),
252 MUX(none
, "mout_spi0", mout_group1_p
, SRC_PERIC1
, 16, 4),
253 MUX(none
, "mout_spi1", mout_group1_p
, SRC_PERIC1
, 20, 4),
254 MUX(none
, "mout_spi2", mout_group1_p
, SRC_PERIC1
, 24, 4),
257 struct samsung_div_clock exynos5250_div_clks
[] __initdata
= {
258 DIV(none
, "div_arm", "mout_cpu", DIV_CPU0
, 0, 3),
259 DIV(none
, "sclk_apll", "mout_apll", DIV_CPU0
, 24, 3),
260 DIV(none
, "aclk66_pre", "sclk_mpll_user", DIV_TOP1
, 24, 3),
261 DIV(none
, "aclk66", "aclk66_pre", DIV_TOP0
, 0, 3),
262 DIV(none
, "aclk266", "sclk_mpll_user", DIV_TOP0
, 16, 3),
263 DIV(none
, "aclk166", "mout_aclk166", DIV_TOP0
, 8, 3),
264 DIV(none
, "aclk333", "mout_aclk333", DIV_TOP0
, 20, 3),
265 DIV(none
, "aclk200", "mout_aclk200", DIV_TOP0
, 12, 3),
266 DIV(none
, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL
, 12, 4),
267 DIV(none
, "div_cam0", "mout_cam0", DIV_GSCL
, 16, 4),
268 DIV(none
, "div_cam1", "mout_cam1", DIV_GSCL
, 20, 4),
269 DIV(none
, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL
, 24, 4),
270 DIV(none
, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL
, 28, 4),
271 DIV(none
, "div_fimd1", "mout_fimd1", DIV_DISP1_0
, 0, 4),
272 DIV(none
, "div_mipi1", "mout_mipi1", DIV_DISP1_0
, 16, 4),
273 DIV(none
, "div_dp", "mout_dp", DIV_DISP1_0
, 24, 4),
274 DIV(none
, "div_jpeg", "mout_jpeg", DIV_GEN
, 4, 4),
275 DIV(none
, "div_audio0", "mout_audio0", DIV_MAU
, 0, 4),
276 DIV(none
, "div_pcm0", "sclk_audio0", DIV_MAU
, 4, 8),
277 DIV(none
, "div_sata", "mout_sata", DIV_FSYS0
, 20, 4),
278 DIV(none
, "div_usb3", "mout_usb3", DIV_FSYS0
, 24, 4),
279 DIV(none
, "div_mmc0", "mout_mmc0", DIV_FSYS1
, 0, 4),
280 DIV(none
, "div_mmc1", "mout_mmc1", DIV_FSYS1
, 16, 4),
281 DIV(none
, "div_mmc2", "mout_mmc2", DIV_FSYS2
, 0, 4),
282 DIV(none
, "div_mmc3", "mout_mmc3", DIV_FSYS2
, 16, 4),
283 DIV(none
, "div_uart0", "mout_uart0", DIV_PERIC0
, 0, 4),
284 DIV(none
, "div_uart1", "mout_uart1", DIV_PERIC0
, 4, 4),
285 DIV(none
, "div_uart2", "mout_uart2", DIV_PERIC0
, 8, 4),
286 DIV(none
, "div_uart3", "mout_uart3", DIV_PERIC0
, 12, 4),
287 DIV(none
, "div_spi0", "mout_spi0", DIV_PERIC1
, 0, 4),
288 DIV(none
, "div_spi1", "mout_spi1", DIV_PERIC1
, 16, 4),
289 DIV(none
, "div_spi2", "mout_spi2", DIV_PERIC2
, 0, 4),
290 DIV(none
, "div_pwm", "mout_pwm", DIV_PERIC3
, 0, 4),
291 DIV(none
, "div_audio1", "mout_audio1", DIV_PERIC4
, 0, 4),
292 DIV(none
, "div_pcm1", "sclk_audio1", DIV_PERIC4
, 4, 8),
293 DIV(none
, "div_audio2", "mout_audio2", DIV_PERIC4
, 16, 4),
294 DIV(none
, "div_pcm2", "sclk_audio2", DIV_PERIC4
, 20, 8),
295 DIV(div_i2s1
, "div_i2s1", "sclk_audio1", DIV_PERIC5
, 0, 6),
296 DIV(div_i2s2
, "div_i2s2", "sclk_audio2", DIV_PERIC5
, 8, 6),
297 DIV(sclk_pixel
, "div_hdmi_pixel", "sclk_vpll", DIV_DISP1_0
, 28, 4),
298 DIV_A(none
, "armclk", "div_arm", DIV_CPU0
, 28, 3, "armclk"),
299 DIV_F(none
, "div_mipi1_pre", "div_mipi1",
300 DIV_DISP1_0
, 20, 4, CLK_SET_RATE_PARENT
, 0),
301 DIV_F(none
, "div_mmc_pre0", "div_mmc0",
302 DIV_FSYS1
, 8, 8, CLK_SET_RATE_PARENT
, 0),
303 DIV_F(none
, "div_mmc_pre1", "div_mmc1",
304 DIV_FSYS1
, 24, 8, CLK_SET_RATE_PARENT
, 0),
305 DIV_F(none
, "div_mmc_pre2", "div_mmc2",
306 DIV_FSYS2
, 8, 8, CLK_SET_RATE_PARENT
, 0),
307 DIV_F(none
, "div_mmc_pre3", "div_mmc3",
308 DIV_FSYS2
, 24, 8, CLK_SET_RATE_PARENT
, 0),
309 DIV_F(none
, "div_spi_pre0", "div_spi0",
310 DIV_PERIC1
, 8, 8, CLK_SET_RATE_PARENT
, 0),
311 DIV_F(none
, "div_spi_pre1", "div_spi1",
312 DIV_PERIC1
, 24, 8, CLK_SET_RATE_PARENT
, 0),
313 DIV_F(none
, "div_spi_pre2", "div_spi2",
314 DIV_PERIC2
, 8, 8, CLK_SET_RATE_PARENT
, 0),
317 struct samsung_gate_clock exynos5250_gate_clks
[] __initdata
= {
318 GATE(gscl0
, "gscl0", "none", GATE_IP_GSCL
, 0, 0, 0),
319 GATE(gscl1
, "gscl1", "none", GATE_IP_GSCL
, 1, 0, 0),
320 GATE(gscl2
, "gscl2", "aclk266", GATE_IP_GSCL
, 2, 0, 0),
321 GATE(gscl3
, "gscl3", "aclk266", GATE_IP_GSCL
, 3, 0, 0),
322 GATE(gscl_wa
, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL
, 5, 0, 0),
323 GATE(gscl_wb
, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL
, 6, 0, 0),
324 GATE(smmu_gscl0
, "smmu_gscl0", "aclk266", GATE_IP_GSCL
, 7, 0, 0),
325 GATE(smmu_gscl1
, "smmu_gscl1", "aclk266", GATE_IP_GSCL
, 8, 0, 0),
326 GATE(smmu_gscl2
, "smmu_gscl2", "aclk266", GATE_IP_GSCL
, 9, 0, 0),
327 GATE(smmu_gscl3
, "smmu_gscl3", "aclk266", GATE_IP_GSCL
, 10, 0, 0),
328 GATE(mfc
, "mfc", "aclk333", GATE_IP_MFC
, 0, 0, 0),
329 GATE(smmu_mfcl
, "smmu_mfcl", "aclk333", GATE_IP_MFC
, 1, 0, 0),
330 GATE(smmu_mfcr
, "smmu_mfcr", "aclk333", GATE_IP_MFC
, 2, 0, 0),
331 GATE(rotator
, "rotator", "aclk266", GATE_IP_GEN
, 1, 0, 0),
332 GATE(jpeg
, "jpeg", "aclk166", GATE_IP_GEN
, 2, 0, 0),
333 GATE(mdma1
, "mdma1", "aclk266", GATE_IP_GEN
, 4, 0, 0),
334 GATE(smmu_rotator
, "smmu_rotator", "aclk266", GATE_IP_GEN
, 6, 0, 0),
335 GATE(smmu_jpeg
, "smmu_jpeg", "aclk166", GATE_IP_GEN
, 7, 0, 0),
336 GATE(smmu_mdma1
, "smmu_mdma1", "aclk266", GATE_IP_GEN
, 9, 0, 0),
337 GATE(pdma0
, "pdma0", "aclk200", GATE_IP_FSYS
, 1, 0, 0),
338 GATE(pdma1
, "pdma1", "aclk200", GATE_IP_FSYS
, 2, 0, 0),
339 GATE(sata
, "sata", "aclk200", GATE_IP_FSYS
, 6, 0, 0),
340 GATE(usbotg
, "usbotg", "aclk200", GATE_IP_FSYS
, 7, 0, 0),
341 GATE(mipi_hsi
, "mipi_hsi", "aclk200", GATE_IP_FSYS
, 8, 0, 0),
342 GATE(sdmmc0
, "sdmmc0", "aclk200", GATE_IP_FSYS
, 12, 0, 0),
343 GATE(sdmmc1
, "sdmmc1", "aclk200", GATE_IP_FSYS
, 13, 0, 0),
344 GATE(sdmmc2
, "sdmmc2", "aclk200", GATE_IP_FSYS
, 14, 0, 0),
345 GATE(sdmmc3
, "sdmmc3", "aclk200", GATE_IP_FSYS
, 15, 0, 0),
346 GATE(sromc
, "sromc", "aclk200", GATE_IP_FSYS
, 17, 0, 0),
347 GATE(usb2
, "usb2", "aclk200", GATE_IP_FSYS
, 18, 0, 0),
348 GATE(usb3
, "usb3", "aclk200", GATE_IP_FSYS
, 19, 0, 0),
349 GATE(sata_phyctrl
, "sata_phyctrl", "aclk200", GATE_IP_FSYS
, 24, 0, 0),
350 GATE(sata_phyi2c
, "sata_phyi2c", "aclk200", GATE_IP_FSYS
, 25, 0, 0),
351 GATE(uart0
, "uart0", "aclk66", GATE_IP_PERIC
, 0, 0, 0),
352 GATE(uart1
, "uart1", "aclk66", GATE_IP_PERIC
, 1, 0, 0),
353 GATE(uart2
, "uart2", "aclk66", GATE_IP_PERIC
, 2, 0, 0),
354 GATE(uart3
, "uart3", "aclk66", GATE_IP_PERIC
, 3, 0, 0),
355 GATE(uart4
, "uart4", "aclk66", GATE_IP_PERIC
, 4, 0, 0),
356 GATE(i2c0
, "i2c0", "aclk66", GATE_IP_PERIC
, 6, 0, 0),
357 GATE(i2c1
, "i2c1", "aclk66", GATE_IP_PERIC
, 7, 0, 0),
358 GATE(i2c2
, "i2c2", "aclk66", GATE_IP_PERIC
, 8, 0, 0),
359 GATE(i2c3
, "i2c3", "aclk66", GATE_IP_PERIC
, 9, 0, 0),
360 GATE(i2c4
, "i2c4", "aclk66", GATE_IP_PERIC
, 10, 0, 0),
361 GATE(i2c5
, "i2c5", "aclk66", GATE_IP_PERIC
, 11, 0, 0),
362 GATE(i2c6
, "i2c6", "aclk66", GATE_IP_PERIC
, 12, 0, 0),
363 GATE(i2c7
, "i2c7", "aclk66", GATE_IP_PERIC
, 13, 0, 0),
364 GATE(i2c_hdmi
, "i2c_hdmi", "aclk66", GATE_IP_PERIC
, 14, 0, 0),
365 GATE(adc
, "adc", "aclk66", GATE_IP_PERIC
, 15, 0, 0),
366 GATE(spi0
, "spi0", "aclk66", GATE_IP_PERIC
, 16, 0, 0),
367 GATE(spi1
, "spi1", "aclk66", GATE_IP_PERIC
, 17, 0, 0),
368 GATE(spi2
, "spi2", "aclk66", GATE_IP_PERIC
, 18, 0, 0),
369 GATE(i2s1
, "i2s1", "aclk66", GATE_IP_PERIC
, 20, 0, 0),
370 GATE(i2s2
, "i2s2", "aclk66", GATE_IP_PERIC
, 21, 0, 0),
371 GATE(pcm1
, "pcm1", "aclk66", GATE_IP_PERIC
, 22, 0, 0),
372 GATE(pcm2
, "pcm2", "aclk66", GATE_IP_PERIC
, 23, 0, 0),
373 GATE(pwm
, "pwm", "aclk66", GATE_IP_PERIC
, 24, 0, 0),
374 GATE(spdif
, "spdif", "aclk66", GATE_IP_PERIC
, 26, 0, 0),
375 GATE(ac97
, "ac97", "aclk66", GATE_IP_PERIC
, 27, 0, 0),
376 GATE(hsi2c0
, "hsi2c0", "aclk66", GATE_IP_PERIC
, 28, 0, 0),
377 GATE(hsi2c1
, "hsi2c1", "aclk66", GATE_IP_PERIC
, 29, 0, 0),
378 GATE(hsi2c2
, "hsi2c2", "aclk66", GATE_IP_PERIC
, 30, 0, 0),
379 GATE(hsi2c3
, "hsi2c3", "aclk66", GATE_IP_PERIC
, 31, 0, 0),
380 GATE(chipid
, "chipid", "aclk66", GATE_IP_PERIS
, 0, 0, 0),
381 GATE(sysreg
, "sysreg", "aclk66", GATE_IP_PERIS
, 1, 0, 0),
382 GATE(pmu
, "pmu", "aclk66", GATE_IP_PERIS
, 2, CLK_IGNORE_UNUSED
, 0),
383 GATE(tzpc0
, "tzpc0", "aclk66", GATE_IP_PERIS
, 6, 0, 0),
384 GATE(tzpc1
, "tzpc1", "aclk66", GATE_IP_PERIS
, 7, 0, 0),
385 GATE(tzpc2
, "tzpc2", "aclk66", GATE_IP_PERIS
, 8, 0, 0),
386 GATE(tzpc3
, "tzpc3", "aclk66", GATE_IP_PERIS
, 9, 0, 0),
387 GATE(tzpc4
, "tzpc4", "aclk66", GATE_IP_PERIS
, 10, 0, 0),
388 GATE(tzpc5
, "tzpc5", "aclk66", GATE_IP_PERIS
, 11, 0, 0),
389 GATE(tzpc6
, "tzpc6", "aclk66", GATE_IP_PERIS
, 12, 0, 0),
390 GATE(tzpc7
, "tzpc7", "aclk66", GATE_IP_PERIS
, 13, 0, 0),
391 GATE(tzpc8
, "tzpc8", "aclk66", GATE_IP_PERIS
, 14, 0, 0),
392 GATE(tzpc9
, "tzpc9", "aclk66", GATE_IP_PERIS
, 15, 0, 0),
393 GATE(hdmi_cec
, "hdmi_cec", "aclk66", GATE_IP_PERIS
, 16, 0, 0),
394 GATE(mct
, "mct", "aclk66", GATE_IP_PERIS
, 18, 0, 0),
395 GATE(wdt
, "wdt", "aclk66", GATE_IP_PERIS
, 19, 0, 0),
396 GATE(rtc
, "rtc", "aclk66", GATE_IP_PERIS
, 20, 0, 0),
397 GATE(tmu
, "tmu", "aclk66", GATE_IP_PERIS
, 21, 0, 0),
398 GATE(cmu_top
, "cmu_top", "aclk66",
399 GATE_IP_PERIS
, 3, CLK_IGNORE_UNUSED
, 0),
400 GATE(cmu_core
, "cmu_core", "aclk66",
401 GATE_IP_PERIS
, 4, CLK_IGNORE_UNUSED
, 0),
402 GATE(cmu_mem
, "cmu_mem", "aclk66",
403 GATE_IP_PERIS
, 5, CLK_IGNORE_UNUSED
, 0),
404 GATE(sclk_cam_bayer
, "sclk_cam_bayer", "div_cam_bayer",
405 SRC_MASK_GSCL
, 12, CLK_SET_RATE_PARENT
, 0),
406 GATE(sclk_cam0
, "sclk_cam0", "div_cam0",
407 SRC_MASK_GSCL
, 16, CLK_SET_RATE_PARENT
, 0),
408 GATE(sclk_cam1
, "sclk_cam1", "div_cam1",
409 SRC_MASK_GSCL
, 20, CLK_SET_RATE_PARENT
, 0),
410 GATE(sclk_gscl_wa
, "sclk_gscl_wa", "div_gscl_wa",
411 SRC_MASK_GSCL
, 24, CLK_SET_RATE_PARENT
, 0),
412 GATE(sclk_gscl_wb
, "sclk_gscl_wb", "div_gscl_wb",
413 SRC_MASK_GSCL
, 28, CLK_SET_RATE_PARENT
, 0),
414 GATE(sclk_fimd1
, "sclk_fimd1", "div_fimd1",
415 SRC_MASK_DISP1_0
, 0, CLK_SET_RATE_PARENT
, 0),
416 GATE(sclk_mipi1
, "sclk_mipi1", "div_mipi1",
417 SRC_MASK_DISP1_0
, 12, CLK_SET_RATE_PARENT
, 0),
418 GATE(sclk_dp
, "sclk_dp", "div_dp",
419 SRC_MASK_DISP1_0
, 16, CLK_SET_RATE_PARENT
, 0),
420 GATE(sclk_hdmi
, "sclk_hdmi", "mout_hdmi",
421 SRC_MASK_DISP1_0
, 20, 0, 0),
422 GATE(sclk_audio0
, "sclk_audio0", "div_audio0",
423 SRC_MASK_MAU
, 0, CLK_SET_RATE_PARENT
, 0),
424 GATE(sclk_mmc0
, "sclk_mmc0", "div_mmc_pre0",
425 SRC_MASK_FSYS
, 0, CLK_SET_RATE_PARENT
, 0),
426 GATE(sclk_mmc1
, "sclk_mmc1", "div_mmc_pre1",
427 SRC_MASK_FSYS
, 4, CLK_SET_RATE_PARENT
, 0),
428 GATE(sclk_mmc2
, "sclk_mmc2", "div_mmc_pre2",
429 SRC_MASK_FSYS
, 8, CLK_SET_RATE_PARENT
, 0),
430 GATE(sclk_mmc3
, "sclk_mmc3", "div_mmc_pre3",
431 SRC_MASK_FSYS
, 12, CLK_SET_RATE_PARENT
, 0),
432 GATE(sclk_sata
, "sclk_sata", "div_sata",
433 SRC_MASK_FSYS
, 24, CLK_SET_RATE_PARENT
, 0),
434 GATE(sclk_usb3
, "sclk_usb3", "div_usb3",
435 SRC_MASK_FSYS
, 28, CLK_SET_RATE_PARENT
, 0),
436 GATE(sclk_jpeg
, "sclk_jpeg", "div_jpeg",
437 SRC_MASK_GEN
, 0, CLK_SET_RATE_PARENT
, 0),
438 GATE(sclk_uart0
, "sclk_uart0", "div_uart0",
439 SRC_MASK_PERIC0
, 0, CLK_SET_RATE_PARENT
, 0),
440 GATE(sclk_uart1
, "sclk_uart1", "div_uart1",
441 SRC_MASK_PERIC0
, 4, CLK_SET_RATE_PARENT
, 0),
442 GATE(sclk_uart2
, "sclk_uart2", "div_uart2",
443 SRC_MASK_PERIC0
, 8, CLK_SET_RATE_PARENT
, 0),
444 GATE(sclk_uart3
, "sclk_uart3", "div_uart3",
445 SRC_MASK_PERIC0
, 12, CLK_SET_RATE_PARENT
, 0),
446 GATE(sclk_pwm
, "sclk_pwm", "div_pwm",
447 SRC_MASK_PERIC0
, 24, CLK_SET_RATE_PARENT
, 0),
448 GATE(sclk_audio1
, "sclk_audio1", "div_audio1",
449 SRC_MASK_PERIC1
, 0, CLK_SET_RATE_PARENT
, 0),
450 GATE(sclk_audio2
, "sclk_audio2", "div_audio2",
451 SRC_MASK_PERIC1
, 4, CLK_SET_RATE_PARENT
, 0),
452 GATE(sclk_spdif
, "sclk_spdif", "mout_spdif",
453 SRC_MASK_PERIC1
, 4, 0, 0),
454 GATE(sclk_spi0
, "sclk_spi0", "div_spi_pre0",
455 SRC_MASK_PERIC1
, 16, CLK_SET_RATE_PARENT
, 0),
456 GATE(sclk_spi1
, "sclk_spi1", "div_spi_pre1",
457 SRC_MASK_PERIC1
, 20, CLK_SET_RATE_PARENT
, 0),
458 GATE(sclk_spi2
, "sclk_spi2", "div_spi_pre2",
459 SRC_MASK_PERIC1
, 24, CLK_SET_RATE_PARENT
, 0),
460 GATE(fimd1
, "fimd1", "aclk200", GATE_IP_DISP1
, 0, 0, 0),
461 GATE(mie1
, "mie1", "aclk200", GATE_IP_DISP1
, 1, 0, 0),
462 GATE(dsim0
, "dsim0", "aclk200", GATE_IP_DISP1
, 3, 0, 0),
463 GATE(dp
, "dp", "aclk200", GATE_IP_DISP1
, 4, 0, 0),
464 GATE(mixer
, "mixer", "aclk200", GATE_IP_DISP1
, 5, 0, 0),
465 GATE(hdmi
, "hdmi", "aclk200", GATE_IP_DISP1
, 6, 0, 0),
468 static __initdata
struct of_device_id ext_clk_match
[] = {
469 { .compatible
= "samsung,clock-xxti", .data
= (void *)0, },
473 /* register exynox5250 clocks */
474 void __init
exynos5250_clk_init(struct device_node
*np
)
476 void __iomem
*reg_base
;
477 struct clk
*apll
, *mpll
, *epll
, *vpll
, *bpll
, *gpll
, *cpll
;
480 reg_base
= of_iomap(np
, 0);
482 panic("%s: failed to map registers\n", __func__
);
484 panic("%s: unable to determine soc\n", __func__
);
487 samsung_clk_init(np
, reg_base
, nr_clks
,
488 exynos5250_clk_regs
, ARRAY_SIZE(exynos5250_clk_regs
),
490 samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks
,
491 ARRAY_SIZE(exynos5250_fixed_rate_ext_clks
),
494 apll
= samsung_clk_register_pll35xx("fout_apll", "fin_pll",
496 mpll
= samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
498 bpll
= samsung_clk_register_pll35xx("fout_bpll", "fin_pll",
500 gpll
= samsung_clk_register_pll35xx("fout_gpll", "fin_pll",
502 cpll
= samsung_clk_register_pll35xx("fout_cpll", "fin_pll",
504 epll
= samsung_clk_register_pll36xx("fout_epll", "fin_pll",
506 vpll
= samsung_clk_register_pll36xx("fout_vpll", "mout_vpllsrc",
509 samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks
,
510 ARRAY_SIZE(exynos5250_fixed_rate_clks
));
511 samsung_clk_register_fixed_factor(exynos5250_fixed_factor_clks
,
512 ARRAY_SIZE(exynos5250_fixed_factor_clks
));
513 samsung_clk_register_mux(exynos5250_mux_clks
,
514 ARRAY_SIZE(exynos5250_mux_clks
));
515 samsung_clk_register_div(exynos5250_div_clks
,
516 ARRAY_SIZE(exynos5250_div_clks
));
517 samsung_clk_register_gate(exynos5250_gate_clks
,
518 ARRAY_SIZE(exynos5250_gate_clks
));
520 pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
521 _get_rate("armclk"));
523 CLK_OF_DECLARE(exynos5250_clk
, "samsung,exynos5250-clock", exynos5250_clk_init
);