arch/arm/mach-omap2/cm3xxx.h

   1 /*
   2  * OMAP2/3 Clock Management (CM) register definitions
   3  *
   4  * Copyright (C) 2007-2009 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2010 Nokia Corporation
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * The CM hardware modules on the OMAP2/3 are quite similar to each
  13  * other.  The CM modules/instances on OMAP4 are quite different, so
  14  * they are handled in a separate file.
  15  */
  16 #ifndef __ARCH_ASM_MACH_OMAP2_CM3XXX_H
  17 #define __ARCH_ASM_MACH_OMAP2_CM3XXX_H
  18
  19 #include "prcm-common.h"
  20 #include "cm2xxx_3xxx.h"
  21
  22 #define OMAP34XX_CM_REGADDR(module, reg)                                \
  23                         OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
  24
  25
  26 /*
  27  * OMAP3-specific global CM registers
  28  * Use cm_{read,write}_reg() with these registers.
  29  * These registers appear once per CM module.
  30  */
  31
  32 #define OMAP3430_CM_REVISION            OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
  33 #define OMAP3430_CM_SYSCONFIG           OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
  34 #define OMAP3430_CM_POLCTRL             OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
  35
  36 #define OMAP3_CM_CLKOUT_CTRL_OFFSET     0x0070
  37 #define OMAP3430_CM_CLKOUT_CTRL         OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
  38
  39 /*
  40  * Module specific CM register offsets from CM_BASE + domain offset
  41  * Use cm_{read,write}_mod_reg() with these registers.
  42  * These register offsets generally appear in more than one PRCM submodule.
  43  */
  44
  45 /* OMAP3-specific register offsets */
  46
  47 #define OMAP3430_CM_CLKEN_PLL                           0x0004
  48 #define OMAP3430ES2_CM_CLKEN2                           0x0004
  49 #define OMAP3430ES2_CM_FCLKEN3                          0x0008
  50 #define OMAP3430_CM_IDLEST_PLL                          CM_IDLEST2
  51 #define OMAP3430_CM_AUTOIDLE_PLL                        CM_AUTOIDLE2
  52 #define OMAP3430ES2_CM_AUTOIDLE2_PLL                    CM_AUTOIDLE2
  53 #define OMAP3430_CM_CLKSEL1                             CM_CLKSEL
  54 #define OMAP3430_CM_CLKSEL1_PLL                         CM_CLKSEL
  55 #define OMAP3430_CM_CLKSEL2_PLL                         CM_CLKSEL2
  56 #define OMAP3430_CM_SLEEPDEP                            CM_CLKSEL2
  57 #define OMAP3430_CM_CLKSEL3                             OMAP2_CM_CLKSTCTRL
  58 #define OMAP3430_CM_CLKSTST                             0x004c
  59 #define OMAP3430ES2_CM_CLKSEL4                          0x004c
  60 #define OMAP3430ES2_CM_CLKSEL5                          0x0050
  61 #define OMAP3430_CM_CLKSEL2_EMU                         0x0050
  62 #define OMAP3430_CM_CLKSEL3_EMU                         0x0054
  63
  64
  65 /* CM_IDLEST bit field values to indicate deasserted IdleReq */
  66
  67 #define OMAP34XX_CM_IDLEST_VAL                          1
  68
  69
  70 #ifndef __ASSEMBLER__
  71
  72 extern void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
  73 extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
  74 extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask);
  75 extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
  76
  77 extern bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask);
  78 extern int omap3xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
  79                                          u8 idlest_shift);
  80
  81 extern int omap3xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
  82                                         s16 *prcm_inst, u8 *idlest_reg_id);
  83
  84 extern void omap3_cm_save_context(void);
  85 extern void omap3_cm_restore_context(void);
  86
  87 extern int __init omap3xxx_cm_init(void);
  88
  89 #endif
  90
  91 #endif