| blob | 669ef51b17a8e12cd73b09f9e9724dda4c09d71c |
1 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
2 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
4 /*
5 * OMAP24XX Clock Management register bits
6 *
7 * Copyright (C) 2007 Texas Instruments, Inc.
8 * Copyright (C) 2007 Nokia Corporation
9 *
10 * Written by Paul Walmsley
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
17 /* Bits shared between registers */
19 /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
20 #define OMAP24XX_EN_CAM_SHIFT 31
21 #define OMAP24XX_EN_CAM_MASK (1 << 31)
22 #define OMAP24XX_EN_WDT4_SHIFT 29
23 #define OMAP24XX_EN_WDT4_MASK (1 << 29)
24 #define OMAP2420_EN_WDT3_SHIFT 28
25 #define OMAP2420_EN_WDT3_MASK (1 << 28)
26 #define OMAP24XX_EN_MSPRO_SHIFT 27
27 #define OMAP24XX_EN_MSPRO_MASK (1 << 27)
28 #define OMAP24XX_EN_FAC_SHIFT 25
29 #define OMAP24XX_EN_FAC_MASK (1 << 25)
30 #define OMAP2420_EN_EAC_SHIFT 24
31 #define OMAP2420_EN_EAC_MASK (1 << 24)
32 #define OMAP24XX_EN_HDQ_SHIFT 23
33 #define OMAP24XX_EN_HDQ_MASK (1 << 23)
34 #define OMAP2420_EN_I2C2_SHIFT 20
35 #define OMAP2420_EN_I2C2_MASK (1 << 20)
36 #define OMAP2420_EN_I2C1_SHIFT 19
37 #define OMAP2420_EN_I2C1_MASK (1 << 19)
39 /* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */
40 #define OMAP2430_EN_MCBSP5_SHIFT 5
41 #define OMAP2430_EN_MCBSP5_MASK (1 << 5)
42 #define OMAP2430_EN_MCBSP4_SHIFT 4
43 #define OMAP2430_EN_MCBSP4_MASK (1 << 4)
44 #define OMAP2430_EN_MCBSP3_SHIFT 3
45 #define OMAP2430_EN_MCBSP3_MASK (1 << 3)
46 #define OMAP24XX_EN_SSI_SHIFT 1
47 #define OMAP24XX_EN_SSI_MASK (1 << 1)
49 /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
50 #define OMAP24XX_EN_MPU_WDT_SHIFT 3
51 #define OMAP24XX_EN_MPU_WDT_MASK (1 << 3)
53 /* Bits specific to each register */
55 /* CM_IDLEST_MPU */
56 /* 2430 only */
57 #define OMAP2430_ST_MPU_MASK (1 << 0)
59 /* CM_CLKSEL_MPU */
60 #define OMAP24XX_CLKSEL_MPU_SHIFT 0
61 #define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0)
62 #define OMAP24XX_CLKSEL_MPU_WIDTH 5
64 /* CM_CLKSTCTRL_MPU */
65 #define OMAP24XX_AUTOSTATE_MPU_SHIFT 0
66 #define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0)
68 /* CM_FCLKEN1_CORE specific bits*/
69 #define OMAP24XX_EN_TV_SHIFT 2
70 #define OMAP24XX_EN_TV_MASK (1 << 2)
71 #define OMAP24XX_EN_DSS2_SHIFT 1
72 #define OMAP24XX_EN_DSS2_MASK (1 << 1)
73 #define OMAP24XX_EN_DSS1_SHIFT 0
74 #define OMAP24XX_EN_DSS1_MASK (1 << 0)
76 /* CM_FCLKEN2_CORE specific bits */
77 #define OMAP2430_EN_I2CHS2_SHIFT 20
78 #define OMAP2430_EN_I2CHS2_MASK (1 << 20)
79 #define OMAP2430_EN_I2CHS1_SHIFT 19
80 #define OMAP2430_EN_I2CHS1_MASK (1 << 19)
81 #define OMAP2430_EN_MMCHSDB2_SHIFT 17
82 #define OMAP2430_EN_MMCHSDB2_MASK (1 << 17)
83 #define OMAP2430_EN_MMCHSDB1_SHIFT 16
84 #define OMAP2430_EN_MMCHSDB1_MASK (1 << 16)
86 /* CM_ICLKEN1_CORE specific bits */
87 #define OMAP24XX_EN_MAILBOXES_SHIFT 30
88 #define OMAP24XX_EN_MAILBOXES_MASK (1 << 30)
89 #define OMAP24XX_EN_DSS_SHIFT 0
90 #define OMAP24XX_EN_DSS_MASK (1 << 0)
92 /* CM_ICLKEN2_CORE specific bits */
94 /* CM_ICLKEN3_CORE */
95 /* 2430 only */
96 #define OMAP2430_EN_SDRC_SHIFT 2
97 #define OMAP2430_EN_SDRC_MASK (1 << 2)
99 /* CM_ICLKEN4_CORE */
100 #define OMAP24XX_EN_PKA_SHIFT 4
101 #define OMAP24XX_EN_PKA_MASK (1 << 4)
102 #define OMAP24XX_EN_AES_SHIFT 3
103 #define OMAP24XX_EN_AES_MASK (1 << 3)
104 #define OMAP24XX_EN_RNG_SHIFT 2
105 #define OMAP24XX_EN_RNG_MASK (1 << 2)
106 #define OMAP24XX_EN_SHA_SHIFT 1
107 #define OMAP24XX_EN_SHA_MASK (1 << 1)
108 #define OMAP24XX_EN_DES_SHIFT 0
109 #define OMAP24XX_EN_DES_MASK (1 << 0)
111 /* CM_IDLEST1_CORE specific bits */
112 #define OMAP24XX_ST_MAILBOXES_SHIFT 30
113 #define OMAP24XX_ST_MAILBOXES_MASK (1 << 30)
114 #define OMAP24XX_ST_WDT4_SHIFT 29
115 #define OMAP24XX_ST_WDT4_MASK (1 << 29)
116 #define OMAP2420_ST_WDT3_SHIFT 28
117 #define OMAP2420_ST_WDT3_MASK (1 << 28)
118 #define OMAP24XX_ST_MSPRO_SHIFT 27
119 #define OMAP24XX_ST_MSPRO_MASK (1 << 27)
120 #define OMAP24XX_ST_FAC_SHIFT 25
121 #define OMAP24XX_ST_FAC_MASK (1 << 25)
122 #define OMAP2420_ST_EAC_SHIFT 24
123 #define OMAP2420_ST_EAC_MASK (1 << 24)
124 #define OMAP24XX_ST_HDQ_SHIFT 23
125 #define OMAP24XX_ST_HDQ_MASK (1 << 23)
126 #define OMAP2420_ST_I2C2_SHIFT 20
127 #define OMAP2420_ST_I2C2_MASK (1 << 20)
128 #define OMAP2430_ST_I2CHS1_SHIFT 19
129 #define OMAP2430_ST_I2CHS1_MASK (1 << 19)
130 #define OMAP2420_ST_I2C1_SHIFT 19
131 #define OMAP2420_ST_I2C1_MASK (1 << 19)
132 #define OMAP2430_ST_I2CHS2_SHIFT 20
133 #define OMAP2430_ST_I2CHS2_MASK (1 << 20)
134 #define OMAP24XX_ST_MCBSP2_SHIFT 16
135 #define OMAP24XX_ST_MCBSP2_MASK (1 << 16)
136 #define OMAP24XX_ST_MCBSP1_SHIFT 15
137 #define OMAP24XX_ST_MCBSP1_MASK (1 << 15)
138 #define OMAP24XX_ST_DSS_SHIFT 0
139 #define OMAP24XX_ST_DSS_MASK (1 << 0)
141 /* CM_IDLEST2_CORE */
142 #define OMAP2430_ST_MCBSP5_SHIFT 5
143 #define OMAP2430_ST_MCBSP5_MASK (1 << 5)
144 #define OMAP2430_ST_MCBSP4_SHIFT 4
145 #define OMAP2430_ST_MCBSP4_MASK (1 << 4)
146 #define OMAP2430_ST_MCBSP3_SHIFT 3
147 #define OMAP2430_ST_MCBSP3_MASK (1 << 3)
148 #define OMAP24XX_ST_SSI_SHIFT 1
149 #define OMAP24XX_ST_SSI_MASK (1 << 1)
151 /* CM_IDLEST3_CORE */
152 /* 2430 only */
153 #define OMAP2430_ST_SDRC_MASK (1 << 2)
155 /* CM_IDLEST4_CORE */
156 #define OMAP24XX_ST_PKA_SHIFT 4
157 #define OMAP24XX_ST_PKA_MASK (1 << 4)
158 #define OMAP24XX_ST_AES_SHIFT 3
159 #define OMAP24XX_ST_AES_MASK (1 << 3)
160 #define OMAP24XX_ST_RNG_SHIFT 2
161 #define OMAP24XX_ST_RNG_MASK (1 << 2)
162 #define OMAP24XX_ST_SHA_SHIFT 1
163 #define OMAP24XX_ST_SHA_MASK (1 << 1)
164 #define OMAP24XX_ST_DES_SHIFT 0
165 #define OMAP24XX_ST_DES_MASK (1 << 0)
167 /* CM_AUTOIDLE1_CORE */
168 #define OMAP24XX_AUTO_CAM_MASK (1 << 31)
169 #define OMAP24XX_AUTO_MAILBOXES_MASK (1 << 30)
170 #define OMAP24XX_AUTO_WDT4_MASK (1 << 29)
171 #define OMAP2420_AUTO_WDT3_MASK (1 << 28)
172 #define OMAP24XX_AUTO_MSPRO_MASK (1 << 27)
173 #define OMAP2420_AUTO_MMC_MASK (1 << 26)
174 #define OMAP24XX_AUTO_FAC_MASK (1 << 25)
175 #define OMAP2420_AUTO_EAC_MASK (1 << 24)
176 #define OMAP24XX_AUTO_HDQ_MASK (1 << 23)
177 #define OMAP24XX_AUTO_UART2_MASK (1 << 22)
178 #define OMAP24XX_AUTO_UART1_MASK (1 << 21)
179 #define OMAP24XX_AUTO_I2C2_MASK (1 << 20)
180 #define OMAP24XX_AUTO_I2C1_MASK (1 << 19)
181 #define OMAP24XX_AUTO_MCSPI2_MASK (1 << 18)
182 #define OMAP24XX_AUTO_MCSPI1_MASK (1 << 17)
183 #define OMAP24XX_AUTO_MCBSP2_MASK (1 << 16)
184 #define OMAP24XX_AUTO_MCBSP1_MASK (1 << 15)
185 #define OMAP24XX_AUTO_GPT12_MASK (1 << 14)
186 #define OMAP24XX_AUTO_GPT11_MASK (1 << 13)
187 #define OMAP24XX_AUTO_GPT10_MASK (1 << 12)
188 #define OMAP24XX_AUTO_GPT9_MASK (1 << 11)
189 #define OMAP24XX_AUTO_GPT8_MASK (1 << 10)
190 #define OMAP24XX_AUTO_GPT7_MASK (1 << 9)
191 #define OMAP24XX_AUTO_GPT6_MASK (1 << 8)
192 #define OMAP24XX_AUTO_GPT5_MASK (1 << 7)
193 #define OMAP24XX_AUTO_GPT4_MASK (1 << 6)
194 #define OMAP24XX_AUTO_GPT3_MASK (1 << 5)
195 #define OMAP24XX_AUTO_GPT2_MASK (1 << 4)
196 #define OMAP2420_AUTO_VLYNQ_MASK (1 << 3)
197 #define OMAP24XX_AUTO_DSS_MASK (1 << 0)
199 /* CM_AUTOIDLE2_CORE */
200 #define OMAP2430_AUTO_MDM_INTC_MASK (1 << 11)
201 #define OMAP2430_AUTO_GPIO5_MASK (1 << 10)
202 #define OMAP2430_AUTO_MCSPI3_MASK (1 << 9)
203 #define OMAP2430_AUTO_MMCHS2_MASK (1 << 8)
204 #define OMAP2430_AUTO_MMCHS1_MASK (1 << 7)
205 #define OMAP2430_AUTO_USBHS_MASK (1 << 6)
206 #define OMAP2430_AUTO_MCBSP5_MASK (1 << 5)
207 #define OMAP2430_AUTO_MCBSP4_MASK (1 << 4)
208 #define OMAP2430_AUTO_MCBSP3_MASK (1 << 3)
209 #define OMAP24XX_AUTO_UART3_MASK (1 << 2)
210 #define OMAP24XX_AUTO_SSI_MASK (1 << 1)
211 #define OMAP24XX_AUTO_USB_MASK (1 << 0)
213 /* CM_AUTOIDLE3_CORE */
214 #define OMAP24XX_AUTO_SDRC_SHIFT 2
215 #define OMAP24XX_AUTO_SDRC_MASK (1 << 2)
216 #define OMAP24XX_AUTO_GPMC_SHIFT 1
217 #define OMAP24XX_AUTO_GPMC_MASK (1 << 1)
218 #define OMAP24XX_AUTO_SDMA_SHIFT 0
219 #define OMAP24XX_AUTO_SDMA_MASK (1 << 0)
221 /* CM_AUTOIDLE4_CORE */
222 #define OMAP24XX_AUTO_PKA_MASK (1 << 4)
223 #define OMAP24XX_AUTO_AES_MASK (1 << 3)
224 #define OMAP24XX_AUTO_RNG_MASK (1 << 2)
225 #define OMAP24XX_AUTO_SHA_MASK (1 << 1)
226 #define OMAP24XX_AUTO_DES_MASK (1 << 0)
228 /* CM_CLKSEL1_CORE */
229 #define OMAP24XX_CLKSEL_USB_SHIFT 25
230 #define OMAP24XX_CLKSEL_USB_MASK (0x7 << 25)
231 #define OMAP24XX_CLKSEL_SSI_SHIFT 20
232 #define OMAP24XX_CLKSEL_SSI_MASK (0x1f << 20)
233 #define OMAP2420_CLKSEL_VLYNQ_SHIFT 15
234 #define OMAP2420_CLKSEL_VLYNQ_MASK (0x1f << 15)
235 #define OMAP24XX_CLKSEL_DSS2_SHIFT 13
236 #define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13)
237 #define OMAP24XX_CLKSEL_DSS1_SHIFT 8
238 #define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8)
239 #define OMAP24XX_CLKSEL_L4_SHIFT 5
240 #define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5)
241 #define OMAP24XX_CLKSEL_L4_WIDTH 2
242 #define OMAP24XX_CLKSEL_L3_SHIFT 0
243 #define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0)
244 #define OMAP24XX_CLKSEL_L3_WIDTH 5
246 /* CM_CLKSEL2_CORE */
247 #define OMAP24XX_CLKSEL_GPT12_SHIFT 22
248 #define OMAP24XX_CLKSEL_GPT12_MASK (0x3 << 22)
249 #define OMAP24XX_CLKSEL_GPT11_SHIFT 20
250 #define OMAP24XX_CLKSEL_GPT11_MASK (0x3 << 20)
251 #define OMAP24XX_CLKSEL_GPT10_SHIFT 18
252 #define OMAP24XX_CLKSEL_GPT10_MASK (0x3 << 18)
253 #define OMAP24XX_CLKSEL_GPT9_SHIFT 16
254 #define OMAP24XX_CLKSEL_GPT9_MASK (0x3 << 16)
255 #define OMAP24XX_CLKSEL_GPT8_SHIFT 14
256 #define OMAP24XX_CLKSEL_GPT8_MASK (0x3 << 14)
257 #define OMAP24XX_CLKSEL_GPT7_SHIFT 12
258 #define OMAP24XX_CLKSEL_GPT7_MASK (0x3 << 12)
259 #define OMAP24XX_CLKSEL_GPT6_SHIFT 10
260 #define OMAP24XX_CLKSEL_GPT6_MASK (0x3 << 10)
261 #define OMAP24XX_CLKSEL_GPT5_SHIFT 8
262 #define OMAP24XX_CLKSEL_GPT5_MASK (0x3 << 8)
263 #define OMAP24XX_CLKSEL_GPT4_SHIFT 6
264 #define OMAP24XX_CLKSEL_GPT4_MASK (0x3 << 6)
265 #define OMAP24XX_CLKSEL_GPT3_SHIFT 4
266 #define OMAP24XX_CLKSEL_GPT3_MASK (0x3 << 4)
267 #define OMAP24XX_CLKSEL_GPT2_SHIFT 2
268 #define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2)
270 /* CM_CLKSTCTRL_CORE */
271 #define OMAP24XX_AUTOSTATE_DSS_SHIFT 2
272 #define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2)
273 #define OMAP24XX_AUTOSTATE_L4_SHIFT 1
274 #define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1)
275 #define OMAP24XX_AUTOSTATE_L3_SHIFT 0
276 #define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0)
278 /* CM_FCLKEN_GFX */
279 #define OMAP24XX_EN_3D_SHIFT 2
280 #define OMAP24XX_EN_3D_MASK (1 << 2)
281 #define OMAP24XX_EN_2D_SHIFT 1
282 #define OMAP24XX_EN_2D_MASK (1 << 1)
284 /* CM_ICLKEN_GFX specific bits */
286 /* CM_IDLEST_GFX specific bits */
288 /* CM_CLKSEL_GFX specific bits */
290 /* CM_CLKSTCTRL_GFX */
291 #define OMAP24XX_AUTOSTATE_GFX_SHIFT 0
292 #define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0)
294 /* CM_FCLKEN_WKUP specific bits */
296 /* CM_ICLKEN_WKUP specific bits */
297 #define OMAP2430_EN_ICR_SHIFT 6
298 #define OMAP2430_EN_ICR_MASK (1 << 6)
299 #define OMAP24XX_EN_OMAPCTRL_SHIFT 5
300 #define OMAP24XX_EN_OMAPCTRL_MASK (1 << 5)
301 #define OMAP24XX_EN_WDT1_SHIFT 4
302 #define OMAP24XX_EN_WDT1_MASK (1 << 4)
303 #define OMAP24XX_EN_32KSYNC_SHIFT 1
304 #define OMAP24XX_EN_32KSYNC_MASK (1 << 1)
306 /* CM_IDLEST_WKUP specific bits */
307 #define OMAP2430_ST_ICR_SHIFT 6
308 #define OMAP2430_ST_ICR_MASK (1 << 6)
309 #define OMAP24XX_ST_OMAPCTRL_SHIFT 5
310 #define OMAP24XX_ST_OMAPCTRL_MASK (1 << 5)
311 #define OMAP24XX_ST_WDT1_SHIFT 4
312 #define OMAP24XX_ST_WDT1_MASK (1 << 4)
313 #define OMAP24XX_ST_MPU_WDT_SHIFT 3
314 #define OMAP24XX_ST_MPU_WDT_MASK (1 << 3)
315 #define OMAP24XX_ST_32KSYNC_SHIFT 1
316 #define OMAP24XX_ST_32KSYNC_MASK (1 << 1)
318 /* CM_AUTOIDLE_WKUP */
319 #define OMAP24XX_AUTO_OMAPCTRL_MASK (1 << 5)
320 #define OMAP24XX_AUTO_WDT1_MASK (1 << 4)
321 #define OMAP24XX_AUTO_MPU_WDT_MASK (1 << 3)
322 #define OMAP24XX_AUTO_GPIOS_MASK (1 << 2)
323 #define OMAP24XX_AUTO_32KSYNC_MASK (1 << 1)
324 #define OMAP24XX_AUTO_GPT1_MASK (1 << 0)
326 /* CM_CLKSEL_WKUP */
327 #define OMAP24XX_CLKSEL_GPT1_SHIFT 0
328 #define OMAP24XX_CLKSEL_GPT1_MASK (0x3 << 0)
330 /* CM_CLKEN_PLL */
331 #define OMAP24XX_EN_54M_PLL_SHIFT 6
332 #define OMAP24XX_EN_54M_PLL_MASK (0x3 << 6)
333 #define OMAP24XX_EN_96M_PLL_SHIFT 2
334 #define OMAP24XX_EN_96M_PLL_MASK (0x3 << 2)
335 #define OMAP24XX_EN_DPLL_SHIFT 0
336 #define OMAP24XX_EN_DPLL_MASK (0x3 << 0)
338 /* CM_IDLEST_CKGEN */
339 #define OMAP24XX_ST_54M_APLL_SHIFT 9
340 #define OMAP24XX_ST_54M_APLL_MASK (1 << 9)
341 #define OMAP24XX_ST_96M_APLL_SHIFT 8
342 #define OMAP24XX_ST_96M_APLL_MASK (1 << 8)
343 #define OMAP24XX_ST_54M_CLK_MASK (1 << 6)
344 #define OMAP24XX_ST_12M_CLK_MASK (1 << 5)
345 #define OMAP24XX_ST_48M_CLK_MASK (1 << 4)
346 #define OMAP24XX_ST_96M_CLK_MASK (1 << 2)
347 #define OMAP24XX_ST_CORE_CLK_SHIFT 0
348 #define OMAP24XX_ST_CORE_CLK_MASK (0x3 << 0)
350 /* CM_AUTOIDLE_PLL */
351 #define OMAP24XX_AUTO_54M_SHIFT 6
352 #define OMAP24XX_AUTO_54M_MASK (0x3 << 6)
353 #define OMAP24XX_AUTO_96M_SHIFT 2
354 #define OMAP24XX_AUTO_96M_MASK (0x3 << 2)
355 #define OMAP24XX_AUTO_DPLL_SHIFT 0
356 #define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0)
358 /* CM_CLKSEL1_PLL */
359 #define OMAP2430_MAXDPLLFASTLOCK_SHIFT 28
360 #define OMAP2430_MAXDPLLFASTLOCK_MASK (0x7 << 28)
361 #define OMAP24XX_APLLS_CLKIN_SHIFT 23
362 #define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23)
363 #define OMAP24XX_DPLL_MULT_SHIFT 12
364 #define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12)
365 #define OMAP24XX_DPLL_DIV_SHIFT 8
366 #define OMAP24XX_DPLL_DIV_MASK (0xf << 8)
367 #define OMAP24XX_54M_SOURCE_SHIFT 5
368 #define OMAP24XX_54M_SOURCE_MASK (1 << 5)
369 #define OMAP24XX_54M_SOURCE_WIDTH 1
370 #define OMAP2430_96M_SOURCE_SHIFT 4
371 #define OMAP2430_96M_SOURCE_MASK (1 << 4)
372 #define OMAP2430_96M_SOURCE_WIDTH 1
373 #define OMAP24XX_48M_SOURCE_SHIFT 3
374 #define OMAP24XX_48M_SOURCE_MASK (1 << 3)
375 #define OMAP2430_ALTCLK_SOURCE_SHIFT 0
376 #define OMAP2430_ALTCLK_SOURCE_MASK (0x7 << 0)
378 /* CM_CLKSEL2_PLL */
379 #define OMAP24XX_CORE_CLK_SRC_SHIFT 0
380 #define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0)
382 /* CM_FCLKEN_DSP */
383 #define OMAP2420_EN_IVA_COP_SHIFT 10
384 #define OMAP2420_EN_IVA_COP_MASK (1 << 10)
385 #define OMAP2420_EN_IVA_MPU_SHIFT 8
386 #define OMAP2420_EN_IVA_MPU_MASK (1 << 8)
387 #define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0
388 #define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_MASK (1 << 0)
390 /* CM_ICLKEN_DSP */
391 #define OMAP2420_EN_DSP_IPI_SHIFT 1
392 #define OMAP2420_EN_DSP_IPI_MASK (1 << 1)
394 /* CM_IDLEST_DSP */
395 #define OMAP2420_ST_IVA_MASK (1 << 8)
396 #define OMAP2420_ST_IPI_MASK (1 << 1)
397 #define OMAP24XX_ST_DSP_MASK (1 << 0)
399 /* CM_AUTOIDLE_DSP */
400 #define OMAP2420_AUTO_DSP_IPI_MASK (1 << 1)
402 /* CM_CLKSEL_DSP */
403 #define OMAP2420_SYNC_IVA_MASK (1 << 13)
404 #define OMAP2420_CLKSEL_IVA_SHIFT 8
405 #define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8)
406 #define OMAP24XX_SYNC_DSP_MASK (1 << 7)
407 #define OMAP24XX_CLKSEL_DSP_IF_SHIFT 5
408 #define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5)
409 #define OMAP24XX_CLKSEL_DSP_SHIFT 0
410 #define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0)
412 /* CM_CLKSTCTRL_DSP */
413 #define OMAP2420_AUTOSTATE_IVA_SHIFT 8
414 #define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8)
415 #define OMAP24XX_AUTOSTATE_DSP_SHIFT 0
416 #define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0)
418 /* CM_FCLKEN_MDM */
419 /* 2430 only */
420 #define OMAP2430_EN_OSC_SHIFT 1
421 #define OMAP2430_EN_OSC_MASK (1 << 1)
423 /* CM_ICLKEN_MDM */
424 /* 2430 only */
425 #define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0
426 #define OMAP2430_CM_ICLKEN_MDM_EN_MDM_MASK (1 << 0)
428 /* CM_IDLEST_MDM specific bits */
429 /* 2430 only */
431 /* CM_AUTOIDLE_MDM */
432 /* 2430 only */
433 #define OMAP2430_AUTO_OSC_MASK (1 << 1)
434 #define OMAP2430_AUTO_MDM_MASK (1 << 0)
436 /* CM_CLKSEL_MDM */
437 /* 2430 only */
438 #define OMAP2430_SYNC_MDM_MASK (1 << 4)
439 #define OMAP2430_CLKSEL_MDM_SHIFT 0
440 #define OMAP2430_CLKSEL_MDM_MASK (0xf << 0)
442 /* CM_CLKSTCTRL_MDM */
443 /* 2430 only */
444 #define OMAP2430_AUTOSTATE_MDM_SHIFT 0
445 #define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0)
447 /* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */
448 #define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0
449 #define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1
452 #endif