| blob | 49fdc432512f572e985440a116188b69843faa80 |
1 config ARM
2 bool
3 default y
4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_WANT_IPC_PARSE_VERSION
9 select BUILDTIME_EXTABLE_SORT if MMU
10 select CPU_PM if (SUSPEND || CPU_IDLE)
11 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
12 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
13 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
14 select GENERIC_IRQ_PROBE
15 select GENERIC_IRQ_SHOW
16 select GENERIC_PCI_IOMAP
17 select GENERIC_SMP_IDLE_THREAD
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_STRNCPY_FROM_USER
20 select GENERIC_STRNLEN_USER
21 select HARDIRQS_SW_RESEND
22 select HAVE_AOUT
23 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
24 select HAVE_ARCH_KGDB
25 select HAVE_ARCH_SECCOMP_FILTER
26 select HAVE_ARCH_TRACEHOOK
27 select HAVE_BPF_JIT
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_DEBUG_KMEMLEAK
30 select HAVE_DMA_API_DEBUG
31 select HAVE_DMA_ATTRS
32 select HAVE_DMA_CONTIGUOUS if MMU
33 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
34 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
35 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
36 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
37 select HAVE_GENERIC_DMA_COHERENT
38 select HAVE_GENERIC_HARDIRQS
39 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
40 select HAVE_IDE if PCI || ISA || PCMCIA
41 select HAVE_IRQ_TIME_ACCOUNTING
42 select HAVE_KERNEL_GZIP
43 select HAVE_KERNEL_LZMA
44 select HAVE_KERNEL_LZO
45 select HAVE_KERNEL_XZ
46 select HAVE_KPROBES if !XIP_KERNEL
47 select HAVE_KRETPROBES if (HAVE_KPROBES)
48 select HAVE_MEMBLOCK
49 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
50 select HAVE_PERF_EVENTS
51 select HAVE_REGS_AND_STACK_ACCESS_API
52 select HAVE_SYSCALL_TRACEPOINTS
53 select HAVE_UID16
54 select KTIME_SCALAR
55 select PERF_USE_VMALLOC
56 select RTC_LIB
57 select SYS_SUPPORTS_APM_EMULATION
58 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
59 select MODULES_USE_ELF_REL
60 select CLONE_BACKWARDS
61 select OLD_SIGSUSPEND3
62 select OLD_SIGACTION
63 select HAVE_CONTEXT_TRACKING
64 help
65 The ARM series is a line of low-power-consumption RISC chip designs
66 licensed by ARM Ltd and targeted at embedded applications and
67 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
68 manufactured, but legacy ARM-based PC hardware remains popular in
69 Europe. There is an ARM Linux project with a web page at
70 <http://www.arm.linux.org.uk/>.
72 config ARM_HAS_SG_CHAIN
73 bool
75 config NEED_SG_DMA_LENGTH
76 bool
78 config ARM_DMA_USE_IOMMU
79 bool
80 select ARM_HAS_SG_CHAIN
81 select NEED_SG_DMA_LENGTH
83 if ARM_DMA_USE_IOMMU
85 config ARM_DMA_IOMMU_ALIGNMENT
86 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
87 range 4 9
88 default 8
89 help
90 DMA mapping framework by default aligns all buffers to the smallest
91 PAGE_SIZE order which is greater than or equal to the requested buffer
92 size. This works well for buffers up to a few hundreds kilobytes, but
93 for larger buffers it just a waste of address space. Drivers which has
94 relatively small addressing window (like 64Mib) might run out of
95 virtual space with just a few allocations.
97 With this parameter you can specify the maximum PAGE_SIZE order for
98 DMA IOMMU buffers. Larger buffers will be aligned only to this
99 specified order. The order is expressed as a power of two multiplied
100 by the PAGE_SIZE.
102 endif
104 config HAVE_PWM
105 bool
107 config MIGHT_HAVE_PCI
108 bool
110 config SYS_SUPPORTS_APM_EMULATION
111 bool
113 config HAVE_TCM
114 bool
115 select GENERIC_ALLOCATOR
117 config HAVE_PROC_CPU
118 bool
120 config NO_IOPORT
121 bool
123 config EISA
124 bool
125 ---help---
126 The Extended Industry Standard Architecture (EISA) bus was
127 developed as an open alternative to the IBM MicroChannel bus.
129 The EISA bus provided some of the features of the IBM MicroChannel
130 bus while maintaining backward compatibility with cards made for
131 the older ISA bus. The EISA bus saw limited use between 1988 and
132 1995 when it was made obsolete by the PCI bus.
134 Say Y here if you are building a kernel for an EISA-based machine.
136 Otherwise, say N.
138 config SBUS
139 bool
141 config STACKTRACE_SUPPORT
142 bool
143 default y
145 config HAVE_LATENCYTOP_SUPPORT
146 bool
147 depends on !SMP
148 default y
150 config LOCKDEP_SUPPORT
151 bool
152 default y
154 config TRACE_IRQFLAGS_SUPPORT
155 bool
156 default y
158 config RWSEM_GENERIC_SPINLOCK
159 bool
160 default y
162 config RWSEM_XCHGADD_ALGORITHM
163 bool
165 config ARCH_HAS_ILOG2_U32
166 bool
168 config ARCH_HAS_ILOG2_U64
169 bool
171 config ARCH_HAS_CPUFREQ
172 bool
173 help
174 Internal node to signify that the ARCH has CPUFREQ support
175 and that the relevant menu configurations are displayed for
176 it.
178 config GENERIC_HWEIGHT
179 bool
180 default y
182 config GENERIC_CALIBRATE_DELAY
183 bool
184 default y
186 config ARCH_MAY_HAVE_PC_FDC
187 bool
189 config ZONE_DMA
190 bool
192 config NEED_DMA_MAP_STATE
193 def_bool y
195 config ARCH_HAS_DMA_SET_COHERENT_MASK
196 bool
198 config GENERIC_ISA_DMA
199 bool
201 config FIQ
202 bool
204 config NEED_RET_TO_USER
205 bool
207 config ARCH_MTD_XIP
208 bool
210 config VECTORS_BASE
211 hex
212 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
213 default DRAM_BASE if REMAP_VECTORS_TO_RAM
214 default 0x00000000
215 help
216 The base address of exception vectors.
218 config ARM_PATCH_PHYS_VIRT
219 bool "Patch physical to virtual translations at runtime" if EMBEDDED
220 default y
221 depends on !XIP_KERNEL && MMU
222 depends on !ARCH_REALVIEW || !SPARSEMEM
223 help
224 Patch phys-to-virt and virt-to-phys translation functions at
225 boot and module load time according to the position of the
226 kernel in system memory.
228 This can only be used with non-XIP MMU kernels where the base
229 of physical memory is at a 16MB boundary.
231 Only disable this option if you know that you do not require
232 this feature (eg, building a kernel for a single machine) and
233 you need to shrink the kernel to the minimal size.
235 config NEED_MACH_GPIO_H
236 bool
237 help
238 Select this when mach/gpio.h is required to provide special
239 definitions for this platform. The need for mach/gpio.h should
240 be avoided when possible.
242 config NEED_MACH_IO_H
243 bool
244 help
245 Select this when mach/io.h is required to provide special
246 definitions for this platform. The need for mach/io.h should
247 be avoided when possible.
249 config NEED_MACH_MEMORY_H
250 bool
251 help
252 Select this when mach/memory.h is required to provide special
253 definitions for this platform. The need for mach/memory.h should
254 be avoided when possible.
256 config PHYS_OFFSET
257 hex "Physical address of main memory" if MMU
258 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
259 default DRAM_BASE if !MMU
260 help
261 Please provide the physical address corresponding to the
262 location of main memory in your system.
264 config GENERIC_BUG
265 def_bool y
266 depends on BUG
268 source "init/Kconfig"
270 source "kernel/Kconfig.freezer"
272 menu "System Type"
274 config MMU
275 bool "MMU-based Paged Memory Management Support"
276 default y
277 help
278 Select if you want MMU-based virtualised addressing space
279 support by paged memory management. If unsure, say 'Y'.
281 #
282 # The "ARM system type" choice list is ordered alphabetically by option
283 # text. Please add new entries in the option alphabetic order.
284 #
285 choice
286 prompt "ARM system type"
287 default ARCH_VERSATILE if !MMU
288 default ARCH_MULTIPLATFORM if MMU
290 config ARCH_MULTIPLATFORM
291 bool "Allow multiple platforms to be selected"
292 depends on MMU
293 select ARM_PATCH_PHYS_VIRT
294 select AUTO_ZRELADDR
295 select COMMON_CLK
296 select MULTI_IRQ_HANDLER
297 select SPARSE_IRQ
298 select USE_OF
300 config ARCH_INTEGRATOR
301 bool "ARM Ltd. Integrator family"
302 select ARCH_HAS_CPUFREQ
303 select ARM_AMBA
304 select COMMON_CLK
305 select COMMON_CLK_VERSATILE
306 select GENERIC_CLOCKEVENTS
307 select HAVE_TCM
308 select ICST
309 select MULTI_IRQ_HANDLER
310 select NEED_MACH_MEMORY_H
311 select PLAT_VERSATILE
312 select SPARSE_IRQ
313 select VERSATILE_FPGA_IRQ
314 help
315 Support for ARM's Integrator platform.
317 config ARCH_REALVIEW
318 bool "ARM Ltd. RealView family"
319 select ARCH_WANT_OPTIONAL_GPIOLIB
320 select ARM_AMBA
321 select ARM_TIMER_SP804
322 select COMMON_CLK
323 select COMMON_CLK_VERSATILE
324 select GENERIC_CLOCKEVENTS
325 select GPIO_PL061 if GPIOLIB
326 select ICST
327 select NEED_MACH_MEMORY_H
328 select PLAT_VERSATILE
329 select PLAT_VERSATILE_CLCD
330 help
331 This enables support for ARM Ltd RealView boards.
333 config ARCH_VERSATILE
334 bool "ARM Ltd. Versatile family"
335 select ARCH_WANT_OPTIONAL_GPIOLIB
336 select ARM_AMBA
337 select ARM_TIMER_SP804
338 select ARM_VIC
339 select CLKDEV_LOOKUP
340 select GENERIC_CLOCKEVENTS
341 select HAVE_MACH_CLKDEV
342 select ICST
343 select PLAT_VERSATILE
344 select PLAT_VERSATILE_CLCD
345 select PLAT_VERSATILE_CLOCK
346 select VERSATILE_FPGA_IRQ
347 help
348 This enables support for ARM Ltd Versatile board.
350 config ARCH_AT91
351 bool "Atmel AT91"
352 select ARCH_REQUIRE_GPIOLIB
353 select CLKDEV_LOOKUP
354 select HAVE_CLK
355 select IRQ_DOMAIN
356 select NEED_MACH_GPIO_H
357 select NEED_MACH_IO_H if PCCARD
358 select PINCTRL
359 select PINCTRL_AT91 if USE_OF
360 help
361 This enables support for systems based on Atmel
362 AT91RM9200 and AT91SAM9* processors.
364 config ARCH_CLPS711X
365 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
366 select ARCH_REQUIRE_GPIOLIB
367 select AUTO_ZRELADDR
368 select CLKDEV_LOOKUP
369 select CLKSRC_MMIO
370 select COMMON_CLK
371 select CPU_ARM720T
372 select GENERIC_CLOCKEVENTS
373 select MFD_SYSCON
374 select MULTI_IRQ_HANDLER
375 select SPARSE_IRQ
376 help
377 Support for Cirrus Logic 711x/721x/731x based boards.
379 config ARCH_GEMINI
380 bool "Cortina Systems Gemini"
381 select ARCH_REQUIRE_GPIOLIB
382 select ARCH_USES_GETTIMEOFFSET
383 select NEED_MACH_GPIO_H
384 select CPU_FA526
385 help
386 Support for the Cortina Systems Gemini family SoCs
388 config ARCH_EBSA110
389 bool "EBSA-110"
390 select ARCH_USES_GETTIMEOFFSET
391 select CPU_SA110
392 select ISA
393 select NEED_MACH_IO_H
394 select NEED_MACH_MEMORY_H
395 select NO_IOPORT
396 help
397 This is an evaluation board for the StrongARM processor available
398 from Digital. It has limited hardware on-board, including an
399 Ethernet interface, two PCMCIA sockets, two serial ports and a
400 parallel port.
402 config ARCH_EP93XX
403 bool "EP93xx-based"
404 select ARCH_HAS_HOLES_MEMORYMODEL
405 select ARCH_REQUIRE_GPIOLIB
406 select ARCH_USES_GETTIMEOFFSET
407 select ARM_AMBA
408 select ARM_VIC
409 select CLKDEV_LOOKUP
410 select CPU_ARM920T
411 select NEED_MACH_MEMORY_H
412 help
413 This enables support for the Cirrus EP93xx series of CPUs.
415 config ARCH_FOOTBRIDGE
416 bool "FootBridge"
417 select CPU_SA110
418 select FOOTBRIDGE
419 select GENERIC_CLOCKEVENTS
420 select HAVE_IDE
421 select NEED_MACH_IO_H if !MMU
422 select NEED_MACH_MEMORY_H
423 help
424 Support for systems based on the DC21285 companion chip
425 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
427 config ARCH_NETX
428 bool "Hilscher NetX based"
429 select ARM_VIC
430 select CLKSRC_MMIO
431 select CPU_ARM926T
432 select GENERIC_CLOCKEVENTS
433 help
434 This enables support for systems based on the Hilscher NetX Soc
436 config ARCH_IOP13XX
437 bool "IOP13xx-based"
438 depends on MMU
439 select ARCH_SUPPORTS_MSI
440 select CPU_XSC3
441 select NEED_MACH_MEMORY_H
442 select NEED_RET_TO_USER
443 select PCI
444 select PLAT_IOP
445 select VMSPLIT_1G
446 help
447 Support for Intel's IOP13XX (XScale) family of processors.
449 config ARCH_IOP32X
450 bool "IOP32x-based"
451 depends on MMU
452 select ARCH_REQUIRE_GPIOLIB
453 select CPU_XSCALE
454 select NEED_MACH_GPIO_H
455 select NEED_RET_TO_USER
456 select PCI
457 select PLAT_IOP
458 help
459 Support for Intel's 80219 and IOP32X (XScale) family of
460 processors.
462 config ARCH_IOP33X
463 bool "IOP33x-based"
464 depends on MMU
465 select ARCH_REQUIRE_GPIOLIB
466 select CPU_XSCALE
467 select NEED_MACH_GPIO_H
468 select NEED_RET_TO_USER
469 select PCI
470 select PLAT_IOP
471 help
472 Support for Intel's IOP33X (XScale) family of processors.
474 config ARCH_IXP4XX
475 bool "IXP4xx-based"
476 depends on MMU
477 select ARCH_HAS_DMA_SET_COHERENT_MASK
478 select ARCH_REQUIRE_GPIOLIB
479 select CLKSRC_MMIO
480 select CPU_XSCALE
481 select DMABOUNCE if PCI
482 select GENERIC_CLOCKEVENTS
483 select MIGHT_HAVE_PCI
484 select NEED_MACH_IO_H
485 select USB_EHCI_BIG_ENDIAN_MMIO
486 select USB_EHCI_BIG_ENDIAN_DESC
487 help
488 Support for Intel's IXP4XX (XScale) family of processors.
490 config ARCH_DOVE
491 bool "Marvell Dove"
492 select ARCH_REQUIRE_GPIOLIB
493 select CPU_PJ4
494 select GENERIC_CLOCKEVENTS
495 select MIGHT_HAVE_PCI
496 select PINCTRL
497 select PINCTRL_DOVE
498 select PLAT_ORION_LEGACY
499 select USB_ARCH_HAS_EHCI
500 select MVEBU_MBUS
501 help
502 Support for the Marvell Dove SoC 88AP510
504 config ARCH_KIRKWOOD
505 bool "Marvell Kirkwood"
506 select ARCH_HAS_CPUFREQ
507 select ARCH_REQUIRE_GPIOLIB
508 select CPU_FEROCEON
509 select GENERIC_CLOCKEVENTS
510 select PCI
511 select PCI_QUIRKS
512 select PINCTRL
513 select PINCTRL_KIRKWOOD
514 select PLAT_ORION_LEGACY
515 select MVEBU_MBUS
516 help
517 Support for the following Marvell Kirkwood series SoCs:
518 88F6180, 88F6192 and 88F6281.
520 config ARCH_MV78XX0
521 bool "Marvell MV78xx0"
522 select ARCH_REQUIRE_GPIOLIB
523 select CPU_FEROCEON
524 select GENERIC_CLOCKEVENTS
525 select PCI
526 select PLAT_ORION_LEGACY
527 select MVEBU_MBUS
528 help
529 Support for the following Marvell MV78xx0 series SoCs:
530 MV781x0, MV782x0.
532 config ARCH_ORION5X
533 bool "Marvell Orion"
534 depends on MMU
535 select ARCH_REQUIRE_GPIOLIB
536 select CPU_FEROCEON
537 select GENERIC_CLOCKEVENTS
538 select PCI
539 select PLAT_ORION_LEGACY
540 select MVEBU_MBUS
541 help
542 Support for the following Marvell Orion 5x series SoCs:
543 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
544 Orion-2 (5281), Orion-1-90 (6183).
546 config ARCH_MMP
547 bool "Marvell PXA168/910/MMP2"
548 depends on MMU
549 select ARCH_REQUIRE_GPIOLIB
550 select CLKDEV_LOOKUP
551 select GENERIC_ALLOCATOR
552 select GENERIC_CLOCKEVENTS
553 select GPIO_PXA
554 select IRQ_DOMAIN
555 select NEED_MACH_GPIO_H
556 select PINCTRL
557 select PLAT_PXA
558 select SPARSE_IRQ
559 help
560 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
562 config ARCH_KS8695
563 bool "Micrel/Kendin KS8695"
564 select ARCH_REQUIRE_GPIOLIB
565 select CLKSRC_MMIO
566 select CPU_ARM922T
567 select GENERIC_CLOCKEVENTS
568 select NEED_MACH_MEMORY_H
569 help
570 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
571 System-on-Chip devices.
573 config ARCH_W90X900
574 bool "Nuvoton W90X900 CPU"
575 select ARCH_REQUIRE_GPIOLIB
576 select CLKDEV_LOOKUP
577 select CLKSRC_MMIO
578 select CPU_ARM926T
579 select GENERIC_CLOCKEVENTS
580 help
581 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
582 At present, the w90x900 has been renamed nuc900, regarding
583 the ARM series product line, you can login the following
584 link address to know more.
586 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
587 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
589 config ARCH_LPC32XX
590 bool "NXP LPC32XX"
591 select ARCH_REQUIRE_GPIOLIB
592 select ARM_AMBA
593 select CLKDEV_LOOKUP
594 select CLKSRC_MMIO
595 select CPU_ARM926T
596 select GENERIC_CLOCKEVENTS
597 select HAVE_IDE
598 select HAVE_PWM
599 select USB_ARCH_HAS_OHCI
600 select USE_OF
601 help
602 Support for the NXP LPC32XX family of processors
604 config ARCH_PXA
605 bool "PXA2xx/PXA3xx-based"
606 depends on MMU
607 select ARCH_HAS_CPUFREQ
608 select ARCH_MTD_XIP
609 select ARCH_REQUIRE_GPIOLIB
610 select ARM_CPU_SUSPEND if PM
611 select AUTO_ZRELADDR
612 select CLKDEV_LOOKUP
613 select CLKSRC_MMIO
614 select GENERIC_CLOCKEVENTS
615 select GPIO_PXA
616 select HAVE_IDE
617 select MULTI_IRQ_HANDLER
618 select NEED_MACH_GPIO_H
619 select PLAT_PXA
620 select SPARSE_IRQ
621 help
622 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
624 config ARCH_MSM
625 bool "Qualcomm MSM"
626 select ARCH_REQUIRE_GPIOLIB
627 select CLKDEV_LOOKUP
628 select GENERIC_CLOCKEVENTS
629 select HAVE_CLK
630 help
631 Support for Qualcomm MSM/QSD based systems. This runs on the
632 apps processor of the MSM/QSD and depends on a shared memory
633 interface to the modem processor which runs the baseband
634 stack and controls some vital subsystems
635 (clock and power control, etc).
637 config ARCH_SHMOBILE
638 bool "Renesas SH-Mobile / R-Mobile"
639 select ARM_PATCH_PHYS_VIRT
640 select CLKDEV_LOOKUP
641 select GENERIC_CLOCKEVENTS
642 select HAVE_ARM_SCU if SMP
643 select HAVE_ARM_TWD if LOCAL_TIMERS
644 select HAVE_CLK
645 select HAVE_MACH_CLKDEV
646 select HAVE_SMP
647 select MIGHT_HAVE_CACHE_L2X0
648 select MULTI_IRQ_HANDLER
649 select NO_IOPORT
650 select PINCTRL
651 select PM_GENERIC_DOMAINS if PM
652 select SPARSE_IRQ
653 help
654 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
656 config ARCH_RPC
657 bool "RiscPC"
658 select ARCH_ACORN
659 select ARCH_MAY_HAVE_PC_FDC
660 select ARCH_SPARSEMEM_ENABLE
661 select ARCH_USES_GETTIMEOFFSET
662 select FIQ
663 select HAVE_IDE
664 select HAVE_PATA_PLATFORM
665 select ISA_DMA_API
666 select NEED_MACH_IO_H
667 select NEED_MACH_MEMORY_H
668 select NO_IOPORT
669 select VIRT_TO_BUS
670 help
671 On the Acorn Risc-PC, Linux can support the internal IDE disk and
672 CD-ROM interface, serial and parallel port, and the floppy drive.
674 config ARCH_SA1100
675 bool "SA1100-based"
676 select ARCH_HAS_CPUFREQ
677 select ARCH_MTD_XIP
678 select ARCH_REQUIRE_GPIOLIB
679 select ARCH_SPARSEMEM_ENABLE
680 select CLKDEV_LOOKUP
681 select CLKSRC_MMIO
682 select CPU_FREQ
683 select CPU_SA1100
684 select GENERIC_CLOCKEVENTS
685 select HAVE_IDE
686 select ISA
687 select NEED_MACH_GPIO_H
688 select NEED_MACH_MEMORY_H
689 select SPARSE_IRQ
690 help
691 Support for StrongARM 11x0 based boards.
693 config ARCH_S3C24XX
694 bool "Samsung S3C24XX SoCs"
695 select ARCH_HAS_CPUFREQ
696 select ARCH_REQUIRE_GPIOLIB
697 select CLKDEV_LOOKUP
698 select CLKSRC_MMIO
699 select GENERIC_CLOCKEVENTS
700 select GPIO_SAMSUNG
701 select HAVE_CLK
702 select HAVE_S3C2410_I2C if I2C
703 select HAVE_S3C2410_WATCHDOG if WATCHDOG
704 select HAVE_S3C_RTC if RTC_CLASS
705 select MULTI_IRQ_HANDLER
706 select NEED_MACH_GPIO_H
707 select NEED_MACH_IO_H
708 select SAMSUNG_ATAGS
709 help
710 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
711 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
712 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
713 Samsung SMDK2410 development board (and derivatives).
715 config ARCH_S3C64XX
716 bool "Samsung S3C64XX"
717 select ARCH_HAS_CPUFREQ
718 select ARCH_REQUIRE_GPIOLIB
719 select ARM_VIC
720 select CLKDEV_LOOKUP
721 select CLKSRC_MMIO
722 select CPU_V6
723 select GENERIC_CLOCKEVENTS
724 select GPIO_SAMSUNG
725 select HAVE_CLK
726 select HAVE_S3C2410_I2C if I2C
727 select HAVE_S3C2410_WATCHDOG if WATCHDOG
728 select HAVE_TCM
729 select NEED_MACH_GPIO_H
730 select NO_IOPORT
731 select PLAT_SAMSUNG
732 select S3C_DEV_NAND
733 select S3C_GPIO_TRACK
734 select SAMSUNG_ATAGS
735 select SAMSUNG_CLKSRC
736 select SAMSUNG_GPIOLIB_4BIT
737 select SAMSUNG_IRQ_VIC_TIMER
738 select SAMSUNG_WDT_RESET
739 select USB_ARCH_HAS_OHCI
740 help
741 Samsung S3C64XX series based systems
743 config ARCH_S5P64X0
744 bool "Samsung S5P6440 S5P6450"
745 select CLKDEV_LOOKUP
746 select CLKSRC_MMIO
747 select CPU_V6
748 select GENERIC_CLOCKEVENTS
749 select GPIO_SAMSUNG
750 select HAVE_CLK
751 select HAVE_S3C2410_I2C if I2C
752 select HAVE_S3C2410_WATCHDOG if WATCHDOG
753 select HAVE_S3C_RTC if RTC_CLASS
754 select NEED_MACH_GPIO_H
755 select SAMSUNG_WDT_RESET
756 select SAMSUNG_ATAGS
757 help
758 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
759 SMDK6450.
761 config ARCH_S5PC100
762 bool "Samsung S5PC100"
763 select ARCH_REQUIRE_GPIOLIB
764 select CLKDEV_LOOKUP
765 select CLKSRC_MMIO
766 select CPU_V7
767 select GENERIC_CLOCKEVENTS
768 select GPIO_SAMSUNG
769 select HAVE_CLK
770 select HAVE_S3C2410_I2C if I2C
771 select HAVE_S3C2410_WATCHDOG if WATCHDOG
772 select HAVE_S3C_RTC if RTC_CLASS
773 select NEED_MACH_GPIO_H
774 select SAMSUNG_WDT_RESET
775 select SAMSUNG_ATAGS
776 help
777 Samsung S5PC100 series based systems
779 config ARCH_S5PV210
780 bool "Samsung S5PV210/S5PC110"
781 select ARCH_HAS_CPUFREQ
782 select ARCH_HAS_HOLES_MEMORYMODEL
783 select ARCH_SPARSEMEM_ENABLE
784 select CLKDEV_LOOKUP
785 select CLKSRC_MMIO
786 select CPU_V7
787 select GENERIC_CLOCKEVENTS
788 select GPIO_SAMSUNG
789 select HAVE_CLK
790 select HAVE_S3C2410_I2C if I2C
791 select HAVE_S3C2410_WATCHDOG if WATCHDOG
792 select HAVE_S3C_RTC if RTC_CLASS
793 select NEED_MACH_GPIO_H
794 select NEED_MACH_MEMORY_H
795 select SAMSUNG_ATAGS
796 help
797 Samsung S5PV210/S5PC110 series based systems
799 config ARCH_EXYNOS
800 bool "Samsung EXYNOS"
801 select ARCH_HAS_CPUFREQ
802 select ARCH_HAS_HOLES_MEMORYMODEL
803 select ARCH_REQUIRE_GPIOLIB
804 select ARCH_SPARSEMEM_ENABLE
805 select ARM_GIC
806 select CLKDEV_LOOKUP
807 select COMMON_CLK
808 select CPU_V7
809 select GENERIC_CLOCKEVENTS
810 select HAVE_CLK
811 select HAVE_S3C2410_I2C if I2C
812 select HAVE_S3C2410_WATCHDOG if WATCHDOG
813 select HAVE_S3C_RTC if RTC_CLASS
814 select NEED_MACH_MEMORY_H
815 select SPARSE_IRQ
816 select USE_OF
817 help
818 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
820 config ARCH_SHARK
821 bool "Shark"
822 select ARCH_USES_GETTIMEOFFSET
823 select CPU_SA110
824 select ISA
825 select ISA_DMA
826 select NEED_MACH_MEMORY_H
827 select PCI
828 select VIRT_TO_BUS
829 select ZONE_DMA
830 help
831 Support for the StrongARM based Digital DNARD machine, also known
832 as "Shark" (<http://www.shark-linux.de/shark.html>).
834 config ARCH_DAVINCI
835 bool "TI DaVinci"
836 select ARCH_HAS_HOLES_MEMORYMODEL
837 select ARCH_REQUIRE_GPIOLIB
838 select CLKDEV_LOOKUP
839 select GENERIC_ALLOCATOR
840 select GENERIC_CLOCKEVENTS
841 select GENERIC_IRQ_CHIP
842 select HAVE_IDE
843 select NEED_MACH_GPIO_H
844 select TI_PRIV_EDMA
845 select USE_OF
846 select ZONE_DMA
847 help
848 Support for TI's DaVinci platform.
850 config ARCH_OMAP1
851 bool "TI OMAP1"
852 depends on MMU
853 select ARCH_HAS_CPUFREQ
854 select ARCH_HAS_HOLES_MEMORYMODEL
855 select ARCH_OMAP
856 select ARCH_REQUIRE_GPIOLIB
857 select CLKDEV_LOOKUP
858 select CLKSRC_MMIO
859 select GENERIC_CLOCKEVENTS
860 select GENERIC_IRQ_CHIP
861 select HAVE_CLK
862 select HAVE_IDE
863 select IRQ_DOMAIN
864 select NEED_MACH_IO_H if PCCARD
865 select NEED_MACH_MEMORY_H
866 help
867 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
869 endchoice
871 menu "Multiple platform selection"
872 depends on ARCH_MULTIPLATFORM
874 comment "CPU Core family selection"
876 config ARCH_MULTI_V4T
877 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
878 depends on !ARCH_MULTI_V6_V7
879 select ARCH_MULTI_V4_V5
880 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
881 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
882 CPU_ARM925T || CPU_ARM940T)
884 config ARCH_MULTI_V5
885 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
886 depends on !ARCH_MULTI_V6_V7
887 select ARCH_MULTI_V4_V5
888 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
889 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
890 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
892 config ARCH_MULTI_V4_V5
893 bool
895 config ARCH_MULTI_V6
896 bool "ARMv6 based platforms (ARM11)"
897 select ARCH_MULTI_V6_V7
898 select CPU_V6
900 config ARCH_MULTI_V7
901 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
902 default y
903 select ARCH_MULTI_V6_V7
904 select CPU_V7
906 config ARCH_MULTI_V6_V7
907 bool
909 config ARCH_MULTI_CPU_AUTO
910 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
911 select ARCH_MULTI_V5
913 endmenu
915 #
916 # This is sorted alphabetically by mach-* pathname. However, plat-*
917 # Kconfigs may be included either alphabetically (according to the
918 # plat- suffix) or along side the corresponding mach-* source.
919 #
920 source "arch/arm/mach-mvebu/Kconfig"
922 source "arch/arm/mach-at91/Kconfig"
924 source "arch/arm/mach-bcm/Kconfig"
926 source "arch/arm/mach-bcm2835/Kconfig"
928 source "arch/arm/mach-clps711x/Kconfig"
930 source "arch/arm/mach-cns3xxx/Kconfig"
932 source "arch/arm/mach-davinci/Kconfig"
934 source "arch/arm/mach-dove/Kconfig"
936 source "arch/arm/mach-ep93xx/Kconfig"
938 source "arch/arm/mach-footbridge/Kconfig"
940 source "arch/arm/mach-gemini/Kconfig"
942 source "arch/arm/mach-highbank/Kconfig"
944 source "arch/arm/mach-integrator/Kconfig"
946 source "arch/arm/mach-iop32x/Kconfig"
948 source "arch/arm/mach-iop33x/Kconfig"
950 source "arch/arm/mach-iop13xx/Kconfig"
952 source "arch/arm/mach-ixp4xx/Kconfig"
954 source "arch/arm/mach-keystone/Kconfig"
956 source "arch/arm/mach-kirkwood/Kconfig"
958 source "arch/arm/mach-ks8695/Kconfig"
960 source "arch/arm/mach-msm/Kconfig"
962 source "arch/arm/mach-mv78xx0/Kconfig"
964 source "arch/arm/mach-imx/Kconfig"
966 source "arch/arm/mach-mxs/Kconfig"
968 source "arch/arm/mach-netx/Kconfig"
970 source "arch/arm/mach-nomadik/Kconfig"
972 source "arch/arm/plat-omap/Kconfig"
974 source "arch/arm/mach-omap1/Kconfig"
976 source "arch/arm/mach-omap2/Kconfig"
978 source "arch/arm/mach-orion5x/Kconfig"
980 source "arch/arm/mach-picoxcell/Kconfig"
982 source "arch/arm/mach-pxa/Kconfig"
983 source "arch/arm/plat-pxa/Kconfig"
985 source "arch/arm/mach-mmp/Kconfig"
987 source "arch/arm/mach-realview/Kconfig"
989 source "arch/arm/mach-rockchip/Kconfig"
991 source "arch/arm/mach-sa1100/Kconfig"
993 source "arch/arm/plat-samsung/Kconfig"
995 source "arch/arm/mach-socfpga/Kconfig"
997 source "arch/arm/mach-spear/Kconfig"
999 source "arch/arm/mach-s3c24xx/Kconfig"
1001 if ARCH_S3C64XX
1002 source "arch/arm/mach-s3c64xx/Kconfig"
1003 endif
1005 source "arch/arm/mach-s5p64x0/Kconfig"
1007 source "arch/arm/mach-s5pc100/Kconfig"
1009 source "arch/arm/mach-s5pv210/Kconfig"
1011 source "arch/arm/mach-exynos/Kconfig"
1013 source "arch/arm/mach-shmobile/Kconfig"
1015 source "arch/arm/mach-sunxi/Kconfig"
1017 source "arch/arm/mach-prima2/Kconfig"
1019 source "arch/arm/mach-tegra/Kconfig"
1021 source "arch/arm/mach-u300/Kconfig"
1023 source "arch/arm/mach-ux500/Kconfig"
1025 source "arch/arm/mach-versatile/Kconfig"
1027 source "arch/arm/mach-vexpress/Kconfig"
1028 source "arch/arm/plat-versatile/Kconfig"
1030 source "arch/arm/mach-virt/Kconfig"
1032 source "arch/arm/mach-vt8500/Kconfig"
1034 source "arch/arm/mach-w90x900/Kconfig"
1036 source "arch/arm/mach-zynq/Kconfig"
1038 # Definitions to make life easier
1039 config ARCH_ACORN
1040 bool
1042 config PLAT_IOP
1043 bool
1044 select GENERIC_CLOCKEVENTS
1046 config PLAT_ORION
1047 bool
1048 select CLKSRC_MMIO
1049 select COMMON_CLK
1050 select GENERIC_IRQ_CHIP
1051 select IRQ_DOMAIN
1053 config PLAT_ORION_LEGACY
1054 bool
1055 select PLAT_ORION
1057 config PLAT_PXA
1058 bool
1060 config PLAT_VERSATILE
1061 bool
1063 config ARM_TIMER_SP804
1064 bool
1065 select CLKSRC_MMIO
1066 select CLKSRC_OF if OF
1068 source arch/arm/mm/Kconfig
1070 config ARM_NR_BANKS
1071 int
1072 default 16 if ARCH_EP93XX
1073 default 8
1075 config IWMMXT
1076 bool "Enable iWMMXt support" if !CPU_PJ4
1077 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1078 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1079 help
1080 Enable support for iWMMXt context switching at run time if
1081 running on a CPU that supports it.
1083 config XSCALE_PMU
1084 bool
1085 depends on CPU_XSCALE
1086 default y
1088 config MULTI_IRQ_HANDLER
1089 bool
1090 help
1091 Allow each machine to specify it's own IRQ handler at run time.
1093 if !MMU
1094 source "arch/arm/Kconfig-nommu"
1095 endif
1097 config PJ4B_ERRATA_4742
1098 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1099 depends on CPU_PJ4B && MACH_ARMADA_370
1100 default y
1101 help
1102 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1103 Event (WFE) IDLE states, a specific timing sensitivity exists between
1104 the retiring WFI/WFE instructions and the newly issued subsequent
1105 instructions. This sensitivity can result in a CPU hang scenario.
1106 Workaround:
1107 The software must insert either a Data Synchronization Barrier (DSB)
1108 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1109 instruction
1111 config ARM_ERRATA_326103
1112 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1113 depends on CPU_V6
1114 help
1115 Executing a SWP instruction to read-only memory does not set bit 11
1116 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1117 treat the access as a read, preventing a COW from occurring and
1118 causing the faulting task to livelock.
1120 config ARM_ERRATA_411920
1121 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1122 depends on CPU_V6 || CPU_V6K
1123 help
1124 Invalidation of the Instruction Cache operation can
1125 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1126 It does not affect the MPCore. This option enables the ARM Ltd.
1127 recommended workaround.
1129 config ARM_ERRATA_430973
1130 bool "ARM errata: Stale prediction on replaced interworking branch"
1131 depends on CPU_V7
1132 help
1133 This option enables the workaround for the 430973 Cortex-A8
1134 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1135 interworking branch is replaced with another code sequence at the
1136 same virtual address, whether due to self-modifying code or virtual
1137 to physical address re-mapping, Cortex-A8 does not recover from the
1138 stale interworking branch prediction. This results in Cortex-A8
1139 executing the new code sequence in the incorrect ARM or Thumb state.
1140 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1141 and also flushes the branch target cache at every context switch.
1142 Note that setting specific bits in the ACTLR register may not be
1143 available in non-secure mode.
1145 config ARM_ERRATA_458693
1146 bool "ARM errata: Processor deadlock when a false hazard is created"
1147 depends on CPU_V7
1148 depends on !ARCH_MULTIPLATFORM
1149 help
1150 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1151 erratum. For very specific sequences of memory operations, it is
1152 possible for a hazard condition intended for a cache line to instead
1153 be incorrectly associated with a different cache line. This false
1154 hazard might then cause a processor deadlock. The workaround enables
1155 the L1 caching of the NEON accesses and disables the PLD instruction
1156 in the ACTLR register. Note that setting specific bits in the ACTLR
1157 register may not be available in non-secure mode.
1159 config ARM_ERRATA_460075
1160 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1161 depends on CPU_V7
1162 depends on !ARCH_MULTIPLATFORM
1163 help
1164 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1165 erratum. Any asynchronous access to the L2 cache may encounter a
1166 situation in which recent store transactions to the L2 cache are lost
1167 and overwritten with stale memory contents from external memory. The
1168 workaround disables the write-allocate mode for the L2 cache via the
1169 ACTLR register. Note that setting specific bits in the ACTLR register
1170 may not be available in non-secure mode.
1172 config ARM_ERRATA_742230
1173 bool "ARM errata: DMB operation may be faulty"
1174 depends on CPU_V7 && SMP
1175 depends on !ARCH_MULTIPLATFORM
1176 help
1177 This option enables the workaround for the 742230 Cortex-A9
1178 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1179 between two write operations may not ensure the correct visibility
1180 ordering of the two writes. This workaround sets a specific bit in
1181 the diagnostic register of the Cortex-A9 which causes the DMB
1182 instruction to behave as a DSB, ensuring the correct behaviour of
1183 the two writes.
1185 config ARM_ERRATA_742231
1186 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1187 depends on CPU_V7 && SMP
1188 depends on !ARCH_MULTIPLATFORM
1189 help
1190 This option enables the workaround for the 742231 Cortex-A9
1191 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1192 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1193 accessing some data located in the same cache line, may get corrupted
1194 data due to bad handling of the address hazard when the line gets
1195 replaced from one of the CPUs at the same time as another CPU is
1196 accessing it. This workaround sets specific bits in the diagnostic
1197 register of the Cortex-A9 which reduces the linefill issuing
1198 capabilities of the processor.
1200 config PL310_ERRATA_588369
1201 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1202 depends on CACHE_L2X0
1203 help
1204 The PL310 L2 cache controller implements three types of Clean &
1205 Invalidate maintenance operations: by Physical Address
1206 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1207 They are architecturally defined to behave as the execution of a
1208 clean operation followed immediately by an invalidate operation,
1209 both performing to the same memory location. This functionality
1210 is not correctly implemented in PL310 as clean lines are not
1211 invalidated as a result of these operations.
1213 config ARM_ERRATA_643719
1214 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1215 depends on CPU_V7 && SMP
1216 help
1217 This option enables the workaround for the 643719 Cortex-A9 (prior to
1218 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1219 register returns zero when it should return one. The workaround
1220 corrects this value, ensuring cache maintenance operations which use
1221 it behave as intended and avoiding data corruption.
1223 config ARM_ERRATA_720789
1224 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1225 depends on CPU_V7
1226 help
1227 This option enables the workaround for the 720789 Cortex-A9 (prior to
1228 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1229 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1230 As a consequence of this erratum, some TLB entries which should be
1231 invalidated are not, resulting in an incoherency in the system page
1232 tables. The workaround changes the TLB flushing routines to invalidate
1233 entries regardless of the ASID.
1235 config PL310_ERRATA_727915
1236 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1237 depends on CACHE_L2X0
1238 help
1239 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1240 operation (offset 0x7FC). This operation runs in background so that
1241 PL310 can handle normal accesses while it is in progress. Under very
1242 rare circumstances, due to this erratum, write data can be lost when
1243 PL310 treats a cacheable write transaction during a Clean &
1244 Invalidate by Way operation.
1246 config ARM_ERRATA_743622
1247 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1248 depends on CPU_V7
1249 depends on !ARCH_MULTIPLATFORM
1250 help
1251 This option enables the workaround for the 743622 Cortex-A9
1252 (r2p*) erratum. Under very rare conditions, a faulty
1253 optimisation in the Cortex-A9 Store Buffer may lead to data
1254 corruption. This workaround sets a specific bit in the diagnostic
1255 register of the Cortex-A9 which disables the Store Buffer
1256 optimisation, preventing the defect from occurring. This has no
1257 visible impact on the overall performance or power consumption of the
1258 processor.
1260 config ARM_ERRATA_751472
1261 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1262 depends on CPU_V7
1263 depends on !ARCH_MULTIPLATFORM
1264 help
1265 This option enables the workaround for the 751472 Cortex-A9 (prior
1266 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1267 completion of a following broadcasted operation if the second
1268 operation is received by a CPU before the ICIALLUIS has completed,
1269 potentially leading to corrupted entries in the cache or TLB.
1271 config PL310_ERRATA_753970
1272 bool "PL310 errata: cache sync operation may be faulty"
1273 depends on CACHE_PL310
1274 help
1275 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1277 Under some condition the effect of cache sync operation on
1278 the store buffer still remains when the operation completes.
1279 This means that the store buffer is always asked to drain and
1280 this prevents it from merging any further writes. The workaround
1281 is to replace the normal offset of cache sync operation (0x730)
1282 by another offset targeting an unmapped PL310 register 0x740.
1283 This has the same effect as the cache sync operation: store buffer
1284 drain and waiting for all buffers empty.
1286 config ARM_ERRATA_754322
1287 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1288 depends on CPU_V7
1289 help
1290 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1291 r3p*) erratum. A speculative memory access may cause a page table walk
1292 which starts prior to an ASID switch but completes afterwards. This
1293 can populate the micro-TLB with a stale entry which may be hit with
1294 the new ASID. This workaround places two dsb instructions in the mm
1295 switching code so that no page table walks can cross the ASID switch.
1297 config ARM_ERRATA_754327
1298 bool "ARM errata: no automatic Store Buffer drain"
1299 depends on CPU_V7 && SMP
1300 help
1301 This option enables the workaround for the 754327 Cortex-A9 (prior to
1302 r2p0) erratum. The Store Buffer does not have any automatic draining
1303 mechanism and therefore a livelock may occur if an external agent
1304 continuously polls a memory location waiting to observe an update.
1305 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1306 written polling loops from denying visibility of updates to memory.
1308 config ARM_ERRATA_364296
1309 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1310 depends on CPU_V6 && !SMP
1311 help
1312 This options enables the workaround for the 364296 ARM1136
1313 r0p2 erratum (possible cache data corruption with
1314 hit-under-miss enabled). It sets the undocumented bit 31 in
1315 the auxiliary control register and the FI bit in the control
1316 register, thus disabling hit-under-miss without putting the
1317 processor into full low interrupt latency mode. ARM11MPCore
1318 is not affected.
1320 config ARM_ERRATA_764369
1321 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1322 depends on CPU_V7 && SMP
1323 help
1324 This option enables the workaround for erratum 764369
1325 affecting Cortex-A9 MPCore with two or more processors (all
1326 current revisions). Under certain timing circumstances, a data
1327 cache line maintenance operation by MVA targeting an Inner
1328 Shareable memory region may fail to proceed up to either the
1329 Point of Coherency or to the Point of Unification of the
1330 system. This workaround adds a DSB instruction before the
1331 relevant cache maintenance functions and sets a specific bit
1332 in the diagnostic control register of the SCU.
1334 config PL310_ERRATA_769419
1335 bool "PL310 errata: no automatic Store Buffer drain"
1336 depends on CACHE_L2X0
1337 help
1338 On revisions of the PL310 prior to r3p2, the Store Buffer does
1339 not automatically drain. This can cause normal, non-cacheable
1340 writes to be retained when the memory system is idle, leading
1341 to suboptimal I/O performance for drivers using coherent DMA.
1342 This option adds a write barrier to the cpu_idle loop so that,
1343 on systems with an outer cache, the store buffer is drained
1344 explicitly.
1346 config ARM_ERRATA_775420
1347 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1348 depends on CPU_V7
1349 help
1350 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1351 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1352 operation aborts with MMU exception, it might cause the processor
1353 to deadlock. This workaround puts DSB before executing ISB if
1354 an abort may occur on cache maintenance.
1356 config ARM_ERRATA_798181
1357 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1358 depends on CPU_V7 && SMP
1359 help
1360 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1361 adequately shooting down all use of the old entries. This
1362 option enables the Linux kernel workaround for this erratum
1363 which sends an IPI to the CPUs that are running the same ASID
1364 as the one being invalidated.
1366 endmenu
1368 source "arch/arm/common/Kconfig"
1370 menu "Bus support"
1372 config ARM_AMBA
1373 bool
1375 config ISA
1376 bool
1377 help
1378 Find out whether you have ISA slots on your motherboard. ISA is the
1379 name of a bus system, i.e. the way the CPU talks to the other stuff
1380 inside your box. Other bus systems are PCI, EISA, MicroChannel
1381 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1382 newer boards don't support it. If you have ISA, say Y, otherwise N.
1384 # Select ISA DMA controller support
1385 config ISA_DMA
1386 bool
1387 select ISA_DMA_API
1389 # Select ISA DMA interface
1390 config ISA_DMA_API
1391 bool
1393 config PCI
1394 bool "PCI support" if MIGHT_HAVE_PCI
1395 help
1396 Find out whether you have a PCI motherboard. PCI is the name of a
1397 bus system, i.e. the way the CPU talks to the other stuff inside
1398 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1399 VESA. If you have PCI, say Y, otherwise N.
1401 config PCI_DOMAINS
1402 bool
1403 depends on PCI
1405 config PCI_NANOENGINE
1406 bool "BSE nanoEngine PCI support"
1407 depends on SA1100_NANOENGINE
1408 help
1409 Enable PCI on the BSE nanoEngine board.
1411 config PCI_SYSCALL
1412 def_bool PCI
1414 # Select the host bridge type
1415 config PCI_HOST_VIA82C505
1416 bool
1417 depends on PCI && ARCH_SHARK
1418 default y
1420 config PCI_HOST_ITE8152
1421 bool
1422 depends on PCI && MACH_ARMCORE
1423 default y
1424 select DMABOUNCE
1426 source "drivers/pci/Kconfig"
1427 source "drivers/pci/pcie/Kconfig"
1429 source "drivers/pcmcia/Kconfig"
1431 endmenu
1433 menu "Kernel Features"
1435 config HAVE_SMP
1436 bool
1437 help
1438 This option should be selected by machines which have an SMP-
1439 capable CPU.
1441 The only effect of this option is to make the SMP-related
1442 options available to the user for configuration.
1444 config SMP
1445 bool "Symmetric Multi-Processing"
1446 depends on CPU_V6K || CPU_V7
1447 depends on GENERIC_CLOCKEVENTS
1448 depends on HAVE_SMP
1449 depends on MMU
1450 select USE_GENERIC_SMP_HELPERS
1451 help
1452 This enables support for systems with more than one CPU. If you have
1453 a system with only one CPU, like most personal computers, say N. If
1454 you have a system with more than one CPU, say Y.
1456 If you say N here, the kernel will run on single and multiprocessor
1457 machines, but will use only one CPU of a multiprocessor machine. If
1458 you say Y here, the kernel will run on many, but not all, single
1459 processor machines. On a single processor machine, the kernel will
1460 run faster if you say N here.
1462 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1463 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1464 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1466 If you don't know what to do here, say N.
1468 config SMP_ON_UP
1469 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1470 depends on SMP && !XIP_KERNEL
1471 default y
1472 help
1473 SMP kernels contain instructions which fail on non-SMP processors.
1474 Enabling this option allows the kernel to modify itself to make
1475 these instructions safe. Disabling it allows about 1K of space
1476 savings.
1478 If you don't know what to do here, say Y.
1480 config ARM_CPU_TOPOLOGY
1481 bool "Support cpu topology definition"
1482 depends on SMP && CPU_V7
1483 default y
1484 help
1485 Support ARM cpu topology definition. The MPIDR register defines
1486 affinity between processors which is then used to describe the cpu
1487 topology of an ARM System.
1489 config SCHED_MC
1490 bool "Multi-core scheduler support"
1491 depends on ARM_CPU_TOPOLOGY
1492 help
1493 Multi-core scheduler support improves the CPU scheduler's decision
1494 making when dealing with multi-core CPU chips at a cost of slightly
1495 increased overhead in some places. If unsure say N here.
1497 config SCHED_SMT
1498 bool "SMT scheduler support"
1499 depends on ARM_CPU_TOPOLOGY
1500 help
1501 Improves the CPU scheduler's decision making when dealing with
1502 MultiThreading at a cost of slightly increased overhead in some
1503 places. If unsure say N here.
1505 config HAVE_ARM_SCU
1506 bool
1507 help
1508 This option enables support for the ARM system coherency unit
1510 config HAVE_ARM_ARCH_TIMER
1511 bool "Architected timer support"
1512 depends on CPU_V7
1513 select ARM_ARCH_TIMER
1514 help
1515 This option enables support for the ARM architected timer
1517 config HAVE_ARM_TWD
1518 bool
1519 depends on SMP
1520 select CLKSRC_OF if OF
1521 help
1522 This options enables support for the ARM timer and watchdog unit
1524 config MCPM
1525 bool "Multi-Cluster Power Management"
1526 depends on CPU_V7 && SMP
1527 help
1528 This option provides the common power management infrastructure
1529 for (multi-)cluster based systems, such as big.LITTLE based
1530 systems.
1532 choice
1533 prompt "Memory split"
1534 default VMSPLIT_3G
1535 help
1536 Select the desired split between kernel and user memory.
1538 If you are not absolutely sure what you are doing, leave this
1539 option alone!
1541 config VMSPLIT_3G
1542 bool "3G/1G user/kernel split"
1543 config VMSPLIT_2G
1544 bool "2G/2G user/kernel split"
1545 config VMSPLIT_1G
1546 bool "1G/3G user/kernel split"
1547 endchoice
1549 config PAGE_OFFSET
1550 hex
1551 default 0x40000000 if VMSPLIT_1G
1552 default 0x80000000 if VMSPLIT_2G
1553 default 0xC0000000
1555 config NR_CPUS
1556 int "Maximum number of CPUs (2-32)"
1557 range 2 32
1558 depends on SMP
1559 default "4"
1561 config HOTPLUG_CPU
1562 bool "Support for hot-pluggable CPUs"
1563 depends on SMP
1564 help
1565 Say Y here to experiment with turning CPUs off and on. CPUs
1566 can be controlled through /sys/devices/system/cpu.
1568 config ARM_PSCI
1569 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1570 depends on CPU_V7
1571 help
1572 Say Y here if you want Linux to communicate with system firmware
1573 implementing the PSCI specification for CPU-centric power
1574 management operations described in ARM document number ARM DEN
1575 0022A ("Power State Coordination Interface System Software on
1576 ARM processors").
1578 config LOCAL_TIMERS
1579 bool "Use local timer interrupts"
1580 depends on SMP
1581 default y
1582 help
1583 Enable support for local timers on SMP platforms, rather then the
1584 legacy IPI broadcast method. Local timers allows the system
1585 accounting to be spread across the timer interval, preventing a
1586 "thundering herd" at every timer tick.
1588 # The GPIO number here must be sorted by descending number. In case of
1589 # a multiplatform kernel, we just want the highest value required by the
1590 # selected platforms.
1591 config ARCH_NR_GPIO
1592 int
1593 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1594 default 512 if SOC_OMAP5
1595 default 512 if ARCH_KEYSTONE
1596 default 392 if ARCH_U8500
1597 default 352 if ARCH_VT8500
1598 default 288 if ARCH_SUNXI
1599 default 264 if MACH_H4700
1600 default 0
1601 help
1602 Maximum number of GPIOs in the system.
1604 If unsure, leave the default value.
1606 source kernel/Kconfig.preempt
1608 config HZ
1609 int
1610 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1611 ARCH_S5PV210 || ARCH_EXYNOS4
1612 default AT91_TIMER_HZ if ARCH_AT91
1613 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1614 default 100
1616 config SCHED_HRTICK
1617 def_bool HIGH_RES_TIMERS
1619 config THUMB2_KERNEL
1620 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1621 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1622 default y if CPU_THUMBONLY
1623 select AEABI
1624 select ARM_ASM_UNIFIED
1625 select ARM_UNWIND
1626 help
1627 By enabling this option, the kernel will be compiled in
1628 Thumb-2 mode. A compiler/assembler that understand the unified
1629 ARM-Thumb syntax is needed.
1631 If unsure, say N.
1633 config THUMB2_AVOID_R_ARM_THM_JUMP11
1634 bool "Work around buggy Thumb-2 short branch relocations in gas"
1635 depends on THUMB2_KERNEL && MODULES
1636 default y
1637 help
1638 Various binutils versions can resolve Thumb-2 branches to
1639 locally-defined, preemptible global symbols as short-range "b.n"
1640 branch instructions.
1642 This is a problem, because there's no guarantee the final
1643 destination of the symbol, or any candidate locations for a
1644 trampoline, are within range of the branch. For this reason, the
1645 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1646 relocation in modules at all, and it makes little sense to add
1647 support.
1649 The symptom is that the kernel fails with an "unsupported
1650 relocation" error when loading some modules.
1652 Until fixed tools are available, passing
1653 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1654 code which hits this problem, at the cost of a bit of extra runtime
1655 stack usage in some cases.
1657 The problem is described in more detail at:
1658 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1660 Only Thumb-2 kernels are affected.
1662 Unless you are sure your tools don't have this problem, say Y.
1664 config ARM_ASM_UNIFIED
1665 bool
1667 config AEABI
1668 bool "Use the ARM EABI to compile the kernel"
1669 help
1670 This option allows for the kernel to be compiled using the latest
1671 ARM ABI (aka EABI). This is only useful if you are using a user
1672 space environment that is also compiled with EABI.
1674 Since there are major incompatibilities between the legacy ABI and
1675 EABI, especially with regard to structure member alignment, this
1676 option also changes the kernel syscall calling convention to
1677 disambiguate both ABIs and allow for backward compatibility support
1678 (selected with CONFIG_OABI_COMPAT).
1680 To use this you need GCC version 4.0.0 or later.
1682 config OABI_COMPAT
1683 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1684 depends on AEABI && !THUMB2_KERNEL
1685 default y
1686 help
1687 This option preserves the old syscall interface along with the
1688 new (ARM EABI) one. It also provides a compatibility layer to
1689 intercept syscalls that have structure arguments which layout
1690 in memory differs between the legacy ABI and the new ARM EABI
1691 (only for non "thumb" binaries). This option adds a tiny
1692 overhead to all syscalls and produces a slightly larger kernel.
1693 If you know you'll be using only pure EABI user space then you
1694 can say N here. If this option is not selected and you attempt
1695 to execute a legacy ABI binary then the result will be
1696 UNPREDICTABLE (in fact it can be predicted that it won't work
1697 at all). If in doubt say Y.
1699 config ARCH_HAS_HOLES_MEMORYMODEL
1700 bool
1702 config ARCH_SPARSEMEM_ENABLE
1703 bool
1705 config ARCH_SPARSEMEM_DEFAULT
1706 def_bool ARCH_SPARSEMEM_ENABLE
1708 config ARCH_SELECT_MEMORY_MODEL
1709 def_bool ARCH_SPARSEMEM_ENABLE
1711 config HAVE_ARCH_PFN_VALID
1712 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1714 config HIGHMEM
1715 bool "High Memory Support"
1716 depends on MMU
1717 help
1718 The address space of ARM processors is only 4 Gigabytes large
1719 and it has to accommodate user address space, kernel address
1720 space as well as some memory mapped IO. That means that, if you
1721 have a large amount of physical memory and/or IO, not all of the
1722 memory can be "permanently mapped" by the kernel. The physical
1723 memory that is not permanently mapped is called "high memory".
1725 Depending on the selected kernel/user memory split, minimum
1726 vmalloc space and actual amount of RAM, you may not need this
1727 option which should result in a slightly faster kernel.
1729 If unsure, say n.
1731 config HIGHPTE
1732 bool "Allocate 2nd-level pagetables from highmem"
1733 depends on HIGHMEM
1735 config HW_PERF_EVENTS
1736 bool "Enable hardware performance counter support for perf events"
1737 depends on PERF_EVENTS
1738 default y
1739 help
1740 Enable hardware performance counter support for perf events. If
1741 disabled, perf events will use software events only.
1743 source "mm/Kconfig"
1745 config FORCE_MAX_ZONEORDER
1746 int "Maximum zone order" if ARCH_SHMOBILE
1747 range 11 64 if ARCH_SHMOBILE
1748 default "12" if SOC_AM33XX
1749 default "9" if SA1111
1750 default "11"
1751 help
1752 The kernel memory allocator divides physically contiguous memory
1753 blocks into "zones", where each zone is a power of two number of
1754 pages. This option selects the largest power of two that the kernel
1755 keeps in the memory allocator. If you need to allocate very large
1756 blocks of physically contiguous memory, then you may need to
1757 increase this value.
1759 This config option is actually maximum order plus one. For example,
1760 a value of 11 means that the largest free memory block is 2^10 pages.
1762 config ALIGNMENT_TRAP
1763 bool
1764 depends on CPU_CP15_MMU
1765 default y if !ARCH_EBSA110
1766 select HAVE_PROC_CPU if PROC_FS
1767 help
1768 ARM processors cannot fetch/store information which is not
1769 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1770 address divisible by 4. On 32-bit ARM processors, these non-aligned
1771 fetch/store instructions will be emulated in software if you say
1772 here, which has a severe performance impact. This is necessary for
1773 correct operation of some network protocols. With an IP-only
1774 configuration it is safe to say N, otherwise say Y.
1776 config UACCESS_WITH_MEMCPY
1777 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1778 depends on MMU
1779 default y if CPU_FEROCEON
1780 help
1781 Implement faster copy_to_user and clear_user methods for CPU
1782 cores where a 8-word STM instruction give significantly higher
1783 memory write throughput than a sequence of individual 32bit stores.
1785 A possible side effect is a slight increase in scheduling latency
1786 between threads sharing the same address space if they invoke
1787 such copy operations with large buffers.
1789 However, if the CPU data cache is using a write-allocate mode,
1790 this option is unlikely to provide any performance gain.
1792 config SECCOMP
1793 bool
1794 prompt "Enable seccomp to safely compute untrusted bytecode"
1795 ---help---
1796 This kernel feature is useful for number crunching applications
1797 that may need to compute untrusted bytecode during their
1798 execution. By using pipes or other transports made available to
1799 the process as file descriptors supporting the read/write
1800 syscalls, it's possible to isolate those applications in
1801 their own address space using seccomp. Once seccomp is
1802 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1803 and the task is only allowed to execute a few safe syscalls
1804 defined by each seccomp mode.
1806 config CC_STACKPROTECTOR
1807 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1808 help
1809 This option turns on the -fstack-protector GCC feature. This
1810 feature puts, at the beginning of functions, a canary value on
1811 the stack just before the return address, and validates
1812 the value just before actually returning. Stack based buffer
1813 overflows (that need to overwrite this return address) now also
1814 overwrite the canary, which gets detected and the attack is then
1815 neutralized via a kernel panic.
1816 This feature requires gcc version 4.2 or above.
1818 config XEN_DOM0
1819 def_bool y
1820 depends on XEN
1822 config XEN
1823 bool "Xen guest support on ARM (EXPERIMENTAL)"
1824 depends on ARM && AEABI && OF
1825 depends on CPU_V7 && !CPU_V6
1826 depends on !GENERIC_ATOMIC64
1827 select ARM_PSCI
1828 help
1829 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1831 endmenu
1833 menu "Boot options"
1835 config USE_OF
1836 bool "Flattened Device Tree support"
1837 select IRQ_DOMAIN
1838 select OF
1839 select OF_EARLY_FLATTREE
1840 help
1841 Include support for flattened device tree machine descriptions.
1843 config ATAGS
1844 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1845 default y
1846 help
1847 This is the traditional way of passing data to the kernel at boot
1848 time. If you are solely relying on the flattened device tree (or
1849 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1850 to remove ATAGS support from your kernel binary. If unsure,
1851 leave this to y.
1853 config DEPRECATED_PARAM_STRUCT
1854 bool "Provide old way to pass kernel parameters"
1855 depends on ATAGS
1856 help
1857 This was deprecated in 2001 and announced to live on for 5 years.
1858 Some old boot loaders still use this way.
1860 # Compressed boot loader in ROM. Yes, we really want to ask about
1861 # TEXT and BSS so we preserve their values in the config files.
1862 config ZBOOT_ROM_TEXT
1863 hex "Compressed ROM boot loader base address"
1864 default "0"
1865 help
1866 The physical address at which the ROM-able zImage is to be
1867 placed in the target. Platforms which normally make use of
1868 ROM-able zImage formats normally set this to a suitable
1869 value in their defconfig file.
1871 If ZBOOT_ROM is not enabled, this has no effect.
1873 config ZBOOT_ROM_BSS
1874 hex "Compressed ROM boot loader BSS address"
1875 default "0"
1876 help
1877 The base address of an area of read/write memory in the target
1878 for the ROM-able zImage which must be available while the
1879 decompressor is running. It must be large enough to hold the
1880 entire decompressed kernel plus an additional 128 KiB.
1881 Platforms which normally make use of ROM-able zImage formats
1882 normally set this to a suitable value in their defconfig file.
1884 If ZBOOT_ROM is not enabled, this has no effect.
1886 config ZBOOT_ROM
1887 bool "Compressed boot loader in ROM/flash"
1888 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1889 help
1890 Say Y here if you intend to execute your compressed kernel image
1891 (zImage) directly from ROM or flash. If unsure, say N.
1893 choice
1894 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1895 depends on ZBOOT_ROM && ARCH_SH7372
1896 default ZBOOT_ROM_NONE
1897 help
1898 Include experimental SD/MMC loading code in the ROM-able zImage.
1899 With this enabled it is possible to write the ROM-able zImage
1900 kernel image to an MMC or SD card and boot the kernel straight
1901 from the reset vector. At reset the processor Mask ROM will load
1902 the first part of the ROM-able zImage which in turn loads the
1903 rest the kernel image to RAM.
1905 config ZBOOT_ROM_NONE
1906 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1907 help
1908 Do not load image from SD or MMC
1910 config ZBOOT_ROM_MMCIF
1911 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1912 help
1913 Load image from MMCIF hardware block.
1915 config ZBOOT_ROM_SH_MOBILE_SDHI
1916 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1917 help
1918 Load image from SDHI hardware block
1920 endchoice
1922 config ARM_APPENDED_DTB
1923 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1924 depends on OF && !ZBOOT_ROM
1925 help
1926 With this option, the boot code will look for a device tree binary
1927 (DTB) appended to zImage
1928 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1930 This is meant as a backward compatibility convenience for those
1931 systems with a bootloader that can't be upgraded to accommodate
1932 the documented boot protocol using a device tree.
1934 Beware that there is very little in terms of protection against
1935 this option being confused by leftover garbage in memory that might
1936 look like a DTB header after a reboot if no actual DTB is appended
1937 to zImage. Do not leave this option active in a production kernel
1938 if you don't intend to always append a DTB. Proper passing of the
1939 location into r2 of a bootloader provided DTB is always preferable
1940 to this option.
1942 config ARM_ATAG_DTB_COMPAT
1943 bool "Supplement the appended DTB with traditional ATAG information"
1944 depends on ARM_APPENDED_DTB
1945 help
1946 Some old bootloaders can't be updated to a DTB capable one, yet
1947 they provide ATAGs with memory configuration, the ramdisk address,
1948 the kernel cmdline string, etc. Such information is dynamically
1949 provided by the bootloader and can't always be stored in a static
1950 DTB. To allow a device tree enabled kernel to be used with such
1951 bootloaders, this option allows zImage to extract the information
1952 from the ATAG list and store it at run time into the appended DTB.
1954 choice
1955 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1956 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1958 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1959 bool "Use bootloader kernel arguments if available"
1960 help
1961 Uses the command-line options passed by the boot loader instead of
1962 the device tree bootargs property. If the boot loader doesn't provide
1963 any, the device tree bootargs property will be used.
1965 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1966 bool "Extend with bootloader kernel arguments"
1967 help
1968 The command-line arguments provided by the boot loader will be
1969 appended to the the device tree bootargs property.
1971 endchoice
1973 config CMDLINE
1974 string "Default kernel command string"
1975 default ""
1976 help
1977 On some architectures (EBSA110 and CATS), there is currently no way
1978 for the boot loader to pass arguments to the kernel. For these
1979 architectures, you should supply some command-line options at build
1980 time by entering them here. As a minimum, you should specify the
1981 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1983 choice
1984 prompt "Kernel command line type" if CMDLINE != ""
1985 default CMDLINE_FROM_BOOTLOADER
1986 depends on ATAGS
1988 config CMDLINE_FROM_BOOTLOADER
1989 bool "Use bootloader kernel arguments if available"
1990 help
1991 Uses the command-line options passed by the boot loader. If
1992 the boot loader doesn't provide any, the default kernel command
1993 string provided in CMDLINE will be used.
1995 config CMDLINE_EXTEND
1996 bool "Extend bootloader kernel arguments"
1997 help
1998 The command-line arguments provided by the boot loader will be
1999 appended to the default kernel command string.
2001 config CMDLINE_FORCE
2002 bool "Always use the default kernel command string"
2003 help
2004 Always use the default kernel command string, even if the boot
2005 loader passes other arguments to the kernel.
2006 This is useful if you cannot or don't want to change the
2007 command-line options your boot loader passes to the kernel.
2008 endchoice
2010 config XIP_KERNEL
2011 bool "Kernel Execute-In-Place from ROM"
2012 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2013 help
2014 Execute-In-Place allows the kernel to run from non-volatile storage
2015 directly addressable by the CPU, such as NOR flash. This saves RAM
2016 space since the text section of the kernel is not loaded from flash
2017 to RAM. Read-write sections, such as the data section and stack,
2018 are still copied to RAM. The XIP kernel is not compressed since
2019 it has to run directly from flash, so it will take more space to
2020 store it. The flash address used to link the kernel object files,
2021 and for storing it, is configuration dependent. Therefore, if you
2022 say Y here, you must know the proper physical address where to
2023 store the kernel image depending on your own flash memory usage.
2025 Also note that the make target becomes "make xipImage" rather than
2026 "make zImage" or "make Image". The final kernel binary to put in
2027 ROM memory will be arch/arm/boot/xipImage.
2029 If unsure, say N.
2031 config XIP_PHYS_ADDR
2032 hex "XIP Kernel Physical Location"
2033 depends on XIP_KERNEL
2034 default "0x00080000"
2035 help
2036 This is the physical address in your flash memory the kernel will
2037 be linked for and stored to. This address is dependent on your
2038 own flash usage.
2040 config KEXEC
2041 bool "Kexec system call (EXPERIMENTAL)"
2042 depends on (!SMP || PM_SLEEP_SMP)
2043 help
2044 kexec is a system call that implements the ability to shutdown your
2045 current kernel, and to start another kernel. It is like a reboot
2046 but it is independent of the system firmware. And like a reboot
2047 you can start any kernel with it, not just Linux.
2049 It is an ongoing process to be certain the hardware in a machine
2050 is properly shutdown, so do not be surprised if this code does not
2051 initially work for you. It may help to enable device hotplugging
2052 support.
2054 config ATAGS_PROC
2055 bool "Export atags in procfs"
2056 depends on ATAGS && KEXEC
2057 default y
2058 help
2059 Should the atags used to boot the kernel be exported in an "atags"
2060 file in procfs. Useful with kexec.
2062 config CRASH_DUMP
2063 bool "Build kdump crash kernel (EXPERIMENTAL)"
2064 help
2065 Generate crash dump after being started by kexec. This should
2066 be normally only set in special crash dump kernels which are
2067 loaded in the main kernel with kexec-tools into a specially
2068 reserved region and then later executed after a crash by
2069 kdump/kexec. The crash dump kernel must be compiled to a
2070 memory address not used by the main kernel
2072 For more details see Documentation/kdump/kdump.txt
2074 config AUTO_ZRELADDR
2075 bool "Auto calculation of the decompressed kernel image address"
2076 depends on !ZBOOT_ROM
2077 help
2078 ZRELADDR is the physical address where the decompressed kernel
2079 image will be placed. If AUTO_ZRELADDR is selected, the address
2080 will be determined at run-time by masking the current IP with
2081 0xf8000000. This assumes the zImage being placed in the first 128MB
2082 from start of memory.
2084 endmenu
2086 menu "CPU Power Management"
2088 if ARCH_HAS_CPUFREQ
2089 source "drivers/cpufreq/Kconfig"
2090 endif
2092 source "drivers/cpuidle/Kconfig"
2094 endmenu
2096 menu "Floating point emulation"
2098 comment "At least one emulation must be selected"
2100 config FPE_NWFPE
2101 bool "NWFPE math emulation"
2102 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2103 ---help---
2104 Say Y to include the NWFPE floating point emulator in the kernel.
2105 This is necessary to run most binaries. Linux does not currently
2106 support floating point hardware so you need to say Y here even if
2107 your machine has an FPA or floating point co-processor podule.
2109 You may say N here if you are going to load the Acorn FPEmulator
2110 early in the bootup.
2112 config FPE_NWFPE_XP
2113 bool "Support extended precision"
2114 depends on FPE_NWFPE
2115 help
2116 Say Y to include 80-bit support in the kernel floating-point
2117 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2118 Note that gcc does not generate 80-bit operations by default,
2119 so in most cases this option only enlarges the size of the
2120 floating point emulator without any good reason.
2122 You almost surely want to say N here.
2124 config FPE_FASTFPE
2125 bool "FastFPE math emulation (EXPERIMENTAL)"
2126 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2127 ---help---
2128 Say Y here to include the FAST floating point emulator in the kernel.
2129 This is an experimental much faster emulator which now also has full
2130 precision for the mantissa. It does not support any exceptions.
2131 It is very simple, and approximately 3-6 times faster than NWFPE.
2133 It should be sufficient for most programs. It may be not suitable
2134 for scientific calculations, but you have to check this for yourself.
2135 If you do not feel you need a faster FP emulation you should better
2136 choose NWFPE.
2138 config VFP
2139 bool "VFP-format floating point maths"
2140 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2141 help
2142 Say Y to include VFP support code in the kernel. This is needed
2143 if your hardware includes a VFP unit.
2145 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2146 release notes and additional status information.
2148 Say N if your target does not have VFP hardware.
2150 config VFPv3
2151 bool
2152 depends on VFP
2153 default y if CPU_V7
2155 config NEON
2156 bool "Advanced SIMD (NEON) Extension support"
2157 depends on VFPv3 && CPU_V7
2158 help
2159 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2160 Extension.
2162 endmenu
2164 menu "Userspace binary formats"
2166 source "fs/Kconfig.binfmt"
2168 config ARTHUR
2169 tristate "RISC OS personality"
2170 depends on !AEABI
2171 help
2172 Say Y here to include the kernel code necessary if you want to run
2173 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2174 experimental; if this sounds frightening, say N and sleep in peace.
2175 You can also say M here to compile this support as a module (which
2176 will be called arthur).
2178 endmenu
2180 menu "Power management options"
2182 source "kernel/power/Kconfig"
2184 config ARCH_SUSPEND_POSSIBLE
2185 depends on !ARCH_S5PC100
2186 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2187 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2188 def_bool y
2190 config ARM_CPU_SUSPEND
2191 def_bool PM_SLEEP
2193 endmenu
2195 source "net/Kconfig"
2197 source "drivers/Kconfig"
2199 source "fs/Kconfig"
2201 source "arch/arm/Kconfig.debug"
2203 source "security/Kconfig"
2205 source "crypto/Kconfig"
2207 source "lib/Kconfig"
2209 source "arch/arm/kvm/Kconfig"