2 * Copyright (C) 2007 Atmel Corporation.
3 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 #include <linux/module.h>
12 #include <linux/of_address.h>
14 #include <asm/system_misc.h>
15 #include <asm/mach/map.h>
17 #include <mach/hardware.h>
19 #include <mach/at91_dbgu.h>
20 #include <mach/at91_pmc.h>
21 #include <mach/at91_shdwc.h>
26 struct at91_init_soc __initdata at91_boot_soc
;
28 struct at91_socinfo at91_soc_initdata
;
29 EXPORT_SYMBOL(at91_soc_initdata
);
31 void __init
at91rm9200_set_type(int type
)
33 if (type
== ARCH_REVISON_9200_PQFP
)
34 at91_soc_initdata
.subtype
= AT91_SOC_RM9200_PQFP
;
36 at91_soc_initdata
.subtype
= AT91_SOC_RM9200_BGA
;
38 pr_info("AT91: filled in soc subtype: %s\n",
39 at91_get_soc_subtype(&at91_soc_initdata
));
42 void __init
at91_init_irq_default(void)
44 at91_init_interrupts(at91_boot_soc
.default_irq_priority
);
47 void __init
at91_init_interrupts(unsigned int *priority
)
49 /* Initialize the AIC interrupt controller */
50 at91_aic_init(priority
);
52 /* Enable GPIO interrupts */
53 at91_gpio_irq_setup();
56 void __iomem
*at91_ramc_base
[2];
57 EXPORT_SYMBOL_GPL(at91_ramc_base
);
59 void __init
at91_ioremap_ramc(int id
, u32 addr
, u32 size
)
61 if (id
< 0 || id
> 1) {
62 pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id
);
65 at91_ramc_base
[id
] = ioremap(addr
, size
);
66 if (!at91_ramc_base
[id
])
67 panic("Impossible to ioremap ramc.%d 0x%x\n", id
, addr
);
70 static struct map_desc sram_desc
[2] __initdata
;
72 void __init
at91_init_sram(int bank
, unsigned long base
, unsigned int length
)
74 struct map_desc
*desc
= &sram_desc
[bank
];
76 desc
->virtual = (unsigned long)AT91_IO_VIRT_BASE
- length
;
78 desc
->virtual -= sram_desc
[bank
- 1].length
;
80 desc
->pfn
= __phys_to_pfn(base
);
81 desc
->length
= length
;
82 desc
->type
= MT_DEVICE
;
84 pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n",
85 base
, length
, desc
->virtual);
87 iotable_init(desc
, 1);
90 static struct map_desc at91_io_desc __initdata __maybe_unused
= {
91 .virtual = (unsigned long)AT91_VA_BASE_SYS
,
92 .pfn
= __phys_to_pfn(AT91_BASE_SYS
),
97 static void __init
soc_detect(u32 dbgu_base
)
101 cidr
= __raw_readl(AT91_IO_P2V(dbgu_base
) + AT91_DBGU_CIDR
);
102 socid
= cidr
& ~AT91_CIDR_VERSION
;
105 case ARCH_ID_AT91RM9200
:
106 at91_soc_initdata
.type
= AT91_SOC_RM9200
;
107 at91_boot_soc
= at91rm9200_soc
;
110 case ARCH_ID_AT91SAM9260
:
111 at91_soc_initdata
.type
= AT91_SOC_SAM9260
;
112 at91_boot_soc
= at91sam9260_soc
;
115 case ARCH_ID_AT91SAM9261
:
116 at91_soc_initdata
.type
= AT91_SOC_SAM9261
;
117 at91_boot_soc
= at91sam9261_soc
;
120 case ARCH_ID_AT91SAM9263
:
121 at91_soc_initdata
.type
= AT91_SOC_SAM9263
;
122 at91_boot_soc
= at91sam9263_soc
;
125 case ARCH_ID_AT91SAM9G20
:
126 at91_soc_initdata
.type
= AT91_SOC_SAM9G20
;
127 at91_boot_soc
= at91sam9260_soc
;
130 case ARCH_ID_AT91SAM9G45
:
131 at91_soc_initdata
.type
= AT91_SOC_SAM9G45
;
132 if (cidr
== ARCH_ID_AT91SAM9G45ES
)
133 at91_soc_initdata
.subtype
= AT91_SOC_SAM9G45ES
;
134 at91_boot_soc
= at91sam9g45_soc
;
137 case ARCH_ID_AT91SAM9RL64
:
138 at91_soc_initdata
.type
= AT91_SOC_SAM9RL
;
139 at91_boot_soc
= at91sam9rl_soc
;
142 case ARCH_ID_AT91SAM9X5
:
143 at91_soc_initdata
.type
= AT91_SOC_SAM9X5
;
144 at91_boot_soc
= at91sam9x5_soc
;
147 case ARCH_ID_AT91SAM9N12
:
148 at91_soc_initdata
.type
= AT91_SOC_SAM9N12
;
149 at91_boot_soc
= at91sam9n12_soc
;
154 if ((cidr
& ~AT91_CIDR_EXT
) == ARCH_ID_AT91SAM9G10
) {
155 at91_soc_initdata
.type
= AT91_SOC_SAM9G10
;
156 at91_boot_soc
= at91sam9261_soc
;
159 else if ((cidr
& AT91_CIDR_ARCH
) == ARCH_FAMILY_AT91SAM9XE
) {
160 at91_soc_initdata
.type
= AT91_SOC_SAM9260
;
161 at91_soc_initdata
.subtype
= AT91_SOC_SAM9XE
;
162 at91_boot_soc
= at91sam9260_soc
;
165 if (!at91_soc_is_detected())
168 at91_soc_initdata
.cidr
= cidr
;
170 /* sub version of soc */
171 at91_soc_initdata
.exid
= __raw_readl(AT91_IO_P2V(dbgu_base
) + AT91_DBGU_EXID
);
173 if (at91_soc_initdata
.type
== AT91_SOC_SAM9G45
) {
174 switch (at91_soc_initdata
.exid
) {
175 case ARCH_EXID_AT91SAM9M10
:
176 at91_soc_initdata
.subtype
= AT91_SOC_SAM9M10
;
178 case ARCH_EXID_AT91SAM9G46
:
179 at91_soc_initdata
.subtype
= AT91_SOC_SAM9G46
;
181 case ARCH_EXID_AT91SAM9M11
:
182 at91_soc_initdata
.subtype
= AT91_SOC_SAM9M11
;
187 if (at91_soc_initdata
.type
== AT91_SOC_SAM9X5
) {
188 switch (at91_soc_initdata
.exid
) {
189 case ARCH_EXID_AT91SAM9G15
:
190 at91_soc_initdata
.subtype
= AT91_SOC_SAM9G15
;
192 case ARCH_EXID_AT91SAM9G35
:
193 at91_soc_initdata
.subtype
= AT91_SOC_SAM9G35
;
195 case ARCH_EXID_AT91SAM9X35
:
196 at91_soc_initdata
.subtype
= AT91_SOC_SAM9X35
;
198 case ARCH_EXID_AT91SAM9G25
:
199 at91_soc_initdata
.subtype
= AT91_SOC_SAM9G25
;
201 case ARCH_EXID_AT91SAM9X25
:
202 at91_soc_initdata
.subtype
= AT91_SOC_SAM9X25
;
208 static const char *soc_name
[] = {
209 [AT91_SOC_RM9200
] = "at91rm9200",
210 [AT91_SOC_SAM9260
] = "at91sam9260",
211 [AT91_SOC_SAM9261
] = "at91sam9261",
212 [AT91_SOC_SAM9263
] = "at91sam9263",
213 [AT91_SOC_SAM9G10
] = "at91sam9g10",
214 [AT91_SOC_SAM9G20
] = "at91sam9g20",
215 [AT91_SOC_SAM9G45
] = "at91sam9g45",
216 [AT91_SOC_SAM9RL
] = "at91sam9rl",
217 [AT91_SOC_SAM9X5
] = "at91sam9x5",
218 [AT91_SOC_SAM9N12
] = "at91sam9n12",
219 [AT91_SOC_NONE
] = "Unknown"
222 const char *at91_get_soc_type(struct at91_socinfo
*c
)
224 return soc_name
[c
->type
];
226 EXPORT_SYMBOL(at91_get_soc_type
);
228 static const char *soc_subtype_name
[] = {
229 [AT91_SOC_RM9200_BGA
] = "at91rm9200 BGA",
230 [AT91_SOC_RM9200_PQFP
] = "at91rm9200 PQFP",
231 [AT91_SOC_SAM9XE
] = "at91sam9xe",
232 [AT91_SOC_SAM9G45ES
] = "at91sam9g45es",
233 [AT91_SOC_SAM9M10
] = "at91sam9m10",
234 [AT91_SOC_SAM9G46
] = "at91sam9g46",
235 [AT91_SOC_SAM9M11
] = "at91sam9m11",
236 [AT91_SOC_SAM9G15
] = "at91sam9g15",
237 [AT91_SOC_SAM9G35
] = "at91sam9g35",
238 [AT91_SOC_SAM9X35
] = "at91sam9x35",
239 [AT91_SOC_SAM9G25
] = "at91sam9g25",
240 [AT91_SOC_SAM9X25
] = "at91sam9x25",
241 [AT91_SOC_SUBTYPE_NONE
] = "Unknown"
244 const char *at91_get_soc_subtype(struct at91_socinfo
*c
)
246 return soc_subtype_name
[c
->subtype
];
248 EXPORT_SYMBOL(at91_get_soc_subtype
);
250 void __init
at91_map_io(void)
252 /* Map peripherals */
253 iotable_init(&at91_io_desc
, 1);
255 at91_soc_initdata
.type
= AT91_SOC_NONE
;
256 at91_soc_initdata
.subtype
= AT91_SOC_SUBTYPE_NONE
;
258 soc_detect(AT91_BASE_DBGU0
);
259 if (!at91_soc_is_detected())
260 soc_detect(AT91_BASE_DBGU1
);
262 if (!at91_soc_is_detected())
263 panic("AT91: Impossible to detect the SOC type");
265 pr_info("AT91: Detected soc type: %s\n",
266 at91_get_soc_type(&at91_soc_initdata
));
267 pr_info("AT91: Detected soc subtype: %s\n",
268 at91_get_soc_subtype(&at91_soc_initdata
));
270 if (!at91_soc_is_enabled())
271 panic("AT91: Soc not enabled");
273 if (at91_boot_soc
.map_io
)
274 at91_boot_soc
.map_io();
277 void __iomem
*at91_shdwc_base
= NULL
;
279 static void at91sam9_poweroff(void)
281 at91_shdwc_write(AT91_SHDW_CR
, AT91_SHDW_KEY
| AT91_SHDW_SHDW
);
284 void __init
at91_ioremap_shdwc(u32 base_addr
)
286 at91_shdwc_base
= ioremap(base_addr
, 16);
287 if (!at91_shdwc_base
)
288 panic("Impossible to ioremap at91_shdwc_base\n");
289 pm_power_off
= at91sam9_poweroff
;
292 void __iomem
*at91_rstc_base
;
294 void __init
at91_ioremap_rstc(u32 base_addr
)
296 at91_rstc_base
= ioremap(base_addr
, 16);
298 panic("Impossible to ioremap at91_rstc_base\n");
301 void __iomem
*at91_matrix_base
;
302 EXPORT_SYMBOL_GPL(at91_matrix_base
);
304 void __init
at91_ioremap_matrix(u32 base_addr
)
306 at91_matrix_base
= ioremap(base_addr
, 512);
307 if (!at91_matrix_base
)
308 panic("Impossible to ioremap at91_matrix_base\n");
311 #if defined(CONFIG_OF)
312 static struct of_device_id rstc_ids
[] = {
313 { .compatible
= "atmel,at91sam9260-rstc", .data
= at91sam9_alt_restart
},
314 { .compatible
= "atmel,at91sam9g45-rstc", .data
= at91sam9g45_restart
},
318 static void at91_dt_rstc(void)
320 struct device_node
*np
;
321 const struct of_device_id
*of_id
;
323 np
= of_find_matching_node(NULL
, rstc_ids
);
325 panic("unable to find compatible rstc node in dtb\n");
327 at91_rstc_base
= of_iomap(np
, 0);
329 panic("unable to map rstc cpu registers\n");
331 of_id
= of_match_node(rstc_ids
, np
);
333 panic("AT91: rtsc no restart function availlable\n");
335 arm_pm_restart
= of_id
->data
;
340 static struct of_device_id ramc_ids
[] = {
341 { .compatible
= "atmel,at91sam9260-sdramc" },
342 { .compatible
= "atmel,at91sam9g45-ddramc" },
346 static void at91_dt_ramc(void)
348 struct device_node
*np
;
350 np
= of_find_matching_node(NULL
, ramc_ids
);
352 panic("unable to find compatible ram conroller node in dtb\n");
354 at91_ramc_base
[0] = of_iomap(np
, 0);
355 if (!at91_ramc_base
[0])
356 panic("unable to map ramc[0] cpu registers\n");
357 /* the controller may have 2 banks */
358 at91_ramc_base
[1] = of_iomap(np
, 1);
363 static struct of_device_id shdwc_ids
[] = {
364 { .compatible
= "atmel,at91sam9260-shdwc", },
365 { .compatible
= "atmel,at91sam9rl-shdwc", },
366 { .compatible
= "atmel,at91sam9x5-shdwc", },
370 static const char *shdwc_wakeup_modes
[] = {
371 [AT91_SHDW_WKMODE0_NONE
] = "none",
372 [AT91_SHDW_WKMODE0_HIGH
] = "high",
373 [AT91_SHDW_WKMODE0_LOW
] = "low",
374 [AT91_SHDW_WKMODE0_ANYLEVEL
] = "any",
377 const int at91_dtget_shdwc_wakeup_mode(struct device_node
*np
)
382 err
= of_property_read_string(np
, "atmel,wakeup-mode", &pm
);
384 return AT91_SHDW_WKMODE0_ANYLEVEL
;
386 for (i
= 0; i
< ARRAY_SIZE(shdwc_wakeup_modes
); i
++)
387 if (!strcasecmp(pm
, shdwc_wakeup_modes
[i
]))
393 static void at91_dt_shdwc(void)
395 struct device_node
*np
;
400 np
= of_find_matching_node(NULL
, shdwc_ids
);
402 pr_debug("AT91: unable to find compatible shutdown (shdwc) conroller node in dtb\n");
406 at91_shdwc_base
= of_iomap(np
, 0);
407 if (!at91_shdwc_base
)
408 panic("AT91: unable to map shdwc cpu registers\n");
410 wakeup_mode
= at91_dtget_shdwc_wakeup_mode(np
);
411 if (wakeup_mode
< 0) {
412 pr_warn("AT91: shdwc unknown wakeup mode\n");
416 if (!of_property_read_u32(np
, "atmel,wakeup-counter", ®
)) {
417 if (reg
> AT91_SHDW_CPTWK0_MAX
) {
418 pr_warn("AT91: shdwc wakeup conter 0x%x > 0x%x reduce it to 0x%x\n",
419 reg
, AT91_SHDW_CPTWK0_MAX
, AT91_SHDW_CPTWK0_MAX
);
420 reg
= AT91_SHDW_CPTWK0_MAX
;
422 mode
|= AT91_SHDW_CPTWK0_(reg
);
425 if (of_property_read_bool(np
, "atmel,wakeup-rtc-timer"))
426 mode
|= AT91_SHDW_RTCWKEN
;
428 if (of_property_read_bool(np
, "atmel,wakeup-rtt-timer"))
429 mode
|= AT91_SHDW_RTTWKEN
;
431 at91_shdwc_write(AT91_SHDW_MR
, wakeup_mode
| mode
);
434 pm_power_off
= at91sam9_poweroff
;
439 void __init
at91_dt_initialize(void)
445 /* Init clock subsystem */
446 at91_dt_clock_init();
448 /* Register the processor-specific clocks */
449 at91_boot_soc
.register_clocks();
451 at91_boot_soc
.init();
455 void __init
at91_initialize(unsigned long main_clock
)
457 at91_boot_soc
.ioremap_registers();
459 /* Init clock subsystem */
460 at91_clock_init(main_clock
);
462 /* Register the processor-specific clocks */
463 at91_boot_soc
.register_clocks();
465 at91_boot_soc
.init();