2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmar.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/pgalloc.h>
40 #include <asm/proto.h>
41 #include <asm/timex.h>
43 #include <asm/i8259.h>
46 #include <mach_apic.h>
48 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
49 static int disable_apic_timer __cpuinitdata
;
50 static int apic_calibrate_pmtmr __initdata
;
55 /* x2apic enabled before OS handover */
56 int x2apic_preenabled
;
58 /* Local APIC timer works in C2 */
59 int local_apic_timer_c2_ok
;
60 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
63 * Debug level, exported for io_apic.c
65 unsigned int apic_verbosity
;
67 /* Have we found an MP table */
70 static struct resource lapic_resource
= {
72 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
75 static unsigned int calibration_result
;
77 static int lapic_next_event(unsigned long delta
,
78 struct clock_event_device
*evt
);
79 static void lapic_timer_setup(enum clock_event_mode mode
,
80 struct clock_event_device
*evt
);
81 static void lapic_timer_broadcast(cpumask_t mask
);
82 static void apic_pm_activate(void);
85 * The local apic timer can be used for any function which is CPU local.
87 static struct clock_event_device lapic_clockevent
= {
89 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
90 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
92 .set_mode
= lapic_timer_setup
,
93 .set_next_event
= lapic_next_event
,
94 .broadcast
= lapic_timer_broadcast
,
98 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
100 static unsigned long apic_phys
;
101 unsigned int __cpuinitdata maxcpus
= NR_CPUS
;
103 unsigned long mp_lapic_addr
;
106 * Get the LAPIC version
108 static inline int lapic_get_version(void)
110 return GET_APIC_VERSION(apic_read(APIC_LVR
));
114 * Check, if the APIC is integrated or a separate chip
116 static inline int lapic_is_integrated(void)
121 return APIC_INTEGRATED(lapic_get_version());
126 * Check, whether this is a modern or a first generation APIC
128 static int modern_apic(void)
130 /* AMD systems use old APIC versions, so check the CPU */
131 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
132 boot_cpu_data
.x86
>= 0xf)
134 return lapic_get_version() >= 0x14;
138 * Paravirt kernels also might be using these below ops. So we still
139 * use generic apic_read()/apic_write(), which might be pointing to different
140 * ops in PARAVIRT case.
142 void xapic_wait_icr_idle(void)
144 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
148 u32
safe_xapic_wait_icr_idle(void)
155 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
159 } while (timeout
++ < 1000);
164 void xapic_icr_write(u32 low
, u32 id
)
166 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
167 apic_write(APIC_ICR
, low
);
170 u64
xapic_icr_read(void)
174 icr2
= apic_read(APIC_ICR2
);
175 icr1
= apic_read(APIC_ICR
);
177 return icr1
| ((u64
)icr2
<< 32);
180 static struct apic_ops xapic_ops
= {
181 .read
= native_apic_mem_read
,
182 .write
= native_apic_mem_write
,
183 .icr_read
= xapic_icr_read
,
184 .icr_write
= xapic_icr_write
,
185 .wait_icr_idle
= xapic_wait_icr_idle
,
186 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
189 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
190 EXPORT_SYMBOL_GPL(apic_ops
);
192 static void x2apic_wait_icr_idle(void)
194 /* no need to wait for icr idle in x2apic */
198 static u32
safe_x2apic_wait_icr_idle(void)
200 /* no need to wait for icr idle in x2apic */
204 void x2apic_icr_write(u32 low
, u32 id
)
206 wrmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), ((__u64
) id
) << 32 | low
);
209 u64
x2apic_icr_read(void)
213 rdmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), val
);
217 static struct apic_ops x2apic_ops
= {
218 .read
= native_apic_msr_read
,
219 .write
= native_apic_msr_write
,
220 .icr_read
= x2apic_icr_read
,
221 .icr_write
= x2apic_icr_write
,
222 .wait_icr_idle
= x2apic_wait_icr_idle
,
223 .safe_wait_icr_idle
= safe_x2apic_wait_icr_idle
,
227 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
229 void __cpuinit
enable_NMI_through_LVT0(void)
233 /* unmask and set to NMI */
236 /* Level triggered for 82489DX (32bit mode) */
237 if (!lapic_is_integrated())
238 v
|= APIC_LVT_LEVEL_TRIGGER
;
240 apic_write(APIC_LVT0
, v
);
244 * lapic_get_maxlvt - get the maximum number of local vector table entries
246 int lapic_get_maxlvt(void)
250 v
= apic_read(APIC_LVR
);
252 * - we always have APIC integrated on 64bit mode
253 * - 82489DXs do not report # of LVT entries
255 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
264 #define APIC_DIVISOR 1
266 #define APIC_DIVISOR 16
270 * This function sets up the local APIC timer, with a timeout of
271 * 'clocks' APIC bus clock. During calibration we actually call
272 * this function twice on the boot CPU, once with a bogus timeout
273 * value, second time for real. The other (noncalibrating) CPUs
274 * call this function only once, with the real, calibrated value.
276 * We do reads before writes even if unnecessary, to get around the
277 * P5 APIC double write bug.
279 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
281 unsigned int lvtt_value
, tmp_value
;
283 lvtt_value
= LOCAL_TIMER_VECTOR
;
285 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
286 if (!lapic_is_integrated())
287 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
290 lvtt_value
|= APIC_LVT_MASKED
;
292 apic_write(APIC_LVTT
, lvtt_value
);
297 tmp_value
= apic_read(APIC_TDCR
);
298 apic_write(APIC_TDCR
,
299 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
303 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
307 * Setup extended LVT, AMD specific (K8, family 10h)
309 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
310 * MCE interrupts are supported. Thus MCE offset must be set to 0.
313 #define APIC_EILVT_LVTOFF_MCE 0
314 #define APIC_EILVT_LVTOFF_IBS 1
316 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
318 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
319 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
324 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
326 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
327 return APIC_EILVT_LVTOFF_MCE
;
330 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
332 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
333 return APIC_EILVT_LVTOFF_IBS
;
337 * Program the next event, relative to now
339 static int lapic_next_event(unsigned long delta
,
340 struct clock_event_device
*evt
)
342 apic_write(APIC_TMICT
, delta
);
347 * Setup the lapic timer in periodic or oneshot mode
349 static void lapic_timer_setup(enum clock_event_mode mode
,
350 struct clock_event_device
*evt
)
355 /* Lapic used as dummy for broadcast ? */
356 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
359 local_irq_save(flags
);
362 case CLOCK_EVT_MODE_PERIODIC
:
363 case CLOCK_EVT_MODE_ONESHOT
:
364 __setup_APIC_LVTT(calibration_result
,
365 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
367 case CLOCK_EVT_MODE_UNUSED
:
368 case CLOCK_EVT_MODE_SHUTDOWN
:
369 v
= apic_read(APIC_LVTT
);
370 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
371 apic_write(APIC_LVTT
, v
);
373 case CLOCK_EVT_MODE_RESUME
:
374 /* Nothing to do here */
378 local_irq_restore(flags
);
382 * Local APIC timer broadcast function
384 static void lapic_timer_broadcast(cpumask_t mask
)
387 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
392 * Setup the local APIC timer for this CPU. Copy the initilized values
393 * of the boot CPU and register the clock event in the framework.
395 static void setup_APIC_timer(void)
397 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
399 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
400 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
402 clockevents_register_device(levt
);
406 * In this function we calibrate APIC bus clocks to the external
407 * timer. Unfortunately we cannot use jiffies and the timer irq
408 * to calibrate, since some later bootup code depends on getting
409 * the first irq? Ugh.
411 * We want to do the calibration only once since we
412 * want to have local timer irqs syncron. CPUs connected
413 * by the same APIC bus have the very same bus frequency.
414 * And we want to have irqs off anyways, no accidental
418 #define TICK_COUNT 100000000
420 static int __init
calibrate_APIC_clock(void)
422 unsigned apic
, apic_start
;
423 unsigned long tsc
, tsc_start
;
429 * Put whatever arbitrary (but long enough) timeout
430 * value into the APIC clock, we just want to get the
431 * counter running for calibration.
433 * No interrupt enable !
435 __setup_APIC_LVTT(250000000, 0, 0);
437 apic_start
= apic_read(APIC_TMCCT
);
438 #ifdef CONFIG_X86_PM_TIMER
439 if (apic_calibrate_pmtmr
&& pmtmr_ioport
) {
440 pmtimer_wait(5000); /* 5ms wait */
441 apic
= apic_read(APIC_TMCCT
);
442 result
= (apic_start
- apic
) * 1000L / 5;
449 apic
= apic_read(APIC_TMCCT
);
451 } while ((tsc
- tsc_start
) < TICK_COUNT
&&
452 (apic_start
- apic
) < TICK_COUNT
);
454 result
= (apic_start
- apic
) * 1000L * tsc_khz
/
460 printk(KERN_DEBUG
"APIC timer calibration result %d\n", result
);
462 printk(KERN_INFO
"Detected %d.%03d MHz APIC timer.\n",
463 result
/ 1000 / 1000, result
/ 1000 % 1000);
465 /* Calculate the scaled math multiplication factor */
466 lapic_clockevent
.mult
= div_sc(result
, NSEC_PER_SEC
,
467 lapic_clockevent
.shift
);
468 lapic_clockevent
.max_delta_ns
=
469 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
470 lapic_clockevent
.min_delta_ns
=
471 clockevent_delta2ns(0xF, &lapic_clockevent
);
473 calibration_result
= (result
* APIC_DIVISOR
) / HZ
;
476 * Do a sanity check on the APIC calibration result
478 if (calibration_result
< (1000000 / HZ
)) {
480 "APIC frequency too slow, disabling apic timer\n");
488 * Setup the boot APIC
490 * Calibrate and verify the result.
492 void __init
setup_boot_APIC_clock(void)
495 * The local apic timer can be disabled via the kernel
496 * commandline or from the CPU detection code. Register the lapic
497 * timer as a dummy clock event source on SMP systems, so the
498 * broadcast mechanism is used. On UP systems simply ignore it.
500 if (disable_apic_timer
) {
501 printk(KERN_INFO
"Disabling APIC timer\n");
502 /* No broadcast on UP ! */
503 if (num_possible_cpus() > 1) {
504 lapic_clockevent
.mult
= 1;
510 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
511 "calibrating APIC timer ...\n");
513 if (calibrate_APIC_clock()) {
514 /* No broadcast on UP ! */
515 if (num_possible_cpus() > 1)
521 * If nmi_watchdog is set to IO_APIC, we need the
522 * PIT/HPET going. Otherwise register lapic as a dummy
525 if (nmi_watchdog
!= NMI_IO_APIC
)
526 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
528 printk(KERN_WARNING
"APIC timer registered as dummy,"
529 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
531 /* Setup the lapic or request the broadcast */
535 void __cpuinit
setup_secondary_APIC_clock(void)
541 * The guts of the apic timer interrupt
543 static void local_apic_timer_interrupt(void)
545 int cpu
= smp_processor_id();
546 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
549 * Normally we should not be here till LAPIC has been initialized but
550 * in some cases like kdump, its possible that there is a pending LAPIC
551 * timer interrupt from previous kernel's context and is delivered in
552 * new kernel the moment interrupts are enabled.
554 * Interrupts are enabled early and LAPIC is setup much later, hence
555 * its possible that when we get here evt->event_handler is NULL.
556 * Check for event_handler being NULL and discard the interrupt as
559 if (!evt
->event_handler
) {
561 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
563 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
568 * the NMI deadlock-detector uses this.
571 add_pda(apic_timer_irqs
, 1);
573 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
576 evt
->event_handler(evt
);
580 * Local APIC timer interrupt. This is the most natural way for doing
581 * local interrupts, but local timer interrupts can be emulated by
582 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
584 * [ if a single-CPU system runs an SMP kernel then we call the local
585 * interrupt as well. Thus we cannot inline the local irq ... ]
587 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
589 struct pt_regs
*old_regs
= set_irq_regs(regs
);
592 * NOTE! We'd better ACK the irq immediately,
593 * because timer handling can be slow.
597 * update_process_times() expects us to have done irq_enter().
598 * Besides, if we don't timer interrupts ignore the global
599 * interrupt lock, which is the WrongThing (tm) to do.
603 local_apic_timer_interrupt();
606 set_irq_regs(old_regs
);
609 int setup_profiling_timer(unsigned int multiplier
)
616 * Local APIC start and shutdown
620 * clear_local_APIC - shutdown the local APIC
622 * This is called, when a CPU is disabled and before rebooting, so the state of
623 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
624 * leftovers during boot.
626 void clear_local_APIC(void)
631 /* APIC hasn't been mapped yet */
635 maxlvt
= lapic_get_maxlvt();
637 * Masking an LVT entry can trigger a local APIC error
638 * if the vector is zero. Mask LVTERR first to prevent this.
641 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
642 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
645 * Careful: we have to set masks only first to deassert
646 * any level-triggered sources.
648 v
= apic_read(APIC_LVTT
);
649 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
650 v
= apic_read(APIC_LVT0
);
651 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
652 v
= apic_read(APIC_LVT1
);
653 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
655 v
= apic_read(APIC_LVTPC
);
656 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
659 /* lets not touch this if we didn't frob it */
660 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
662 v
= apic_read(APIC_LVTTHMR
);
663 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
667 * Clean APIC state for other OSs:
669 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
670 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
671 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
673 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
675 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
677 /* Integrated APIC (!82489DX) ? */
678 if (lapic_is_integrated()) {
680 /* Clear ESR due to Pentium errata 3AP and 11AP */
681 apic_write(APIC_ESR
, 0);
687 * disable_local_APIC - clear and disable the local APIC
689 void disable_local_APIC(void)
696 * Disable APIC (implies clearing of registers
699 value
= apic_read(APIC_SPIV
);
700 value
&= ~APIC_SPIV_APIC_ENABLED
;
701 apic_write(APIC_SPIV
, value
);
705 * When LAPIC was disabled by the BIOS and enabled by the kernel,
706 * restore the disabled state.
708 if (enabled_via_apicbase
) {
711 rdmsr(MSR_IA32_APICBASE
, l
, h
);
712 l
&= ~MSR_IA32_APICBASE_ENABLE
;
713 wrmsr(MSR_IA32_APICBASE
, l
, h
);
719 * If Linux enabled the LAPIC against the BIOS default disable it down before
720 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
721 * not power-off. Additionally clear all LVT entries before disable_local_APIC
722 * for the case where Linux didn't enable the LAPIC.
724 void lapic_shutdown(void)
731 local_irq_save(flags
);
734 if (!enabled_via_apicbase
)
738 disable_local_APIC();
741 local_irq_restore(flags
);
745 * This is to verify that we're looking at a real local APIC.
746 * Check these against your board if the CPUs aren't getting
747 * started for no apparent reason.
749 int __init
verify_local_APIC(void)
751 unsigned int reg0
, reg1
;
754 * The version register is read-only in a real APIC.
756 reg0
= apic_read(APIC_LVR
);
757 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
758 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
759 reg1
= apic_read(APIC_LVR
);
760 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
763 * The two version reads above should print the same
764 * numbers. If the second one is different, then we
765 * poke at a non-APIC.
771 * Check if the version looks reasonably.
773 reg1
= GET_APIC_VERSION(reg0
);
774 if (reg1
== 0x00 || reg1
== 0xff)
776 reg1
= lapic_get_maxlvt();
777 if (reg1
< 0x02 || reg1
== 0xff)
781 * The ID register is read/write in a real APIC.
783 reg0
= apic_read(APIC_ID
);
784 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
785 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
786 reg1
= apic_read(APIC_ID
);
787 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
788 apic_write(APIC_ID
, reg0
);
789 if (reg1
!= (reg0
^ APIC_ID_MASK
))
793 * The next two are just to see if we have sane values.
794 * They're only really relevant if we're in Virtual Wire
795 * compatibility mode, but most boxes are anymore.
797 reg0
= apic_read(APIC_LVT0
);
798 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
799 reg1
= apic_read(APIC_LVT1
);
800 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
806 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
808 void __init
sync_Arb_IDs(void)
811 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
814 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
820 apic_wait_icr_idle();
822 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
823 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
824 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
828 * An initial setup of the virtual wire mode.
830 void __init
init_bsp_APIC(void)
835 * Don't do the setup now if we have a SMP BIOS as the
836 * through-I/O-APIC virtual wire mode might be active.
838 if (smp_found_config
|| !cpu_has_apic
)
842 * Do not trust the local APIC being empty at bootup.
849 value
= apic_read(APIC_SPIV
);
850 value
&= ~APIC_VECTOR_MASK
;
851 value
|= APIC_SPIV_APIC_ENABLED
;
854 /* This bit is reserved on P4/Xeon and should be cleared */
855 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
856 (boot_cpu_data
.x86
== 15))
857 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
860 value
|= APIC_SPIV_FOCUS_DISABLED
;
861 value
|= SPURIOUS_APIC_VECTOR
;
862 apic_write(APIC_SPIV
, value
);
865 * Set up the virtual wire mode.
867 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
869 if (!lapic_is_integrated()) /* 82489DX */
870 value
|= APIC_LVT_LEVEL_TRIGGER
;
871 apic_write(APIC_LVT1
, value
);
874 static void __cpuinit
lapic_setup_esr(void)
876 unsigned long oldvalue
, value
, maxlvt
;
877 if (lapic_is_integrated() && !esr_disable
) {
880 * Something untraceable is creating bad interrupts on
881 * secondary quads ... for the moment, just leave the
882 * ESR disabled - we can't do anything useful with the
883 * errors anyway - mbligh
885 printk(KERN_INFO
"Leaving ESR disabled.\n");
889 maxlvt
= lapic_get_maxlvt();
890 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
891 apic_write(APIC_ESR
, 0);
892 oldvalue
= apic_read(APIC_ESR
);
894 /* enables sending errors */
895 value
= ERROR_APIC_VECTOR
;
896 apic_write(APIC_LVTERR
, value
);
898 * spec says clear errors after enabling vector.
901 apic_write(APIC_ESR
, 0);
902 value
= apic_read(APIC_ESR
);
903 if (value
!= oldvalue
)
904 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
905 "vector: 0x%08lx after: 0x%08lx\n",
908 printk(KERN_INFO
"No ESR for 82489DX.\n");
914 * setup_local_APIC - setup the local APIC
916 void __cpuinit
setup_local_APIC(void)
922 value
= apic_read(APIC_LVR
);
924 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f);
927 * Double-check whether this APIC is really registered.
928 * This is meaningless in clustered apic mode, so we skip it.
930 if (!apic_id_registered())
934 * Intel recommends to set DFR, LDR and TPR before enabling
935 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
936 * document number 292116). So here it goes...
941 * Set Task Priority to 'accept all'. We never change this
944 value
= apic_read(APIC_TASKPRI
);
945 value
&= ~APIC_TPRI_MASK
;
946 apic_write(APIC_TASKPRI
, value
);
949 * After a crash, we no longer service the interrupts and a pending
950 * interrupt from previous kernel might still have ISR bit set.
952 * Most probably by now CPU has serviced that pending interrupt and
953 * it might not have done the ack_APIC_irq() because it thought,
954 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
955 * does not clear the ISR bit and cpu thinks it has already serivced
956 * the interrupt. Hence a vector might get locked. It was noticed
957 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
959 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
960 value
= apic_read(APIC_ISR
+ i
*0x10);
961 for (j
= 31; j
>= 0; j
--) {
968 * Now that we are all set up, enable the APIC
970 value
= apic_read(APIC_SPIV
);
971 value
&= ~APIC_VECTOR_MASK
;
975 value
|= APIC_SPIV_APIC_ENABLED
;
977 /* We always use processor focus */
980 * Set spurious IRQ vector
982 value
|= SPURIOUS_APIC_VECTOR
;
983 apic_write(APIC_SPIV
, value
);
988 * set up through-local-APIC on the BP's LINT0. This is not
989 * strictly necessary in pure symmetric-IO mode, but sometimes
990 * we delegate interrupts to the 8259A.
993 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
995 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
996 if (!smp_processor_id() && !value
) {
997 value
= APIC_DM_EXTINT
;
998 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1001 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1002 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1003 smp_processor_id());
1005 apic_write(APIC_LVT0
, value
);
1008 * only the BP should see the LINT1 NMI signal, obviously.
1010 if (!smp_processor_id())
1011 value
= APIC_DM_NMI
;
1013 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1014 apic_write(APIC_LVT1
, value
);
1018 void __cpuinit
end_local_APIC_setup(void)
1022 #ifdef CONFIG_X86_32
1024 /* Disable the local apic timer */
1025 value
= apic_read(APIC_LVTT
);
1026 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1027 apic_write(APIC_LVTT
, value
);
1030 setup_apic_nmi_watchdog(NULL
);
1034 void check_x2apic(void)
1038 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1040 if (msr
& X2APIC_ENABLE
) {
1041 printk("x2apic enabled by BIOS, switching to x2apic ops\n");
1042 x2apic_preenabled
= x2apic
= 1;
1043 apic_ops
= &x2apic_ops
;
1047 void enable_x2apic(void)
1051 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1052 if (!(msr
& X2APIC_ENABLE
)) {
1053 printk("Enabling x2apic\n");
1054 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1058 void enable_IR_x2apic(void)
1060 #ifdef CONFIG_INTR_REMAP
1062 unsigned long flags
;
1064 if (!cpu_has_x2apic
)
1067 if (!x2apic_preenabled
&& disable_x2apic
) {
1069 "Skipped enabling x2apic and Interrupt-remapping "
1070 "because of nox2apic\n");
1074 if (x2apic_preenabled
&& disable_x2apic
)
1075 panic("Bios already enabled x2apic, can't enforce nox2apic");
1077 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1079 "Skipped enabling x2apic and Interrupt-remapping "
1080 "because of skipping io-apic setup\n");
1084 ret
= dmar_table_init();
1087 "dmar_table_init() failed with %d:\n", ret
);
1089 if (x2apic_preenabled
)
1090 panic("x2apic enabled by bios. But IR enabling failed");
1093 "Not enabling x2apic,Intr-remapping\n");
1097 local_irq_save(flags
);
1099 save_mask_IO_APIC_setup();
1101 ret
= enable_intr_remapping(1);
1103 if (ret
&& x2apic_preenabled
) {
1104 local_irq_restore(flags
);
1105 panic("x2apic enabled by bios. But IR enabling failed");
1113 apic_ops
= &x2apic_ops
;
1119 * IR enabling failed
1121 restore_IO_APIC_setup();
1123 reinit_intr_remapped_IO_APIC(x2apic_preenabled
);
1126 local_irq_restore(flags
);
1129 if (!x2apic_preenabled
)
1131 "Enabled x2apic and interrupt-remapping\n");
1134 "Enabled Interrupt-remapping\n");
1137 "Failed to enable Interrupt-remapping and x2apic\n");
1139 if (!cpu_has_x2apic
)
1142 if (x2apic_preenabled
)
1143 panic("x2apic enabled prior OS handover,"
1144 " enable CONFIG_INTR_REMAP");
1146 printk(KERN_INFO
"Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1154 * Detect and enable local APICs on non-SMP boards.
1155 * Original code written by Keir Fraser.
1156 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1157 * not correctly set up (usually the APIC timer won't work etc.)
1159 static int __init
detect_init_APIC(void)
1161 if (!cpu_has_apic
) {
1162 printk(KERN_INFO
"No local APIC present\n");
1166 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1167 boot_cpu_physical_apicid
= 0;
1171 void __init
early_init_lapic_mapping(void)
1173 unsigned long phys_addr
;
1176 * If no local APIC can be found then go out
1177 * : it means there is no mpatable and MADT
1179 if (!smp_found_config
)
1182 phys_addr
= mp_lapic_addr
;
1184 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1185 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1186 APIC_BASE
, phys_addr
);
1189 * Fetch the APIC ID of the BSP in case we have a
1190 * default configuration (or the MP table is broken).
1192 boot_cpu_physical_apicid
= read_apic_id();
1196 * init_apic_mappings - initialize APIC mappings
1198 void __init
init_apic_mappings(void)
1201 boot_cpu_physical_apicid
= read_apic_id();
1206 * If no local APIC can be found then set up a fake all
1207 * zeroes page to simulate the local APIC and another
1208 * one for the IO-APIC.
1210 if (!smp_found_config
&& detect_init_APIC()) {
1211 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1212 apic_phys
= __pa(apic_phys
);
1214 apic_phys
= mp_lapic_addr
;
1216 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1217 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1218 APIC_BASE
, apic_phys
);
1221 * Fetch the APIC ID of the BSP in case we have a
1222 * default configuration (or the MP table is broken).
1224 boot_cpu_physical_apicid
= read_apic_id();
1228 * This initializes the IO-APIC and APIC hardware if this is
1231 int apic_version
[MAX_APICS
];
1233 int __init
APIC_init_uniprocessor(void)
1236 printk(KERN_INFO
"Apic disabled\n");
1239 if (!cpu_has_apic
) {
1241 printk(KERN_INFO
"Apic disabled by BIOS\n");
1246 setup_apic_routing();
1248 verify_local_APIC();
1252 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1253 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1258 * Now enable IO-APICs, actually call clear_IO_APIC
1259 * We need clear_IO_APIC before enabling vector on BP
1261 if (!skip_ioapic_setup
&& nr_ioapics
)
1264 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1265 localise_nmi_watchdog();
1266 end_local_APIC_setup();
1268 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1272 setup_boot_APIC_clock();
1273 check_nmi_watchdog();
1278 * Local APIC interrupts
1282 * This interrupt should _never_ happen with our APIC/SMP architecture
1284 asmlinkage
void smp_spurious_interrupt(void)
1290 * Check if this really is a spurious interrupt and ACK it
1291 * if it is a vectored one. Just in case...
1292 * Spurious interrupts should not be ACKed.
1294 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1295 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1298 add_pda(irq_spurious_count
, 1);
1303 * This interrupt should never happen with our APIC/SMP architecture
1305 asmlinkage
void smp_error_interrupt(void)
1311 /* First tickle the hardware, only then report what went on. -- REW */
1312 v
= apic_read(APIC_ESR
);
1313 apic_write(APIC_ESR
, 0);
1314 v1
= apic_read(APIC_ESR
);
1316 atomic_inc(&irq_err_count
);
1318 /* Here is what the APIC error bits mean:
1321 2: Send accept error
1322 3: Receive accept error
1324 5: Send illegal vector
1325 6: Received illegal vector
1326 7: Illegal register address
1328 printk(KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)\n",
1329 smp_processor_id(), v
, v1
);
1334 * connect_bsp_APIC - attach the APIC to the interrupt system
1336 void __init
connect_bsp_APIC(void)
1338 #ifdef CONFIG_X86_32
1341 * Do not trust the local APIC being empty at bootup.
1345 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1346 * local APIC to INT and NMI lines.
1348 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1349 "enabling APIC mode.\n");
1358 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1359 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1361 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1364 void disconnect_bsp_APIC(int virt_wire_setup
)
1366 #ifdef CONFIG_X86_32
1369 * Put the board back into PIC mode (has an effect only on
1370 * certain older boards). Note that APIC interrupts, including
1371 * IPIs, won't work beyond this point! The only exception are
1374 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1375 "entering PIC mode.\n");
1382 /* Go back to Virtual Wire compatibility mode */
1385 /* For the spurious interrupt use vector F, and enable it */
1386 value
= apic_read(APIC_SPIV
);
1387 value
&= ~APIC_VECTOR_MASK
;
1388 value
|= APIC_SPIV_APIC_ENABLED
;
1390 apic_write(APIC_SPIV
, value
);
1392 if (!virt_wire_setup
) {
1394 * For LVT0 make it edge triggered, active high,
1395 * external and enabled
1397 value
= apic_read(APIC_LVT0
);
1398 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1399 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1400 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1401 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1402 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1403 apic_write(APIC_LVT0
, value
);
1406 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1410 * For LVT1 make it edge triggered, active high,
1413 value
= apic_read(APIC_LVT1
);
1414 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1415 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1416 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1417 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1418 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1419 apic_write(APIC_LVT1
, value
);
1422 void __cpuinit
generic_processor_info(int apicid
, int version
)
1430 if (version
== 0x0) {
1431 printk(KERN_WARNING
"BIOS bug, APIC version is 0 for CPU#%d! "
1432 "fixing up to 0x10. (tell your hw vendor)\n",
1436 apic_version
[apicid
] = version
;
1438 if (num_processors
>= NR_CPUS
) {
1439 printk(KERN_WARNING
"WARNING: NR_CPUS limit of %i reached."
1440 " Processor ignored.\n", NR_CPUS
);
1444 if (num_processors
>= maxcpus
) {
1445 printk(KERN_WARNING
"WARNING: maxcpus limit of %i reached."
1446 " Processor ignored.\n", maxcpus
);
1451 cpus_complement(tmp_map
, cpu_present_map
);
1452 cpu
= first_cpu(tmp_map
);
1454 physid_set(apicid
, phys_cpu_present_map
);
1455 if (apicid
== boot_cpu_physical_apicid
) {
1457 * x86_bios_cpu_apicid is required to have processors listed
1458 * in same order as logical cpu numbers. Hence the first
1459 * entry is BSP, and so on.
1463 if (apicid
> max_physical_apicid
)
1464 max_physical_apicid
= apicid
;
1466 #ifdef CONFIG_X86_32
1468 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1469 * but we need to work other dependencies like SMP_SUSPEND etc
1470 * before this can be done without some confusion.
1471 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1472 * - Ashok Raj <ashok.raj@intel.com>
1474 if (max_physical_apicid
>= 8) {
1475 switch (boot_cpu_data
.x86_vendor
) {
1476 case X86_VENDOR_INTEL
:
1477 if (!APIC_XAPIC(version
)) {
1481 /* If P4 and above fall through */
1482 case X86_VENDOR_AMD
:
1488 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1489 /* are we being called early in kernel startup? */
1490 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1491 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1492 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1494 cpu_to_apicid
[cpu
] = apicid
;
1495 bios_cpu_apicid
[cpu
] = apicid
;
1497 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1498 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1502 cpu_set(cpu
, cpu_possible_map
);
1503 cpu_set(cpu
, cpu_present_map
);
1506 int hard_smp_processor_id(void)
1508 return read_apic_id();
1518 * 'active' is true if the local APIC was enabled by us and
1519 * not the BIOS; this signifies that we are also responsible
1520 * for disabling it before entering apm/acpi suspend
1523 /* r/w apic fields */
1524 unsigned int apic_id
;
1525 unsigned int apic_taskpri
;
1526 unsigned int apic_ldr
;
1527 unsigned int apic_dfr
;
1528 unsigned int apic_spiv
;
1529 unsigned int apic_lvtt
;
1530 unsigned int apic_lvtpc
;
1531 unsigned int apic_lvt0
;
1532 unsigned int apic_lvt1
;
1533 unsigned int apic_lvterr
;
1534 unsigned int apic_tmict
;
1535 unsigned int apic_tdcr
;
1536 unsigned int apic_thmr
;
1539 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1541 unsigned long flags
;
1544 if (!apic_pm_state
.active
)
1547 maxlvt
= lapic_get_maxlvt();
1549 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1550 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1551 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1552 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1553 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1554 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1556 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1557 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1558 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1559 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1560 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1561 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1562 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1564 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1567 local_irq_save(flags
);
1568 disable_local_APIC();
1569 local_irq_restore(flags
);
1573 static int lapic_resume(struct sys_device
*dev
)
1576 unsigned long flags
;
1579 if (!apic_pm_state
.active
)
1582 maxlvt
= lapic_get_maxlvt();
1584 local_irq_save(flags
);
1586 #ifdef CONFIG_X86_64
1593 * Make sure the APICBASE points to the right address
1595 * FIXME! This will be wrong if we ever support suspend on
1596 * SMP! We'll need to do this as part of the CPU restore!
1598 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1599 l
&= ~MSR_IA32_APICBASE_BASE
;
1600 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1601 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1604 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1605 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1606 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1607 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1608 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1609 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1610 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1611 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1612 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1614 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1617 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1618 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1619 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1620 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1621 apic_write(APIC_ESR
, 0);
1622 apic_read(APIC_ESR
);
1623 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1624 apic_write(APIC_ESR
, 0);
1625 apic_read(APIC_ESR
);
1627 local_irq_restore(flags
);
1633 * This device has no shutdown method - fully functioning local APICs
1634 * are needed on every CPU up until machine_halt/restart/poweroff.
1637 static struct sysdev_class lapic_sysclass
= {
1639 .resume
= lapic_resume
,
1640 .suspend
= lapic_suspend
,
1643 static struct sys_device device_lapic
= {
1645 .cls
= &lapic_sysclass
,
1648 static void __cpuinit
apic_pm_activate(void)
1650 apic_pm_state
.active
= 1;
1653 static int __init
init_lapic_sysfs(void)
1659 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1661 error
= sysdev_class_register(&lapic_sysclass
);
1663 error
= sysdev_register(&device_lapic
);
1666 device_initcall(init_lapic_sysfs
);
1668 #else /* CONFIG_PM */
1670 static void apic_pm_activate(void) { }
1672 #endif /* CONFIG_PM */
1675 * apic_is_clustered_box() -- Check if we can expect good TSC
1677 * Thus far, the major user of this is IBM's Summit2 series:
1679 * Clustered boxes may have unsynced TSC problems if they are
1680 * multi-chassis. Use available data to take a good guess.
1681 * If in doubt, go HPET.
1683 __cpuinit
int apic_is_clustered_box(void)
1685 int i
, clusters
, zeros
;
1687 u16
*bios_cpu_apicid
;
1688 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
1691 * there is not this kind of box with AMD CPU yet.
1692 * Some AMD box with quadcore cpu and 8 sockets apicid
1693 * will be [4, 0x23] or [8, 0x27] could be thought to
1694 * vsmp box still need checking...
1696 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
1699 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1700 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
1702 for (i
= 0; i
< NR_CPUS
; i
++) {
1703 /* are we being called early in kernel startup? */
1704 if (bios_cpu_apicid
) {
1705 id
= bios_cpu_apicid
[i
];
1707 else if (i
< nr_cpu_ids
) {
1709 id
= per_cpu(x86_bios_cpu_apicid
, i
);
1716 if (id
!= BAD_APICID
)
1717 __set_bit(APIC_CLUSTERID(id
), clustermap
);
1720 /* Problem: Partially populated chassis may not have CPUs in some of
1721 * the APIC clusters they have been allocated. Only present CPUs have
1722 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1723 * Since clusters are allocated sequentially, count zeros only if
1724 * they are bounded by ones.
1728 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
1729 if (test_bit(i
, clustermap
)) {
1730 clusters
+= 1 + zeros
;
1736 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1737 * not guaranteed to be synced between boards
1739 if (is_vsmp_box() && clusters
> 1)
1743 * If clusters > 2, then should be multi-chassis.
1744 * May have to revisit this when multi-core + hyperthreaded CPUs come
1745 * out, but AFAIK this will work even for them.
1747 return (clusters
> 2);
1750 static __init
int setup_nox2apic(char *str
)
1753 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_X2APIC
);
1756 early_param("nox2apic", setup_nox2apic
);
1760 * APIC command line parameters
1762 static int __init
apic_set_verbosity(char *str
)
1765 skip_ioapic_setup
= 0;
1769 if (strcmp("debug", str
) == 0)
1770 apic_verbosity
= APIC_DEBUG
;
1771 else if (strcmp("verbose", str
) == 0)
1772 apic_verbosity
= APIC_VERBOSE
;
1774 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
1775 " use apic=verbose or apic=debug\n", str
);
1781 early_param("apic", apic_set_verbosity
);
1783 static __init
int setup_disableapic(char *str
)
1786 setup_clear_cpu_cap(X86_FEATURE_APIC
);
1789 early_param("disableapic", setup_disableapic
);
1791 /* same as disableapic, for compatibility */
1792 static __init
int setup_nolapic(char *str
)
1794 return setup_disableapic(str
);
1796 early_param("nolapic", setup_nolapic
);
1798 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1800 local_apic_timer_c2_ok
= 1;
1803 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1805 static int __init
parse_disable_apic_timer(char *arg
)
1807 disable_apic_timer
= 1;
1810 early_param("noapictimer", parse_disable_apic_timer
);
1812 static int __init
parse_nolapic_timer(char *arg
)
1814 disable_apic_timer
= 1;
1817 early_param("nolapic_timer", parse_nolapic_timer
);
1819 static __init
int setup_apicpmtimer(char *s
)
1821 apic_calibrate_pmtmr
= 1;
1825 __setup("apicpmtimer", setup_apicpmtimer
);
1827 static int __init
lapic_insert_resource(void)
1832 /* Put local APIC into the resource map. */
1833 lapic_resource
.start
= apic_phys
;
1834 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
1835 insert_resource(&iomem_resource
, &lapic_resource
);
1841 * need call insert after e820_reserve_resources()
1842 * that is using request_resource
1844 late_initcall(lapic_insert_resource
);