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[SCSI] qla2xxx: Add APEX support.
[linux-2.6.git] / drivers / scsi / qla2xxx / qla_sup.c
blobf32a4b032967ed64bc58dfeba21272709f55e1ef
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8
9 #include <linux/delay.h>
10 #include <linux/slab.h>
11 #include <linux/vmalloc.h>
12 #include <asm/uaccess.h>
13
14 /*
15 * NVRAM support routines
16 */
17
18 /**
19 * qla2x00_lock_nvram_access() -
20 * @ha: HA context
21 */
22 static void
23 qla2x00_lock_nvram_access(struct qla_hw_data *ha)
24 {
25 uint16_t data;
26 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
27
28 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
29 data = RD_REG_WORD(&reg->nvram);
30 while (data & NVR_BUSY) {
31 udelay(100);
32 data = RD_REG_WORD(&reg->nvram);
33 }
34
35 /* Lock resource */
36 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
37 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
38 udelay(5);
39 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
40 while ((data & BIT_0) == 0) {
41 /* Lock failed */
42 udelay(100);
43 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
44 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
45 udelay(5);
46 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
47 }
48 }
49 }
50
51 /**
52 * qla2x00_unlock_nvram_access() -
53 * @ha: HA context
54 */
55 static void
56 qla2x00_unlock_nvram_access(struct qla_hw_data *ha)
57 {
58 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
59
60 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
61 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
62 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
63 }
64 }
65
66 /**
67 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
68 * @ha: HA context
69 * @data: Serial interface selector
70 */
71 static void
72 qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data)
73 {
74 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
75
76 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
77 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
78 NVRAM_DELAY();
79 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_CLOCK |
80 NVR_WRT_ENABLE);
81 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
82 NVRAM_DELAY();
83 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
84 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
85 NVRAM_DELAY();
86 }
87
88 /**
89 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
90 * NVRAM.
91 * @ha: HA context
92 * @nv_cmd: NVRAM command
93 *
94 * Bit definitions for NVRAM command:
95 *
96 * Bit 26 = start bit
97 * Bit 25, 24 = opcode
98 * Bit 23-16 = address
99 * Bit 15-0 = write data
100 *
101 * Returns the word read from nvram @addr.
102 */
103 static uint16_t
104 qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd)
105 {
106 uint8_t cnt;
107 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
108 uint16_t data = 0;
109 uint16_t reg_data;
110
111 /* Send command to NVRAM. */
112 nv_cmd <<= 5;
113 for (cnt = 0; cnt < 11; cnt++) {
114 if (nv_cmd & BIT_31)
115 qla2x00_nv_write(ha, NVR_DATA_OUT);
116 else
117 qla2x00_nv_write(ha, 0);
118 nv_cmd <<= 1;
119 }
120
121 /* Read data from NVRAM. */
122 for (cnt = 0; cnt < 16; cnt++) {
123 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
124 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
125 NVRAM_DELAY();
126 data <<= 1;
127 reg_data = RD_REG_WORD(&reg->nvram);
128 if (reg_data & NVR_DATA_IN)
129 data |= BIT_0;
130 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
131 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
132 NVRAM_DELAY();
133 }
134
135 /* Deselect chip. */
136 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
137 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
138 NVRAM_DELAY();
139
140 return data;
141 }
142
143
144 /**
145 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
146 * request routine to get the word from NVRAM.
147 * @ha: HA context
148 * @addr: Address in NVRAM to read
149 *
150 * Returns the word read from nvram @addr.
151 */
152 static uint16_t
153 qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr)
154 {
155 uint16_t data;
156 uint32_t nv_cmd;
157
158 nv_cmd = addr << 16;
159 nv_cmd |= NV_READ_OP;
160 data = qla2x00_nvram_request(ha, nv_cmd);
161
162 return (data);
163 }
164
165 /**
166 * qla2x00_nv_deselect() - Deselect NVRAM operations.
167 * @ha: HA context
168 */
169 static void
170 qla2x00_nv_deselect(struct qla_hw_data *ha)
171 {
172 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
173
174 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
175 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
176 NVRAM_DELAY();
177 }
178
179 /**
180 * qla2x00_write_nvram_word() - Write NVRAM data.
181 * @ha: HA context
182 * @addr: Address in NVRAM to write
183 * @data: word to program
184 */
185 static void
186 qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data)
187 {
188 int count;
189 uint16_t word;
190 uint32_t nv_cmd, wait_cnt;
191 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
192
193 qla2x00_nv_write(ha, NVR_DATA_OUT);
194 qla2x00_nv_write(ha, 0);
195 qla2x00_nv_write(ha, 0);
196
197 for (word = 0; word < 8; word++)
198 qla2x00_nv_write(ha, NVR_DATA_OUT);
199
200 qla2x00_nv_deselect(ha);
201
202 /* Write data */
203 nv_cmd = (addr << 16) | NV_WRITE_OP;
204 nv_cmd |= data;
205 nv_cmd <<= 5;
206 for (count = 0; count < 27; count++) {
207 if (nv_cmd & BIT_31)
208 qla2x00_nv_write(ha, NVR_DATA_OUT);
209 else
210 qla2x00_nv_write(ha, 0);
211
212 nv_cmd <<= 1;
213 }
214
215 qla2x00_nv_deselect(ha);
216
217 /* Wait for NVRAM to become ready */
218 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
219 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
220 wait_cnt = NVR_WAIT_CNT;
221 do {
222 if (!--wait_cnt) {
223 DEBUG9_10(qla_printk(KERN_WARNING, ha,
224 "NVRAM didn't go ready...\n"));
225 break;
226 }
227 NVRAM_DELAY();
228 word = RD_REG_WORD(&reg->nvram);
229 } while ((word & NVR_DATA_IN) == 0);
230
231 qla2x00_nv_deselect(ha);
232
233 /* Disable writes */
234 qla2x00_nv_write(ha, NVR_DATA_OUT);
235 for (count = 0; count < 10; count++)
236 qla2x00_nv_write(ha, 0);
237
238 qla2x00_nv_deselect(ha);
239 }
240
241 static int
242 qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
243 uint16_t data, uint32_t tmo)
244 {
245 int ret, count;
246 uint16_t word;
247 uint32_t nv_cmd;
248 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
249
250 ret = QLA_SUCCESS;
251
252 qla2x00_nv_write(ha, NVR_DATA_OUT);
253 qla2x00_nv_write(ha, 0);
254 qla2x00_nv_write(ha, 0);
255
256 for (word = 0; word < 8; word++)
257 qla2x00_nv_write(ha, NVR_DATA_OUT);
258
259 qla2x00_nv_deselect(ha);
260
261 /* Write data */
262 nv_cmd = (addr << 16) | NV_WRITE_OP;
263 nv_cmd |= data;
264 nv_cmd <<= 5;
265 for (count = 0; count < 27; count++) {
266 if (nv_cmd & BIT_31)
267 qla2x00_nv_write(ha, NVR_DATA_OUT);
268 else
269 qla2x00_nv_write(ha, 0);
270
271 nv_cmd <<= 1;
272 }
273
274 qla2x00_nv_deselect(ha);
275
276 /* Wait for NVRAM to become ready */
277 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
278 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
279 do {
280 NVRAM_DELAY();
281 word = RD_REG_WORD(&reg->nvram);
282 if (!--tmo) {
283 ret = QLA_FUNCTION_FAILED;
284 break;
285 }
286 } while ((word & NVR_DATA_IN) == 0);
287
288 qla2x00_nv_deselect(ha);
289
290 /* Disable writes */
291 qla2x00_nv_write(ha, NVR_DATA_OUT);
292 for (count = 0; count < 10; count++)
293 qla2x00_nv_write(ha, 0);
294
295 qla2x00_nv_deselect(ha);
296
297 return ret;
298 }
299
300 /**
301 * qla2x00_clear_nvram_protection() -
302 * @ha: HA context
303 */
304 static int
305 qla2x00_clear_nvram_protection(struct qla_hw_data *ha)
306 {
307 int ret, stat;
308 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
309 uint32_t word, wait_cnt;
310 uint16_t wprot, wprot_old;
311
312 /* Clear NVRAM write protection. */
313 ret = QLA_FUNCTION_FAILED;
314
315 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
316 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
317 __constant_cpu_to_le16(0x1234), 100000);
318 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
319 if (stat != QLA_SUCCESS || wprot != 0x1234) {
320 /* Write enable. */
321 qla2x00_nv_write(ha, NVR_DATA_OUT);
322 qla2x00_nv_write(ha, 0);
323 qla2x00_nv_write(ha, 0);
324 for (word = 0; word < 8; word++)
325 qla2x00_nv_write(ha, NVR_DATA_OUT);
326
327 qla2x00_nv_deselect(ha);
328
329 /* Enable protection register. */
330 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
331 qla2x00_nv_write(ha, NVR_PR_ENABLE);
332 qla2x00_nv_write(ha, NVR_PR_ENABLE);
333 for (word = 0; word < 8; word++)
334 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
335
336 qla2x00_nv_deselect(ha);
337
338 /* Clear protection register (ffff is cleared). */
339 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
340 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
341 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
342 for (word = 0; word < 8; word++)
343 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
344
345 qla2x00_nv_deselect(ha);
346
347 /* Wait for NVRAM to become ready. */
348 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
349 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
350 wait_cnt = NVR_WAIT_CNT;
351 do {
352 if (!--wait_cnt) {
353 DEBUG9_10(qla_printk(KERN_WARNING, ha,
354 "NVRAM didn't go ready...\n"));
355 break;
356 }
357 NVRAM_DELAY();
358 word = RD_REG_WORD(&reg->nvram);
359 } while ((word & NVR_DATA_IN) == 0);
360
361 if (wait_cnt)
362 ret = QLA_SUCCESS;
363 } else
364 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
365
366 return ret;
367 }
368
369 static void
370 qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
371 {
372 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
373 uint32_t word, wait_cnt;
374
375 if (stat != QLA_SUCCESS)
376 return;
377
378 /* Set NVRAM write protection. */
379 /* Write enable. */
380 qla2x00_nv_write(ha, NVR_DATA_OUT);
381 qla2x00_nv_write(ha, 0);
382 qla2x00_nv_write(ha, 0);
383 for (word = 0; word < 8; word++)
384 qla2x00_nv_write(ha, NVR_DATA_OUT);
385
386 qla2x00_nv_deselect(ha);
387
388 /* Enable protection register. */
389 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
390 qla2x00_nv_write(ha, NVR_PR_ENABLE);
391 qla2x00_nv_write(ha, NVR_PR_ENABLE);
392 for (word = 0; word < 8; word++)
393 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
394
395 qla2x00_nv_deselect(ha);
396
397 /* Enable protection register. */
398 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
399 qla2x00_nv_write(ha, NVR_PR_ENABLE);
400 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
401 for (word = 0; word < 8; word++)
402 qla2x00_nv_write(ha, NVR_PR_ENABLE);
403
404 qla2x00_nv_deselect(ha);
405
406 /* Wait for NVRAM to become ready. */
407 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
408 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
409 wait_cnt = NVR_WAIT_CNT;
410 do {
411 if (!--wait_cnt) {
412 DEBUG9_10(qla_printk(KERN_WARNING, ha,
413 "NVRAM didn't go ready...\n"));
414 break;
415 }
416 NVRAM_DELAY();
417 word = RD_REG_WORD(&reg->nvram);
418 } while ((word & NVR_DATA_IN) == 0);
419 }
420
421
422 /*****************************************************************************/
423 /* Flash Manipulation Routines */
424 /*****************************************************************************/
425
426 #define OPTROM_BURST_SIZE 0x1000
427 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
428
429 static inline uint32_t
430 flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr)
431 {
432 return ha->flash_conf_off | faddr;
433 }
434
435 static inline uint32_t
436 flash_data_addr(struct qla_hw_data *ha, uint32_t faddr)
437 {
438 return ha->flash_data_off | faddr;
439 }
440
441 static inline uint32_t
442 nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr)
443 {
444 return ha->nvram_conf_off | naddr;
445 }
446
447 static inline uint32_t
448 nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr)
449 {
450 return ha->nvram_data_off | naddr;
451 }
452
453 static uint32_t
454 qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr)
455 {
456 int rval;
457 uint32_t cnt, data;
458 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
459
460 WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
461 /* Wait for READ cycle to complete. */
462 rval = QLA_SUCCESS;
463 for (cnt = 3000;
464 (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
465 rval == QLA_SUCCESS; cnt--) {
466 if (cnt)
467 udelay(10);
468 else
469 rval = QLA_FUNCTION_TIMEOUT;
470 cond_resched();
471 }
472
473 /* TODO: What happens if we time out? */
474 data = 0xDEADDEAD;
475 if (rval == QLA_SUCCESS)
476 data = RD_REG_DWORD(&reg->flash_data);
477
478 return data;
479 }
480
481 uint32_t *
482 qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
483 uint32_t dwords)
484 {
485 uint32_t i;
486 struct qla_hw_data *ha = vha->hw;
487
488 /* Dword reads to flash. */
489 for (i = 0; i < dwords; i++, faddr++)
490 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
491 flash_data_addr(ha, faddr)));
492
493 return dwptr;
494 }
495
496 static int
497 qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
498 {
499 int rval;
500 uint32_t cnt;
501 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
502
503 WRT_REG_DWORD(&reg->flash_data, data);
504 RD_REG_DWORD(&reg->flash_data); /* PCI Posting. */
505 WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
506 /* Wait for Write cycle to complete. */
507 rval = QLA_SUCCESS;
508 for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
509 rval == QLA_SUCCESS; cnt--) {
510 if (cnt)
511 udelay(10);
512 else
513 rval = QLA_FUNCTION_TIMEOUT;
514 cond_resched();
515 }
516 return rval;
517 }
518
519 static void
520 qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
521 uint8_t *flash_id)
522 {
523 uint32_t ids;
524
525 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab));
526 *man_id = LSB(ids);
527 *flash_id = MSB(ids);
528
529 /* Check if man_id and flash_id are valid. */
530 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
531 /* Read information using 0x9f opcode
532 * Device ID, Mfg ID would be read in the format:
533 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
534 * Example: ATMEL 0x00 01 45 1F
535 * Extract MFG and Dev ID from last two bytes.
536 */
537 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f));
538 *man_id = LSB(ids);
539 *flash_id = MSB(ids);
540 }
541 }
542
543 static int
544 qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
545 {
546 const char *loc, *locations[] = { "DEF", "PCI" };
547 uint32_t pcihdr, pcids;
548 uint32_t *dcode;
549 uint8_t *buf, *bcode, last_image;
550 uint16_t cnt, chksum, *wptr;
551 struct qla_flt_location *fltl;
552 struct qla_hw_data *ha = vha->hw;
553 struct req_que *req = ha->req_q_map[0];
554
555 /*
556 * FLT-location structure resides after the last PCI region.
557 */
558
559 /* Begin with sane defaults. */
560 loc = locations[0];
561 *start = 0;
562 if (IS_QLA24XX_TYPE(ha))
563 *start = FA_FLASH_LAYOUT_ADDR_24;
564 else if (IS_QLA25XX(ha))
565 *start = FA_FLASH_LAYOUT_ADDR;
566 else if (IS_QLA81XX(ha))
567 *start = FA_FLASH_LAYOUT_ADDR_81;
568 /* Begin with first PCI expansion ROM header. */
569 buf = (uint8_t *)req->ring;
570 dcode = (uint32_t *)req->ring;
571 pcihdr = 0;
572 last_image = 1;
573 do {
574 /* Verify PCI expansion ROM header. */
575 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
576 bcode = buf + (pcihdr % 4);
577 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
578 goto end;
579
580 /* Locate PCI data structure. */
581 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
582 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
583 bcode = buf + (pcihdr % 4);
584
585 /* Validate signature of PCI data structure. */
586 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
587 bcode[0x2] != 'I' || bcode[0x3] != 'R')
588 goto end;
589
590 last_image = bcode[0x15] & BIT_7;
591
592 /* Locate next PCI expansion ROM. */
593 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
594 } while (!last_image);
595
596 /* Now verify FLT-location structure. */
597 fltl = (struct qla_flt_location *)req->ring;
598 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2,
599 sizeof(struct qla_flt_location) >> 2);
600 if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
601 fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
602 goto end;
603
604 wptr = (uint16_t *)req->ring;
605 cnt = sizeof(struct qla_flt_location) >> 1;
606 for (chksum = 0; cnt; cnt--)
607 chksum += le16_to_cpu(*wptr++);
608 if (chksum) {
609 qla_printk(KERN_ERR, ha,
610 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
611 qla2x00_dump_buffer(buf, sizeof(struct qla_flt_location));
612 return QLA_FUNCTION_FAILED;
613 }
614
615 /* Good data. Use specified location. */
616 loc = locations[1];
617 *start = (le16_to_cpu(fltl->start_hi) << 16 |
618 le16_to_cpu(fltl->start_lo)) >> 2;
619 end:
620 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
621 return QLA_SUCCESS;
622 }
623
624 static void
625 qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
626 {
627 const char *loc, *locations[] = { "DEF", "FLT" };
628 const uint32_t def_fw[] =
629 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 };
630 const uint32_t def_boot[] =
631 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 };
632 const uint32_t def_vpd_nvram[] =
633 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 };
634 const uint32_t def_vpd0[] =
635 { 0, 0, FA_VPD0_ADDR_81 };
636 const uint32_t def_vpd1[] =
637 { 0, 0, FA_VPD1_ADDR_81 };
638 const uint32_t def_nvram0[] =
639 { 0, 0, FA_NVRAM0_ADDR_81 };
640 const uint32_t def_nvram1[] =
641 { 0, 0, FA_NVRAM1_ADDR_81 };
642 const uint32_t def_fdt[] =
643 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR,
644 FA_FLASH_DESCR_ADDR_81 };
645 const uint32_t def_npiv_conf0[] =
646 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR,
647 FA_NPIV_CONF0_ADDR_81 };
648 const uint32_t def_npiv_conf1[] =
649 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR,
650 FA_NPIV_CONF1_ADDR_81 };
651 const uint32_t fcp_prio_cfg0[] =
652 { FA_FCP_PRIO0_ADDR, FA_FCP_PRIO0_ADDR_25,
653 0 };
654 const uint32_t fcp_prio_cfg1[] =
655 { FA_FCP_PRIO1_ADDR, FA_FCP_PRIO1_ADDR_25,
656 0 };
657 uint32_t def;
658 uint16_t *wptr;
659 uint16_t cnt, chksum;
660 uint32_t start;
661 struct qla_flt_header *flt;
662 struct qla_flt_region *region;
663 struct qla_hw_data *ha = vha->hw;
664 struct req_que *req = ha->req_q_map[0];
665
666 ha->flt_region_flt = flt_addr;
667 wptr = (uint16_t *)req->ring;
668 flt = (struct qla_flt_header *)req->ring;
669 region = (struct qla_flt_region *)&flt[1];
670 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
671 flt_addr << 2, OPTROM_BURST_SIZE);
672 if (*wptr == __constant_cpu_to_le16(0xffff))
673 goto no_flash_data;
674 if (flt->version != __constant_cpu_to_le16(1)) {
675 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported FLT detected: "
676 "version=0x%x length=0x%x checksum=0x%x.\n",
677 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
678 le16_to_cpu(flt->checksum)));
679 goto no_flash_data;
680 }
681
682 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
683 for (chksum = 0; cnt; cnt--)
684 chksum += le16_to_cpu(*wptr++);
685 if (chksum) {
686 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
687 "version=0x%x length=0x%x checksum=0x%x.\n",
688 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
689 chksum));
690 goto no_flash_data;
691 }
692
693 loc = locations[1];
694 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
695 for ( ; cnt; cnt--, region++) {
696 /* Store addresses as DWORD offsets. */
697 start = le32_to_cpu(region->start) >> 2;
698
699 DEBUG3(qla_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
700 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
701 le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
702
703 switch (le32_to_cpu(region->code) & 0xff) {
704 case FLT_REG_FW:
705 ha->flt_region_fw = start;
706 break;
707 case FLT_REG_BOOT_CODE:
708 ha->flt_region_boot = start;
709 break;
710 case FLT_REG_VPD_0:
711 ha->flt_region_vpd_nvram = start;
712 if (ha->flags.port0)
713 ha->flt_region_vpd = start;
714 break;
715 case FLT_REG_VPD_1:
716 if (!ha->flags.port0)
717 ha->flt_region_vpd = start;
718 break;
719 case FLT_REG_NVRAM_0:
720 if (ha->flags.port0)
721 ha->flt_region_nvram = start;
722 break;
723 case FLT_REG_NVRAM_1:
724 if (!ha->flags.port0)
725 ha->flt_region_nvram = start;
726 break;
727 case FLT_REG_FDT:
728 ha->flt_region_fdt = start;
729 break;
730 case FLT_REG_NPIV_CONF_0:
731 if (ha->flags.port0)
732 ha->flt_region_npiv_conf = start;
733 break;
734 case FLT_REG_NPIV_CONF_1:
735 if (!ha->flags.port0)
736 ha->flt_region_npiv_conf = start;
737 break;
738 case FLT_REG_GOLD_FW:
739 ha->flt_region_gold_fw = start;
740 break;
741 case FLT_REG_FCP_PRIO_0:
742 if (!(PCI_FUNC(ha->pdev->devfn) & 1))
743 ha->flt_region_fcp_prio = start;
744 break;
745 case FLT_REG_FCP_PRIO_1:
746 if (PCI_FUNC(ha->pdev->devfn) & 1)
747 ha->flt_region_fcp_prio = start;
748 break;
749 }
750 }
751 goto done;
752
753 no_flash_data:
754 /* Use hardcoded defaults. */
755 loc = locations[0];
756 def = 0;
757 if (IS_QLA24XX_TYPE(ha))
758 def = 0;
759 else if (IS_QLA25XX(ha))
760 def = 1;
761 else if (IS_QLA81XX(ha))
762 def = 2;
763 ha->flt_region_fw = def_fw[def];
764 ha->flt_region_boot = def_boot[def];
765 ha->flt_region_vpd_nvram = def_vpd_nvram[def];
766 ha->flt_region_vpd = ha->flags.port0 ?
767 def_vpd0[def] : def_vpd1[def];
768 ha->flt_region_nvram = ha->flags.port0 ?
769 def_nvram0[def] : def_nvram1[def];
770 ha->flt_region_fdt = def_fdt[def];
771 ha->flt_region_npiv_conf = ha->flags.port0 ?
772 def_npiv_conf0[def] : def_npiv_conf1[def];
773 ha->flt_region_fcp_prio = ha->flags.port0 ?
774 fcp_prio_cfg0[def] : fcp_prio_cfg1[def];
775 done:
776 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLT[%s]: boot=0x%x fw=0x%x "
777 "vpd_nvram=0x%x vpd=0x%x nvram=0x%x fdt=0x%x flt=0x%x "
778 "npiv=0x%x.\n", loc, ha->flt_region_boot, ha->flt_region_fw,
779 ha->flt_region_vpd_nvram, ha->flt_region_vpd, ha->flt_region_nvram,
780 ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf));
781 }
782
783 static void
784 qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
785 {
786 #define FLASH_BLK_SIZE_4K 0x1000
787 #define FLASH_BLK_SIZE_32K 0x8000
788 #define FLASH_BLK_SIZE_64K 0x10000
789 const char *loc, *locations[] = { "MID", "FDT" };
790 uint16_t cnt, chksum;
791 uint16_t *wptr;
792 struct qla_fdt_layout *fdt;
793 uint8_t man_id, flash_id;
794 uint16_t mid, fid;
795 struct qla_hw_data *ha = vha->hw;
796 struct req_que *req = ha->req_q_map[0];
797
798 wptr = (uint16_t *)req->ring;
799 fdt = (struct qla_fdt_layout *)req->ring;
800 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
801 ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
802 if (*wptr == __constant_cpu_to_le16(0xffff))
803 goto no_flash_data;
804 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
805 fdt->sig[3] != 'D')
806 goto no_flash_data;
807
808 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
809 cnt++)
810 chksum += le16_to_cpu(*wptr++);
811 if (chksum) {
812 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
813 "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
814 le16_to_cpu(fdt->version)));
815 DEBUG9(qla2x00_dump_buffer((uint8_t *)fdt, sizeof(*fdt)));
816 goto no_flash_data;
817 }
818
819 loc = locations[1];
820 mid = le16_to_cpu(fdt->man_id);
821 fid = le16_to_cpu(fdt->id);
822 ha->fdt_wrt_disable = fdt->wrt_disable_bits;
823 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0300 | fdt->erase_cmd);
824 ha->fdt_block_size = le32_to_cpu(fdt->block_size);
825 if (fdt->unprotect_sec_cmd) {
826 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 |
827 fdt->unprotect_sec_cmd);
828 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
829 flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd):
830 flash_conf_addr(ha, 0x0336);
831 }
832 goto done;
833 no_flash_data:
834 loc = locations[0];
835 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
836 mid = man_id;
837 fid = flash_id;
838 ha->fdt_wrt_disable = 0x9c;
839 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8);
840 switch (man_id) {
841 case 0xbf: /* STT flash. */
842 if (flash_id == 0x8e)
843 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
844 else
845 ha->fdt_block_size = FLASH_BLK_SIZE_32K;
846
847 if (flash_id == 0x80)
848 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352);
849 break;
850 case 0x13: /* ST M25P80. */
851 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
852 break;
853 case 0x1f: /* Atmel 26DF081A. */
854 ha->fdt_block_size = FLASH_BLK_SIZE_4K;
855 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320);
856 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339);
857 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336);
858 break;
859 default:
860 /* Default to 64 kb sector size. */
861 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
862 break;
863 }
864 done:
865 DEBUG2(qla_printk(KERN_DEBUG, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
866 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
867 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
868 ha->fdt_unprotect_sec_cmd, ha->fdt_wrt_disable,
869 ha->fdt_block_size));
870 }
871
872 int
873 qla2xxx_get_flash_info(scsi_qla_host_t *vha)
874 {
875 int ret;
876 uint32_t flt_addr;
877 struct qla_hw_data *ha = vha->hw;
878
879 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA81XX(ha))
880 return QLA_SUCCESS;
881
882 ret = qla2xxx_find_flt_start(vha, &flt_addr);
883 if (ret != QLA_SUCCESS)
884 return ret;
885
886 qla2xxx_get_flt_info(vha, flt_addr);
887 qla2xxx_get_fdt_info(vha);
888
889 return QLA_SUCCESS;
890 }
891
892 void
893 qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
894 {
895 #define NPIV_CONFIG_SIZE (16*1024)
896 void *data;
897 uint16_t *wptr;
898 uint16_t cnt, chksum;
899 int i;
900 struct qla_npiv_header hdr;
901 struct qla_npiv_entry *entry;
902 struct qla_hw_data *ha = vha->hw;
903
904 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA81XX(ha))
905 return;
906
907 ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
908 ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
909 if (hdr.version == __constant_cpu_to_le16(0xffff))
910 return;
911 if (hdr.version != __constant_cpu_to_le16(1)) {
912 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported NPIV-Config "
913 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
914 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
915 le16_to_cpu(hdr.checksum)));
916 return;
917 }
918
919 data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
920 if (!data) {
921 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV-Config: Unable to "
922 "allocate memory.\n"));
923 return;
924 }
925
926 ha->isp_ops->read_optrom(vha, (uint8_t *)data,
927 ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
928
929 cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) *
930 sizeof(struct qla_npiv_entry)) >> 1;
931 for (wptr = data, chksum = 0; cnt; cnt--)
932 chksum += le16_to_cpu(*wptr++);
933 if (chksum) {
934 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent NPIV-Config "
935 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
936 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
937 chksum));
938 goto done;
939 }
940
941 entry = data + sizeof(struct qla_npiv_header);
942 cnt = le16_to_cpu(hdr.entries);
943 for (i = 0; cnt; cnt--, entry++, i++) {
944 uint16_t flags;
945 struct fc_vport_identifiers vid;
946 struct fc_vport *vport;
947
948 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry));
949
950 flags = le16_to_cpu(entry->flags);
951 if (flags == 0xffff)
952 continue;
953 if ((flags & BIT_0) == 0)
954 continue;
955
956 memset(&vid, 0, sizeof(vid));
957 vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
958 vid.vport_type = FC_PORTTYPE_NPIV;
959 vid.disable = false;
960 vid.port_name = wwn_to_u64(entry->port_name);
961 vid.node_name = wwn_to_u64(entry->node_name);
962
963 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV[%02x]: wwpn=%llx "
964 "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt,
965 (unsigned long long)vid.port_name,
966 (unsigned long long)vid.node_name,
967 le16_to_cpu(entry->vf_id),
968 entry->q_qos, entry->f_qos));
969
970 if (i < QLA_PRECONFIG_VPORTS) {
971 vport = fc_vport_create(vha->host, 0, &vid);
972 if (!vport)
973 qla_printk(KERN_INFO, ha,
974 "NPIV-Config: Failed to create vport [%02x]: "
975 "wwpn=%llx wwnn=%llx.\n", cnt,
976 (unsigned long long)vid.port_name,
977 (unsigned long long)vid.node_name);
978 }
979 }
980 done:
981 kfree(data);
982 }
983
984 static int
985 qla24xx_unprotect_flash(scsi_qla_host_t *vha)
986 {
987 struct qla_hw_data *ha = vha->hw;
988 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
989
990 if (ha->flags.fac_supported)
991 return qla81xx_fac_do_write_enable(vha, 1);
992
993 /* Enable flash write. */
994 WRT_REG_DWORD(&reg->ctrl_status,
995 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
996 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
997
998 if (!ha->fdt_wrt_disable)
999 goto done;
1000
1001 /* Disable flash write-protection, first clear SR protection bit */
1002 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
1003 /* Then write zero again to clear remaining SR bits.*/
1004 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
1005 done:
1006 return QLA_SUCCESS;
1007 }
1008
1009 static int
1010 qla24xx_protect_flash(scsi_qla_host_t *vha)
1011 {
1012 uint32_t cnt;
1013 struct qla_hw_data *ha = vha->hw;
1014 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1015
1016 if (ha->flags.fac_supported)
1017 return qla81xx_fac_do_write_enable(vha, 0);
1018
1019 if (!ha->fdt_wrt_disable)
1020 goto skip_wrt_protect;
1021
1022 /* Enable flash write-protection and wait for completion. */
1023 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101),
1024 ha->fdt_wrt_disable);
1025 for (cnt = 300; cnt &&
1026 qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0;
1027 cnt--) {
1028 udelay(10);
1029 }
1030
1031 skip_wrt_protect:
1032 /* Disable flash write. */
1033 WRT_REG_DWORD(&reg->ctrl_status,
1034 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1035 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1036
1037 return QLA_SUCCESS;
1038 }
1039
1040 static int
1041 qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata)
1042 {
1043 struct qla_hw_data *ha = vha->hw;
1044 uint32_t start, finish;
1045
1046 if (ha->flags.fac_supported) {
1047 start = fdata >> 2;
1048 finish = start + (ha->fdt_block_size >> 2) - 1;
1049 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha,
1050 start), flash_data_addr(ha, finish));
1051 }
1052
1053 return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
1054 (fdata & 0xff00) | ((fdata << 16) & 0xff0000) |
1055 ((fdata >> 16) & 0xff));
1056 }
1057
1058 static int
1059 qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
1060 uint32_t dwords)
1061 {
1062 int ret;
1063 uint32_t liter;
1064 uint32_t sec_mask, rest_addr;
1065 uint32_t fdata;
1066 dma_addr_t optrom_dma;
1067 void *optrom = NULL;
1068 struct qla_hw_data *ha = vha->hw;
1069
1070 /* Prepare burst-capable write on supported ISPs. */
1071 if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && !(faddr & 0xfff) &&
1072 dwords > OPTROM_BURST_DWORDS) {
1073 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1074 &optrom_dma, GFP_KERNEL);
1075 if (!optrom) {
1076 qla_printk(KERN_DEBUG, ha,
1077 "Unable to allocate memory for optrom burst write "
1078 "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
1079 }
1080 }
1081
1082 rest_addr = (ha->fdt_block_size >> 2) - 1;
1083 sec_mask = ~rest_addr;
1084
1085 ret = qla24xx_unprotect_flash(vha);
1086 if (ret != QLA_SUCCESS) {
1087 qla_printk(KERN_WARNING, ha,
1088 "Unable to unprotect flash for update.\n");
1089 goto done;
1090 }
1091
1092 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
1093 fdata = (faddr & sec_mask) << 2;
1094
1095 /* Are we at the beginning of a sector? */
1096 if ((faddr & rest_addr) == 0) {
1097 /* Do sector unprotect. */
1098 if (ha->fdt_unprotect_sec_cmd)
1099 qla24xx_write_flash_dword(ha,
1100 ha->fdt_unprotect_sec_cmd,
1101 (fdata & 0xff00) | ((fdata << 16) &
1102 0xff0000) | ((fdata >> 16) & 0xff));
1103 ret = qla24xx_erase_sector(vha, fdata);
1104 if (ret != QLA_SUCCESS) {
1105 DEBUG9(qla_printk(KERN_WARNING, ha,
1106 "Unable to erase sector: address=%x.\n",
1107 faddr));
1108 break;
1109 }
1110 }
1111
1112 /* Go with burst-write. */
1113 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
1114 /* Copy data to DMA'ble buffer. */
1115 memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
1116
1117 ret = qla2x00_load_ram(vha, optrom_dma,
1118 flash_data_addr(ha, faddr),
1119 OPTROM_BURST_DWORDS);
1120 if (ret != QLA_SUCCESS) {
1121 qla_printk(KERN_WARNING, ha,
1122 "Unable to burst-write optrom segment "
1123 "(%x/%x/%llx).\n", ret,
1124 flash_data_addr(ha, faddr),
1125 (unsigned long long)optrom_dma);
1126 qla_printk(KERN_WARNING, ha,
1127 "Reverting to slow-write.\n");
1128
1129 dma_free_coherent(&ha->pdev->dev,
1130 OPTROM_BURST_SIZE, optrom, optrom_dma);
1131 optrom = NULL;
1132 } else {
1133 liter += OPTROM_BURST_DWORDS - 1;
1134 faddr += OPTROM_BURST_DWORDS - 1;
1135 dwptr += OPTROM_BURST_DWORDS - 1;
1136 continue;
1137 }
1138 }
1139
1140 ret = qla24xx_write_flash_dword(ha,
1141 flash_data_addr(ha, faddr), cpu_to_le32(*dwptr));
1142 if (ret != QLA_SUCCESS) {
1143 DEBUG9(printk("%s(%ld) Unable to program flash "
1144 "address=%x data=%x.\n", __func__,
1145 vha->host_no, faddr, *dwptr));
1146 break;
1147 }
1148
1149 /* Do sector protect. */
1150 if (ha->fdt_unprotect_sec_cmd &&
1151 ((faddr & rest_addr) == rest_addr))
1152 qla24xx_write_flash_dword(ha,
1153 ha->fdt_protect_sec_cmd,
1154 (fdata & 0xff00) | ((fdata << 16) &
1155 0xff0000) | ((fdata >> 16) & 0xff));
1156 }
1157
1158 ret = qla24xx_protect_flash(vha);
1159 if (ret != QLA_SUCCESS)
1160 qla_printk(KERN_WARNING, ha,
1161 "Unable to protect flash after update.\n");
1162 done:
1163 if (optrom)
1164 dma_free_coherent(&ha->pdev->dev,
1165 OPTROM_BURST_SIZE, optrom, optrom_dma);
1166
1167 return ret;
1168 }
1169
1170 uint8_t *
1171 qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1172 uint32_t bytes)
1173 {
1174 uint32_t i;
1175 uint16_t *wptr;
1176 struct qla_hw_data *ha = vha->hw;
1177
1178 /* Word reads to NVRAM via registers. */
1179 wptr = (uint16_t *)buf;
1180 qla2x00_lock_nvram_access(ha);
1181 for (i = 0; i < bytes >> 1; i++, naddr++)
1182 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1183 naddr));
1184 qla2x00_unlock_nvram_access(ha);
1185
1186 return buf;
1187 }
1188
1189 uint8_t *
1190 qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1191 uint32_t bytes)
1192 {
1193 uint32_t i;
1194 uint32_t *dwptr;
1195 struct qla_hw_data *ha = vha->hw;
1196
1197 /* Dword reads to flash. */
1198 dwptr = (uint32_t *)buf;
1199 for (i = 0; i < bytes >> 2; i++, naddr++)
1200 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1201 nvram_data_addr(ha, naddr)));
1202
1203 return buf;
1204 }
1205
1206 int
1207 qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1208 uint32_t bytes)
1209 {
1210 int ret, stat;
1211 uint32_t i;
1212 uint16_t *wptr;
1213 unsigned long flags;
1214 struct qla_hw_data *ha = vha->hw;
1215
1216 ret = QLA_SUCCESS;
1217
1218 spin_lock_irqsave(&ha->hardware_lock, flags);
1219 qla2x00_lock_nvram_access(ha);
1220
1221 /* Disable NVRAM write-protection. */
1222 stat = qla2x00_clear_nvram_protection(ha);
1223
1224 wptr = (uint16_t *)buf;
1225 for (i = 0; i < bytes >> 1; i++, naddr++) {
1226 qla2x00_write_nvram_word(ha, naddr,
1227 cpu_to_le16(*wptr));
1228 wptr++;
1229 }
1230
1231 /* Enable NVRAM write-protection. */
1232 qla2x00_set_nvram_protection(ha, stat);
1233
1234 qla2x00_unlock_nvram_access(ha);
1235 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1236
1237 return ret;
1238 }
1239
1240 int
1241 qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1242 uint32_t bytes)
1243 {
1244 int ret;
1245 uint32_t i;
1246 uint32_t *dwptr;
1247 struct qla_hw_data *ha = vha->hw;
1248 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1249
1250 ret = QLA_SUCCESS;
1251
1252 /* Enable flash write. */
1253 WRT_REG_DWORD(&reg->ctrl_status,
1254 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1255 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1256
1257 /* Disable NVRAM write-protection. */
1258 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1259 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1260
1261 /* Dword writes to flash. */
1262 dwptr = (uint32_t *)buf;
1263 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1264 ret = qla24xx_write_flash_dword(ha,
1265 nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr));
1266 if (ret != QLA_SUCCESS) {
1267 DEBUG9(qla_printk(KERN_WARNING, ha,
1268 "Unable to program nvram address=%x data=%x.\n",
1269 naddr, *dwptr));
1270 break;
1271 }
1272 }
1273
1274 /* Enable NVRAM write-protection. */
1275 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c);
1276
1277 /* Disable flash write. */
1278 WRT_REG_DWORD(&reg->ctrl_status,
1279 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1280 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1281
1282 return ret;
1283 }
1284
1285 uint8_t *
1286 qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1287 uint32_t bytes)
1288 {
1289 uint32_t i;
1290 uint32_t *dwptr;
1291 struct qla_hw_data *ha = vha->hw;
1292
1293 /* Dword reads to flash. */
1294 dwptr = (uint32_t *)buf;
1295 for (i = 0; i < bytes >> 2; i++, naddr++)
1296 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1297 flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr)));
1298
1299 return buf;
1300 }
1301
1302 int
1303 qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1304 uint32_t bytes)
1305 {
1306 struct qla_hw_data *ha = vha->hw;
1307 #define RMW_BUFFER_SIZE (64 * 1024)
1308 uint8_t *dbuf;
1309
1310 dbuf = vmalloc(RMW_BUFFER_SIZE);
1311 if (!dbuf)
1312 return QLA_MEMORY_ALLOC_FAILED;
1313 ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1314 RMW_BUFFER_SIZE);
1315 memcpy(dbuf + (naddr << 2), buf, bytes);
1316 ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1317 RMW_BUFFER_SIZE);
1318 vfree(dbuf);
1319
1320 return QLA_SUCCESS;
1321 }
1322
1323 static inline void
1324 qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1325 {
1326 if (IS_QLA2322(ha)) {
1327 /* Flip all colors. */
1328 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1329 /* Turn off. */
1330 ha->beacon_color_state = 0;
1331 *pflags = GPIO_LED_ALL_OFF;
1332 } else {
1333 /* Turn on. */
1334 ha->beacon_color_state = QLA_LED_ALL_ON;
1335 *pflags = GPIO_LED_RGA_ON;
1336 }
1337 } else {
1338 /* Flip green led only. */
1339 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1340 /* Turn off. */
1341 ha->beacon_color_state = 0;
1342 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1343 } else {
1344 /* Turn on. */
1345 ha->beacon_color_state = QLA_LED_GRN_ON;
1346 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1347 }
1348 }
1349 }
1350
1351 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1352
1353 void
1354 qla2x00_beacon_blink(struct scsi_qla_host *vha)
1355 {
1356 uint16_t gpio_enable;
1357 uint16_t gpio_data;
1358 uint16_t led_color = 0;
1359 unsigned long flags;
1360 struct qla_hw_data *ha = vha->hw;
1361 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1362
1363 spin_lock_irqsave(&ha->hardware_lock, flags);
1364
1365 /* Save the Original GPIOE. */
1366 if (ha->pio_address) {
1367 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1368 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1369 } else {
1370 gpio_enable = RD_REG_WORD(&reg->gpioe);
1371 gpio_data = RD_REG_WORD(&reg->gpiod);
1372 }
1373
1374 /* Set the modified gpio_enable values */
1375 gpio_enable |= GPIO_LED_MASK;
1376
1377 if (ha->pio_address) {
1378 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1379 } else {
1380 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1381 RD_REG_WORD(&reg->gpioe);
1382 }
1383
1384 qla2x00_flip_colors(ha, &led_color);
1385
1386 /* Clear out any previously set LED color. */
1387 gpio_data &= ~GPIO_LED_MASK;
1388
1389 /* Set the new input LED color to GPIOD. */
1390 gpio_data |= led_color;
1391
1392 /* Set the modified gpio_data values */
1393 if (ha->pio_address) {
1394 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1395 } else {
1396 WRT_REG_WORD(&reg->gpiod, gpio_data);
1397 RD_REG_WORD(&reg->gpiod);
1398 }
1399
1400 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1401 }
1402
1403 int
1404 qla2x00_beacon_on(struct scsi_qla_host *vha)
1405 {
1406 uint16_t gpio_enable;
1407 uint16_t gpio_data;
1408 unsigned long flags;
1409 struct qla_hw_data *ha = vha->hw;
1410 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1411
1412 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1413 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1414
1415 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1416 qla_printk(KERN_WARNING, ha,
1417 "Unable to update fw options (beacon on).\n");
1418 return QLA_FUNCTION_FAILED;
1419 }
1420
1421 /* Turn off LEDs. */
1422 spin_lock_irqsave(&ha->hardware_lock, flags);
1423 if (ha->pio_address) {
1424 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1425 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1426 } else {
1427 gpio_enable = RD_REG_WORD(&reg->gpioe);
1428 gpio_data = RD_REG_WORD(&reg->gpiod);
1429 }
1430 gpio_enable |= GPIO_LED_MASK;
1431
1432 /* Set the modified gpio_enable values. */
1433 if (ha->pio_address) {
1434 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1435 } else {
1436 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1437 RD_REG_WORD(&reg->gpioe);
1438 }
1439
1440 /* Clear out previously set LED colour. */
1441 gpio_data &= ~GPIO_LED_MASK;
1442 if (ha->pio_address) {
1443 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1444 } else {
1445 WRT_REG_WORD(&reg->gpiod, gpio_data);
1446 RD_REG_WORD(&reg->gpiod);
1447 }
1448 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1449
1450 /*
1451 * Let the per HBA timer kick off the blinking process based on
1452 * the following flags. No need to do anything else now.
1453 */
1454 ha->beacon_blink_led = 1;
1455 ha->beacon_color_state = 0;
1456
1457 return QLA_SUCCESS;
1458 }
1459
1460 int
1461 qla2x00_beacon_off(struct scsi_qla_host *vha)
1462 {
1463 int rval = QLA_SUCCESS;
1464 struct qla_hw_data *ha = vha->hw;
1465
1466 ha->beacon_blink_led = 0;
1467
1468 /* Set the on flag so when it gets flipped it will be off. */
1469 if (IS_QLA2322(ha))
1470 ha->beacon_color_state = QLA_LED_ALL_ON;
1471 else
1472 ha->beacon_color_state = QLA_LED_GRN_ON;
1473
1474 ha->isp_ops->beacon_blink(vha); /* This turns green LED off */
1475
1476 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1477 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1478
1479 rval = qla2x00_set_fw_options(vha, ha->fw_options);
1480 if (rval != QLA_SUCCESS)
1481 qla_printk(KERN_WARNING, ha,
1482 "Unable to update fw options (beacon off).\n");
1483 return rval;
1484 }
1485
1486
1487 static inline void
1488 qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1489 {
1490 /* Flip all colors. */
1491 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1492 /* Turn off. */
1493 ha->beacon_color_state = 0;
1494 *pflags = 0;
1495 } else {
1496 /* Turn on. */
1497 ha->beacon_color_state = QLA_LED_ALL_ON;
1498 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1499 }
1500 }
1501
1502 void
1503 qla24xx_beacon_blink(struct scsi_qla_host *vha)
1504 {
1505 uint16_t led_color = 0;
1506 uint32_t gpio_data;
1507 unsigned long flags;
1508 struct qla_hw_data *ha = vha->hw;
1509 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1510
1511 /* Save the Original GPIOD. */
1512 spin_lock_irqsave(&ha->hardware_lock, flags);
1513 gpio_data = RD_REG_DWORD(&reg->gpiod);
1514
1515 /* Enable the gpio_data reg for update. */
1516 gpio_data |= GPDX_LED_UPDATE_MASK;
1517
1518 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1519 gpio_data = RD_REG_DWORD(&reg->gpiod);
1520
1521 /* Set the color bits. */
1522 qla24xx_flip_colors(ha, &led_color);
1523
1524 /* Clear out any previously set LED color. */
1525 gpio_data &= ~GPDX_LED_COLOR_MASK;
1526
1527 /* Set the new input LED color to GPIOD. */
1528 gpio_data |= led_color;
1529
1530 /* Set the modified gpio_data values. */
1531 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1532 gpio_data = RD_REG_DWORD(&reg->gpiod);
1533 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1534 }
1535
1536 int
1537 qla24xx_beacon_on(struct scsi_qla_host *vha)
1538 {
1539 uint32_t gpio_data;
1540 unsigned long flags;
1541 struct qla_hw_data *ha = vha->hw;
1542 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1543
1544 if (ha->beacon_blink_led == 0) {
1545 /* Enable firmware for update */
1546 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1547
1548 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS)
1549 return QLA_FUNCTION_FAILED;
1550
1551 if (qla2x00_get_fw_options(vha, ha->fw_options) !=
1552 QLA_SUCCESS) {
1553 qla_printk(KERN_WARNING, ha,
1554 "Unable to update fw options (beacon on).\n");
1555 return QLA_FUNCTION_FAILED;
1556 }
1557
1558 spin_lock_irqsave(&ha->hardware_lock, flags);
1559 gpio_data = RD_REG_DWORD(&reg->gpiod);
1560
1561 /* Enable the gpio_data reg for update. */
1562 gpio_data |= GPDX_LED_UPDATE_MASK;
1563 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1564 RD_REG_DWORD(&reg->gpiod);
1565
1566 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1567 }
1568
1569 /* So all colors blink together. */
1570 ha->beacon_color_state = 0;
1571
1572 /* Let the per HBA timer kick off the blinking process. */
1573 ha->beacon_blink_led = 1;
1574
1575 return QLA_SUCCESS;
1576 }
1577
1578 int
1579 qla24xx_beacon_off(struct scsi_qla_host *vha)
1580 {
1581 uint32_t gpio_data;
1582 unsigned long flags;
1583 struct qla_hw_data *ha = vha->hw;
1584 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1585
1586 ha->beacon_blink_led = 0;
1587 ha->beacon_color_state = QLA_LED_ALL_ON;
1588
1589 ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */
1590
1591 /* Give control back to firmware. */
1592 spin_lock_irqsave(&ha->hardware_lock, flags);
1593 gpio_data = RD_REG_DWORD(&reg->gpiod);
1594
1595 /* Disable the gpio_data reg for update. */
1596 gpio_data &= ~GPDX_LED_UPDATE_MASK;
1597 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1598 RD_REG_DWORD(&reg->gpiod);
1599 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1600
1601 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1602
1603 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1604 qla_printk(KERN_WARNING, ha,
1605 "Unable to update fw options (beacon off).\n");
1606 return QLA_FUNCTION_FAILED;
1607 }
1608
1609 if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1610 qla_printk(KERN_WARNING, ha,
1611 "Unable to get fw options (beacon off).\n");
1612 return QLA_FUNCTION_FAILED;
1613 }
1614
1615 return QLA_SUCCESS;
1616 }
1617
1618
1619 /*
1620 * Flash support routines
1621 */
1622
1623 /**
1624 * qla2x00_flash_enable() - Setup flash for reading and writing.
1625 * @ha: HA context
1626 */
1627 static void
1628 qla2x00_flash_enable(struct qla_hw_data *ha)
1629 {
1630 uint16_t data;
1631 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1632
1633 data = RD_REG_WORD(&reg->ctrl_status);
1634 data |= CSR_FLASH_ENABLE;
1635 WRT_REG_WORD(&reg->ctrl_status, data);
1636 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1637 }
1638
1639 /**
1640 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1641 * @ha: HA context
1642 */
1643 static void
1644 qla2x00_flash_disable(struct qla_hw_data *ha)
1645 {
1646 uint16_t data;
1647 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1648
1649 data = RD_REG_WORD(&reg->ctrl_status);
1650 data &= ~(CSR_FLASH_ENABLE);
1651 WRT_REG_WORD(&reg->ctrl_status, data);
1652 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1653 }
1654
1655 /**
1656 * qla2x00_read_flash_byte() - Reads a byte from flash
1657 * @ha: HA context
1658 * @addr: Address in flash to read
1659 *
1660 * A word is read from the chip, but, only the lower byte is valid.
1661 *
1662 * Returns the byte read from flash @addr.
1663 */
1664 static uint8_t
1665 qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr)
1666 {
1667 uint16_t data;
1668 uint16_t bank_select;
1669 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1670
1671 bank_select = RD_REG_WORD(&reg->ctrl_status);
1672
1673 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1674 /* Specify 64K address range: */
1675 /* clear out Module Select and Flash Address bits [19:16]. */
1676 bank_select &= ~0xf8;
1677 bank_select |= addr >> 12 & 0xf0;
1678 bank_select |= CSR_FLASH_64K_BANK;
1679 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1680 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1681
1682 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1683 data = RD_REG_WORD(&reg->flash_data);
1684
1685 return (uint8_t)data;
1686 }
1687
1688 /* Setup bit 16 of flash address. */
1689 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1690 bank_select |= CSR_FLASH_64K_BANK;
1691 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1692 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1693 } else if (((addr & BIT_16) == 0) &&
1694 (bank_select & CSR_FLASH_64K_BANK)) {
1695 bank_select &= ~(CSR_FLASH_64K_BANK);
1696 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1697 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1698 }
1699
1700 /* Always perform IO mapped accesses to the FLASH registers. */
1701 if (ha->pio_address) {
1702 uint16_t data2;
1703
1704 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1705 do {
1706 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1707 barrier();
1708 cpu_relax();
1709 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1710 } while (data != data2);
1711 } else {
1712 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1713 data = qla2x00_debounce_register(&reg->flash_data);
1714 }
1715
1716 return (uint8_t)data;
1717 }
1718
1719 /**
1720 * qla2x00_write_flash_byte() - Write a byte to flash
1721 * @ha: HA context
1722 * @addr: Address in flash to write
1723 * @data: Data to write
1724 */
1725 static void
1726 qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)
1727 {
1728 uint16_t bank_select;
1729 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1730
1731 bank_select = RD_REG_WORD(&reg->ctrl_status);
1732 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1733 /* Specify 64K address range: */
1734 /* clear out Module Select and Flash Address bits [19:16]. */
1735 bank_select &= ~0xf8;
1736 bank_select |= addr >> 12 & 0xf0;
1737 bank_select |= CSR_FLASH_64K_BANK;
1738 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1739 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1740
1741 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1742 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1743 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1744 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1745
1746 return;
1747 }
1748
1749 /* Setup bit 16 of flash address. */
1750 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1751 bank_select |= CSR_FLASH_64K_BANK;
1752 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1753 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1754 } else if (((addr & BIT_16) == 0) &&
1755 (bank_select & CSR_FLASH_64K_BANK)) {
1756 bank_select &= ~(CSR_FLASH_64K_BANK);
1757 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1758 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1759 }
1760
1761 /* Always perform IO mapped accesses to the FLASH registers. */
1762 if (ha->pio_address) {
1763 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1764 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
1765 } else {
1766 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1767 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1768 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1769 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1770 }
1771 }
1772
1773 /**
1774 * qla2x00_poll_flash() - Polls flash for completion.
1775 * @ha: HA context
1776 * @addr: Address in flash to poll
1777 * @poll_data: Data to be polled
1778 * @man_id: Flash manufacturer ID
1779 * @flash_id: Flash ID
1780 *
1781 * This function polls the device until bit 7 of what is read matches data
1782 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
1783 * out (a fatal error). The flash book recommeds reading bit 7 again after
1784 * reading bit 5 as a 1.
1785 *
1786 * Returns 0 on success, else non-zero.
1787 */
1788 static int
1789 qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,
1790 uint8_t man_id, uint8_t flash_id)
1791 {
1792 int status;
1793 uint8_t flash_data;
1794 uint32_t cnt;
1795
1796 status = 1;
1797
1798 /* Wait for 30 seconds for command to finish. */
1799 poll_data &= BIT_7;
1800 for (cnt = 3000000; cnt; cnt--) {
1801 flash_data = qla2x00_read_flash_byte(ha, addr);
1802 if ((flash_data & BIT_7) == poll_data) {
1803 status = 0;
1804 break;
1805 }
1806
1807 if (man_id != 0x40 && man_id != 0xda) {
1808 if ((flash_data & BIT_5) && cnt > 2)
1809 cnt = 2;
1810 }
1811 udelay(10);
1812 barrier();
1813 cond_resched();
1814 }
1815 return status;
1816 }
1817
1818 /**
1819 * qla2x00_program_flash_address() - Programs a flash address
1820 * @ha: HA context
1821 * @addr: Address in flash to program
1822 * @data: Data to be written in flash
1823 * @man_id: Flash manufacturer ID
1824 * @flash_id: Flash ID
1825 *
1826 * Returns 0 on success, else non-zero.
1827 */
1828 static int
1829 qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr,
1830 uint8_t data, uint8_t man_id, uint8_t flash_id)
1831 {
1832 /* Write Program Command Sequence. */
1833 if (IS_OEM_001(ha)) {
1834 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1835 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1836 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1837 qla2x00_write_flash_byte(ha, addr, data);
1838 } else {
1839 if (man_id == 0xda && flash_id == 0xc1) {
1840 qla2x00_write_flash_byte(ha, addr, data);
1841 if (addr & 0x7e)
1842 return 0;
1843 } else {
1844 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1845 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1846 qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1847 qla2x00_write_flash_byte(ha, addr, data);
1848 }
1849 }
1850
1851 udelay(150);
1852
1853 /* Wait for write to complete. */
1854 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1855 }
1856
1857 /**
1858 * qla2x00_erase_flash() - Erase the flash.
1859 * @ha: HA context
1860 * @man_id: Flash manufacturer ID
1861 * @flash_id: Flash ID
1862 *
1863 * Returns 0 on success, else non-zero.
1864 */
1865 static int
1866 qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)
1867 {
1868 /* Individual Sector Erase Command Sequence */
1869 if (IS_OEM_001(ha)) {
1870 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1871 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1872 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1873 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1874 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1875 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1876 } else {
1877 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1878 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1879 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1880 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1881 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1882 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1883 }
1884
1885 udelay(150);
1886
1887 /* Wait for erase to complete. */
1888 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1889 }
1890
1891 /**
1892 * qla2x00_erase_flash_sector() - Erase a flash sector.
1893 * @ha: HA context
1894 * @addr: Flash sector to erase
1895 * @sec_mask: Sector address mask
1896 * @man_id: Flash manufacturer ID
1897 * @flash_id: Flash ID
1898 *
1899 * Returns 0 on success, else non-zero.
1900 */
1901 static int
1902 qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr,
1903 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1904 {
1905 /* Individual Sector Erase Command Sequence */
1906 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1907 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1908 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1909 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1910 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1911 if (man_id == 0x1f && flash_id == 0x13)
1912 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
1913 else
1914 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
1915
1916 udelay(150);
1917
1918 /* Wait for erase to complete. */
1919 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
1920 }
1921
1922 /**
1923 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1924 * @man_id: Flash manufacturer ID
1925 * @flash_id: Flash ID
1926 */
1927 static void
1928 qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
1929 uint8_t *flash_id)
1930 {
1931 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1932 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1933 qla2x00_write_flash_byte(ha, 0x5555, 0x90);
1934 *man_id = qla2x00_read_flash_byte(ha, 0x0000);
1935 *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
1936 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1937 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1938 qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
1939 }
1940
1941 static void
1942 qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,
1943 uint32_t saddr, uint32_t length)
1944 {
1945 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1946 uint32_t midpoint, ilength;
1947 uint8_t data;
1948
1949 midpoint = length / 2;
1950
1951 WRT_REG_WORD(&reg->nvram, 0);
1952 RD_REG_WORD(&reg->nvram);
1953 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
1954 if (ilength == midpoint) {
1955 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1956 RD_REG_WORD(&reg->nvram);
1957 }
1958 data = qla2x00_read_flash_byte(ha, saddr);
1959 if (saddr % 100)
1960 udelay(10);
1961 *tmp_buf = data;
1962 cond_resched();
1963 }
1964 }
1965
1966 static inline void
1967 qla2x00_suspend_hba(struct scsi_qla_host *vha)
1968 {
1969 int cnt;
1970 unsigned long flags;
1971 struct qla_hw_data *ha = vha->hw;
1972 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1973
1974 /* Suspend HBA. */
1975 scsi_block_requests(vha->host);
1976 ha->isp_ops->disable_intrs(ha);
1977 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1978
1979 /* Pause RISC. */
1980 spin_lock_irqsave(&ha->hardware_lock, flags);
1981 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1982 RD_REG_WORD(&reg->hccr);
1983 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1984 for (cnt = 0; cnt < 30000; cnt++) {
1985 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
1986 break;
1987 udelay(100);
1988 }
1989 } else {
1990 udelay(10);
1991 }
1992 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1993 }
1994
1995 static inline void
1996 qla2x00_resume_hba(struct scsi_qla_host *vha)
1997 {
1998 struct qla_hw_data *ha = vha->hw;
1999
2000 /* Resume HBA. */
2001 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2002 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2003 qla2xxx_wake_dpc(vha);
2004 qla2x00_wait_for_chip_reset(vha);
2005 scsi_unblock_requests(vha->host);
2006 }
2007
2008 uint8_t *
2009 qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2010 uint32_t offset, uint32_t length)
2011 {
2012 uint32_t addr, midpoint;
2013 uint8_t *data;
2014 struct qla_hw_data *ha = vha->hw;
2015 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2016
2017 /* Suspend HBA. */
2018 qla2x00_suspend_hba(vha);
2019
2020 /* Go with read. */
2021 midpoint = ha->optrom_size / 2;
2022
2023 qla2x00_flash_enable(ha);
2024 WRT_REG_WORD(&reg->nvram, 0);
2025 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
2026 for (addr = offset, data = buf; addr < length; addr++, data++) {
2027 if (addr == midpoint) {
2028 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2029 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
2030 }
2031
2032 *data = qla2x00_read_flash_byte(ha, addr);
2033 }
2034 qla2x00_flash_disable(ha);
2035
2036 /* Resume HBA. */
2037 qla2x00_resume_hba(vha);
2038
2039 return buf;
2040 }
2041
2042 int
2043 qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2044 uint32_t offset, uint32_t length)
2045 {
2046
2047 int rval;
2048 uint8_t man_id, flash_id, sec_number, data;
2049 uint16_t wd;
2050 uint32_t addr, liter, sec_mask, rest_addr;
2051 struct qla_hw_data *ha = vha->hw;
2052 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2053
2054 /* Suspend HBA. */
2055 qla2x00_suspend_hba(vha);
2056
2057 rval = QLA_SUCCESS;
2058 sec_number = 0;
2059
2060 /* Reset ISP chip. */
2061 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2062 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
2063
2064 /* Go with write. */
2065 qla2x00_flash_enable(ha);
2066 do { /* Loop once to provide quick error exit */
2067 /* Structure of flash memory based on manufacturer */
2068 if (IS_OEM_001(ha)) {
2069 /* OEM variant with special flash part. */
2070 man_id = flash_id = 0;
2071 rest_addr = 0xffff;
2072 sec_mask = 0x10000;
2073 goto update_flash;
2074 }
2075 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
2076 switch (man_id) {
2077 case 0x20: /* ST flash. */
2078 if (flash_id == 0xd2 || flash_id == 0xe3) {
2079 /*
2080 * ST m29w008at part - 64kb sector size with
2081 * 32kb,8kb,8kb,16kb sectors at memory address
2082 * 0xf0000.
2083 */
2084 rest_addr = 0xffff;
2085 sec_mask = 0x10000;
2086 break;
2087 }
2088 /*
2089 * ST m29w010b part - 16kb sector size
2090 * Default to 16kb sectors
2091 */
2092 rest_addr = 0x3fff;
2093 sec_mask = 0x1c000;
2094 break;
2095 case 0x40: /* Mostel flash. */
2096 /* Mostel v29c51001 part - 512 byte sector size. */
2097 rest_addr = 0x1ff;
2098 sec_mask = 0x1fe00;
2099 break;
2100 case 0xbf: /* SST flash. */
2101 /* SST39sf10 part - 4kb sector size. */
2102 rest_addr = 0xfff;
2103 sec_mask = 0x1f000;
2104 break;
2105 case 0xda: /* Winbond flash. */
2106 /* Winbond W29EE011 part - 256 byte sector size. */
2107 rest_addr = 0x7f;
2108 sec_mask = 0x1ff80;
2109 break;
2110 case 0xc2: /* Macronix flash. */
2111 /* 64k sector size. */
2112 if (flash_id == 0x38 || flash_id == 0x4f) {
2113 rest_addr = 0xffff;
2114 sec_mask = 0x10000;
2115 break;
2116 }
2117 /* Fall through... */
2118
2119 case 0x1f: /* Atmel flash. */
2120 /* 512k sector size. */
2121 if (flash_id == 0x13) {
2122 rest_addr = 0x7fffffff;
2123 sec_mask = 0x80000000;
2124 break;
2125 }
2126 /* Fall through... */
2127
2128 case 0x01: /* AMD flash. */
2129 if (flash_id == 0x38 || flash_id == 0x40 ||
2130 flash_id == 0x4f) {
2131 /* Am29LV081 part - 64kb sector size. */
2132 /* Am29LV002BT part - 64kb sector size. */
2133 rest_addr = 0xffff;
2134 sec_mask = 0x10000;
2135 break;
2136 } else if (flash_id == 0x3e) {
2137 /*
2138 * Am29LV008b part - 64kb sector size with
2139 * 32kb,8kb,8kb,16kb sector at memory address
2140 * h0xf0000.
2141 */
2142 rest_addr = 0xffff;
2143 sec_mask = 0x10000;
2144 break;
2145 } else if (flash_id == 0x20 || flash_id == 0x6e) {
2146 /*
2147 * Am29LV010 part or AM29f010 - 16kb sector
2148 * size.
2149 */
2150 rest_addr = 0x3fff;
2151 sec_mask = 0x1c000;
2152 break;
2153 } else if (flash_id == 0x6d) {
2154 /* Am29LV001 part - 8kb sector size. */
2155 rest_addr = 0x1fff;
2156 sec_mask = 0x1e000;
2157 break;
2158 }
2159 default:
2160 /* Default to 16 kb sector size. */
2161 rest_addr = 0x3fff;
2162 sec_mask = 0x1c000;
2163 break;
2164 }
2165
2166 update_flash:
2167 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2168 if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2169 rval = QLA_FUNCTION_FAILED;
2170 break;
2171 }
2172 }
2173
2174 for (addr = offset, liter = 0; liter < length; liter++,
2175 addr++) {
2176 data = buf[liter];
2177 /* Are we at the beginning of a sector? */
2178 if ((addr & rest_addr) == 0) {
2179 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2180 if (addr >= 0x10000UL) {
2181 if (((addr >> 12) & 0xf0) &&
2182 ((man_id == 0x01 &&
2183 flash_id == 0x3e) ||
2184 (man_id == 0x20 &&
2185 flash_id == 0xd2))) {
2186 sec_number++;
2187 if (sec_number == 1) {
2188 rest_addr =
2189 0x7fff;
2190 sec_mask =
2191 0x18000;
2192 } else if (
2193 sec_number == 2 ||
2194 sec_number == 3) {
2195 rest_addr =
2196 0x1fff;
2197 sec_mask =
2198 0x1e000;
2199 } else if (
2200 sec_number == 4) {
2201 rest_addr =
2202 0x3fff;
2203 sec_mask =
2204 0x1c000;
2205 }
2206 }
2207 }
2208 } else if (addr == ha->optrom_size / 2) {
2209 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2210 RD_REG_WORD(&reg->nvram);
2211 }
2212
2213 if (flash_id == 0xda && man_id == 0xc1) {
2214 qla2x00_write_flash_byte(ha, 0x5555,
2215 0xaa);
2216 qla2x00_write_flash_byte(ha, 0x2aaa,
2217 0x55);
2218 qla2x00_write_flash_byte(ha, 0x5555,
2219 0xa0);
2220 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2221 /* Then erase it */
2222 if (qla2x00_erase_flash_sector(ha,
2223 addr, sec_mask, man_id,
2224 flash_id)) {
2225 rval = QLA_FUNCTION_FAILED;
2226 break;
2227 }
2228 if (man_id == 0x01 && flash_id == 0x6d)
2229 sec_number++;
2230 }
2231 }
2232
2233 if (man_id == 0x01 && flash_id == 0x6d) {
2234 if (sec_number == 1 &&
2235 addr == (rest_addr - 1)) {
2236 rest_addr = 0x0fff;
2237 sec_mask = 0x1f000;
2238 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2239 rest_addr = 0x3fff;
2240 sec_mask = 0x1c000;
2241 }
2242 }
2243
2244 if (qla2x00_program_flash_address(ha, addr, data,
2245 man_id, flash_id)) {
2246 rval = QLA_FUNCTION_FAILED;
2247 break;
2248 }
2249 cond_resched();
2250 }
2251 } while (0);
2252 qla2x00_flash_disable(ha);
2253
2254 /* Resume HBA. */
2255 qla2x00_resume_hba(vha);
2256
2257 return rval;
2258 }
2259
2260 uint8_t *
2261 qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2262 uint32_t offset, uint32_t length)
2263 {
2264 struct qla_hw_data *ha = vha->hw;
2265
2266 /* Suspend HBA. */
2267 scsi_block_requests(vha->host);
2268 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2269
2270 /* Go with read. */
2271 qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2);
2272
2273 /* Resume HBA. */
2274 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2275 scsi_unblock_requests(vha->host);
2276
2277 return buf;
2278 }
2279
2280 int
2281 qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2282 uint32_t offset, uint32_t length)
2283 {
2284 int rval;
2285 struct qla_hw_data *ha = vha->hw;
2286
2287 /* Suspend HBA. */
2288 scsi_block_requests(vha->host);
2289 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2290
2291 /* Go with write. */
2292 rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2,
2293 length >> 2);
2294
2295 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2296 scsi_unblock_requests(vha->host);
2297
2298 return rval;
2299 }
2300
2301 uint8_t *
2302 qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2303 uint32_t offset, uint32_t length)
2304 {
2305 int rval;
2306 dma_addr_t optrom_dma;
2307 void *optrom;
2308 uint8_t *pbuf;
2309 uint32_t faddr, left, burst;
2310 struct qla_hw_data *ha = vha->hw;
2311
2312 if (IS_QLA25XX(ha) || IS_QLA81XX(ha))
2313 goto try_fast;
2314 if (offset & 0xfff)
2315 goto slow_read;
2316 if (length < OPTROM_BURST_SIZE)
2317 goto slow_read;
2318
2319 try_fast:
2320 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2321 &optrom_dma, GFP_KERNEL);
2322 if (!optrom) {
2323 qla_printk(KERN_DEBUG, ha,
2324 "Unable to allocate memory for optrom burst read "
2325 "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
2326
2327 goto slow_read;
2328 }
2329
2330 pbuf = buf;
2331 faddr = offset >> 2;
2332 left = length >> 2;
2333 burst = OPTROM_BURST_DWORDS;
2334 while (left != 0) {
2335 if (burst > left)
2336 burst = left;
2337
2338 rval = qla2x00_dump_ram(vha, optrom_dma,
2339 flash_data_addr(ha, faddr), burst);
2340 if (rval) {
2341 qla_printk(KERN_WARNING, ha,
2342 "Unable to burst-read optrom segment "
2343 "(%x/%x/%llx).\n", rval,
2344 flash_data_addr(ha, faddr),
2345 (unsigned long long)optrom_dma);
2346 qla_printk(KERN_WARNING, ha,
2347 "Reverting to slow-read.\n");
2348
2349 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2350 optrom, optrom_dma);
2351 goto slow_read;
2352 }
2353
2354 memcpy(pbuf, optrom, burst * 4);
2355
2356 left -= burst;
2357 faddr += burst;
2358 pbuf += burst * 4;
2359 }
2360
2361 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
2362 optrom_dma);
2363
2364 return buf;
2365
2366 slow_read:
2367 return qla24xx_read_optrom_data(vha, buf, offset, length);
2368 }
2369
2370 /**
2371 * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2372 * @ha: HA context
2373 * @pcids: Pointer to the FCODE PCI data structure
2374 *
2375 * The process of retrieving the FCODE version information is at best
2376 * described as interesting.
2377 *
2378 * Within the first 100h bytes of the image an ASCII string is present
2379 * which contains several pieces of information including the FCODE
2380 * version. Unfortunately it seems the only reliable way to retrieve
2381 * the version is by scanning for another sentinel within the string,
2382 * the FCODE build date:
2383 *
2384 * ... 2.00.02 10/17/02 ...
2385 *
2386 * Returns QLA_SUCCESS on successful retrieval of version.
2387 */
2388 static void
2389 qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids)
2390 {
2391 int ret = QLA_FUNCTION_FAILED;
2392 uint32_t istart, iend, iter, vend;
2393 uint8_t do_next, rbyte, *vbyte;
2394
2395 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2396
2397 /* Skip the PCI data structure. */
2398 istart = pcids +
2399 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2400 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2401 iend = istart + 0x100;
2402 do {
2403 /* Scan for the sentinel date string...eeewww. */
2404 do_next = 0;
2405 iter = istart;
2406 while ((iter < iend) && !do_next) {
2407 iter++;
2408 if (qla2x00_read_flash_byte(ha, iter) == '/') {
2409 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2410 '/')
2411 do_next++;
2412 else if (qla2x00_read_flash_byte(ha,
2413 iter + 3) == '/')
2414 do_next++;
2415 }
2416 }
2417 if (!do_next)
2418 break;
2419
2420 /* Backtrack to previous ' ' (space). */
2421 do_next = 0;
2422 while ((iter > istart) && !do_next) {
2423 iter--;
2424 if (qla2x00_read_flash_byte(ha, iter) == ' ')
2425 do_next++;
2426 }
2427 if (!do_next)
2428 break;
2429
2430 /*
2431 * Mark end of version tag, and find previous ' ' (space) or
2432 * string length (recent FCODE images -- major hack ahead!!!).
2433 */
2434 vend = iter - 1;
2435 do_next = 0;
2436 while ((iter > istart) && !do_next) {
2437 iter--;
2438 rbyte = qla2x00_read_flash_byte(ha, iter);
2439 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2440 do_next++;
2441 }
2442 if (!do_next)
2443 break;
2444
2445 /* Mark beginning of version tag, and copy data. */
2446 iter++;
2447 if ((vend - iter) &&
2448 ((vend - iter) < sizeof(ha->fcode_revision))) {
2449 vbyte = ha->fcode_revision;
2450 while (iter <= vend) {
2451 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2452 iter++;
2453 }
2454 ret = QLA_SUCCESS;
2455 }
2456 } while (0);
2457
2458 if (ret != QLA_SUCCESS)
2459 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2460 }
2461
2462 int
2463 qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2464 {
2465 int ret = QLA_SUCCESS;
2466 uint8_t code_type, last_image;
2467 uint32_t pcihdr, pcids;
2468 uint8_t *dbyte;
2469 uint16_t *dcode;
2470 struct qla_hw_data *ha = vha->hw;
2471
2472 if (!ha->pio_address || !mbuf)
2473 return QLA_FUNCTION_FAILED;
2474
2475 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2476 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2477 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2478 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2479
2480 qla2x00_flash_enable(ha);
2481
2482 /* Begin with first PCI expansion ROM header. */
2483 pcihdr = 0;
2484 last_image = 1;
2485 do {
2486 /* Verify PCI expansion ROM header. */
2487 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2488 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2489 /* No signature */
2490 DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2491 "signature.\n"));
2492 ret = QLA_FUNCTION_FAILED;
2493 break;
2494 }
2495
2496 /* Locate PCI data structure. */
2497 pcids = pcihdr +
2498 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2499 qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2500
2501 /* Validate signature of PCI data structure. */
2502 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2503 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2504 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2505 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2506 /* Incorrect header. */
2507 DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2508 "found pcir_adr=%x.\n", pcids));
2509 ret = QLA_FUNCTION_FAILED;
2510 break;
2511 }
2512
2513 /* Read version */
2514 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2515 switch (code_type) {
2516 case ROM_CODE_TYPE_BIOS:
2517 /* Intel x86, PC-AT compatible. */
2518 ha->bios_revision[0] =
2519 qla2x00_read_flash_byte(ha, pcids + 0x12);
2520 ha->bios_revision[1] =
2521 qla2x00_read_flash_byte(ha, pcids + 0x13);
2522 DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
2523 ha->bios_revision[1], ha->bios_revision[0]));
2524 break;
2525 case ROM_CODE_TYPE_FCODE:
2526 /* Open Firmware standard for PCI (FCode). */
2527 /* Eeeewww... */
2528 qla2x00_get_fcode_version(ha, pcids);
2529 break;
2530 case ROM_CODE_TYPE_EFI:
2531 /* Extensible Firmware Interface (EFI). */
2532 ha->efi_revision[0] =
2533 qla2x00_read_flash_byte(ha, pcids + 0x12);
2534 ha->efi_revision[1] =
2535 qla2x00_read_flash_byte(ha, pcids + 0x13);
2536 DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
2537 ha->efi_revision[1], ha->efi_revision[0]));
2538 break;
2539 default:
2540 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2541 "type %x at pcids %x.\n", code_type, pcids));
2542 break;
2543 }
2544
2545 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2546
2547 /* Locate next PCI expansion ROM. */
2548 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2549 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2550 } while (!last_image);
2551
2552 if (IS_QLA2322(ha)) {
2553 /* Read firmware image information. */
2554 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2555 dbyte = mbuf;
2556 memset(dbyte, 0, 8);
2557 dcode = (uint16_t *)dbyte;
2558
2559 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
2560 8);
2561 DEBUG3(qla_printk(KERN_DEBUG, ha, "dumping fw ver from "
2562 "flash:\n"));
2563 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8));
2564
2565 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2566 dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2567 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2568 dcode[3] == 0)) {
2569 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2570 "revision at %x.\n", ha->flt_region_fw * 4));
2571 } else {
2572 /* values are in big endian */
2573 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2574 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2575 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2576 }
2577 }
2578
2579 qla2x00_flash_disable(ha);
2580
2581 return ret;
2582 }
2583
2584 int
2585 qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2586 {
2587 int ret = QLA_SUCCESS;
2588 uint32_t pcihdr, pcids;
2589 uint32_t *dcode;
2590 uint8_t *bcode;
2591 uint8_t code_type, last_image;
2592 int i;
2593 struct qla_hw_data *ha = vha->hw;
2594
2595 if (!mbuf)
2596 return QLA_FUNCTION_FAILED;
2597
2598 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2599 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2600 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2601 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2602
2603 dcode = mbuf;
2604
2605 /* Begin with first PCI expansion ROM header. */
2606 pcihdr = ha->flt_region_boot << 2;
2607 last_image = 1;
2608 do {
2609 /* Verify PCI expansion ROM header. */
2610 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
2611 bcode = mbuf + (pcihdr % 4);
2612 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2613 /* No signature */
2614 DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2615 "signature.\n"));
2616 ret = QLA_FUNCTION_FAILED;
2617 break;
2618 }
2619
2620 /* Locate PCI data structure. */
2621 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2622
2623 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
2624 bcode = mbuf + (pcihdr % 4);
2625
2626 /* Validate signature of PCI data structure. */
2627 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2628 bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2629 /* Incorrect header. */
2630 DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2631 "found pcir_adr=%x.\n", pcids));
2632 ret = QLA_FUNCTION_FAILED;
2633 break;
2634 }
2635
2636 /* Read version */
2637 code_type = bcode[0x14];
2638 switch (code_type) {
2639 case ROM_CODE_TYPE_BIOS:
2640 /* Intel x86, PC-AT compatible. */
2641 ha->bios_revision[0] = bcode[0x12];
2642 ha->bios_revision[1] = bcode[0x13];
2643 DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
2644 ha->bios_revision[1], ha->bios_revision[0]));
2645 break;
2646 case ROM_CODE_TYPE_FCODE:
2647 /* Open Firmware standard for PCI (FCode). */
2648 ha->fcode_revision[0] = bcode[0x12];
2649 ha->fcode_revision[1] = bcode[0x13];
2650 DEBUG3(qla_printk(KERN_DEBUG, ha, "read FCODE %d.%d.\n",
2651 ha->fcode_revision[1], ha->fcode_revision[0]));
2652 break;
2653 case ROM_CODE_TYPE_EFI:
2654 /* Extensible Firmware Interface (EFI). */
2655 ha->efi_revision[0] = bcode[0x12];
2656 ha->efi_revision[1] = bcode[0x13];
2657 DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
2658 ha->efi_revision[1], ha->efi_revision[0]));
2659 break;
2660 default:
2661 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2662 "type %x at pcids %x.\n", code_type, pcids));
2663 break;
2664 }
2665
2666 last_image = bcode[0x15] & BIT_7;
2667
2668 /* Locate next PCI expansion ROM. */
2669 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2670 } while (!last_image);
2671
2672 /* Read firmware image information. */
2673 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2674 dcode = mbuf;
2675
2676 qla24xx_read_flash_data(vha, dcode, ha->flt_region_fw + 4, 4);
2677 for (i = 0; i < 4; i++)
2678 dcode[i] = be32_to_cpu(dcode[i]);
2679
2680 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2681 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2682 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2683 dcode[3] == 0)) {
2684 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2685 "revision at %x.\n", ha->flt_region_fw * 4));
2686 } else {
2687 ha->fw_revision[0] = dcode[0];
2688 ha->fw_revision[1] = dcode[1];
2689 ha->fw_revision[2] = dcode[2];
2690 ha->fw_revision[3] = dcode[3];
2691 }
2692
2693 return ret;
2694 }
2695
2696 static int
2697 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
2698 {
2699 if (pos >= end || *pos != 0x82)
2700 return 0;
2701
2702 pos += 3 + pos[1];
2703 if (pos >= end || *pos != 0x90)
2704 return 0;
2705
2706 pos += 3 + pos[1];
2707 if (pos >= end || *pos != 0x78)
2708 return 0;
2709
2710 return 1;
2711 }
2712
2713 int
2714 qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size)
2715 {
2716 struct qla_hw_data *ha = vha->hw;
2717 uint8_t *pos = ha->vpd;
2718 uint8_t *end = pos + ha->vpd_size;
2719 int len = 0;
2720
2721 if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
2722 return 0;
2723
2724 while (pos < end && *pos != 0x78) {
2725 len = (*pos == 0x82) ? pos[1] : pos[2];
2726
2727 if (!strncmp(pos, key, strlen(key)))
2728 break;
2729
2730 if (*pos != 0x90 && *pos != 0x91)
2731 pos += len;
2732
2733 pos += 3;
2734 }
2735
2736 if (pos < end - len && *pos != 0x78)
2737 return snprintf(str, size, "%.*s", len, pos + 3);
2738
2739 return 0;
2740 }
2741
2742 int
2743 qla24xx_read_fcp_prio_cfg(scsi_qla_host_t *vha)
2744 {
2745 int len, max_len;
2746 uint32_t fcp_prio_addr;
2747 struct qla_hw_data *ha = vha->hw;
2748
2749 if (!ha->fcp_prio_cfg) {
2750 ha->fcp_prio_cfg = vmalloc(FCP_PRIO_CFG_SIZE);
2751 if (!ha->fcp_prio_cfg) {
2752 qla_printk(KERN_WARNING, ha,
2753 "Unable to allocate memory for fcp priority data "
2754 "(%x).\n", FCP_PRIO_CFG_SIZE);
2755 return QLA_FUNCTION_FAILED;
2756 }
2757 }
2758 memset(ha->fcp_prio_cfg, 0, FCP_PRIO_CFG_SIZE);
2759
2760 fcp_prio_addr = ha->flt_region_fcp_prio;
2761
2762 /* first read the fcp priority data header from flash */
2763 ha->isp_ops->read_optrom(vha, (uint8_t *)ha->fcp_prio_cfg,
2764 fcp_prio_addr << 2, FCP_PRIO_CFG_HDR_SIZE);
2765
2766 if (!qla24xx_fcp_prio_cfg_valid(ha->fcp_prio_cfg, 0))
2767 goto fail;
2768
2769 /* read remaining FCP CMD config data from flash */
2770 fcp_prio_addr += (FCP_PRIO_CFG_HDR_SIZE >> 2);
2771 len = ha->fcp_prio_cfg->num_entries * FCP_PRIO_CFG_ENTRY_SIZE;
2772 max_len = FCP_PRIO_CFG_SIZE - FCP_PRIO_CFG_HDR_SIZE;
2773
2774 ha->isp_ops->read_optrom(vha, (uint8_t *)&ha->fcp_prio_cfg->entry[0],
2775 fcp_prio_addr << 2, (len < max_len ? len : max_len));
2776
2777 /* revalidate the entire FCP priority config data, including entries */
2778 if (!qla24xx_fcp_prio_cfg_valid(ha->fcp_prio_cfg, 1))
2779 goto fail;
2780
2781 ha->flags.fcp_prio_enabled = 1;
2782 return QLA_SUCCESS;
2783 fail:
2784 vfree(ha->fcp_prio_cfg);
2785 ha->fcp_prio_cfg = NULL;
2786 return QLA_FUNCTION_FAILED;
2787 }
Linus' kernel tree