1 menu "RAM/ROM/Flash chip drivers"
5 tristate "Detect flash chips by Common Flash Interface (CFI) probe"
9 The Common Flash Interface specification was developed by Intel,
10 AMD and other flash manufactures that provides a universal method
11 for probing the capabilities of flash devices. If you wish to
12 support any device that is CFI-compliant, you need to enable this
13 option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
14 for more information on CFI.
17 tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
20 This option enables JEDEC-style probing of flash chips which are not
21 compatible with the Common Flash Interface, but will use the common
22 CFI-targeted flash drivers for any chips which are identified which
23 are in fact compatible in all but the probe method. This actually
24 covers most AMD/Fujitsu-compatible chips and also non-CFI
30 config MTD_CFI_ADV_OPTIONS
31 bool "Flash chip driver advanced configuration options"
32 depends on MTD_GEN_PROBE
34 If you need to specify a specific endianness for access to flash
35 chips, or if you wish to reduce the size of the kernel by including
36 support for only specific arrangements of flash chips, say 'Y'. This
37 option does not directly affect the code, but will enable other
38 configuration options which allow you to do so.
43 prompt "Flash cmd/query data swapping"
44 depends on MTD_CFI_ADV_OPTIONS
45 default MTD_CFI_NOSWAP
47 This option defines the way in which the CPU attempts to arrange
48 data bits when writing the 'magic' commands to the chips. Saying
49 'NO', which is the default when CONFIG_MTD_CFI_ADV_OPTIONS isn't
50 enabled, means that the CPU will not do any swapping; the chips
51 are expected to be wired to the CPU in 'host-endian' form.
52 Specific arrangements are possible with the BIG_ENDIAN_BYTE and
53 LITTLE_ENDIAN_BYTE, if the bytes are reversed.
58 config MTD_CFI_BE_BYTE_SWAP
59 bool "BIG_ENDIAN_BYTE"
61 config MTD_CFI_LE_BYTE_SWAP
62 bool "LITTLE_ENDIAN_BYTE"
66 config MTD_CFI_GEOMETRY
67 bool "Specific CFI Flash geometry selection"
68 depends on MTD_CFI_ADV_OPTIONS
70 This option does not affect the code directly, but will enable
71 some other configuration options which would allow you to reduce
72 the size of the kernel by including support for only certain
73 arrangements of CFI chips. If unsure, say 'N' and all options
74 which are supported by the current code will be enabled.
76 config MTD_MAP_BANK_WIDTH_1
77 bool "Support 8-bit buswidth" if MTD_CFI_GEOMETRY
80 If you wish to support CFI devices on a physical bus which is
83 config MTD_MAP_BANK_WIDTH_2
84 bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
87 If you wish to support CFI devices on a physical bus which is
88 16 bits wide, say 'Y'.
90 config MTD_MAP_BANK_WIDTH_4
91 bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
94 If you wish to support CFI devices on a physical bus which is
95 32 bits wide, say 'Y'.
97 config MTD_MAP_BANK_WIDTH_8
98 bool "Support 64-bit buswidth" if MTD_CFI_GEOMETRY
101 If you wish to support CFI devices on a physical bus which is
102 64 bits wide, say 'Y'.
104 config MTD_MAP_BANK_WIDTH_16
105 bool "Support 128-bit buswidth" if MTD_CFI_GEOMETRY
108 If you wish to support CFI devices on a physical bus which is
109 128 bits wide, say 'Y'.
111 config MTD_MAP_BANK_WIDTH_32
112 bool "Support 256-bit buswidth" if MTD_CFI_GEOMETRY
115 If you wish to support CFI devices on a physical bus which is
116 256 bits wide, say 'Y'.
119 bool "Support 1-chip flash interleave" if MTD_CFI_GEOMETRY
122 If your flash chips are not interleaved - i.e. you only have one
123 flash chip addressed by each bus cycle, then say 'Y'.
126 bool "Support 2-chip flash interleave" if MTD_CFI_GEOMETRY
129 If your flash chips are interleaved in pairs - i.e. you have two
130 flash chips addressed by each bus cycle, then say 'Y'.
133 bool "Support 4-chip flash interleave" if MTD_CFI_GEOMETRY
136 If your flash chips are interleaved in fours - i.e. you have four
137 flash chips addressed by each bus cycle, then say 'Y'.
140 bool "Support 8-chip flash interleave" if MTD_CFI_GEOMETRY
143 If your flash chips are interleaved in eights - i.e. you have eight
144 flash chips addressed by each bus cycle, then say 'Y'.
147 bool "Protection Registers aka one-time programmable (OTP) bits"
148 depends on MTD_CFI_ADV_OPTIONS
152 This enables support for reading, writing and locking so called
153 "Protection Registers" present on some flash chips.
154 A subset of them are pre-programmed at the factory with a
155 unique set of values. The rest is user-programmable.
157 The user-programmable Protection Registers contain one-time
158 programmable (OTP) bits; when programmed, register bits cannot be
159 erased. Each Protection Register can be accessed multiple times to
160 program individual bits, as long as the register remains unlocked.
162 Each Protection Register has an associated Lock Register bit. When a
163 Lock Register bit is programmed, the associated Protection Register
164 can only be read; it can no longer be programmed. Additionally,
165 because the Lock Register bits themselves are OTP, when programmed,
166 Lock Register bits cannot be erased. Therefore, when a Protection
167 Register is locked, it cannot be unlocked.
169 This feature should therefore be used with extreme care. Any mistake
170 in the programming of OTP bits will waste them.
172 config MTD_CFI_INTELEXT
173 tristate "Support for Intel/Sharp flash chips"
174 depends on MTD_GEN_PROBE
177 The Common Flash Interface defines a number of different command
178 sets which a CFI-compliant chip may claim to implement. This code
179 provides support for one of those command sets, used on Intel
180 StrataFlash and other parts.
182 config MTD_CFI_AMDSTD
183 tristate "Support for AMD/Fujitsu/Spansion flash chips"
184 depends on MTD_GEN_PROBE
187 The Common Flash Interface defines a number of different command
188 sets which a CFI-compliant chip may claim to implement. This code
189 provides support for one of those command sets, used on chips
190 including the AMD Am29LV320.
193 tristate "Support for ST (Advanced Architecture) flash chips"
194 depends on MTD_GEN_PROBE
197 The Common Flash Interface defines a number of different command
198 sets which a CFI-compliant chip may claim to implement. This code
199 provides support for one of those command sets.
205 tristate "Support for RAM chips in bus mapping"
207 This option enables basic support for RAM chips accessed through
208 a bus mapping driver.
211 tristate "Support for ROM chips in bus mapping"
213 This option enables basic support for ROM chips accessed through
214 a bus mapping driver.
217 tristate "Support for absent chips in bus mapping"
219 This option enables support for a dummy probing driver used to
220 allocated placeholder MTD devices on systems that have socketed
221 or removable media. Use of this driver as a fallback chip probe
222 preserves the expected registration order of MTD device nodes on
223 the system regardless of media presence. Device nodes created
224 with this driver will return -ENODEV upon access.
227 bool "XIP aware MTD support"
228 depends on !SMP && (MTD_CFI_INTELEXT || MTD_CFI_AMDSTD) && ARCH_MTD_XIP
229 default y if XIP_KERNEL
231 This allows MTD support to work with flash memory which is also
232 used for XIP purposes. If you're not sure what this is all about