arch/arm/plat-s5p/clock.c

   1 /* linux/arch/arm/plat-s5p/clock.c
   2  *
   3  * Copyright 2009 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * S5P - Common clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/init.h>
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/io.h>
  22 #include <asm/div64.h>
  23
  24 #include <plat/clock.h>
  25 #include <plat/clock-clksrc.h>
  26 #include <plat/s5p-clock.h>
  27
  28 /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
  29  * clk_ext_xtal_mux.
  30 */
  31 struct clk clk_ext_xtal_mux = {
  32         .name           = "ext_xtal",
  33         .id             = -1,
  34 };
  35
  36 /* 48MHz USB Phy clock output */
  37 struct clk clk_48m = {
  38         .name           = "clk_48m",
  39         .id             = -1,
  40         .rate           = 48000000,
  41 };
  42
  43 /* APLL clock output
  44  * No need .ctrlbit, this is always on
  45 */
  46 struct clk clk_fout_apll = {
  47         .name           = "fout_apll",
  48         .id             = -1,
  49 };
  50
  51 /* MPLL clock output
  52  * No need .ctrlbit, this is always on
  53 */
  54 struct clk clk_fout_mpll = {
  55         .name           = "fout_mpll",
  56         .id             = -1,
  57 };
  58
  59 /* EPLL clock output */
  60 struct clk clk_fout_epll = {
  61         .name           = "fout_epll",
  62         .id             = -1,
  63         .ctrlbit        = (1 << 31),
  64 };
  65
  66 /* ARM clock */
  67 struct clk clk_arm = {
  68         .name           = "armclk",
  69         .id             = -1,
  70         .rate           = 0,
  71         .ctrlbit        = 0,
  72 };
  73
  74 /* Possible clock sources for APLL Mux */
  75 static struct clk *clk_src_apll_list[] = {
  76         [0] = &clk_fin_apll,
  77         [1] = &clk_fout_apll,
  78 };
  79
  80 struct clksrc_sources clk_src_apll = {
  81         .sources        = clk_src_apll_list,
  82         .nr_sources     = ARRAY_SIZE(clk_src_apll_list),
  83 };
  84
  85 /* Possible clock sources for MPLL Mux */
  86 static struct clk *clk_src_mpll_list[] = {
  87         [0] = &clk_fin_mpll,
  88         [1] = &clk_fout_mpll,
  89 };
  90
  91 struct clksrc_sources clk_src_mpll = {
  92         .sources        = clk_src_mpll_list,
  93         .nr_sources     = ARRAY_SIZE(clk_src_mpll_list),
  94 };
  95
  96 /* Possible clock sources for EPLL Mux */
  97 static struct clk *clk_src_epll_list[] = {
  98         [0] = &clk_fin_epll,
  99         [1] = &clk_fout_epll,
 100 };
 101
 102 struct clksrc_sources clk_src_epll = {
 103         .sources        = clk_src_epll_list,
 104         .nr_sources     = ARRAY_SIZE(clk_src_epll_list),
 105 };
 106
 107 int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable)
 108 {
 109         unsigned int ctrlbit = clk->ctrlbit;
 110         u32 con;
 111
 112         con = __raw_readl(reg);
 113         con = enable ? (con | ctrlbit) : (con & ~ctrlbit);
 114         __raw_writel(con, reg);
 115         return 0;
 116 }
 117
 118 static struct clk *s5p_clks[] __initdata = {
 119         &clk_ext_xtal_mux,
 120         &clk_48m,
 121         &clk_fout_apll,
 122         &clk_fout_mpll,
 123         &clk_fout_epll,
 124         &clk_arm,
 125 };
 126
 127 void __init s5p_register_clocks(unsigned long xtal_freq)
 128 {
 129         int ret;
 130
 131         clk_ext_xtal_mux.rate = xtal_freq;
 132
 133         ret = s3c24xx_register_clocks(s5p_clks, ARRAY_SIZE(s5p_clks));
 134         if (ret > 0)
 135                 printk(KERN_ERR "Failed to register s5p clocks\n");
 136 }