2 * MUSB OTG driver peripheral support
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <linux/kernel.h>
37 #include <linux/list.h>
38 #include <linux/timer.h>
39 #include <linux/module.h>
40 #include <linux/smp.h>
41 #include <linux/spinlock.h>
42 #include <linux/delay.h>
43 #include <linux/moduleparam.h>
44 #include <linux/stat.h>
45 #include <linux/dma-mapping.h>
47 #include "musb_core.h"
50 /* MUSB PERIPHERAL status 3-mar-2006:
52 * - EP0 seems solid. It passes both USBCV and usbtest control cases.
55 * + remote wakeup to Linux hosts work, but saw USBCV failures;
56 * in one test run (operator error?)
57 * + endpoint halt tests -- in both usbtest and usbcv -- seem
58 * to break when dma is enabled ... is something wrongly
61 * - Mass storage behaved ok when last tested. Network traffic patterns
62 * (with lots of short transfers etc) need retesting; they turn up the
63 * worst cases of the DMA, since short packets are typical but are not
67 * + both pio and dma behave in with network and g_zero tests
68 * + no cppi throughput issues other than no-hw-queueing
69 * + failed with FLAT_REG (DaVinci)
70 * + seems to behave with double buffering, PIO -and- CPPI
71 * + with gadgetfs + AIO, requests got lost?
74 * + both pio and dma behave in with network and g_zero tests
75 * + dma is slow in typical case (short_not_ok is clear)
76 * + double buffering ok with PIO
77 * + double buffering *FAILS* with CPPI, wrong data bytes sometimes
78 * + request lossage observed with gadgetfs
80 * - ISO not tested ... might work, but only weakly isochronous
82 * - Gadget driver disabling of softconnect during bind() is ignored; so
83 * drivers can't hold off host requests until userspace is ready.
84 * (Workaround: they can turn it off later.)
86 * - PORTABILITY (assumes PIO works):
87 * + DaVinci, basically works with cppi dma
88 * + OMAP 2430, ditto with mentor dma
89 * + TUSB 6010, platform-specific dma in the works
92 /* ----------------------------------------------------------------------- */
95 * Immediately complete a request.
97 * @param request the request to complete
98 * @param status the status to complete the request with
99 * Context: controller locked, IRQs blocked.
101 void musb_g_giveback(
103 struct usb_request
*request
,
105 __releases(ep
->musb
->lock
)
106 __acquires(ep
->musb
->lock
)
108 struct musb_request
*req
;
112 req
= to_musb_request(request
);
114 list_del(&request
->list
);
115 if (req
->request
.status
== -EINPROGRESS
)
116 req
->request
.status
= status
;
120 spin_unlock(&musb
->lock
);
121 if (is_dma_capable()) {
123 dma_unmap_single(musb
->controller
,
129 req
->request
.dma
= DMA_ADDR_INVALID
;
131 } else if (req
->request
.dma
!= DMA_ADDR_INVALID
)
132 dma_sync_single_for_cpu(musb
->controller
,
139 if (request
->status
== 0)
140 DBG(5, "%s done request %p, %d/%d\n",
141 ep
->end_point
.name
, request
,
142 req
->request
.actual
, req
->request
.length
);
144 DBG(2, "%s request %p, %d/%d fault %d\n",
145 ep
->end_point
.name
, request
,
146 req
->request
.actual
, req
->request
.length
,
148 req
->request
.complete(&req
->ep
->end_point
, &req
->request
);
149 spin_lock(&musb
->lock
);
153 /* ----------------------------------------------------------------------- */
156 * Abort requests queued to an endpoint using the status. Synchronous.
157 * caller locked controller and blocked irqs, and selected this ep.
159 static void nuke(struct musb_ep
*ep
, const int status
)
161 struct musb_request
*req
= NULL
;
162 void __iomem
*epio
= ep
->musb
->endpoints
[ep
->current_epnum
].regs
;
166 if (is_dma_capable() && ep
->dma
) {
167 struct dma_controller
*c
= ep
->musb
->dma_controller
;
172 * The programming guide says that we must not clear
173 * the DMAMODE bit before DMAENAB, so we only
174 * clear it in the second write...
176 musb_writew(epio
, MUSB_TXCSR
,
177 MUSB_TXCSR_DMAMODE
| MUSB_TXCSR_FLUSHFIFO
);
178 musb_writew(epio
, MUSB_TXCSR
,
179 0 | MUSB_TXCSR_FLUSHFIFO
);
181 musb_writew(epio
, MUSB_RXCSR
,
182 0 | MUSB_RXCSR_FLUSHFIFO
);
183 musb_writew(epio
, MUSB_RXCSR
,
184 0 | MUSB_RXCSR_FLUSHFIFO
);
187 value
= c
->channel_abort(ep
->dma
);
188 DBG(value
? 1 : 6, "%s: abort DMA --> %d\n", ep
->name
, value
);
189 c
->channel_release(ep
->dma
);
193 while (!list_empty(&(ep
->req_list
))) {
194 req
= container_of(ep
->req_list
.next
, struct musb_request
,
196 musb_g_giveback(ep
, &req
->request
, status
);
200 /* ----------------------------------------------------------------------- */
202 /* Data transfers - pure PIO, pure DMA, or mixed mode */
205 * This assumes the separate CPPI engine is responding to DMA requests
206 * from the usb core ... sequenced a bit differently from mentor dma.
209 static inline int max_ep_writesize(struct musb
*musb
, struct musb_ep
*ep
)
211 if (can_bulk_split(musb
, ep
->type
))
212 return ep
->hw_ep
->max_packet_sz_tx
;
214 return ep
->packet_sz
;
218 #ifdef CONFIG_USB_INVENTRA_DMA
220 /* Peripheral tx (IN) using Mentor DMA works as follows:
221 Only mode 0 is used for transfers <= wPktSize,
222 mode 1 is used for larger transfers,
224 One of the following happens:
225 - Host sends IN token which causes an endpoint interrupt
227 -> if DMA is currently busy, exit.
228 -> if queue is non-empty, txstate().
230 - Request is queued by the gadget driver.
231 -> if queue was previously empty, txstate()
236 | (data is transferred to the FIFO, then sent out when
237 | IN token(s) are recd from Host.
238 | -> DMA interrupt on completion
240 | -> stop DMA, ~DMAENAB,
241 | -> set TxPktRdy for last short pkt or zlp
242 | -> Complete Request
243 | -> Continue next request (call txstate)
244 |___________________________________|
246 * Non-Mentor DMA engines can of course work differently, such as by
247 * upleveling from irq-per-packet to irq-per-buffer.
253 * An endpoint is transmitting data. This can be called either from
254 * the IRQ routine or from ep.queue() to kickstart a request on an
257 * Context: controller locked, IRQs blocked, endpoint selected
259 static void txstate(struct musb
*musb
, struct musb_request
*req
)
261 u8 epnum
= req
->epnum
;
262 struct musb_ep
*musb_ep
;
263 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
264 struct usb_request
*request
;
265 u16 fifo_count
= 0, csr
;
270 /* we shouldn't get here while DMA is active ... but we do ... */
271 if (dma_channel_status(musb_ep
->dma
) == MUSB_DMA_STATUS_BUSY
) {
272 DBG(4, "dma pending...\n");
276 /* read TXCSR before */
277 csr
= musb_readw(epio
, MUSB_TXCSR
);
279 request
= &req
->request
;
280 fifo_count
= min(max_ep_writesize(musb
, musb_ep
),
281 (int)(request
->length
- request
->actual
));
283 if (csr
& MUSB_TXCSR_TXPKTRDY
) {
284 DBG(5, "%s old packet still ready , txcsr %03x\n",
285 musb_ep
->end_point
.name
, csr
);
289 if (csr
& MUSB_TXCSR_P_SENDSTALL
) {
290 DBG(5, "%s stalling, txcsr %03x\n",
291 musb_ep
->end_point
.name
, csr
);
295 DBG(4, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
296 epnum
, musb_ep
->packet_sz
, fifo_count
,
299 #ifndef CONFIG_MUSB_PIO_ONLY
300 if (is_dma_capable() && musb_ep
->dma
) {
301 struct dma_controller
*c
= musb
->dma_controller
;
303 use_dma
= (request
->dma
!= DMA_ADDR_INVALID
);
305 /* MUSB_TXCSR_P_ISO is still set correctly */
307 #ifdef CONFIG_USB_INVENTRA_DMA
311 /* setup DMA, then program endpoint CSR */
312 request_size
= min_t(size_t, request
->length
,
313 musb_ep
->dma
->max_len
);
314 if (request_size
< musb_ep
->packet_sz
)
315 musb_ep
->dma
->desired_mode
= 0;
317 musb_ep
->dma
->desired_mode
= 1;
319 use_dma
= use_dma
&& c
->channel_program(
320 musb_ep
->dma
, musb_ep
->packet_sz
,
321 musb_ep
->dma
->desired_mode
,
322 request
->dma
+ request
->actual
, request_size
);
324 if (musb_ep
->dma
->desired_mode
== 0) {
326 * We must not clear the DMAMODE bit
327 * before the DMAENAB bit -- and the
328 * latter doesn't always get cleared
329 * before we get here...
331 csr
&= ~(MUSB_TXCSR_AUTOSET
332 | MUSB_TXCSR_DMAENAB
);
333 musb_writew(epio
, MUSB_TXCSR
, csr
334 | MUSB_TXCSR_P_WZC_BITS
);
335 csr
&= ~MUSB_TXCSR_DMAMODE
;
336 csr
|= (MUSB_TXCSR_DMAENAB
|
338 /* against programming guide */
340 csr
|= (MUSB_TXCSR_AUTOSET
345 csr
&= ~MUSB_TXCSR_P_UNDERRUN
;
346 musb_writew(epio
, MUSB_TXCSR
, csr
);
350 #elif defined(CONFIG_USB_TI_CPPI_DMA)
351 /* program endpoint CSR first, then setup DMA */
352 csr
&= ~(MUSB_TXCSR_P_UNDERRUN
| MUSB_TXCSR_TXPKTRDY
);
353 csr
|= MUSB_TXCSR_DMAENAB
| MUSB_TXCSR_DMAMODE
|
355 musb_writew(epio
, MUSB_TXCSR
,
356 (MUSB_TXCSR_P_WZC_BITS
& ~MUSB_TXCSR_P_UNDERRUN
)
359 /* ensure writebuffer is empty */
360 csr
= musb_readw(epio
, MUSB_TXCSR
);
362 /* NOTE host side sets DMAENAB later than this; both are
363 * OK since the transfer dma glue (between CPPI and Mentor
364 * fifos) just tells CPPI it could start. Data only moves
365 * to the USB TX fifo when both fifos are ready.
368 /* "mode" is irrelevant here; handle terminating ZLPs like
369 * PIO does, since the hardware RNDIS mode seems unreliable
370 * except for the last-packet-is-already-short case.
372 use_dma
= use_dma
&& c
->channel_program(
373 musb_ep
->dma
, musb_ep
->packet_sz
,
378 c
->channel_release(musb_ep
->dma
);
380 csr
&= ~MUSB_TXCSR_DMAENAB
;
381 musb_writew(epio
, MUSB_TXCSR
, csr
);
382 /* invariant: prequest->buf is non-null */
384 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
385 use_dma
= use_dma
&& c
->channel_program(
386 musb_ep
->dma
, musb_ep
->packet_sz
,
395 musb_write_fifo(musb_ep
->hw_ep
, fifo_count
,
396 (u8
*) (request
->buf
+ request
->actual
));
397 request
->actual
+= fifo_count
;
398 csr
|= MUSB_TXCSR_TXPKTRDY
;
399 csr
&= ~MUSB_TXCSR_P_UNDERRUN
;
400 musb_writew(epio
, MUSB_TXCSR
, csr
);
403 /* host may already have the data when this message shows... */
404 DBG(3, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
405 musb_ep
->end_point
.name
, use_dma
? "dma" : "pio",
406 request
->actual
, request
->length
,
407 musb_readw(epio
, MUSB_TXCSR
),
409 musb_readw(epio
, MUSB_TXMAXP
));
413 * FIFO state update (e.g. data ready).
414 * Called from IRQ, with controller locked.
416 void musb_g_tx(struct musb
*musb
, u8 epnum
)
419 struct usb_request
*request
;
420 u8 __iomem
*mbase
= musb
->mregs
;
421 struct musb_ep
*musb_ep
= &musb
->endpoints
[epnum
].ep_in
;
422 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
423 struct dma_channel
*dma
;
425 musb_ep_select(mbase
, epnum
);
426 request
= next_request(musb_ep
);
428 csr
= musb_readw(epio
, MUSB_TXCSR
);
429 DBG(4, "<== %s, txcsr %04x\n", musb_ep
->end_point
.name
, csr
);
431 dma
= is_dma_capable() ? musb_ep
->dma
: NULL
;
434 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
435 * probably rates reporting as a host error.
437 if (csr
& MUSB_TXCSR_P_SENTSTALL
) {
438 csr
|= MUSB_TXCSR_P_WZC_BITS
;
439 csr
&= ~MUSB_TXCSR_P_SENTSTALL
;
440 musb_writew(epio
, MUSB_TXCSR
, csr
);
444 if (csr
& MUSB_TXCSR_P_UNDERRUN
) {
445 /* We NAKed, no big deal... little reason to care. */
446 csr
|= MUSB_TXCSR_P_WZC_BITS
;
447 csr
&= ~(MUSB_TXCSR_P_UNDERRUN
| MUSB_TXCSR_TXPKTRDY
);
448 musb_writew(epio
, MUSB_TXCSR
, csr
);
449 DBG(20, "underrun on ep%d, req %p\n", epnum
, request
);
452 if (dma_channel_status(dma
) == MUSB_DMA_STATUS_BUSY
) {
454 * SHOULD NOT HAPPEN... has with CPPI though, after
455 * changing SENDSTALL (and other cases); harmless?
457 DBG(5, "%s dma still busy?\n", musb_ep
->end_point
.name
);
464 if (dma
&& (csr
& MUSB_TXCSR_DMAENAB
)) {
466 csr
|= MUSB_TXCSR_P_WZC_BITS
;
467 csr
&= ~(MUSB_TXCSR_DMAENAB
| MUSB_TXCSR_P_UNDERRUN
|
468 MUSB_TXCSR_TXPKTRDY
);
469 musb_writew(epio
, MUSB_TXCSR
, csr
);
470 /* Ensure writebuffer is empty. */
471 csr
= musb_readw(epio
, MUSB_TXCSR
);
472 request
->actual
+= musb_ep
->dma
->actual_len
;
473 DBG(4, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
474 epnum
, csr
, musb_ep
->dma
->actual_len
, request
);
477 if (is_dma
|| request
->actual
== request
->length
) {
479 * First, maybe a terminating short packet. Some DMA
480 * engines might handle this by themselves.
482 if ((request
->zero
&& request
->length
483 && request
->length
% musb_ep
->packet_sz
== 0)
484 #ifdef CONFIG_USB_INVENTRA_DMA
485 || (is_dma
&& (!dma
->desired_mode
||
487 (musb_ep
->packet_sz
- 1))))
491 * On DMA completion, FIFO may not be
494 if (csr
& MUSB_TXCSR_TXPKTRDY
)
497 DBG(4, "sending zero pkt\n");
498 musb_writew(epio
, MUSB_TXCSR
, MUSB_TXCSR_MODE
499 | MUSB_TXCSR_TXPKTRDY
);
503 /* ... or if not, then complete it. */
504 musb_g_giveback(musb_ep
, request
, 0);
507 * Kickstart next transfer if appropriate;
508 * the packet that just completed might not
509 * be transmitted for hours or days.
510 * REVISIT for double buffering...
511 * FIXME revisit for stalls too...
513 musb_ep_select(mbase
, epnum
);
514 csr
= musb_readw(epio
, MUSB_TXCSR
);
515 if (csr
& MUSB_TXCSR_FIFONOTEMPTY
)
518 request
= musb_ep
->desc
? next_request(musb_ep
) : NULL
;
520 DBG(4, "%s idle now\n",
521 musb_ep
->end_point
.name
);
526 txstate(musb
, to_musb_request(request
));
530 /* ------------------------------------------------------------ */
532 #ifdef CONFIG_USB_INVENTRA_DMA
534 /* Peripheral rx (OUT) using Mentor DMA works as follows:
535 - Only mode 0 is used.
537 - Request is queued by the gadget class driver.
538 -> if queue was previously empty, rxstate()
540 - Host sends OUT token which causes an endpoint interrupt
542 | -> if request queued, call rxstate
544 | | -> DMA interrupt on completion
548 | | -> if data recd = max expected
549 | | by the request, or host
550 | | sent a short packet,
551 | | complete the request,
552 | | and start the next one.
553 | |_____________________________________|
554 | else just wait for the host
555 | to send the next OUT token.
556 |__________________________________________________|
558 * Non-Mentor DMA engines can of course work differently.
564 * Context: controller locked, IRQs blocked, endpoint selected
566 static void rxstate(struct musb
*musb
, struct musb_request
*req
)
568 const u8 epnum
= req
->epnum
;
569 struct usb_request
*request
= &req
->request
;
570 struct musb_ep
*musb_ep
= &musb
->endpoints
[epnum
].ep_out
;
571 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
572 unsigned fifo_count
= 0;
573 u16 len
= musb_ep
->packet_sz
;
574 u16 csr
= musb_readw(epio
, MUSB_RXCSR
);
576 /* We shouldn't get here while DMA is active, but we do... */
577 if (dma_channel_status(musb_ep
->dma
) == MUSB_DMA_STATUS_BUSY
) {
578 DBG(4, "DMA pending...\n");
582 if (csr
& MUSB_RXCSR_P_SENDSTALL
) {
583 DBG(5, "%s stalling, RXCSR %04x\n",
584 musb_ep
->end_point
.name
, csr
);
588 if (is_cppi_enabled() && musb_ep
->dma
) {
589 struct dma_controller
*c
= musb
->dma_controller
;
590 struct dma_channel
*channel
= musb_ep
->dma
;
592 /* NOTE: CPPI won't actually stop advancing the DMA
593 * queue after short packet transfers, so this is almost
594 * always going to run as IRQ-per-packet DMA so that
595 * faults will be handled correctly.
597 if (c
->channel_program(channel
,
599 !request
->short_not_ok
,
600 request
->dma
+ request
->actual
,
601 request
->length
- request
->actual
)) {
603 /* make sure that if an rxpkt arrived after the irq,
604 * the cppi engine will be ready to take it as soon
607 csr
&= ~(MUSB_RXCSR_AUTOCLEAR
608 | MUSB_RXCSR_DMAMODE
);
609 csr
|= MUSB_RXCSR_DMAENAB
| MUSB_RXCSR_P_WZC_BITS
;
610 musb_writew(epio
, MUSB_RXCSR
, csr
);
615 if (csr
& MUSB_RXCSR_RXPKTRDY
) {
616 len
= musb_readw(epio
, MUSB_RXCOUNT
);
617 if (request
->actual
< request
->length
) {
618 #ifdef CONFIG_USB_INVENTRA_DMA
619 if (is_dma_capable() && musb_ep
->dma
) {
620 struct dma_controller
*c
;
621 struct dma_channel
*channel
;
624 c
= musb
->dma_controller
;
625 channel
= musb_ep
->dma
;
627 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
628 * mode 0 only. So we do not get endpoint interrupts due to DMA
629 * completion. We only get interrupts from DMA controller.
631 * We could operate in DMA mode 1 if we knew the size of the tranfer
632 * in advance. For mass storage class, request->length = what the host
633 * sends, so that'd work. But for pretty much everything else,
634 * request->length is routinely more than what the host sends. For
635 * most these gadgets, end of is signified either by a short packet,
636 * or filling the last byte of the buffer. (Sending extra data in
637 * that last pckate should trigger an overflow fault.) But in mode 1,
638 * we don't get DMA completion interrrupt for short packets.
640 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
641 * to get endpoint interrupt on every DMA req, but that didn't seem
644 * REVISIT an updated g_file_storage can set req->short_not_ok, which
645 * then becomes usable as a runtime "use mode 1" hint...
648 csr
|= MUSB_RXCSR_DMAENAB
;
650 csr
|= MUSB_RXCSR_AUTOCLEAR
;
651 /* csr |= MUSB_RXCSR_DMAMODE; */
653 /* this special sequence (enabling and then
654 * disabling MUSB_RXCSR_DMAMODE) is required
655 * to get DMAReq to activate
657 musb_writew(epio
, MUSB_RXCSR
,
658 csr
| MUSB_RXCSR_DMAMODE
);
660 musb_writew(epio
, MUSB_RXCSR
, csr
);
662 if (request
->actual
< request
->length
) {
663 int transfer_size
= 0;
665 transfer_size
= min(request
->length
,
670 if (transfer_size
<= musb_ep
->packet_sz
)
671 musb_ep
->dma
->desired_mode
= 0;
673 musb_ep
->dma
->desired_mode
= 1;
675 use_dma
= c
->channel_program(
678 channel
->desired_mode
,
687 #endif /* Mentor's DMA */
689 fifo_count
= request
->length
- request
->actual
;
690 DBG(3, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
691 musb_ep
->end_point
.name
,
695 fifo_count
= min_t(unsigned, len
, fifo_count
);
697 #ifdef CONFIG_USB_TUSB_OMAP_DMA
698 if (tusb_dma_omap() && musb_ep
->dma
) {
699 struct dma_controller
*c
= musb
->dma_controller
;
700 struct dma_channel
*channel
= musb_ep
->dma
;
701 u32 dma_addr
= request
->dma
+ request
->actual
;
704 ret
= c
->channel_program(channel
,
706 channel
->desired_mode
,
714 musb_read_fifo(musb_ep
->hw_ep
, fifo_count
, (u8
*)
715 (request
->buf
+ request
->actual
));
716 request
->actual
+= fifo_count
;
718 /* REVISIT if we left anything in the fifo, flush
719 * it and report -EOVERFLOW
723 csr
|= MUSB_RXCSR_P_WZC_BITS
;
724 csr
&= ~MUSB_RXCSR_RXPKTRDY
;
725 musb_writew(epio
, MUSB_RXCSR
, csr
);
729 /* reach the end or short packet detected */
730 if (request
->actual
== request
->length
|| len
< musb_ep
->packet_sz
)
731 musb_g_giveback(musb_ep
, request
, 0);
735 * Data ready for a request; called from IRQ
737 void musb_g_rx(struct musb
*musb
, u8 epnum
)
740 struct usb_request
*request
;
741 void __iomem
*mbase
= musb
->mregs
;
742 struct musb_ep
*musb_ep
= &musb
->endpoints
[epnum
].ep_out
;
743 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
744 struct dma_channel
*dma
;
746 musb_ep_select(mbase
, epnum
);
748 request
= next_request(musb_ep
);
752 csr
= musb_readw(epio
, MUSB_RXCSR
);
753 dma
= is_dma_capable() ? musb_ep
->dma
: NULL
;
755 DBG(4, "<== %s, rxcsr %04x%s %p\n", musb_ep
->end_point
.name
,
756 csr
, dma
? " (dma)" : "", request
);
758 if (csr
& MUSB_RXCSR_P_SENTSTALL
) {
759 csr
|= MUSB_RXCSR_P_WZC_BITS
;
760 csr
&= ~MUSB_RXCSR_P_SENTSTALL
;
761 musb_writew(epio
, MUSB_RXCSR
, csr
);
765 if (csr
& MUSB_RXCSR_P_OVERRUN
) {
766 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
767 csr
&= ~MUSB_RXCSR_P_OVERRUN
;
768 musb_writew(epio
, MUSB_RXCSR
, csr
);
770 DBG(3, "%s iso overrun on %p\n", musb_ep
->name
, request
);
771 if (request
&& request
->status
== -EINPROGRESS
)
772 request
->status
= -EOVERFLOW
;
774 if (csr
& MUSB_RXCSR_INCOMPRX
) {
775 /* REVISIT not necessarily an error */
776 DBG(4, "%s, incomprx\n", musb_ep
->end_point
.name
);
779 if (dma_channel_status(dma
) == MUSB_DMA_STATUS_BUSY
) {
780 /* "should not happen"; likely RXPKTRDY pending for DMA */
781 DBG((csr
& MUSB_RXCSR_DMAENAB
) ? 4 : 1,
782 "%s busy, csr %04x\n",
783 musb_ep
->end_point
.name
, csr
);
787 if (dma
&& (csr
& MUSB_RXCSR_DMAENAB
)) {
788 csr
&= ~(MUSB_RXCSR_AUTOCLEAR
790 | MUSB_RXCSR_DMAMODE
);
791 musb_writew(epio
, MUSB_RXCSR
,
792 MUSB_RXCSR_P_WZC_BITS
| csr
);
794 request
->actual
+= musb_ep
->dma
->actual_len
;
796 DBG(4, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
798 musb_readw(epio
, MUSB_RXCSR
),
799 musb_ep
->dma
->actual_len
, request
);
801 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA)
802 /* Autoclear doesn't clear RxPktRdy for short packets */
803 if ((dma
->desired_mode
== 0)
805 & (musb_ep
->packet_sz
- 1))) {
807 csr
&= ~MUSB_RXCSR_RXPKTRDY
;
808 musb_writew(epio
, MUSB_RXCSR
, csr
);
811 /* incomplete, and not short? wait for next IN packet */
812 if ((request
->actual
< request
->length
)
813 && (musb_ep
->dma
->actual_len
814 == musb_ep
->packet_sz
))
817 musb_g_giveback(musb_ep
, request
, 0);
819 request
= next_request(musb_ep
);
824 /* analyze request if the ep is hot */
826 rxstate(musb
, to_musb_request(request
));
828 DBG(3, "packet waiting for %s%s request\n",
829 musb_ep
->desc
? "" : "inactive ",
830 musb_ep
->end_point
.name
);
834 /* ------------------------------------------------------------ */
836 static int musb_gadget_enable(struct usb_ep
*ep
,
837 const struct usb_endpoint_descriptor
*desc
)
840 struct musb_ep
*musb_ep
;
841 struct musb_hw_ep
*hw_ep
;
848 int status
= -EINVAL
;
853 musb_ep
= to_musb_ep(ep
);
854 hw_ep
= musb_ep
->hw_ep
;
856 musb
= musb_ep
->musb
;
858 epnum
= musb_ep
->current_epnum
;
860 spin_lock_irqsave(&musb
->lock
, flags
);
866 musb_ep
->type
= usb_endpoint_type(desc
);
868 /* check direction and (later) maxpacket size against endpoint */
869 if (usb_endpoint_num(desc
) != epnum
)
872 /* REVISIT this rules out high bandwidth periodic transfers */
873 tmp
= le16_to_cpu(desc
->wMaxPacketSize
);
876 musb_ep
->packet_sz
= tmp
;
878 /* enable the interrupts for the endpoint, set the endpoint
879 * packet size (or fail), set the mode, clear the fifo
881 musb_ep_select(mbase
, epnum
);
882 if (usb_endpoint_dir_in(desc
)) {
883 u16 int_txe
= musb_readw(mbase
, MUSB_INTRTXE
);
885 if (hw_ep
->is_shared_fifo
)
889 if (tmp
> hw_ep
->max_packet_sz_tx
)
892 int_txe
|= (1 << epnum
);
893 musb_writew(mbase
, MUSB_INTRTXE
, int_txe
);
895 /* REVISIT if can_bulk_split(), use by updating "tmp";
896 * likewise high bandwidth periodic tx
898 /* Set TXMAXP with the FIFO size of the endpoint
899 * to disable double buffering mode. Currently, It seems that double
900 * buffering has problem if musb RTL revision number < 2.0.
902 if (musb
->hwvers
< MUSB_HWVERS_2000
)
903 musb_writew(regs
, MUSB_TXMAXP
, hw_ep
->max_packet_sz_tx
);
905 musb_writew(regs
, MUSB_TXMAXP
, tmp
);
907 csr
= MUSB_TXCSR_MODE
| MUSB_TXCSR_CLRDATATOG
;
908 if (musb_readw(regs
, MUSB_TXCSR
)
909 & MUSB_TXCSR_FIFONOTEMPTY
)
910 csr
|= MUSB_TXCSR_FLUSHFIFO
;
911 if (musb_ep
->type
== USB_ENDPOINT_XFER_ISOC
)
912 csr
|= MUSB_TXCSR_P_ISO
;
914 /* set twice in case of double buffering */
915 musb_writew(regs
, MUSB_TXCSR
, csr
);
916 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
917 musb_writew(regs
, MUSB_TXCSR
, csr
);
920 u16 int_rxe
= musb_readw(mbase
, MUSB_INTRRXE
);
922 if (hw_ep
->is_shared_fifo
)
926 if (tmp
> hw_ep
->max_packet_sz_rx
)
929 int_rxe
|= (1 << epnum
);
930 musb_writew(mbase
, MUSB_INTRRXE
, int_rxe
);
932 /* REVISIT if can_bulk_combine() use by updating "tmp"
933 * likewise high bandwidth periodic rx
935 /* Set RXMAXP with the FIFO size of the endpoint
936 * to disable double buffering mode.
938 if (musb
->hwvers
< MUSB_HWVERS_2000
)
939 musb_writew(regs
, MUSB_RXMAXP
, hw_ep
->max_packet_sz_rx
);
941 musb_writew(regs
, MUSB_RXMAXP
, tmp
);
943 /* force shared fifo to OUT-only mode */
944 if (hw_ep
->is_shared_fifo
) {
945 csr
= musb_readw(regs
, MUSB_TXCSR
);
946 csr
&= ~(MUSB_TXCSR_MODE
| MUSB_TXCSR_TXPKTRDY
);
947 musb_writew(regs
, MUSB_TXCSR
, csr
);
950 csr
= MUSB_RXCSR_FLUSHFIFO
| MUSB_RXCSR_CLRDATATOG
;
951 if (musb_ep
->type
== USB_ENDPOINT_XFER_ISOC
)
952 csr
|= MUSB_RXCSR_P_ISO
;
953 else if (musb_ep
->type
== USB_ENDPOINT_XFER_INT
)
954 csr
|= MUSB_RXCSR_DISNYET
;
956 /* set twice in case of double buffering */
957 musb_writew(regs
, MUSB_RXCSR
, csr
);
958 musb_writew(regs
, MUSB_RXCSR
, csr
);
961 /* NOTE: all the I/O code _should_ work fine without DMA, in case
962 * for some reason you run out of channels here.
964 if (is_dma_capable() && musb
->dma_controller
) {
965 struct dma_controller
*c
= musb
->dma_controller
;
967 musb_ep
->dma
= c
->channel_alloc(c
, hw_ep
,
968 (desc
->bEndpointAddress
& USB_DIR_IN
));
972 musb_ep
->desc
= desc
;
977 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
978 musb_driver_name
, musb_ep
->end_point
.name
,
979 ({ char *s
; switch (musb_ep
->type
) {
980 case USB_ENDPOINT_XFER_BULK
: s
= "bulk"; break;
981 case USB_ENDPOINT_XFER_INT
: s
= "int"; break;
982 default: s
= "iso"; break;
984 musb_ep
->is_in
? "IN" : "OUT",
985 musb_ep
->dma
? "dma, " : "",
988 schedule_work(&musb
->irq_work
);
991 spin_unlock_irqrestore(&musb
->lock
, flags
);
996 * Disable an endpoint flushing all requests queued.
998 static int musb_gadget_disable(struct usb_ep
*ep
)
1000 unsigned long flags
;
1003 struct musb_ep
*musb_ep
;
1007 musb_ep
= to_musb_ep(ep
);
1008 musb
= musb_ep
->musb
;
1009 epnum
= musb_ep
->current_epnum
;
1010 epio
= musb
->endpoints
[epnum
].regs
;
1012 spin_lock_irqsave(&musb
->lock
, flags
);
1013 musb_ep_select(musb
->mregs
, epnum
);
1015 /* zero the endpoint sizes */
1016 if (musb_ep
->is_in
) {
1017 u16 int_txe
= musb_readw(musb
->mregs
, MUSB_INTRTXE
);
1018 int_txe
&= ~(1 << epnum
);
1019 musb_writew(musb
->mregs
, MUSB_INTRTXE
, int_txe
);
1020 musb_writew(epio
, MUSB_TXMAXP
, 0);
1022 u16 int_rxe
= musb_readw(musb
->mregs
, MUSB_INTRRXE
);
1023 int_rxe
&= ~(1 << epnum
);
1024 musb_writew(musb
->mregs
, MUSB_INTRRXE
, int_rxe
);
1025 musb_writew(epio
, MUSB_RXMAXP
, 0);
1028 musb_ep
->desc
= NULL
;
1030 /* abort all pending DMA and requests */
1031 nuke(musb_ep
, -ESHUTDOWN
);
1033 schedule_work(&musb
->irq_work
);
1035 spin_unlock_irqrestore(&(musb
->lock
), flags
);
1037 DBG(2, "%s\n", musb_ep
->end_point
.name
);
1043 * Allocate a request for an endpoint.
1044 * Reused by ep0 code.
1046 struct usb_request
*musb_alloc_request(struct usb_ep
*ep
, gfp_t gfp_flags
)
1048 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1049 struct musb_request
*request
= NULL
;
1051 request
= kzalloc(sizeof *request
, gfp_flags
);
1053 INIT_LIST_HEAD(&request
->request
.list
);
1054 request
->request
.dma
= DMA_ADDR_INVALID
;
1055 request
->epnum
= musb_ep
->current_epnum
;
1056 request
->ep
= musb_ep
;
1059 return &request
->request
;
1064 * Reused by ep0 code.
1066 void musb_free_request(struct usb_ep
*ep
, struct usb_request
*req
)
1068 kfree(to_musb_request(req
));
1071 static LIST_HEAD(buffers
);
1073 struct free_record
{
1074 struct list_head list
;
1081 * Context: controller locked, IRQs blocked.
1083 static void musb_ep_restart(struct musb
*musb
, struct musb_request
*req
)
1085 DBG(3, "<== %s request %p len %u on hw_ep%d\n",
1086 req
->tx
? "TX/IN" : "RX/OUT",
1087 &req
->request
, req
->request
.length
, req
->epnum
);
1089 musb_ep_select(musb
->mregs
, req
->epnum
);
1096 static int musb_gadget_queue(struct usb_ep
*ep
, struct usb_request
*req
,
1099 struct musb_ep
*musb_ep
;
1100 struct musb_request
*request
;
1103 unsigned long lockflags
;
1110 musb_ep
= to_musb_ep(ep
);
1111 musb
= musb_ep
->musb
;
1113 request
= to_musb_request(req
);
1114 request
->musb
= musb
;
1116 if (request
->ep
!= musb_ep
)
1119 DBG(4, "<== to %s request=%p\n", ep
->name
, req
);
1121 /* request is mine now... */
1122 request
->request
.actual
= 0;
1123 request
->request
.status
= -EINPROGRESS
;
1124 request
->epnum
= musb_ep
->current_epnum
;
1125 request
->tx
= musb_ep
->is_in
;
1127 if (is_dma_capable() && musb_ep
->dma
) {
1128 if (request
->request
.dma
== DMA_ADDR_INVALID
) {
1129 request
->request
.dma
= dma_map_single(
1131 request
->request
.buf
,
1132 request
->request
.length
,
1136 request
->mapped
= 1;
1138 dma_sync_single_for_device(musb
->controller
,
1139 request
->request
.dma
,
1140 request
->request
.length
,
1144 request
->mapped
= 0;
1146 } else if (!req
->buf
) {
1149 request
->mapped
= 0;
1151 spin_lock_irqsave(&musb
->lock
, lockflags
);
1153 /* don't queue if the ep is down */
1154 if (!musb_ep
->desc
) {
1155 DBG(4, "req %p queued to %s while ep %s\n",
1156 req
, ep
->name
, "disabled");
1157 status
= -ESHUTDOWN
;
1161 /* add request to the list */
1162 list_add_tail(&(request
->request
.list
), &(musb_ep
->req_list
));
1164 /* it this is the head of the queue, start i/o ... */
1165 if (!musb_ep
->busy
&& &request
->request
.list
== musb_ep
->req_list
.next
)
1166 musb_ep_restart(musb
, request
);
1169 spin_unlock_irqrestore(&musb
->lock
, lockflags
);
1173 static int musb_gadget_dequeue(struct usb_ep
*ep
, struct usb_request
*request
)
1175 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1176 struct usb_request
*r
;
1177 unsigned long flags
;
1179 struct musb
*musb
= musb_ep
->musb
;
1181 if (!ep
|| !request
|| to_musb_request(request
)->ep
!= musb_ep
)
1184 spin_lock_irqsave(&musb
->lock
, flags
);
1186 list_for_each_entry(r
, &musb_ep
->req_list
, list
) {
1191 DBG(3, "request %p not queued to %s\n", request
, ep
->name
);
1196 /* if the hardware doesn't have the request, easy ... */
1197 if (musb_ep
->req_list
.next
!= &request
->list
|| musb_ep
->busy
)
1198 musb_g_giveback(musb_ep
, request
, -ECONNRESET
);
1200 /* ... else abort the dma transfer ... */
1201 else if (is_dma_capable() && musb_ep
->dma
) {
1202 struct dma_controller
*c
= musb
->dma_controller
;
1204 musb_ep_select(musb
->mregs
, musb_ep
->current_epnum
);
1205 if (c
->channel_abort
)
1206 status
= c
->channel_abort(musb_ep
->dma
);
1210 musb_g_giveback(musb_ep
, request
, -ECONNRESET
);
1212 /* NOTE: by sticking to easily tested hardware/driver states,
1213 * we leave counting of in-flight packets imprecise.
1215 musb_g_giveback(musb_ep
, request
, -ECONNRESET
);
1219 spin_unlock_irqrestore(&musb
->lock
, flags
);
1224 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1225 * data but will queue requests.
1227 * exported to ep0 code
1229 static int musb_gadget_set_halt(struct usb_ep
*ep
, int value
)
1231 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1232 u8 epnum
= musb_ep
->current_epnum
;
1233 struct musb
*musb
= musb_ep
->musb
;
1234 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
1235 void __iomem
*mbase
;
1236 unsigned long flags
;
1238 struct musb_request
*request
;
1243 mbase
= musb
->mregs
;
1245 spin_lock_irqsave(&musb
->lock
, flags
);
1247 if ((USB_ENDPOINT_XFER_ISOC
== musb_ep
->type
)) {
1252 musb_ep_select(mbase
, epnum
);
1254 request
= to_musb_request(next_request(musb_ep
));
1257 DBG(3, "request in progress, cannot halt %s\n",
1262 /* Cannot portably stall with non-empty FIFO */
1263 if (musb_ep
->is_in
) {
1264 csr
= musb_readw(epio
, MUSB_TXCSR
);
1265 if (csr
& MUSB_TXCSR_FIFONOTEMPTY
) {
1266 DBG(3, "FIFO busy, cannot halt %s\n", ep
->name
);
1272 musb_ep
->wedged
= 0;
1274 /* set/clear the stall and toggle bits */
1275 DBG(2, "%s: %s stall\n", ep
->name
, value
? "set" : "clear");
1276 if (musb_ep
->is_in
) {
1277 csr
= musb_readw(epio
, MUSB_TXCSR
);
1278 csr
|= MUSB_TXCSR_P_WZC_BITS
1279 | MUSB_TXCSR_CLRDATATOG
;
1281 csr
|= MUSB_TXCSR_P_SENDSTALL
;
1283 csr
&= ~(MUSB_TXCSR_P_SENDSTALL
1284 | MUSB_TXCSR_P_SENTSTALL
);
1285 csr
&= ~MUSB_TXCSR_TXPKTRDY
;
1286 musb_writew(epio
, MUSB_TXCSR
, csr
);
1288 csr
= musb_readw(epio
, MUSB_RXCSR
);
1289 csr
|= MUSB_RXCSR_P_WZC_BITS
1290 | MUSB_RXCSR_FLUSHFIFO
1291 | MUSB_RXCSR_CLRDATATOG
;
1293 csr
|= MUSB_RXCSR_P_SENDSTALL
;
1295 csr
&= ~(MUSB_RXCSR_P_SENDSTALL
1296 | MUSB_RXCSR_P_SENTSTALL
);
1297 musb_writew(epio
, MUSB_RXCSR
, csr
);
1300 /* maybe start the first request in the queue */
1301 if (!musb_ep
->busy
&& !value
&& request
) {
1302 DBG(3, "restarting the request\n");
1303 musb_ep_restart(musb
, request
);
1307 spin_unlock_irqrestore(&musb
->lock
, flags
);
1312 * Sets the halt feature with the clear requests ignored
1314 static int musb_gadget_set_wedge(struct usb_ep
*ep
)
1316 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1321 musb_ep
->wedged
= 1;
1323 return usb_ep_set_halt(ep
);
1326 static int musb_gadget_fifo_status(struct usb_ep
*ep
)
1328 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1329 void __iomem
*epio
= musb_ep
->hw_ep
->regs
;
1330 int retval
= -EINVAL
;
1332 if (musb_ep
->desc
&& !musb_ep
->is_in
) {
1333 struct musb
*musb
= musb_ep
->musb
;
1334 int epnum
= musb_ep
->current_epnum
;
1335 void __iomem
*mbase
= musb
->mregs
;
1336 unsigned long flags
;
1338 spin_lock_irqsave(&musb
->lock
, flags
);
1340 musb_ep_select(mbase
, epnum
);
1341 /* FIXME return zero unless RXPKTRDY is set */
1342 retval
= musb_readw(epio
, MUSB_RXCOUNT
);
1344 spin_unlock_irqrestore(&musb
->lock
, flags
);
1349 static void musb_gadget_fifo_flush(struct usb_ep
*ep
)
1351 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1352 struct musb
*musb
= musb_ep
->musb
;
1353 u8 epnum
= musb_ep
->current_epnum
;
1354 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
1355 void __iomem
*mbase
;
1356 unsigned long flags
;
1359 mbase
= musb
->mregs
;
1361 spin_lock_irqsave(&musb
->lock
, flags
);
1362 musb_ep_select(mbase
, (u8
) epnum
);
1364 /* disable interrupts */
1365 int_txe
= musb_readw(mbase
, MUSB_INTRTXE
);
1366 musb_writew(mbase
, MUSB_INTRTXE
, int_txe
& ~(1 << epnum
));
1368 if (musb_ep
->is_in
) {
1369 csr
= musb_readw(epio
, MUSB_TXCSR
);
1370 if (csr
& MUSB_TXCSR_FIFONOTEMPTY
) {
1371 csr
|= MUSB_TXCSR_FLUSHFIFO
| MUSB_TXCSR_P_WZC_BITS
;
1372 musb_writew(epio
, MUSB_TXCSR
, csr
);
1373 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1374 musb_writew(epio
, MUSB_TXCSR
, csr
);
1377 csr
= musb_readw(epio
, MUSB_RXCSR
);
1378 csr
|= MUSB_RXCSR_FLUSHFIFO
| MUSB_RXCSR_P_WZC_BITS
;
1379 musb_writew(epio
, MUSB_RXCSR
, csr
);
1380 musb_writew(epio
, MUSB_RXCSR
, csr
);
1383 /* re-enable interrupt */
1384 musb_writew(mbase
, MUSB_INTRTXE
, int_txe
);
1385 spin_unlock_irqrestore(&musb
->lock
, flags
);
1388 static const struct usb_ep_ops musb_ep_ops
= {
1389 .enable
= musb_gadget_enable
,
1390 .disable
= musb_gadget_disable
,
1391 .alloc_request
= musb_alloc_request
,
1392 .free_request
= musb_free_request
,
1393 .queue
= musb_gadget_queue
,
1394 .dequeue
= musb_gadget_dequeue
,
1395 .set_halt
= musb_gadget_set_halt
,
1396 .set_wedge
= musb_gadget_set_wedge
,
1397 .fifo_status
= musb_gadget_fifo_status
,
1398 .fifo_flush
= musb_gadget_fifo_flush
1401 /* ----------------------------------------------------------------------- */
1403 static int musb_gadget_get_frame(struct usb_gadget
*gadget
)
1405 struct musb
*musb
= gadget_to_musb(gadget
);
1407 return (int)musb_readw(musb
->mregs
, MUSB_FRAME
);
1410 static int musb_gadget_wakeup(struct usb_gadget
*gadget
)
1412 struct musb
*musb
= gadget_to_musb(gadget
);
1413 void __iomem
*mregs
= musb
->mregs
;
1414 unsigned long flags
;
1415 int status
= -EINVAL
;
1419 spin_lock_irqsave(&musb
->lock
, flags
);
1421 switch (musb
->xceiv
->state
) {
1422 case OTG_STATE_B_PERIPHERAL
:
1423 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1424 * that's part of the standard usb 1.1 state machine, and
1425 * doesn't affect OTG transitions.
1427 if (musb
->may_wakeup
&& musb
->is_suspended
)
1430 case OTG_STATE_B_IDLE
:
1431 /* Start SRP ... OTG not required. */
1432 devctl
= musb_readb(mregs
, MUSB_DEVCTL
);
1433 DBG(2, "Sending SRP: devctl: %02x\n", devctl
);
1434 devctl
|= MUSB_DEVCTL_SESSION
;
1435 musb_writeb(mregs
, MUSB_DEVCTL
, devctl
);
1436 devctl
= musb_readb(mregs
, MUSB_DEVCTL
);
1438 while (!(devctl
& MUSB_DEVCTL_SESSION
)) {
1439 devctl
= musb_readb(mregs
, MUSB_DEVCTL
);
1444 while (devctl
& MUSB_DEVCTL_SESSION
) {
1445 devctl
= musb_readb(mregs
, MUSB_DEVCTL
);
1450 /* Block idling for at least 1s */
1451 musb_platform_try_idle(musb
,
1452 jiffies
+ msecs_to_jiffies(1 * HZ
));
1457 DBG(2, "Unhandled wake: %s\n", otg_state_string(musb
));
1463 power
= musb_readb(mregs
, MUSB_POWER
);
1464 power
|= MUSB_POWER_RESUME
;
1465 musb_writeb(mregs
, MUSB_POWER
, power
);
1466 DBG(2, "issue wakeup\n");
1468 /* FIXME do this next chunk in a timer callback, no udelay */
1471 power
= musb_readb(mregs
, MUSB_POWER
);
1472 power
&= ~MUSB_POWER_RESUME
;
1473 musb_writeb(mregs
, MUSB_POWER
, power
);
1475 spin_unlock_irqrestore(&musb
->lock
, flags
);
1480 musb_gadget_set_self_powered(struct usb_gadget
*gadget
, int is_selfpowered
)
1482 struct musb
*musb
= gadget_to_musb(gadget
);
1484 musb
->is_self_powered
= !!is_selfpowered
;
1488 static void musb_pullup(struct musb
*musb
, int is_on
)
1492 power
= musb_readb(musb
->mregs
, MUSB_POWER
);
1494 power
|= MUSB_POWER_SOFTCONN
;
1496 power
&= ~MUSB_POWER_SOFTCONN
;
1498 /* FIXME if on, HdrcStart; if off, HdrcStop */
1500 DBG(3, "gadget %s D+ pullup %s\n",
1501 musb
->gadget_driver
->function
, is_on
? "on" : "off");
1502 musb_writeb(musb
->mregs
, MUSB_POWER
, power
);
1506 static int musb_gadget_vbus_session(struct usb_gadget
*gadget
, int is_active
)
1508 DBG(2, "<= %s =>\n", __func__
);
1511 * FIXME iff driver's softconnect flag is set (as it is during probe,
1512 * though that can clear it), just musb_pullup().
1519 static int musb_gadget_vbus_draw(struct usb_gadget
*gadget
, unsigned mA
)
1521 struct musb
*musb
= gadget_to_musb(gadget
);
1523 if (!musb
->xceiv
->set_power
)
1525 return otg_set_power(musb
->xceiv
, mA
);
1528 static int musb_gadget_pullup(struct usb_gadget
*gadget
, int is_on
)
1530 struct musb
*musb
= gadget_to_musb(gadget
);
1531 unsigned long flags
;
1535 /* NOTE: this assumes we are sensing vbus; we'd rather
1536 * not pullup unless the B-session is active.
1538 spin_lock_irqsave(&musb
->lock
, flags
);
1539 if (is_on
!= musb
->softconnect
) {
1540 musb
->softconnect
= is_on
;
1541 musb_pullup(musb
, is_on
);
1543 spin_unlock_irqrestore(&musb
->lock
, flags
);
1547 static const struct usb_gadget_ops musb_gadget_operations
= {
1548 .get_frame
= musb_gadget_get_frame
,
1549 .wakeup
= musb_gadget_wakeup
,
1550 .set_selfpowered
= musb_gadget_set_self_powered
,
1551 /* .vbus_session = musb_gadget_vbus_session, */
1552 .vbus_draw
= musb_gadget_vbus_draw
,
1553 .pullup
= musb_gadget_pullup
,
1556 /* ----------------------------------------------------------------------- */
1560 /* Only this registration code "knows" the rule (from USB standards)
1561 * about there being only one external upstream port. It assumes
1562 * all peripheral ports are external...
1564 static struct musb
*the_gadget
;
1566 static void musb_gadget_release(struct device
*dev
)
1568 /* kref_put(WHAT) */
1569 dev_dbg(dev
, "%s\n", __func__
);
1574 init_peripheral_ep(struct musb
*musb
, struct musb_ep
*ep
, u8 epnum
, int is_in
)
1576 struct musb_hw_ep
*hw_ep
= musb
->endpoints
+ epnum
;
1578 memset(ep
, 0, sizeof *ep
);
1580 ep
->current_epnum
= epnum
;
1585 INIT_LIST_HEAD(&ep
->req_list
);
1587 sprintf(ep
->name
, "ep%d%s", epnum
,
1588 (!epnum
|| hw_ep
->is_shared_fifo
) ? "" : (
1589 is_in
? "in" : "out"));
1590 ep
->end_point
.name
= ep
->name
;
1591 INIT_LIST_HEAD(&ep
->end_point
.ep_list
);
1593 ep
->end_point
.maxpacket
= 64;
1594 ep
->end_point
.ops
= &musb_g_ep0_ops
;
1595 musb
->g
.ep0
= &ep
->end_point
;
1598 ep
->end_point
.maxpacket
= hw_ep
->max_packet_sz_tx
;
1600 ep
->end_point
.maxpacket
= hw_ep
->max_packet_sz_rx
;
1601 ep
->end_point
.ops
= &musb_ep_ops
;
1602 list_add_tail(&ep
->end_point
.ep_list
, &musb
->g
.ep_list
);
1607 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1608 * to the rest of the driver state.
1610 static inline void __init
musb_g_init_endpoints(struct musb
*musb
)
1613 struct musb_hw_ep
*hw_ep
;
1616 /* intialize endpoint list just once */
1617 INIT_LIST_HEAD(&(musb
->g
.ep_list
));
1619 for (epnum
= 0, hw_ep
= musb
->endpoints
;
1620 epnum
< musb
->nr_endpoints
;
1622 if (hw_ep
->is_shared_fifo
/* || !epnum */) {
1623 init_peripheral_ep(musb
, &hw_ep
->ep_in
, epnum
, 0);
1626 if (hw_ep
->max_packet_sz_tx
) {
1627 init_peripheral_ep(musb
, &hw_ep
->ep_in
,
1631 if (hw_ep
->max_packet_sz_rx
) {
1632 init_peripheral_ep(musb
, &hw_ep
->ep_out
,
1640 /* called once during driver setup to initialize and link into
1641 * the driver model; memory is zeroed.
1643 int __init
musb_gadget_setup(struct musb
*musb
)
1647 /* REVISIT minor race: if (erroneously) setting up two
1648 * musb peripherals at the same time, only the bus lock
1655 musb
->g
.ops
= &musb_gadget_operations
;
1656 musb
->g
.is_dualspeed
= 1;
1657 musb
->g
.speed
= USB_SPEED_UNKNOWN
;
1659 /* this "gadget" abstracts/virtualizes the controller */
1660 dev_set_name(&musb
->g
.dev
, "gadget");
1661 musb
->g
.dev
.parent
= musb
->controller
;
1662 musb
->g
.dev
.dma_mask
= musb
->controller
->dma_mask
;
1663 musb
->g
.dev
.release
= musb_gadget_release
;
1664 musb
->g
.name
= musb_driver_name
;
1666 if (is_otg_enabled(musb
))
1669 musb_g_init_endpoints(musb
);
1671 musb
->is_active
= 0;
1672 musb_platform_try_idle(musb
, 0);
1674 status
= device_register(&musb
->g
.dev
);
1680 void musb_gadget_cleanup(struct musb
*musb
)
1682 if (musb
!= the_gadget
)
1685 device_unregister(&musb
->g
.dev
);
1690 * Register the gadget driver. Used by gadget drivers when
1691 * registering themselves with the controller.
1693 * -EINVAL something went wrong (not driver)
1694 * -EBUSY another gadget is already using the controller
1695 * -ENOMEM no memeory to perform the operation
1697 * @param driver the gadget driver
1698 * @return <0 if error, 0 if everything is fine
1700 int usb_gadget_register_driver(struct usb_gadget_driver
*driver
)
1703 unsigned long flags
;
1704 struct musb
*musb
= the_gadget
;
1707 || driver
->speed
!= USB_SPEED_HIGH
1712 /* driver must be initialized to support peripheral mode */
1714 DBG(1, "%s, no dev??\n", __func__
);
1718 DBG(3, "registering driver %s\n", driver
->function
);
1719 spin_lock_irqsave(&musb
->lock
, flags
);
1721 if (musb
->gadget_driver
) {
1722 DBG(1, "%s is already bound to %s\n",
1724 musb
->gadget_driver
->driver
.name
);
1727 musb
->gadget_driver
= driver
;
1728 musb
->g
.dev
.driver
= &driver
->driver
;
1729 driver
->driver
.bus
= NULL
;
1730 musb
->softconnect
= 1;
1734 spin_unlock_irqrestore(&musb
->lock
, flags
);
1737 retval
= driver
->bind(&musb
->g
);
1739 DBG(3, "bind to driver %s failed --> %d\n",
1740 driver
->driver
.name
, retval
);
1741 musb
->gadget_driver
= NULL
;
1742 musb
->g
.dev
.driver
= NULL
;
1745 spin_lock_irqsave(&musb
->lock
, flags
);
1747 otg_set_peripheral(musb
->xceiv
, &musb
->g
);
1748 musb
->xceiv
->state
= OTG_STATE_B_IDLE
;
1749 musb
->is_active
= 1;
1751 /* FIXME this ignores the softconnect flag. Drivers are
1752 * allowed hold the peripheral inactive until for example
1753 * userspace hooks up printer hardware or DSP codecs, so
1754 * hosts only see fully functional devices.
1757 if (!is_otg_enabled(musb
))
1760 otg_set_peripheral(musb
->xceiv
, &musb
->g
);
1762 spin_unlock_irqrestore(&musb
->lock
, flags
);
1764 if (is_otg_enabled(musb
)) {
1765 DBG(3, "OTG startup...\n");
1767 /* REVISIT: funcall to other code, which also
1768 * handles power budgeting ... this way also
1769 * ensures HdrcStart is indirectly called.
1771 retval
= usb_add_hcd(musb_to_hcd(musb
), -1, 0);
1773 DBG(1, "add_hcd failed, %d\n", retval
);
1774 spin_lock_irqsave(&musb
->lock
, flags
);
1775 otg_set_peripheral(musb
->xceiv
, NULL
);
1776 musb
->gadget_driver
= NULL
;
1777 musb
->g
.dev
.driver
= NULL
;
1778 spin_unlock_irqrestore(&musb
->lock
, flags
);
1785 EXPORT_SYMBOL(usb_gadget_register_driver
);
1787 static void stop_activity(struct musb
*musb
, struct usb_gadget_driver
*driver
)
1790 struct musb_hw_ep
*hw_ep
;
1792 /* don't disconnect if it's not connected */
1793 if (musb
->g
.speed
== USB_SPEED_UNKNOWN
)
1796 musb
->g
.speed
= USB_SPEED_UNKNOWN
;
1798 /* deactivate the hardware */
1799 if (musb
->softconnect
) {
1800 musb
->softconnect
= 0;
1801 musb_pullup(musb
, 0);
1805 /* killing any outstanding requests will quiesce the driver;
1806 * then report disconnect
1809 for (i
= 0, hw_ep
= musb
->endpoints
;
1810 i
< musb
->nr_endpoints
;
1812 musb_ep_select(musb
->mregs
, i
);
1813 if (hw_ep
->is_shared_fifo
/* || !epnum */) {
1814 nuke(&hw_ep
->ep_in
, -ESHUTDOWN
);
1816 if (hw_ep
->max_packet_sz_tx
)
1817 nuke(&hw_ep
->ep_in
, -ESHUTDOWN
);
1818 if (hw_ep
->max_packet_sz_rx
)
1819 nuke(&hw_ep
->ep_out
, -ESHUTDOWN
);
1823 spin_unlock(&musb
->lock
);
1824 driver
->disconnect(&musb
->g
);
1825 spin_lock(&musb
->lock
);
1830 * Unregister the gadget driver. Used by gadget drivers when
1831 * unregistering themselves from the controller.
1833 * @param driver the gadget driver to unregister
1835 int usb_gadget_unregister_driver(struct usb_gadget_driver
*driver
)
1837 unsigned long flags
;
1839 struct musb
*musb
= the_gadget
;
1841 if (!driver
|| !driver
->unbind
|| !musb
)
1844 /* REVISIT always use otg_set_peripheral() here too;
1845 * this needs to shut down the OTG engine.
1848 spin_lock_irqsave(&musb
->lock
, flags
);
1850 #ifdef CONFIG_USB_MUSB_OTG
1851 musb_hnp_stop(musb
);
1854 if (musb
->gadget_driver
== driver
) {
1856 (void) musb_gadget_vbus_draw(&musb
->g
, 0);
1858 musb
->xceiv
->state
= OTG_STATE_UNDEFINED
;
1859 stop_activity(musb
, driver
);
1860 otg_set_peripheral(musb
->xceiv
, NULL
);
1862 DBG(3, "unregistering driver %s\n", driver
->function
);
1863 spin_unlock_irqrestore(&musb
->lock
, flags
);
1864 driver
->unbind(&musb
->g
);
1865 spin_lock_irqsave(&musb
->lock
, flags
);
1867 musb
->gadget_driver
= NULL
;
1868 musb
->g
.dev
.driver
= NULL
;
1870 musb
->is_active
= 0;
1871 musb_platform_try_idle(musb
, 0);
1874 spin_unlock_irqrestore(&musb
->lock
, flags
);
1876 if (is_otg_enabled(musb
) && retval
== 0) {
1877 usb_remove_hcd(musb_to_hcd(musb
));
1878 /* FIXME we need to be able to register another
1879 * gadget driver here and have everything work;
1880 * that currently misbehaves.
1886 EXPORT_SYMBOL(usb_gadget_unregister_driver
);
1889 /* ----------------------------------------------------------------------- */
1891 /* lifecycle operations called through plat_uds.c */
1893 void musb_g_resume(struct musb
*musb
)
1895 musb
->is_suspended
= 0;
1896 switch (musb
->xceiv
->state
) {
1897 case OTG_STATE_B_IDLE
:
1899 case OTG_STATE_B_WAIT_ACON
:
1900 case OTG_STATE_B_PERIPHERAL
:
1901 musb
->is_active
= 1;
1902 if (musb
->gadget_driver
&& musb
->gadget_driver
->resume
) {
1903 spin_unlock(&musb
->lock
);
1904 musb
->gadget_driver
->resume(&musb
->g
);
1905 spin_lock(&musb
->lock
);
1909 WARNING("unhandled RESUME transition (%s)\n",
1910 otg_state_string(musb
));
1914 /* called when SOF packets stop for 3+ msec */
1915 void musb_g_suspend(struct musb
*musb
)
1919 devctl
= musb_readb(musb
->mregs
, MUSB_DEVCTL
);
1920 DBG(3, "devctl %02x\n", devctl
);
1922 switch (musb
->xceiv
->state
) {
1923 case OTG_STATE_B_IDLE
:
1924 if ((devctl
& MUSB_DEVCTL_VBUS
) == MUSB_DEVCTL_VBUS
)
1925 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
1927 case OTG_STATE_B_PERIPHERAL
:
1928 musb
->is_suspended
= 1;
1929 if (musb
->gadget_driver
&& musb
->gadget_driver
->suspend
) {
1930 spin_unlock(&musb
->lock
);
1931 musb
->gadget_driver
->suspend(&musb
->g
);
1932 spin_lock(&musb
->lock
);
1936 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
1937 * A_PERIPHERAL may need care too
1939 WARNING("unhandled SUSPEND transition (%s)\n",
1940 otg_state_string(musb
));
1944 /* Called during SRP */
1945 void musb_g_wakeup(struct musb
*musb
)
1947 musb_gadget_wakeup(&musb
->g
);
1950 /* called when VBUS drops below session threshold, and in other cases */
1951 void musb_g_disconnect(struct musb
*musb
)
1953 void __iomem
*mregs
= musb
->mregs
;
1954 u8 devctl
= musb_readb(mregs
, MUSB_DEVCTL
);
1956 DBG(3, "devctl %02x\n", devctl
);
1959 musb_writeb(mregs
, MUSB_DEVCTL
, devctl
& MUSB_DEVCTL_SESSION
);
1961 /* don't draw vbus until new b-default session */
1962 (void) musb_gadget_vbus_draw(&musb
->g
, 0);
1964 musb
->g
.speed
= USB_SPEED_UNKNOWN
;
1965 if (musb
->gadget_driver
&& musb
->gadget_driver
->disconnect
) {
1966 spin_unlock(&musb
->lock
);
1967 musb
->gadget_driver
->disconnect(&musb
->g
);
1968 spin_lock(&musb
->lock
);
1971 switch (musb
->xceiv
->state
) {
1973 #ifdef CONFIG_USB_MUSB_OTG
1974 DBG(2, "Unhandled disconnect %s, setting a_idle\n",
1975 otg_state_string(musb
));
1976 musb
->xceiv
->state
= OTG_STATE_A_IDLE
;
1977 MUSB_HST_MODE(musb
);
1979 case OTG_STATE_A_PERIPHERAL
:
1980 musb
->xceiv
->state
= OTG_STATE_A_WAIT_BCON
;
1981 MUSB_HST_MODE(musb
);
1983 case OTG_STATE_B_WAIT_ACON
:
1984 case OTG_STATE_B_HOST
:
1986 case OTG_STATE_B_PERIPHERAL
:
1987 case OTG_STATE_B_IDLE
:
1988 musb
->xceiv
->state
= OTG_STATE_B_IDLE
;
1990 case OTG_STATE_B_SRP_INIT
:
1994 musb
->is_active
= 0;
1997 void musb_g_reset(struct musb
*musb
)
1998 __releases(musb
->lock
)
1999 __acquires(musb
->lock
)
2001 void __iomem
*mbase
= musb
->mregs
;
2002 u8 devctl
= musb_readb(mbase
, MUSB_DEVCTL
);
2005 DBG(3, "<== %s addr=%x driver '%s'\n",
2006 (devctl
& MUSB_DEVCTL_BDEVICE
)
2007 ? "B-Device" : "A-Device",
2008 musb_readb(mbase
, MUSB_FADDR
),
2010 ? musb
->gadget_driver
->driver
.name
2014 /* report disconnect, if we didn't already (flushing EP state) */
2015 if (musb
->g
.speed
!= USB_SPEED_UNKNOWN
)
2016 musb_g_disconnect(musb
);
2019 else if (devctl
& MUSB_DEVCTL_HR
)
2020 musb_writeb(mbase
, MUSB_DEVCTL
, MUSB_DEVCTL_SESSION
);
2023 /* what speed did we negotiate? */
2024 power
= musb_readb(mbase
, MUSB_POWER
);
2025 musb
->g
.speed
= (power
& MUSB_POWER_HSMODE
)
2026 ? USB_SPEED_HIGH
: USB_SPEED_FULL
;
2028 /* start in USB_STATE_DEFAULT */
2029 musb
->is_active
= 1;
2030 musb
->is_suspended
= 0;
2031 MUSB_DEV_MODE(musb
);
2033 musb
->ep0_state
= MUSB_EP0_STAGE_SETUP
;
2035 musb
->may_wakeup
= 0;
2036 musb
->g
.b_hnp_enable
= 0;
2037 musb
->g
.a_alt_hnp_support
= 0;
2038 musb
->g
.a_hnp_support
= 0;
2040 /* Normal reset, as B-Device;
2041 * or else after HNP, as A-Device
2043 if (devctl
& MUSB_DEVCTL_BDEVICE
) {
2044 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
2045 musb
->g
.is_a_peripheral
= 0;
2046 } else if (is_otg_enabled(musb
)) {
2047 musb
->xceiv
->state
= OTG_STATE_A_PERIPHERAL
;
2048 musb
->g
.is_a_peripheral
= 1;
2052 /* start with default limits on VBUS power draw */
2053 (void) musb_gadget_vbus_draw(&musb
->g
,
2054 is_otg_enabled(musb
) ? 8 : 100);