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ath9k: Nuke unneccesary helper function to see if aggr is active
[linux-2.6.git] / drivers / net / wireless / ath / ath9k / xmit.c
blobaca3526b6c699c9f37cde9cc48256265c9472918
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "ath9k.h"
18
19 #define BITS_PER_BYTE 8
20 #define OFDM_PLCP_BITS 22
21 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
22 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
23 #define L_STF 8
24 #define L_LTF 8
25 #define L_SIG 4
26 #define HT_SIG 8
27 #define HT_STF 4
28 #define HT_LTF(_ns) (4 * (_ns))
29 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
30 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
31 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
32 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
33
34 #define OFDM_SIFS_TIME 16
35
36 static u32 bits_per_symbol[][2] = {
37 /* 20MHz 40MHz */
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
46 { 52, 108 }, /* 8: BPSK */
47 { 104, 216 }, /* 9: QPSK 1/2 */
48 { 156, 324 }, /* 10: QPSK 3/4 */
49 { 208, 432 }, /* 11: 16-QAM 1/2 */
50 { 312, 648 }, /* 12: 16-QAM 3/4 */
51 { 416, 864 }, /* 13: 64-QAM 2/3 */
52 { 468, 972 }, /* 14: 64-QAM 3/4 */
53 { 520, 1080 }, /* 15: 64-QAM 5/6 */
54 };
55
56 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
57
58 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
59 struct ath_atx_tid *tid,
60 struct list_head *bf_head);
61 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
62 struct list_head *bf_q,
63 int txok, int sendbar);
64 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
65 struct list_head *head);
66 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf);
67 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
68 int txok);
69 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
70 int nbad, int txok, bool update_rc);
71
72 /*********************/
73 /* Aggregation logic */
74 /*********************/
75
76 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
77 {
78 struct ath_atx_ac *ac = tid->ac;
79
80 if (tid->paused)
81 return;
82
83 if (tid->sched)
84 return;
85
86 tid->sched = true;
87 list_add_tail(&tid->list, &ac->tid_q);
88
89 if (ac->sched)
90 return;
91
92 ac->sched = true;
93 list_add_tail(&ac->list, &txq->axq_acq);
94 }
95
96 static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
97 {
98 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
99
100 spin_lock_bh(&txq->axq_lock);
101 tid->paused++;
102 spin_unlock_bh(&txq->axq_lock);
103 }
104
105 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
106 {
107 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
108
109 ASSERT(tid->paused > 0);
110 spin_lock_bh(&txq->axq_lock);
111
112 tid->paused--;
113
114 if (tid->paused > 0)
115 goto unlock;
116
117 if (list_empty(&tid->buf_q))
118 goto unlock;
119
120 ath_tx_queue_tid(txq, tid);
121 ath_txq_schedule(sc, txq);
122 unlock:
123 spin_unlock_bh(&txq->axq_lock);
124 }
125
126 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
127 {
128 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
129 struct ath_buf *bf;
130 struct list_head bf_head;
131 INIT_LIST_HEAD(&bf_head);
132
133 ASSERT(tid->paused > 0);
134 spin_lock_bh(&txq->axq_lock);
135
136 tid->paused--;
137
138 if (tid->paused > 0) {
139 spin_unlock_bh(&txq->axq_lock);
140 return;
141 }
142
143 while (!list_empty(&tid->buf_q)) {
144 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
145 ASSERT(!bf_isretried(bf));
146 list_move_tail(&bf->list, &bf_head);
147 ath_tx_send_ht_normal(sc, txq, tid, &bf_head);
148 }
149
150 spin_unlock_bh(&txq->axq_lock);
151 }
152
153 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
154 int seqno)
155 {
156 int index, cindex;
157
158 index = ATH_BA_INDEX(tid->seq_start, seqno);
159 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
160
161 tid->tx_buf[cindex] = NULL;
162
163 while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) {
164 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
165 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
166 }
167 }
168
169 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
170 struct ath_buf *bf)
171 {
172 int index, cindex;
173
174 if (bf_isretried(bf))
175 return;
176
177 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
178 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
179
180 ASSERT(tid->tx_buf[cindex] == NULL);
181 tid->tx_buf[cindex] = bf;
182
183 if (index >= ((tid->baw_tail - tid->baw_head) &
184 (ATH_TID_MAX_BUFS - 1))) {
185 tid->baw_tail = cindex;
186 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
187 }
188 }
189
190 /*
191 * TODO: For frame(s) that are in the retry state, we will reuse the
192 * sequence number(s) without setting the retry bit. The
193 * alternative is to give up on these and BAR the receiver's window
194 * forward.
195 */
196 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
197 struct ath_atx_tid *tid)
198
199 {
200 struct ath_buf *bf;
201 struct list_head bf_head;
202 INIT_LIST_HEAD(&bf_head);
203
204 for (;;) {
205 if (list_empty(&tid->buf_q))
206 break;
207
208 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
209 list_move_tail(&bf->list, &bf_head);
210
211 if (bf_isretried(bf))
212 ath_tx_update_baw(sc, tid, bf->bf_seqno);
213
214 spin_unlock(&txq->axq_lock);
215 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
216 spin_lock(&txq->axq_lock);
217 }
218
219 tid->seq_next = tid->seq_start;
220 tid->baw_tail = tid->baw_head;
221 }
222
223 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf)
224 {
225 struct sk_buff *skb;
226 struct ieee80211_hdr *hdr;
227
228 bf->bf_state.bf_type |= BUF_RETRY;
229 bf->bf_retries++;
230
231 skb = bf->bf_mpdu;
232 hdr = (struct ieee80211_hdr *)skb->data;
233 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
234 }
235
236 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
237 {
238 struct ath_buf *tbf;
239
240 spin_lock_bh(&sc->tx.txbuflock);
241 ASSERT(!list_empty((&sc->tx.txbuf)));
242 tbf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
243 list_del(&tbf->list);
244 spin_unlock_bh(&sc->tx.txbuflock);
245
246 ATH_TXBUF_RESET(tbf);
247
248 tbf->bf_mpdu = bf->bf_mpdu;
249 tbf->bf_buf_addr = bf->bf_buf_addr;
250 *(tbf->bf_desc) = *(bf->bf_desc);
251 tbf->bf_state = bf->bf_state;
252 tbf->bf_dmacontext = bf->bf_dmacontext;
253
254 return tbf;
255 }
256
257 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
258 struct ath_buf *bf, struct list_head *bf_q,
259 int txok)
260 {
261 struct ath_node *an = NULL;
262 struct sk_buff *skb;
263 struct ieee80211_sta *sta;
264 struct ieee80211_hdr *hdr;
265 struct ath_atx_tid *tid = NULL;
266 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
267 struct ath_desc *ds = bf_last->bf_desc;
268 struct list_head bf_head, bf_pending;
269 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
270 u32 ba[WME_BA_BMP_SIZE >> 5];
271 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
272 bool rc_update = true;
273
274 skb = bf->bf_mpdu;
275 hdr = (struct ieee80211_hdr *)skb->data;
276
277 rcu_read_lock();
278
279 sta = ieee80211_find_sta(sc->hw, hdr->addr1);
280 if (!sta) {
281 rcu_read_unlock();
282 return;
283 }
284
285 an = (struct ath_node *)sta->drv_priv;
286 tid = ATH_AN_2_TID(an, bf->bf_tidno);
287
288 isaggr = bf_isaggr(bf);
289 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
290
291 if (isaggr && txok) {
292 if (ATH_DS_TX_BA(ds)) {
293 seq_st = ATH_DS_BA_SEQ(ds);
294 memcpy(ba, ATH_DS_BA_BITMAP(ds),
295 WME_BA_BMP_SIZE >> 3);
296 } else {
297 /*
298 * AR5416 can become deaf/mute when BA
299 * issue happens. Chip needs to be reset.
300 * But AP code may have sychronization issues
301 * when perform internal reset in this routine.
302 * Only enable reset in STA mode for now.
303 */
304 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
305 needreset = 1;
306 }
307 }
308
309 INIT_LIST_HEAD(&bf_pending);
310 INIT_LIST_HEAD(&bf_head);
311
312 nbad = ath_tx_num_badfrms(sc, bf, txok);
313 while (bf) {
314 txfail = txpending = 0;
315 bf_next = bf->bf_next;
316
317 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
318 /* transmit completion, subframe is
319 * acked by block ack */
320 acked_cnt++;
321 } else if (!isaggr && txok) {
322 /* transmit completion */
323 acked_cnt++;
324 } else {
325 if (!(tid->state & AGGR_CLEANUP) &&
326 ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) {
327 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
328 ath_tx_set_retry(sc, bf);
329 txpending = 1;
330 } else {
331 bf->bf_state.bf_type |= BUF_XRETRY;
332 txfail = 1;
333 sendbar = 1;
334 txfail_cnt++;
335 }
336 } else {
337 /*
338 * cleanup in progress, just fail
339 * the un-acked sub-frames
340 */
341 txfail = 1;
342 }
343 }
344
345 if (bf_next == NULL) {
346 /*
347 * Make sure the last desc is reclaimed if it
348 * not a holding desc.
349 */
350 if (!bf_last->bf_stale)
351 list_move_tail(&bf->list, &bf_head);
352 else
353 INIT_LIST_HEAD(&bf_head);
354 } else {
355 ASSERT(!list_empty(bf_q));
356 list_move_tail(&bf->list, &bf_head);
357 }
358
359 if (!txpending) {
360 /*
361 * complete the acked-ones/xretried ones; update
362 * block-ack window
363 */
364 spin_lock_bh(&txq->axq_lock);
365 ath_tx_update_baw(sc, tid, bf->bf_seqno);
366 spin_unlock_bh(&txq->axq_lock);
367
368 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
369 ath_tx_rc_status(bf, ds, nbad, txok, true);
370 rc_update = false;
371 } else {
372 ath_tx_rc_status(bf, ds, nbad, txok, false);
373 }
374
375 ath_tx_complete_buf(sc, bf, &bf_head, !txfail, sendbar);
376 } else {
377 /* retry the un-acked ones */
378 if (bf->bf_next == NULL && bf_last->bf_stale) {
379 struct ath_buf *tbf;
380
381 tbf = ath_clone_txbuf(sc, bf_last);
382 ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc);
383 list_add_tail(&tbf->list, &bf_head);
384 } else {
385 /*
386 * Clear descriptor status words for
387 * software retry
388 */
389 ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc);
390 }
391
392 /*
393 * Put this buffer to the temporary pending
394 * queue to retain ordering
395 */
396 list_splice_tail_init(&bf_head, &bf_pending);
397 }
398
399 bf = bf_next;
400 }
401
402 if (tid->state & AGGR_CLEANUP) {
403 if (tid->baw_head == tid->baw_tail) {
404 tid->state &= ~AGGR_ADDBA_COMPLETE;
405 tid->addba_exchangeattempts = 0;
406 tid->state &= ~AGGR_CLEANUP;
407
408 /* send buffered frames as singles */
409 ath_tx_flush_tid(sc, tid);
410 }
411 rcu_read_unlock();
412 return;
413 }
414
415 /* prepend un-acked frames to the beginning of the pending frame queue */
416 if (!list_empty(&bf_pending)) {
417 spin_lock_bh(&txq->axq_lock);
418 list_splice(&bf_pending, &tid->buf_q);
419 ath_tx_queue_tid(txq, tid);
420 spin_unlock_bh(&txq->axq_lock);
421 }
422
423 rcu_read_unlock();
424
425 if (needreset)
426 ath_reset(sc, false);
427 }
428
429 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
430 struct ath_atx_tid *tid)
431 {
432 const struct ath_rate_table *rate_table = sc->cur_rate_table;
433 struct sk_buff *skb;
434 struct ieee80211_tx_info *tx_info;
435 struct ieee80211_tx_rate *rates;
436 struct ath_tx_info_priv *tx_info_priv;
437 u32 max_4ms_framelen, frmlen;
438 u16 aggr_limit, legacy = 0, maxampdu;
439 int i;
440
441 skb = bf->bf_mpdu;
442 tx_info = IEEE80211_SKB_CB(skb);
443 rates = tx_info->control.rates;
444 tx_info_priv = (struct ath_tx_info_priv *)tx_info->rate_driver_data[0];
445
446 /*
447 * Find the lowest frame length among the rate series that will have a
448 * 4ms transmit duration.
449 * TODO - TXOP limit needs to be considered.
450 */
451 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
452
453 for (i = 0; i < 4; i++) {
454 if (rates[i].count) {
455 if (!WLAN_RC_PHY_HT(rate_table->info[rates[i].idx].phy)) {
456 legacy = 1;
457 break;
458 }
459
460 frmlen = rate_table->info[rates[i].idx].max_4ms_framelen;
461 max_4ms_framelen = min(max_4ms_framelen, frmlen);
462 }
463 }
464
465 /*
466 * limit aggregate size by the minimum rate if rate selected is
467 * not a probe rate, if rate selected is a probe rate then
468 * avoid aggregation of this packet.
469 */
470 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
471 return 0;
472
473 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_DEFAULT);
474
475 /*
476 * h/w can accept aggregates upto 16 bit lengths (65535).
477 * The IE, however can hold upto 65536, which shows up here
478 * as zero. Ignore 65536 since we are constrained by hw.
479 */
480 maxampdu = tid->an->maxampdu;
481 if (maxampdu)
482 aggr_limit = min(aggr_limit, maxampdu);
483
484 return aggr_limit;
485 }
486
487 /*
488 * Returns the number of delimiters to be added to
489 * meet the minimum required mpdudensity.
490 * caller should make sure that the rate is HT rate .
491 */
492 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
493 struct ath_buf *bf, u16 frmlen)
494 {
495 const struct ath_rate_table *rt = sc->cur_rate_table;
496 struct sk_buff *skb = bf->bf_mpdu;
497 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
498 u32 nsymbits, nsymbols, mpdudensity;
499 u16 minlen;
500 u8 rc, flags, rix;
501 int width, half_gi, ndelim, mindelim;
502
503 /* Select standard number of delimiters based on frame length alone */
504 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
505
506 /*
507 * If encryption enabled, hardware requires some more padding between
508 * subframes.
509 * TODO - this could be improved to be dependent on the rate.
510 * The hardware can keep up at lower rates, but not higher rates
511 */
512 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
513 ndelim += ATH_AGGR_ENCRYPTDELIM;
514
515 /*
516 * Convert desired mpdu density from microeconds to bytes based
517 * on highest rate in rate series (i.e. first rate) to determine
518 * required minimum length for subframe. Take into account
519 * whether high rate is 20 or 40Mhz and half or full GI.
520 */
521 mpdudensity = tid->an->mpdudensity;
522
523 /*
524 * If there is no mpdu density restriction, no further calculation
525 * is needed.
526 */
527 if (mpdudensity == 0)
528 return ndelim;
529
530 rix = tx_info->control.rates[0].idx;
531 flags = tx_info->control.rates[0].flags;
532 rc = rt->info[rix].ratecode;
533 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
534 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
535
536 if (half_gi)
537 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity);
538 else
539 nsymbols = NUM_SYMBOLS_PER_USEC(mpdudensity);
540
541 if (nsymbols == 0)
542 nsymbols = 1;
543
544 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
545 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
546
547 if (frmlen < minlen) {
548 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
549 ndelim = max(mindelim, ndelim);
550 }
551
552 return ndelim;
553 }
554
555 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
556 struct ath_atx_tid *tid,
557 struct list_head *bf_q)
558 {
559 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
560 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
561 int rl = 0, nframes = 0, ndelim, prev_al = 0;
562 u16 aggr_limit = 0, al = 0, bpad = 0,
563 al_delta, h_baw = tid->baw_size / 2;
564 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
565
566 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
567
568 do {
569 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
570
571 /* do not step over block-ack window */
572 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
573 status = ATH_AGGR_BAW_CLOSED;
574 break;
575 }
576
577 if (!rl) {
578 aggr_limit = ath_lookup_rate(sc, bf, tid);
579 rl = 1;
580 }
581
582 /* do not exceed aggregation limit */
583 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
584
585 if (nframes &&
586 (aggr_limit < (al + bpad + al_delta + prev_al))) {
587 status = ATH_AGGR_LIMITED;
588 break;
589 }
590
591 /* do not exceed subframe limit */
592 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
593 status = ATH_AGGR_LIMITED;
594 break;
595 }
596 nframes++;
597
598 /* add padding for previous frame to aggregation length */
599 al += bpad + al_delta;
600
601 /*
602 * Get the delimiters needed to meet the MPDU
603 * density for this node.
604 */
605 ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen);
606 bpad = PADBYTES(al_delta) + (ndelim << 2);
607
608 bf->bf_next = NULL;
609 bf->bf_desc->ds_link = 0;
610
611 /* link buffers of this frame to the aggregate */
612 ath_tx_addto_baw(sc, tid, bf);
613 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
614 list_move_tail(&bf->list, bf_q);
615 if (bf_prev) {
616 bf_prev->bf_next = bf;
617 bf_prev->bf_desc->ds_link = bf->bf_daddr;
618 }
619 bf_prev = bf;
620 } while (!list_empty(&tid->buf_q));
621
622 bf_first->bf_al = al;
623 bf_first->bf_nframes = nframes;
624
625 return status;
626 #undef PADBYTES
627 }
628
629 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
630 struct ath_atx_tid *tid)
631 {
632 struct ath_buf *bf;
633 enum ATH_AGGR_STATUS status;
634 struct list_head bf_q;
635
636 do {
637 if (list_empty(&tid->buf_q))
638 return;
639
640 INIT_LIST_HEAD(&bf_q);
641
642 status = ath_tx_form_aggr(sc, tid, &bf_q);
643
644 /*
645 * no frames picked up to be aggregated;
646 * block-ack window is not open.
647 */
648 if (list_empty(&bf_q))
649 break;
650
651 bf = list_first_entry(&bf_q, struct ath_buf, list);
652 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
653
654 /* if only one frame, send as non-aggregate */
655 if (bf->bf_nframes == 1) {
656 bf->bf_state.bf_type &= ~BUF_AGGR;
657 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
658 ath_buf_set_rate(sc, bf);
659 ath_tx_txqaddbuf(sc, txq, &bf_q);
660 continue;
661 }
662
663 /* setup first desc of aggregate */
664 bf->bf_state.bf_type |= BUF_AGGR;
665 ath_buf_set_rate(sc, bf);
666 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
667
668 /* anchor last desc of aggregate */
669 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
670
671 txq->axq_aggr_depth++;
672 ath_tx_txqaddbuf(sc, txq, &bf_q);
673
674 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
675 status != ATH_AGGR_BAW_CLOSED);
676 }
677
678 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
679 u16 tid, u16 *ssn)
680 {
681 struct ath_atx_tid *txtid;
682 struct ath_node *an;
683
684 an = (struct ath_node *)sta->drv_priv;
685
686 if (sc->sc_flags & SC_OP_TXAGGR) {
687 txtid = ATH_AN_2_TID(an, tid);
688 txtid->state |= AGGR_ADDBA_PROGRESS;
689 ath_tx_pause_tid(sc, txtid);
690 *ssn = txtid->seq_start;
691 }
692
693 return 0;
694 }
695
696 int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
697 {
698 struct ath_node *an = (struct ath_node *)sta->drv_priv;
699 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
700 struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum];
701 struct ath_buf *bf;
702 struct list_head bf_head;
703 INIT_LIST_HEAD(&bf_head);
704
705 if (txtid->state & AGGR_CLEANUP)
706 return 0;
707
708 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
709 txtid->state &= ~AGGR_ADDBA_PROGRESS;
710 txtid->addba_exchangeattempts = 0;
711 return 0;
712 }
713
714 ath_tx_pause_tid(sc, txtid);
715
716 /* drop all software retried frames and mark this TID */
717 spin_lock_bh(&txq->axq_lock);
718 while (!list_empty(&txtid->buf_q)) {
719 bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
720 if (!bf_isretried(bf)) {
721 /*
722 * NB: it's based on the assumption that
723 * software retried frame will always stay
724 * at the head of software queue.
725 */
726 break;
727 }
728 list_move_tail(&bf->list, &bf_head);
729 ath_tx_update_baw(sc, txtid, bf->bf_seqno);
730 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
731 }
732 spin_unlock_bh(&txq->axq_lock);
733
734 if (txtid->baw_head != txtid->baw_tail) {
735 txtid->state |= AGGR_CLEANUP;
736 } else {
737 txtid->state &= ~AGGR_ADDBA_COMPLETE;
738 txtid->addba_exchangeattempts = 0;
739 ath_tx_flush_tid(sc, txtid);
740 }
741
742 return 0;
743 }
744
745 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
746 {
747 struct ath_atx_tid *txtid;
748 struct ath_node *an;
749
750 an = (struct ath_node *)sta->drv_priv;
751
752 if (sc->sc_flags & SC_OP_TXAGGR) {
753 txtid = ATH_AN_2_TID(an, tid);
754 txtid->baw_size =
755 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
756 txtid->state |= AGGR_ADDBA_COMPLETE;
757 txtid->state &= ~AGGR_ADDBA_PROGRESS;
758 ath_tx_resume_tid(sc, txtid);
759 }
760 }
761
762 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno)
763 {
764 struct ath_atx_tid *txtid;
765
766 if (!(sc->sc_flags & SC_OP_TXAGGR))
767 return false;
768
769 txtid = ATH_AN_2_TID(an, tidno);
770
771 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
772 if (!(txtid->state & AGGR_ADDBA_PROGRESS) &&
773 (txtid->addba_exchangeattempts < ADDBA_EXCHANGE_ATTEMPTS)) {
774 txtid->addba_exchangeattempts++;
775 return true;
776 }
777 }
778
779 return false;
780 }
781
782 /********************/
783 /* Queue Management */
784 /********************/
785
786 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
787 struct ath_txq *txq)
788 {
789 struct ath_atx_ac *ac, *ac_tmp;
790 struct ath_atx_tid *tid, *tid_tmp;
791
792 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
793 list_del(&ac->list);
794 ac->sched = false;
795 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
796 list_del(&tid->list);
797 tid->sched = false;
798 ath_tid_drain(sc, txq, tid);
799 }
800 }
801 }
802
803 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
804 {
805 struct ath_hw *ah = sc->sc_ah;
806 struct ath9k_tx_queue_info qi;
807 int qnum;
808
809 memset(&qi, 0, sizeof(qi));
810 qi.tqi_subtype = subtype;
811 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
812 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
813 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
814 qi.tqi_physCompBuf = 0;
815
816 /*
817 * Enable interrupts only for EOL and DESC conditions.
818 * We mark tx descriptors to receive a DESC interrupt
819 * when a tx queue gets deep; otherwise waiting for the
820 * EOL to reap descriptors. Note that this is done to
821 * reduce interrupt load and this only defers reaping
822 * descriptors, never transmitting frames. Aside from
823 * reducing interrupts this also permits more concurrency.
824 * The only potential downside is if the tx queue backs
825 * up in which case the top half of the kernel may backup
826 * due to a lack of tx descriptors.
827 *
828 * The UAPSD queue is an exception, since we take a desc-
829 * based intr on the EOSP frames.
830 */
831 if (qtype == ATH9K_TX_QUEUE_UAPSD)
832 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
833 else
834 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
835 TXQ_FLAG_TXDESCINT_ENABLE;
836 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
837 if (qnum == -1) {
838 /*
839 * NB: don't print a message, this happens
840 * normally on parts with too few tx queues
841 */
842 return NULL;
843 }
844 if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
845 DPRINTF(sc, ATH_DBG_FATAL,
846 "qnum %u out of range, max %u!\n",
847 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
848 ath9k_hw_releasetxqueue(ah, qnum);
849 return NULL;
850 }
851 if (!ATH_TXQ_SETUP(sc, qnum)) {
852 struct ath_txq *txq = &sc->tx.txq[qnum];
853
854 txq->axq_qnum = qnum;
855 txq->axq_link = NULL;
856 INIT_LIST_HEAD(&txq->axq_q);
857 INIT_LIST_HEAD(&txq->axq_acq);
858 spin_lock_init(&txq->axq_lock);
859 txq->axq_depth = 0;
860 txq->axq_aggr_depth = 0;
861 txq->axq_totalqueued = 0;
862 txq->axq_linkbuf = NULL;
863 sc->tx.txqsetup |= 1<<qnum;
864 }
865 return &sc->tx.txq[qnum];
866 }
867
868 static int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
869 {
870 int qnum;
871
872 switch (qtype) {
873 case ATH9K_TX_QUEUE_DATA:
874 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
875 DPRINTF(sc, ATH_DBG_FATAL,
876 "HAL AC %u out of range, max %zu!\n",
877 haltype, ARRAY_SIZE(sc->tx.hwq_map));
878 return -1;
879 }
880 qnum = sc->tx.hwq_map[haltype];
881 break;
882 case ATH9K_TX_QUEUE_BEACON:
883 qnum = sc->beacon.beaconq;
884 break;
885 case ATH9K_TX_QUEUE_CAB:
886 qnum = sc->beacon.cabq->axq_qnum;
887 break;
888 default:
889 qnum = -1;
890 }
891 return qnum;
892 }
893
894 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
895 {
896 struct ath_txq *txq = NULL;
897 int qnum;
898
899 qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
900 txq = &sc->tx.txq[qnum];
901
902 spin_lock_bh(&txq->axq_lock);
903
904 if (txq->axq_depth >= (ATH_TXBUF - 20)) {
905 DPRINTF(sc, ATH_DBG_XMIT,
906 "TX queue: %d is full, depth: %d\n",
907 qnum, txq->axq_depth);
908 ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb));
909 txq->stopped = 1;
910 spin_unlock_bh(&txq->axq_lock);
911 return NULL;
912 }
913
914 spin_unlock_bh(&txq->axq_lock);
915
916 return txq;
917 }
918
919 int ath_txq_update(struct ath_softc *sc, int qnum,
920 struct ath9k_tx_queue_info *qinfo)
921 {
922 struct ath_hw *ah = sc->sc_ah;
923 int error = 0;
924 struct ath9k_tx_queue_info qi;
925
926 if (qnum == sc->beacon.beaconq) {
927 /*
928 * XXX: for beacon queue, we just save the parameter.
929 * It will be picked up by ath_beaconq_config when
930 * it's necessary.
931 */
932 sc->beacon.beacon_qi = *qinfo;
933 return 0;
934 }
935
936 ASSERT(sc->tx.txq[qnum].axq_qnum == qnum);
937
938 ath9k_hw_get_txq_props(ah, qnum, &qi);
939 qi.tqi_aifs = qinfo->tqi_aifs;
940 qi.tqi_cwmin = qinfo->tqi_cwmin;
941 qi.tqi_cwmax = qinfo->tqi_cwmax;
942 qi.tqi_burstTime = qinfo->tqi_burstTime;
943 qi.tqi_readyTime = qinfo->tqi_readyTime;
944
945 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
946 DPRINTF(sc, ATH_DBG_FATAL,
947 "Unable to update hardware queue %u!\n", qnum);
948 error = -EIO;
949 } else {
950 ath9k_hw_resettxqueue(ah, qnum);
951 }
952
953 return error;
954 }
955
956 int ath_cabq_update(struct ath_softc *sc)
957 {
958 struct ath9k_tx_queue_info qi;
959 int qnum = sc->beacon.cabq->axq_qnum;
960
961 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
962 /*
963 * Ensure the readytime % is within the bounds.
964 */
965 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
966 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
967 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
968 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
969
970 qi.tqi_readyTime = (sc->beacon_interval *
971 sc->config.cabqReadytime) / 100;
972 ath_txq_update(sc, qnum, &qi);
973
974 return 0;
975 }
976
977 /*
978 * Drain a given TX queue (could be Beacon or Data)
979 *
980 * This assumes output has been stopped and
981 * we do not need to block ath_tx_tasklet.
982 */
983 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
984 {
985 struct ath_buf *bf, *lastbf;
986 struct list_head bf_head;
987
988 INIT_LIST_HEAD(&bf_head);
989
990 for (;;) {
991 spin_lock_bh(&txq->axq_lock);
992
993 if (list_empty(&txq->axq_q)) {
994 txq->axq_link = NULL;
995 txq->axq_linkbuf = NULL;
996 spin_unlock_bh(&txq->axq_lock);
997 break;
998 }
999
1000 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1001
1002 if (bf->bf_stale) {
1003 list_del(&bf->list);
1004 spin_unlock_bh(&txq->axq_lock);
1005
1006 spin_lock_bh(&sc->tx.txbuflock);
1007 list_add_tail(&bf->list, &sc->tx.txbuf);
1008 spin_unlock_bh(&sc->tx.txbuflock);
1009 continue;
1010 }
1011
1012 lastbf = bf->bf_lastbf;
1013 if (!retry_tx)
1014 lastbf->bf_desc->ds_txstat.ts_flags =
1015 ATH9K_TX_SW_ABORTED;
1016
1017 /* remove ath_buf's of the same mpdu from txq */
1018 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
1019 txq->axq_depth--;
1020
1021 spin_unlock_bh(&txq->axq_lock);
1022
1023 if (bf_isampdu(bf))
1024 ath_tx_complete_aggr(sc, txq, bf, &bf_head, 0);
1025 else
1026 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
1027 }
1028
1029 /* flush any pending frames if aggregation is enabled */
1030 if (sc->sc_flags & SC_OP_TXAGGR) {
1031 if (!retry_tx) {
1032 spin_lock_bh(&txq->axq_lock);
1033 ath_txq_drain_pending_buffers(sc, txq);
1034 spin_unlock_bh(&txq->axq_lock);
1035 }
1036 }
1037 }
1038
1039 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1040 {
1041 struct ath_hw *ah = sc->sc_ah;
1042 struct ath_txq *txq;
1043 int i, npend = 0;
1044
1045 if (sc->sc_flags & SC_OP_INVALID)
1046 return;
1047
1048 /* Stop beacon queue */
1049 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1050
1051 /* Stop data queues */
1052 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1053 if (ATH_TXQ_SETUP(sc, i)) {
1054 txq = &sc->tx.txq[i];
1055 ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1056 npend += ath9k_hw_numtxpending(ah, txq->axq_qnum);
1057 }
1058 }
1059
1060 if (npend) {
1061 int r;
1062
1063 DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n");
1064
1065 spin_lock_bh(&sc->sc_resetlock);
1066 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true);
1067 if (r)
1068 DPRINTF(sc, ATH_DBG_FATAL,
1069 "Unable to reset hardware; reset status %d\n",
1070 r);
1071 spin_unlock_bh(&sc->sc_resetlock);
1072 }
1073
1074 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1075 if (ATH_TXQ_SETUP(sc, i))
1076 ath_draintxq(sc, &sc->tx.txq[i], retry_tx);
1077 }
1078 }
1079
1080 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1081 {
1082 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1083 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1084 }
1085
1086 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1087 {
1088 struct ath_atx_ac *ac;
1089 struct ath_atx_tid *tid;
1090
1091 if (list_empty(&txq->axq_acq))
1092 return;
1093
1094 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1095 list_del(&ac->list);
1096 ac->sched = false;
1097
1098 do {
1099 if (list_empty(&ac->tid_q))
1100 return;
1101
1102 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
1103 list_del(&tid->list);
1104 tid->sched = false;
1105
1106 if (tid->paused)
1107 continue;
1108
1109 if ((txq->axq_depth % 2) == 0)
1110 ath_tx_sched_aggr(sc, txq, tid);
1111
1112 /*
1113 * add tid to round-robin queue if more frames
1114 * are pending for the tid
1115 */
1116 if (!list_empty(&tid->buf_q))
1117 ath_tx_queue_tid(txq, tid);
1118
1119 break;
1120 } while (!list_empty(&ac->tid_q));
1121
1122 if (!list_empty(&ac->tid_q)) {
1123 if (!ac->sched) {
1124 ac->sched = true;
1125 list_add_tail(&ac->list, &txq->axq_acq);
1126 }
1127 }
1128 }
1129
1130 int ath_tx_setup(struct ath_softc *sc, int haltype)
1131 {
1132 struct ath_txq *txq;
1133
1134 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
1135 DPRINTF(sc, ATH_DBG_FATAL,
1136 "HAL AC %u out of range, max %zu!\n",
1137 haltype, ARRAY_SIZE(sc->tx.hwq_map));
1138 return 0;
1139 }
1140 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
1141 if (txq != NULL) {
1142 sc->tx.hwq_map[haltype] = txq->axq_qnum;
1143 return 1;
1144 } else
1145 return 0;
1146 }
1147
1148 /***********/
1149 /* TX, DMA */
1150 /***********/
1151
1152 /*
1153 * Insert a chain of ath_buf (descriptors) on a txq and
1154 * assume the descriptors are already chained together by caller.
1155 */
1156 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1157 struct list_head *head)
1158 {
1159 struct ath_hw *ah = sc->sc_ah;
1160 struct ath_buf *bf;
1161
1162 /*
1163 * Insert the frame on the outbound list and
1164 * pass it on to the hardware.
1165 */
1166
1167 if (list_empty(head))
1168 return;
1169
1170 bf = list_first_entry(head, struct ath_buf, list);
1171
1172 list_splice_tail_init(head, &txq->axq_q);
1173 txq->axq_depth++;
1174 txq->axq_totalqueued++;
1175 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
1176
1177 DPRINTF(sc, ATH_DBG_QUEUE,
1178 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1179
1180 if (txq->axq_link == NULL) {
1181 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1182 DPRINTF(sc, ATH_DBG_XMIT,
1183 "TXDP[%u] = %llx (%p)\n",
1184 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1185 } else {
1186 *txq->axq_link = bf->bf_daddr;
1187 DPRINTF(sc, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
1188 txq->axq_qnum, txq->axq_link,
1189 ito64(bf->bf_daddr), bf->bf_desc);
1190 }
1191 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
1192 ath9k_hw_txstart(ah, txq->axq_qnum);
1193 }
1194
1195 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
1196 {
1197 struct ath_buf *bf = NULL;
1198
1199 spin_lock_bh(&sc->tx.txbuflock);
1200
1201 if (unlikely(list_empty(&sc->tx.txbuf))) {
1202 spin_unlock_bh(&sc->tx.txbuflock);
1203 return NULL;
1204 }
1205
1206 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
1207 list_del(&bf->list);
1208
1209 spin_unlock_bh(&sc->tx.txbuflock);
1210
1211 return bf;
1212 }
1213
1214 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1215 struct list_head *bf_head,
1216 struct ath_tx_control *txctl)
1217 {
1218 struct ath_buf *bf;
1219
1220 bf = list_first_entry(bf_head, struct ath_buf, list);
1221 bf->bf_state.bf_type |= BUF_AMPDU;
1222
1223 /*
1224 * Do not queue to h/w when any of the following conditions is true:
1225 * - there are pending frames in software queue
1226 * - the TID is currently paused for ADDBA/BAR request
1227 * - seqno is not within block-ack window
1228 * - h/w queue depth exceeds low water mark
1229 */
1230 if (!list_empty(&tid->buf_q) || tid->paused ||
1231 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
1232 txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1233 /*
1234 * Add this frame to software queue for scheduling later
1235 * for aggregation.
1236 */
1237 list_move_tail(&bf->list, &tid->buf_q);
1238 ath_tx_queue_tid(txctl->txq, tid);
1239 return;
1240 }
1241
1242 /* Add sub-frame to BAW */
1243 ath_tx_addto_baw(sc, tid, bf);
1244
1245 /* Queue to h/w without aggregation */
1246 bf->bf_nframes = 1;
1247 bf->bf_lastbf = bf;
1248 ath_buf_set_rate(sc, bf);
1249 ath_tx_txqaddbuf(sc, txctl->txq, bf_head);
1250 }
1251
1252 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
1253 struct ath_atx_tid *tid,
1254 struct list_head *bf_head)
1255 {
1256 struct ath_buf *bf;
1257
1258 bf = list_first_entry(bf_head, struct ath_buf, list);
1259 bf->bf_state.bf_type &= ~BUF_AMPDU;
1260
1261 /* update starting sequence number for subsequent ADDBA request */
1262 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1263
1264 bf->bf_nframes = 1;
1265 bf->bf_lastbf = bf;
1266 ath_buf_set_rate(sc, bf);
1267 ath_tx_txqaddbuf(sc, txq, bf_head);
1268 }
1269
1270 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1271 struct list_head *bf_head)
1272 {
1273 struct ath_buf *bf;
1274
1275 bf = list_first_entry(bf_head, struct ath_buf, list);
1276
1277 bf->bf_lastbf = bf;
1278 bf->bf_nframes = 1;
1279 ath_buf_set_rate(sc, bf);
1280 ath_tx_txqaddbuf(sc, txq, bf_head);
1281 }
1282
1283 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1284 {
1285 struct ieee80211_hdr *hdr;
1286 enum ath9k_pkt_type htype;
1287 __le16 fc;
1288
1289 hdr = (struct ieee80211_hdr *)skb->data;
1290 fc = hdr->frame_control;
1291
1292 if (ieee80211_is_beacon(fc))
1293 htype = ATH9K_PKT_TYPE_BEACON;
1294 else if (ieee80211_is_probe_resp(fc))
1295 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1296 else if (ieee80211_is_atim(fc))
1297 htype = ATH9K_PKT_TYPE_ATIM;
1298 else if (ieee80211_is_pspoll(fc))
1299 htype = ATH9K_PKT_TYPE_PSPOLL;
1300 else
1301 htype = ATH9K_PKT_TYPE_NORMAL;
1302
1303 return htype;
1304 }
1305
1306 static bool is_pae(struct sk_buff *skb)
1307 {
1308 struct ieee80211_hdr *hdr;
1309 __le16 fc;
1310
1311 hdr = (struct ieee80211_hdr *)skb->data;
1312 fc = hdr->frame_control;
1313
1314 if (ieee80211_is_data(fc)) {
1315 if (ieee80211_is_nullfunc(fc) ||
1316 /* Port Access Entity (IEEE 802.1X) */
1317 (skb->protocol == cpu_to_be16(ETH_P_PAE))) {
1318 return true;
1319 }
1320 }
1321
1322 return false;
1323 }
1324
1325 static int get_hw_crypto_keytype(struct sk_buff *skb)
1326 {
1327 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1328
1329 if (tx_info->control.hw_key) {
1330 if (tx_info->control.hw_key->alg == ALG_WEP)
1331 return ATH9K_KEY_TYPE_WEP;
1332 else if (tx_info->control.hw_key->alg == ALG_TKIP)
1333 return ATH9K_KEY_TYPE_TKIP;
1334 else if (tx_info->control.hw_key->alg == ALG_CCMP)
1335 return ATH9K_KEY_TYPE_AES;
1336 }
1337
1338 return ATH9K_KEY_TYPE_CLEAR;
1339 }
1340
1341 static void assign_aggr_tid_seqno(struct sk_buff *skb,
1342 struct ath_buf *bf)
1343 {
1344 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1345 struct ieee80211_hdr *hdr;
1346 struct ath_node *an;
1347 struct ath_atx_tid *tid;
1348 __le16 fc;
1349 u8 *qc;
1350
1351 if (!tx_info->control.sta)
1352 return;
1353
1354 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1355 hdr = (struct ieee80211_hdr *)skb->data;
1356 fc = hdr->frame_control;
1357
1358 if (ieee80211_is_data_qos(fc)) {
1359 qc = ieee80211_get_qos_ctl(hdr);
1360 bf->bf_tidno = qc[0] & 0xf;
1361 }
1362
1363 /*
1364 * For HT capable stations, we save tidno for later use.
1365 * We also override seqno set by upper layer with the one
1366 * in tx aggregation state.
1367 *
1368 * If fragmentation is on, the sequence number is
1369 * not overridden, since it has been
1370 * incremented by the fragmentation routine.
1371 *
1372 * FIXME: check if the fragmentation threshold exceeds
1373 * IEEE80211 max.
1374 */
1375 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1376 hdr->seq_ctrl = cpu_to_le16(tid->seq_next <<
1377 IEEE80211_SEQ_SEQ_SHIFT);
1378 bf->bf_seqno = tid->seq_next;
1379 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1380 }
1381
1382 static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb,
1383 struct ath_txq *txq)
1384 {
1385 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1386 int flags = 0;
1387
1388 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
1389 flags |= ATH9K_TXDESC_INTREQ;
1390
1391 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1392 flags |= ATH9K_TXDESC_NOACK;
1393
1394 return flags;
1395 }
1396
1397 /*
1398 * rix - rate index
1399 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1400 * width - 0 for 20 MHz, 1 for 40 MHz
1401 * half_gi - to use 4us v/s 3.6 us for symbol time
1402 */
1403 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
1404 int width, int half_gi, bool shortPreamble)
1405 {
1406 const struct ath_rate_table *rate_table = sc->cur_rate_table;
1407 u32 nbits, nsymbits, duration, nsymbols;
1408 u8 rc;
1409 int streams, pktlen;
1410
1411 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
1412 rc = rate_table->info[rix].ratecode;
1413
1414 /* for legacy rates, use old function to compute packet duration */
1415 if (!IS_HT_RATE(rc))
1416 return ath9k_hw_computetxtime(sc->sc_ah, rate_table, pktlen,
1417 rix, shortPreamble);
1418
1419 /* find number of symbols: PLCP + data */
1420 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1421 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
1422 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1423
1424 if (!half_gi)
1425 duration = SYMBOL_TIME(nsymbols);
1426 else
1427 duration = SYMBOL_TIME_HALFGI(nsymbols);
1428
1429 /* addup duration for legacy/ht training and signal fields */
1430 streams = HT_RC_2_STREAMS(rc);
1431 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1432
1433 return duration;
1434 }
1435
1436 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
1437 {
1438 const struct ath_rate_table *rt = sc->cur_rate_table;
1439 struct ath9k_11n_rate_series series[4];
1440 struct sk_buff *skb;
1441 struct ieee80211_tx_info *tx_info;
1442 struct ieee80211_tx_rate *rates;
1443 struct ieee80211_hdr *hdr;
1444 int i, flags = 0;
1445 u8 rix = 0, ctsrate = 0;
1446 bool is_pspoll;
1447
1448 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1449
1450 skb = bf->bf_mpdu;
1451 tx_info = IEEE80211_SKB_CB(skb);
1452 rates = tx_info->control.rates;
1453 hdr = (struct ieee80211_hdr *)skb->data;
1454 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1455
1456 /*
1457 * We check if Short Preamble is needed for the CTS rate by
1458 * checking the BSS's global flag.
1459 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1460 */
1461 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1462 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode |
1463 rt->info[tx_info->control.rts_cts_rate_idx].short_preamble;
1464 else
1465 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode;
1466
1467 /*
1468 * ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive.
1469 * Check the first rate in the series to decide whether RTS/CTS
1470 * or CTS-to-self has to be used.
1471 */
1472 if (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)
1473 flags = ATH9K_TXDESC_CTSENA;
1474 else if (rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
1475 flags = ATH9K_TXDESC_RTSENA;
1476
1477 /* FIXME: Handle aggregation protection */
1478 if (sc->config.ath_aggr_prot &&
1479 (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) {
1480 flags = ATH9K_TXDESC_RTSENA;
1481 }
1482
1483 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1484 if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit))
1485 flags &= ~(ATH9K_TXDESC_RTSENA);
1486
1487 for (i = 0; i < 4; i++) {
1488 if (!rates[i].count || (rates[i].idx < 0))
1489 continue;
1490
1491 rix = rates[i].idx;
1492 series[i].Tries = rates[i].count;
1493 series[i].ChSel = sc->tx_chainmask;
1494
1495 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1496 series[i].Rate = rt->info[rix].ratecode |
1497 rt->info[rix].short_preamble;
1498 else
1499 series[i].Rate = rt->info[rix].ratecode;
1500
1501 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)
1502 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1503 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1504 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1505 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1506 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1507
1508 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
1509 (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) != 0,
1510 (rates[i].flags & IEEE80211_TX_RC_SHORT_GI),
1511 (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE));
1512 }
1513
1514 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1515 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1516 bf->bf_lastbf->bf_desc,
1517 !is_pspoll, ctsrate,
1518 0, series, 4, flags);
1519
1520 if (sc->config.ath_aggr_prot && flags)
1521 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
1522 }
1523
1524 static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
1525 struct sk_buff *skb,
1526 struct ath_tx_control *txctl)
1527 {
1528 struct ath_wiphy *aphy = hw->priv;
1529 struct ath_softc *sc = aphy->sc;
1530 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1531 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1532 struct ath_tx_info_priv *tx_info_priv;
1533 int hdrlen;
1534 __le16 fc;
1535
1536 tx_info_priv = kzalloc(sizeof(*tx_info_priv), GFP_ATOMIC);
1537 if (unlikely(!tx_info_priv))
1538 return -ENOMEM;
1539 tx_info->rate_driver_data[0] = tx_info_priv;
1540 tx_info_priv->aphy = aphy;
1541 tx_info_priv->frame_type = txctl->frame_type;
1542 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1543 fc = hdr->frame_control;
1544
1545 ATH_TXBUF_RESET(bf);
1546
1547 bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3);
1548
1549 if (conf_is_ht(&sc->hw->conf) && !is_pae(skb))
1550 bf->bf_state.bf_type |= BUF_HT;
1551
1552 bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq);
1553
1554 bf->bf_keytype = get_hw_crypto_keytype(skb);
1555 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
1556 bf->bf_frmlen += tx_info->control.hw_key->icv_len;
1557 bf->bf_keyix = tx_info->control.hw_key->hw_key_idx;
1558 } else {
1559 bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
1560 }
1561
1562 if (ieee80211_is_data_qos(fc) && (sc->sc_flags & SC_OP_TXAGGR))
1563 assign_aggr_tid_seqno(skb, bf);
1564
1565 bf->bf_mpdu = skb;
1566
1567 bf->bf_dmacontext = dma_map_single(sc->dev, skb->data,
1568 skb->len, DMA_TO_DEVICE);
1569 if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) {
1570 bf->bf_mpdu = NULL;
1571 kfree(tx_info_priv);
1572 tx_info->rate_driver_data[0] = NULL;
1573 DPRINTF(sc, ATH_DBG_FATAL, "dma_mapping_error() on TX\n");
1574 return -ENOMEM;
1575 }
1576
1577 bf->bf_buf_addr = bf->bf_dmacontext;
1578 return 0;
1579 }
1580
1581 /* FIXME: tx power */
1582 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1583 struct ath_tx_control *txctl)
1584 {
1585 struct sk_buff *skb = bf->bf_mpdu;
1586 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1587 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1588 struct ath_node *an = NULL;
1589 struct list_head bf_head;
1590 struct ath_desc *ds;
1591 struct ath_atx_tid *tid;
1592 struct ath_hw *ah = sc->sc_ah;
1593 int frm_type;
1594 __le16 fc;
1595
1596 frm_type = get_hw_packet_type(skb);
1597 fc = hdr->frame_control;
1598
1599 INIT_LIST_HEAD(&bf_head);
1600 list_add_tail(&bf->list, &bf_head);
1601
1602 ds = bf->bf_desc;
1603 ds->ds_link = 0;
1604 ds->ds_data = bf->bf_buf_addr;
1605
1606 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
1607 bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
1608
1609 ath9k_hw_filltxdesc(ah, ds,
1610 skb->len, /* segment length */
1611 true, /* first segment */
1612 true, /* last segment */
1613 ds); /* first descriptor */
1614
1615 spin_lock_bh(&txctl->txq->axq_lock);
1616
1617 if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) &&
1618 tx_info->control.sta) {
1619 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1620 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1621
1622 if (!ieee80211_is_data_qos(fc)) {
1623 ath_tx_send_normal(sc, txctl->txq, &bf_head);
1624 goto tx_done;
1625 }
1626
1627 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
1628 /*
1629 * Try aggregation if it's a unicast data frame
1630 * and the destination is HT capable.
1631 */
1632 ath_tx_send_ampdu(sc, tid, &bf_head, txctl);
1633 } else {
1634 /*
1635 * Send this frame as regular when ADDBA
1636 * exchange is neither complete nor pending.
1637 */
1638 ath_tx_send_ht_normal(sc, txctl->txq,
1639 tid, &bf_head);
1640 }
1641 } else {
1642 ath_tx_send_normal(sc, txctl->txq, &bf_head);
1643 }
1644
1645 tx_done:
1646 spin_unlock_bh(&txctl->txq->axq_lock);
1647 }
1648
1649 /* Upon failure caller should free skb */
1650 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1651 struct ath_tx_control *txctl)
1652 {
1653 struct ath_wiphy *aphy = hw->priv;
1654 struct ath_softc *sc = aphy->sc;
1655 struct ath_buf *bf;
1656 int r;
1657
1658 bf = ath_tx_get_buffer(sc);
1659 if (!bf) {
1660 DPRINTF(sc, ATH_DBG_XMIT, "TX buffers are full\n");
1661 return -1;
1662 }
1663
1664 r = ath_tx_setup_buffer(hw, bf, skb, txctl);
1665 if (unlikely(r)) {
1666 struct ath_txq *txq = txctl->txq;
1667
1668 DPRINTF(sc, ATH_DBG_FATAL, "TX mem alloc failure\n");
1669
1670 /* upon ath_tx_processq() this TX queue will be resumed, we
1671 * guarantee this will happen by knowing beforehand that
1672 * we will at least have to run TX completionon one buffer
1673 * on the queue */
1674 spin_lock_bh(&txq->axq_lock);
1675 if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) {
1676 ieee80211_stop_queue(sc->hw,
1677 skb_get_queue_mapping(skb));
1678 txq->stopped = 1;
1679 }
1680 spin_unlock_bh(&txq->axq_lock);
1681
1682 spin_lock_bh(&sc->tx.txbuflock);
1683 list_add_tail(&bf->list, &sc->tx.txbuf);
1684 spin_unlock_bh(&sc->tx.txbuflock);
1685
1686 return r;
1687 }
1688
1689 ath_tx_start_dma(sc, bf, txctl);
1690
1691 return 0;
1692 }
1693
1694 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1695 {
1696 struct ath_wiphy *aphy = hw->priv;
1697 struct ath_softc *sc = aphy->sc;
1698 int hdrlen, padsize;
1699 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1700 struct ath_tx_control txctl;
1701
1702 memset(&txctl, 0, sizeof(struct ath_tx_control));
1703
1704 /*
1705 * As a temporary workaround, assign seq# here; this will likely need
1706 * to be cleaned up to work better with Beacon transmission and virtual
1707 * BSSes.
1708 */
1709 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1710 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1711 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1712 sc->tx.seq_no += 0x10;
1713 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1714 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1715 }
1716
1717 /* Add the padding after the header if this is not already done */
1718 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1719 if (hdrlen & 3) {
1720 padsize = hdrlen % 4;
1721 if (skb_headroom(skb) < padsize) {
1722 DPRINTF(sc, ATH_DBG_XMIT, "TX CABQ padding failed\n");
1723 dev_kfree_skb_any(skb);
1724 return;
1725 }
1726 skb_push(skb, padsize);
1727 memmove(skb->data, skb->data + padsize, hdrlen);
1728 }
1729
1730 txctl.txq = sc->beacon.cabq;
1731
1732 DPRINTF(sc, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb);
1733
1734 if (ath_tx_start(hw, skb, &txctl) != 0) {
1735 DPRINTF(sc, ATH_DBG_XMIT, "CABQ TX failed\n");
1736 goto exit;
1737 }
1738
1739 return;
1740 exit:
1741 dev_kfree_skb_any(skb);
1742 }
1743
1744 /*****************/
1745 /* TX Completion */
1746 /*****************/
1747
1748 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1749 int tx_flags)
1750 {
1751 struct ieee80211_hw *hw = sc->hw;
1752 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1753 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
1754 int hdrlen, padsize;
1755 int frame_type = ATH9K_NOT_INTERNAL;
1756
1757 DPRINTF(sc, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1758
1759 if (tx_info_priv) {
1760 hw = tx_info_priv->aphy->hw;
1761 frame_type = tx_info_priv->frame_type;
1762 }
1763
1764 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
1765 tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) {
1766 kfree(tx_info_priv);
1767 tx_info->rate_driver_data[0] = NULL;
1768 }
1769
1770 if (tx_flags & ATH_TX_BAR)
1771 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1772
1773 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1774 /* Frame was ACKed */
1775 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1776 }
1777
1778 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1779 padsize = hdrlen & 3;
1780 if (padsize && hdrlen >= 24) {
1781 /*
1782 * Remove MAC header padding before giving the frame back to
1783 * mac80211.
1784 */
1785 memmove(skb->data + padsize, skb->data, hdrlen);
1786 skb_pull(skb, padsize);
1787 }
1788
1789 if (sc->sc_flags & SC_OP_WAIT_FOR_TX_ACK) {
1790 sc->sc_flags &= ~SC_OP_WAIT_FOR_TX_ACK;
1791 DPRINTF(sc, ATH_DBG_PS, "Going back to sleep after having "
1792 "received TX status (0x%x)\n",
1793 sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
1794 SC_OP_WAIT_FOR_CAB |
1795 SC_OP_WAIT_FOR_PSPOLL_DATA |
1796 SC_OP_WAIT_FOR_TX_ACK));
1797 }
1798
1799 if (frame_type == ATH9K_NOT_INTERNAL)
1800 ieee80211_tx_status(hw, skb);
1801 else
1802 ath9k_tx_status(hw, skb);
1803 }
1804
1805 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1806 struct list_head *bf_q,
1807 int txok, int sendbar)
1808 {
1809 struct sk_buff *skb = bf->bf_mpdu;
1810 unsigned long flags;
1811 int tx_flags = 0;
1812
1813
1814 if (sendbar)
1815 tx_flags = ATH_TX_BAR;
1816
1817 if (!txok) {
1818 tx_flags |= ATH_TX_ERROR;
1819
1820 if (bf_isxretried(bf))
1821 tx_flags |= ATH_TX_XRETRY;
1822 }
1823
1824 dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE);
1825 ath_tx_complete(sc, skb, tx_flags);
1826
1827 /*
1828 * Return the list of ath_buf of this mpdu to free queue
1829 */
1830 spin_lock_irqsave(&sc->tx.txbuflock, flags);
1831 list_splice_tail_init(bf_q, &sc->tx.txbuf);
1832 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1833 }
1834
1835 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
1836 int txok)
1837 {
1838 struct ath_buf *bf_last = bf->bf_lastbf;
1839 struct ath_desc *ds = bf_last->bf_desc;
1840 u16 seq_st = 0;
1841 u32 ba[WME_BA_BMP_SIZE >> 5];
1842 int ba_index;
1843 int nbad = 0;
1844 int isaggr = 0;
1845
1846 if (ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED)
1847 return 0;
1848
1849 isaggr = bf_isaggr(bf);
1850 if (isaggr) {
1851 seq_st = ATH_DS_BA_SEQ(ds);
1852 memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3);
1853 }
1854
1855 while (bf) {
1856 ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
1857 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
1858 nbad++;
1859
1860 bf = bf->bf_next;
1861 }
1862
1863 return nbad;
1864 }
1865
1866 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
1867 int nbad, int txok, bool update_rc)
1868 {
1869 struct sk_buff *skb = bf->bf_mpdu;
1870 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1871 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1872 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
1873 struct ieee80211_hw *hw = tx_info_priv->aphy->hw;
1874 u8 i, tx_rateindex;
1875
1876 if (txok)
1877 tx_info->status.ack_signal = ds->ds_txstat.ts_rssi;
1878
1879 tx_rateindex = ds->ds_txstat.ts_rateindex;
1880 WARN_ON(tx_rateindex >= hw->max_rates);
1881
1882 tx_info_priv->update_rc = update_rc;
1883 if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
1884 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1885
1886 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
1887 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
1888 if (ieee80211_is_data(hdr->frame_control)) {
1889 memcpy(&tx_info_priv->tx, &ds->ds_txstat,
1890 sizeof(tx_info_priv->tx));
1891 tx_info_priv->n_frames = bf->bf_nframes;
1892 tx_info_priv->n_bad_frames = nbad;
1893 }
1894 }
1895
1896 for (i = tx_rateindex + 1; i < hw->max_rates; i++)
1897 tx_info->status.rates[i].count = 0;
1898
1899 tx_info->status.rates[tx_rateindex].count = bf->bf_retries + 1;
1900 }
1901
1902 static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
1903 {
1904 int qnum;
1905
1906 spin_lock_bh(&txq->axq_lock);
1907 if (txq->stopped &&
1908 sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) {
1909 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc);
1910 if (qnum != -1) {
1911 ieee80211_wake_queue(sc->hw, qnum);
1912 txq->stopped = 0;
1913 }
1914 }
1915 spin_unlock_bh(&txq->axq_lock);
1916 }
1917
1918 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1919 {
1920 struct ath_hw *ah = sc->sc_ah;
1921 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1922 struct list_head bf_head;
1923 struct ath_desc *ds;
1924 int txok;
1925 int status;
1926
1927 DPRINTF(sc, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
1928 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
1929 txq->axq_link);
1930
1931 for (;;) {
1932 spin_lock_bh(&txq->axq_lock);
1933 if (list_empty(&txq->axq_q)) {
1934 txq->axq_link = NULL;
1935 txq->axq_linkbuf = NULL;
1936 spin_unlock_bh(&txq->axq_lock);
1937 break;
1938 }
1939 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1940
1941 /*
1942 * There is a race condition that a BH gets scheduled
1943 * after sw writes TxE and before hw re-load the last
1944 * descriptor to get the newly chained one.
1945 * Software must keep the last DONE descriptor as a
1946 * holding descriptor - software does so by marking
1947 * it with the STALE flag.
1948 */
1949 bf_held = NULL;
1950 if (bf->bf_stale) {
1951 bf_held = bf;
1952 if (list_is_last(&bf_held->list, &txq->axq_q)) {
1953 txq->axq_link = NULL;
1954 txq->axq_linkbuf = NULL;
1955 spin_unlock_bh(&txq->axq_lock);
1956
1957 /*
1958 * The holding descriptor is the last
1959 * descriptor in queue. It's safe to remove
1960 * the last holding descriptor in BH context.
1961 */
1962 spin_lock_bh(&sc->tx.txbuflock);
1963 list_move_tail(&bf_held->list, &sc->tx.txbuf);
1964 spin_unlock_bh(&sc->tx.txbuflock);
1965
1966 break;
1967 } else {
1968 bf = list_entry(bf_held->list.next,
1969 struct ath_buf, list);
1970 }
1971 }
1972
1973 lastbf = bf->bf_lastbf;
1974 ds = lastbf->bf_desc;
1975
1976 status = ath9k_hw_txprocdesc(ah, ds);
1977 if (status == -EINPROGRESS) {
1978 spin_unlock_bh(&txq->axq_lock);
1979 break;
1980 }
1981 if (bf->bf_desc == txq->axq_lastdsWithCTS)
1982 txq->axq_lastdsWithCTS = NULL;
1983 if (ds == txq->axq_gatingds)
1984 txq->axq_gatingds = NULL;
1985
1986 /*
1987 * Remove ath_buf's of the same transmit unit from txq,
1988 * however leave the last descriptor back as the holding
1989 * descriptor for hw.
1990 */
1991 lastbf->bf_stale = true;
1992 INIT_LIST_HEAD(&bf_head);
1993 if (!list_is_singular(&lastbf->list))
1994 list_cut_position(&bf_head,
1995 &txq->axq_q, lastbf->list.prev);
1996
1997 txq->axq_depth--;
1998 if (bf_isaggr(bf))
1999 txq->axq_aggr_depth--;
2000
2001 txok = (ds->ds_txstat.ts_status == 0);
2002 spin_unlock_bh(&txq->axq_lock);
2003
2004 if (bf_held) {
2005 spin_lock_bh(&sc->tx.txbuflock);
2006 list_move_tail(&bf_held->list, &sc->tx.txbuf);
2007 spin_unlock_bh(&sc->tx.txbuflock);
2008 }
2009
2010 if (!bf_isampdu(bf)) {
2011 /*
2012 * This frame is sent out as a single frame.
2013 * Use hardware retry status for this frame.
2014 */
2015 bf->bf_retries = ds->ds_txstat.ts_longretry;
2016 if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY)
2017 bf->bf_state.bf_type |= BUF_XRETRY;
2018 ath_tx_rc_status(bf, ds, 0, txok, true);
2019 }
2020
2021 if (bf_isampdu(bf))
2022 ath_tx_complete_aggr(sc, txq, bf, &bf_head, txok);
2023 else
2024 ath_tx_complete_buf(sc, bf, &bf_head, txok, 0);
2025
2026 ath_wake_mac80211_queue(sc, txq);
2027
2028 spin_lock_bh(&txq->axq_lock);
2029 if (sc->sc_flags & SC_OP_TXAGGR)
2030 ath_txq_schedule(sc, txq);
2031 spin_unlock_bh(&txq->axq_lock);
2032 }
2033 }
2034
2035
2036 void ath_tx_tasklet(struct ath_softc *sc)
2037 {
2038 int i;
2039 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2040
2041 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2042
2043 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2044 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2045 ath_tx_processq(sc, &sc->tx.txq[i]);
2046 }
2047 }
2048
2049 /*****************/
2050 /* Init, Cleanup */
2051 /*****************/
2052
2053 int ath_tx_init(struct ath_softc *sc, int nbufs)
2054 {
2055 int error = 0;
2056
2057 spin_lock_init(&sc->tx.txbuflock);
2058
2059 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2060 "tx", nbufs, 1);
2061 if (error != 0) {
2062 DPRINTF(sc, ATH_DBG_FATAL,
2063 "Failed to allocate tx descriptors: %d\n", error);
2064 goto err;
2065 }
2066
2067 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2068 "beacon", ATH_BCBUF, 1);
2069 if (error != 0) {
2070 DPRINTF(sc, ATH_DBG_FATAL,
2071 "Failed to allocate beacon descriptors: %d\n", error);
2072 goto err;
2073 }
2074
2075 err:
2076 if (error != 0)
2077 ath_tx_cleanup(sc);
2078
2079 return error;
2080 }
2081
2082 void ath_tx_cleanup(struct ath_softc *sc)
2083 {
2084 if (sc->beacon.bdma.dd_desc_len != 0)
2085 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2086
2087 if (sc->tx.txdma.dd_desc_len != 0)
2088 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2089 }
2090
2091 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2092 {
2093 struct ath_atx_tid *tid;
2094 struct ath_atx_ac *ac;
2095 int tidno, acno;
2096
2097 for (tidno = 0, tid = &an->tid[tidno];
2098 tidno < WME_NUM_TID;
2099 tidno++, tid++) {
2100 tid->an = an;
2101 tid->tidno = tidno;
2102 tid->seq_start = tid->seq_next = 0;
2103 tid->baw_size = WME_MAX_BA;
2104 tid->baw_head = tid->baw_tail = 0;
2105 tid->sched = false;
2106 tid->paused = false;
2107 tid->state &= ~AGGR_CLEANUP;
2108 INIT_LIST_HEAD(&tid->buf_q);
2109 acno = TID_TO_WME_AC(tidno);
2110 tid->ac = &an->ac[acno];
2111 tid->state &= ~AGGR_ADDBA_COMPLETE;
2112 tid->state &= ~AGGR_ADDBA_PROGRESS;
2113 tid->addba_exchangeattempts = 0;
2114 }
2115
2116 for (acno = 0, ac = &an->ac[acno];
2117 acno < WME_NUM_AC; acno++, ac++) {
2118 ac->sched = false;
2119 INIT_LIST_HEAD(&ac->tid_q);
2120
2121 switch (acno) {
2122 case WME_AC_BE:
2123 ac->qnum = ath_tx_get_qnum(sc,
2124 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
2125 break;
2126 case WME_AC_BK:
2127 ac->qnum = ath_tx_get_qnum(sc,
2128 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK);
2129 break;
2130 case WME_AC_VI:
2131 ac->qnum = ath_tx_get_qnum(sc,
2132 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI);
2133 break;
2134 case WME_AC_VO:
2135 ac->qnum = ath_tx_get_qnum(sc,
2136 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO);
2137 break;
2138 }
2139 }
2140 }
2141
2142 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2143 {
2144 int i;
2145 struct ath_atx_ac *ac, *ac_tmp;
2146 struct ath_atx_tid *tid, *tid_tmp;
2147 struct ath_txq *txq;
2148
2149 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2150 if (ATH_TXQ_SETUP(sc, i)) {
2151 txq = &sc->tx.txq[i];
2152
2153 spin_lock(&txq->axq_lock);
2154
2155 list_for_each_entry_safe(ac,
2156 ac_tmp, &txq->axq_acq, list) {
2157 tid = list_first_entry(&ac->tid_q,
2158 struct ath_atx_tid, list);
2159 if (tid && tid->an != an)
2160 continue;
2161 list_del(&ac->list);
2162 ac->sched = false;
2163
2164 list_for_each_entry_safe(tid,
2165 tid_tmp, &ac->tid_q, list) {
2166 list_del(&tid->list);
2167 tid->sched = false;
2168 ath_tid_drain(sc, txq, tid);
2169 tid->state &= ~AGGR_ADDBA_COMPLETE;
2170 tid->addba_exchangeattempts = 0;
2171 tid->state &= ~AGGR_CLEANUP;
2172 }
2173 }
2174
2175 spin_unlock(&txq->axq_lock);
2176 }
2177 }
2178 }
Linus' kernel tree