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Merge branch 'master' of git://git.infradead.org/users/linville/wireless
[linux-2.6.git] / drivers / net / wireless / ath / ath9k / recv.c
blob49843500fe7cd5faafd5f809fcf5515b2e50b4ab
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/dma-mapping.h>
18 #include "ath9k.h"
19 #include "ar9003_mac.h"
20
21 #define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb))
22
23 static inline bool ath_is_alt_ant_ratio_better(int alt_ratio, int maxdelta,
24 int mindelta, int main_rssi_avg,
25 int alt_rssi_avg, int pkt_count)
26 {
27 return (((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
28 (alt_rssi_avg > main_rssi_avg + maxdelta)) ||
29 (alt_rssi_avg > main_rssi_avg + mindelta)) && (pkt_count > 50);
30 }
31
32 static inline bool ath_ant_div_comb_alt_check(u8 div_group, int alt_ratio,
33 int curr_main_set, int curr_alt_set,
34 int alt_rssi_avg, int main_rssi_avg)
35 {
36 bool result = false;
37 switch (div_group) {
38 case 0:
39 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
40 result = true;
41 break;
42 case 1:
43 case 2:
44 if ((((curr_main_set == ATH_ANT_DIV_COMB_LNA2) &&
45 (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) &&
46 (alt_rssi_avg >= (main_rssi_avg - 5))) ||
47 ((curr_main_set == ATH_ANT_DIV_COMB_LNA1) &&
48 (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) &&
49 (alt_rssi_avg >= (main_rssi_avg - 2)))) &&
50 (alt_rssi_avg >= 4))
51 result = true;
52 else
53 result = false;
54 break;
55 }
56
57 return result;
58 }
59
60 static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
61 {
62 return sc->ps_enabled &&
63 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
64 }
65
66 /*
67 * Setup and link descriptors.
68 *
69 * 11N: we can no longer afford to self link the last descriptor.
70 * MAC acknowledges BA status as long as it copies frames to host
71 * buffer (or rx fifo). This can incorrectly acknowledge packets
72 * to a sender if last desc is self-linked.
73 */
74 static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
75 {
76 struct ath_hw *ah = sc->sc_ah;
77 struct ath_common *common = ath9k_hw_common(ah);
78 struct ath_desc *ds;
79 struct sk_buff *skb;
80
81 ATH_RXBUF_RESET(bf);
82
83 ds = bf->bf_desc;
84 ds->ds_link = 0; /* link to null */
85 ds->ds_data = bf->bf_buf_addr;
86
87 /* virtual addr of the beginning of the buffer. */
88 skb = bf->bf_mpdu;
89 BUG_ON(skb == NULL);
90 ds->ds_vdata = skb->data;
91
92 /*
93 * setup rx descriptors. The rx_bufsize here tells the hardware
94 * how much data it can DMA to us and that we are prepared
95 * to process
96 */
97 ath9k_hw_setuprxdesc(ah, ds,
98 common->rx_bufsize,
99 0);
100
101 if (sc->rx.rxlink == NULL)
102 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
103 else
104 *sc->rx.rxlink = bf->bf_daddr;
105
106 sc->rx.rxlink = &ds->ds_link;
107 }
108
109 static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
110 {
111 /* XXX block beacon interrupts */
112 ath9k_hw_setantenna(sc->sc_ah, antenna);
113 sc->rx.defant = antenna;
114 sc->rx.rxotherant = 0;
115 }
116
117 static void ath_opmode_init(struct ath_softc *sc)
118 {
119 struct ath_hw *ah = sc->sc_ah;
120 struct ath_common *common = ath9k_hw_common(ah);
121
122 u32 rfilt, mfilt[2];
123
124 /* configure rx filter */
125 rfilt = ath_calcrxfilter(sc);
126 ath9k_hw_setrxfilter(ah, rfilt);
127
128 /* configure bssid mask */
129 ath_hw_setbssidmask(common);
130
131 /* configure operational mode */
132 ath9k_hw_setopmode(ah);
133
134 /* calculate and install multicast filter */
135 mfilt[0] = mfilt[1] = ~0;
136 ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
137 }
138
139 static bool ath_rx_edma_buf_link(struct ath_softc *sc,
140 enum ath9k_rx_qtype qtype)
141 {
142 struct ath_hw *ah = sc->sc_ah;
143 struct ath_rx_edma *rx_edma;
144 struct sk_buff *skb;
145 struct ath_buf *bf;
146
147 rx_edma = &sc->rx.rx_edma[qtype];
148 if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
149 return false;
150
151 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
152 list_del_init(&bf->list);
153
154 skb = bf->bf_mpdu;
155
156 ATH_RXBUF_RESET(bf);
157 memset(skb->data, 0, ah->caps.rx_status_len);
158 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
159 ah->caps.rx_status_len, DMA_TO_DEVICE);
160
161 SKB_CB_ATHBUF(skb) = bf;
162 ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
163 skb_queue_tail(&rx_edma->rx_fifo, skb);
164
165 return true;
166 }
167
168 static void ath_rx_addbuffer_edma(struct ath_softc *sc,
169 enum ath9k_rx_qtype qtype, int size)
170 {
171 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
172 u32 nbuf = 0;
173
174 if (list_empty(&sc->rx.rxbuf)) {
175 ath_dbg(common, ATH_DBG_QUEUE, "No free rx buf available\n");
176 return;
177 }
178
179 while (!list_empty(&sc->rx.rxbuf)) {
180 nbuf++;
181
182 if (!ath_rx_edma_buf_link(sc, qtype))
183 break;
184
185 if (nbuf >= size)
186 break;
187 }
188 }
189
190 static void ath_rx_remove_buffer(struct ath_softc *sc,
191 enum ath9k_rx_qtype qtype)
192 {
193 struct ath_buf *bf;
194 struct ath_rx_edma *rx_edma;
195 struct sk_buff *skb;
196
197 rx_edma = &sc->rx.rx_edma[qtype];
198
199 while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
200 bf = SKB_CB_ATHBUF(skb);
201 BUG_ON(!bf);
202 list_add_tail(&bf->list, &sc->rx.rxbuf);
203 }
204 }
205
206 static void ath_rx_edma_cleanup(struct ath_softc *sc)
207 {
208 struct ath_hw *ah = sc->sc_ah;
209 struct ath_common *common = ath9k_hw_common(ah);
210 struct ath_buf *bf;
211
212 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
213 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
214
215 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
216 if (bf->bf_mpdu) {
217 dma_unmap_single(sc->dev, bf->bf_buf_addr,
218 common->rx_bufsize,
219 DMA_BIDIRECTIONAL);
220 dev_kfree_skb_any(bf->bf_mpdu);
221 bf->bf_buf_addr = 0;
222 bf->bf_mpdu = NULL;
223 }
224 }
225
226 INIT_LIST_HEAD(&sc->rx.rxbuf);
227
228 kfree(sc->rx.rx_bufptr);
229 sc->rx.rx_bufptr = NULL;
230 }
231
232 static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
233 {
234 skb_queue_head_init(&rx_edma->rx_fifo);
235 skb_queue_head_init(&rx_edma->rx_buffers);
236 rx_edma->rx_fifo_hwsize = size;
237 }
238
239 static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
240 {
241 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
242 struct ath_hw *ah = sc->sc_ah;
243 struct sk_buff *skb;
244 struct ath_buf *bf;
245 int error = 0, i;
246 u32 size;
247
248 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
249 ah->caps.rx_status_len);
250
251 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
252 ah->caps.rx_lp_qdepth);
253 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
254 ah->caps.rx_hp_qdepth);
255
256 size = sizeof(struct ath_buf) * nbufs;
257 bf = kzalloc(size, GFP_KERNEL);
258 if (!bf)
259 return -ENOMEM;
260
261 INIT_LIST_HEAD(&sc->rx.rxbuf);
262 sc->rx.rx_bufptr = bf;
263
264 for (i = 0; i < nbufs; i++, bf++) {
265 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
266 if (!skb) {
267 error = -ENOMEM;
268 goto rx_init_fail;
269 }
270
271 memset(skb->data, 0, common->rx_bufsize);
272 bf->bf_mpdu = skb;
273
274 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
275 common->rx_bufsize,
276 DMA_BIDIRECTIONAL);
277 if (unlikely(dma_mapping_error(sc->dev,
278 bf->bf_buf_addr))) {
279 dev_kfree_skb_any(skb);
280 bf->bf_mpdu = NULL;
281 bf->bf_buf_addr = 0;
282 ath_err(common,
283 "dma_mapping_error() on RX init\n");
284 error = -ENOMEM;
285 goto rx_init_fail;
286 }
287
288 list_add_tail(&bf->list, &sc->rx.rxbuf);
289 }
290
291 return 0;
292
293 rx_init_fail:
294 ath_rx_edma_cleanup(sc);
295 return error;
296 }
297
298 static void ath_edma_start_recv(struct ath_softc *sc)
299 {
300 spin_lock_bh(&sc->rx.rxbuflock);
301
302 ath9k_hw_rxena(sc->sc_ah);
303
304 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP,
305 sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize);
306
307 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
308 sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);
309
310 ath_opmode_init(sc);
311
312 ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
313
314 spin_unlock_bh(&sc->rx.rxbuflock);
315 }
316
317 static void ath_edma_stop_recv(struct ath_softc *sc)
318 {
319 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
320 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
321 }
322
323 int ath_rx_init(struct ath_softc *sc, int nbufs)
324 {
325 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
326 struct sk_buff *skb;
327 struct ath_buf *bf;
328 int error = 0;
329
330 spin_lock_init(&sc->sc_pcu_lock);
331 sc->sc_flags &= ~SC_OP_RXFLUSH;
332 spin_lock_init(&sc->rx.rxbuflock);
333
334 common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 +
335 sc->sc_ah->caps.rx_status_len;
336
337 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
338 return ath_rx_edma_init(sc, nbufs);
339 } else {
340 ath_dbg(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
341 common->cachelsz, common->rx_bufsize);
342
343 /* Initialize rx descriptors */
344
345 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
346 "rx", nbufs, 1, 0);
347 if (error != 0) {
348 ath_err(common,
349 "failed to allocate rx descriptors: %d\n",
350 error);
351 goto err;
352 }
353
354 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
355 skb = ath_rxbuf_alloc(common, common->rx_bufsize,
356 GFP_KERNEL);
357 if (skb == NULL) {
358 error = -ENOMEM;
359 goto err;
360 }
361
362 bf->bf_mpdu = skb;
363 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
364 common->rx_bufsize,
365 DMA_FROM_DEVICE);
366 if (unlikely(dma_mapping_error(sc->dev,
367 bf->bf_buf_addr))) {
368 dev_kfree_skb_any(skb);
369 bf->bf_mpdu = NULL;
370 bf->bf_buf_addr = 0;
371 ath_err(common,
372 "dma_mapping_error() on RX init\n");
373 error = -ENOMEM;
374 goto err;
375 }
376 }
377 sc->rx.rxlink = NULL;
378 }
379
380 err:
381 if (error)
382 ath_rx_cleanup(sc);
383
384 return error;
385 }
386
387 void ath_rx_cleanup(struct ath_softc *sc)
388 {
389 struct ath_hw *ah = sc->sc_ah;
390 struct ath_common *common = ath9k_hw_common(ah);
391 struct sk_buff *skb;
392 struct ath_buf *bf;
393
394 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
395 ath_rx_edma_cleanup(sc);
396 return;
397 } else {
398 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
399 skb = bf->bf_mpdu;
400 if (skb) {
401 dma_unmap_single(sc->dev, bf->bf_buf_addr,
402 common->rx_bufsize,
403 DMA_FROM_DEVICE);
404 dev_kfree_skb(skb);
405 bf->bf_buf_addr = 0;
406 bf->bf_mpdu = NULL;
407 }
408 }
409
410 if (sc->rx.rxdma.dd_desc_len != 0)
411 ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
412 }
413 }
414
415 /*
416 * Calculate the receive filter according to the
417 * operating mode and state:
418 *
419 * o always accept unicast, broadcast, and multicast traffic
420 * o maintain current state of phy error reception (the hal
421 * may enable phy error frames for noise immunity work)
422 * o probe request frames are accepted only when operating in
423 * hostap, adhoc, or monitor modes
424 * o enable promiscuous mode according to the interface state
425 * o accept beacons:
426 * - when operating in adhoc mode so the 802.11 layer creates
427 * node table entries for peers,
428 * - when operating in station mode for collecting rssi data when
429 * the station is otherwise quiet, or
430 * - when operating as a repeater so we see repeater-sta beacons
431 * - when scanning
432 */
433
434 u32 ath_calcrxfilter(struct ath_softc *sc)
435 {
436 #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR)
437
438 u32 rfilt;
439
440 rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE)
441 | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
442 | ATH9K_RX_FILTER_MCAST;
443
444 if (sc->rx.rxfilter & FIF_PROBE_REQ)
445 rfilt |= ATH9K_RX_FILTER_PROBEREQ;
446
447 /*
448 * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
449 * mode interface or when in monitor mode. AP mode does not need this
450 * since it receives all in-BSS frames anyway.
451 */
452 if (sc->sc_ah->is_monitoring)
453 rfilt |= ATH9K_RX_FILTER_PROM;
454
455 if (sc->rx.rxfilter & FIF_CONTROL)
456 rfilt |= ATH9K_RX_FILTER_CONTROL;
457
458 if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
459 (sc->nvifs <= 1) &&
460 !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC))
461 rfilt |= ATH9K_RX_FILTER_MYBEACON;
462 else
463 rfilt |= ATH9K_RX_FILTER_BEACON;
464
465 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
466 (sc->rx.rxfilter & FIF_PSPOLL))
467 rfilt |= ATH9K_RX_FILTER_PSPOLL;
468
469 if (conf_is_ht(&sc->hw->conf))
470 rfilt |= ATH9K_RX_FILTER_COMP_BAR;
471
472 if (sc->nvifs > 1 || (sc->rx.rxfilter & FIF_OTHER_BSS)) {
473 /* The following may also be needed for other older chips */
474 if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160)
475 rfilt |= ATH9K_RX_FILTER_PROM;
476 rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
477 }
478
479 return rfilt;
480
481 #undef RX_FILTER_PRESERVE
482 }
483
484 int ath_startrecv(struct ath_softc *sc)
485 {
486 struct ath_hw *ah = sc->sc_ah;
487 struct ath_buf *bf, *tbf;
488
489 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
490 ath_edma_start_recv(sc);
491 return 0;
492 }
493
494 spin_lock_bh(&sc->rx.rxbuflock);
495 if (list_empty(&sc->rx.rxbuf))
496 goto start_recv;
497
498 sc->rx.rxlink = NULL;
499 list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
500 ath_rx_buf_link(sc, bf);
501 }
502
503 /* We could have deleted elements so the list may be empty now */
504 if (list_empty(&sc->rx.rxbuf))
505 goto start_recv;
506
507 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
508 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
509 ath9k_hw_rxena(ah);
510
511 start_recv:
512 ath_opmode_init(sc);
513 ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
514
515 spin_unlock_bh(&sc->rx.rxbuflock);
516
517 return 0;
518 }
519
520 bool ath_stoprecv(struct ath_softc *sc)
521 {
522 struct ath_hw *ah = sc->sc_ah;
523 bool stopped, reset = false;
524
525 spin_lock_bh(&sc->rx.rxbuflock);
526 ath9k_hw_abortpcurecv(ah);
527 ath9k_hw_setrxfilter(ah, 0);
528 stopped = ath9k_hw_stopdmarecv(ah, &reset);
529
530 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
531 ath_edma_stop_recv(sc);
532 else
533 sc->rx.rxlink = NULL;
534 spin_unlock_bh(&sc->rx.rxbuflock);
535
536 if (!(ah->ah_flags & AH_UNPLUGGED) &&
537 unlikely(!stopped)) {
538 ath_err(ath9k_hw_common(sc->sc_ah),
539 "Could not stop RX, we could be "
540 "confusing the DMA engine when we start RX up\n");
541 ATH_DBG_WARN_ON_ONCE(!stopped);
542 }
543 return stopped && !reset;
544 }
545
546 void ath_flushrecv(struct ath_softc *sc)
547 {
548 sc->sc_flags |= SC_OP_RXFLUSH;
549 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
550 ath_rx_tasklet(sc, 1, true);
551 ath_rx_tasklet(sc, 1, false);
552 sc->sc_flags &= ~SC_OP_RXFLUSH;
553 }
554
555 static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
556 {
557 /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
558 struct ieee80211_mgmt *mgmt;
559 u8 *pos, *end, id, elen;
560 struct ieee80211_tim_ie *tim;
561
562 mgmt = (struct ieee80211_mgmt *)skb->data;
563 pos = mgmt->u.beacon.variable;
564 end = skb->data + skb->len;
565
566 while (pos + 2 < end) {
567 id = *pos++;
568 elen = *pos++;
569 if (pos + elen > end)
570 break;
571
572 if (id == WLAN_EID_TIM) {
573 if (elen < sizeof(*tim))
574 break;
575 tim = (struct ieee80211_tim_ie *) pos;
576 if (tim->dtim_count != 0)
577 break;
578 return tim->bitmap_ctrl & 0x01;
579 }
580
581 pos += elen;
582 }
583
584 return false;
585 }
586
587 static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
588 {
589 struct ieee80211_mgmt *mgmt;
590 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
591
592 if (skb->len < 24 + 8 + 2 + 2)
593 return;
594
595 mgmt = (struct ieee80211_mgmt *)skb->data;
596 if (memcmp(common->curbssid, mgmt->bssid, ETH_ALEN) != 0) {
597 /* TODO: This doesn't work well if you have stations
598 * associated to two different APs because curbssid
599 * is just the last AP that any of the stations associated
600 * with.
601 */
602 return; /* not from our current AP */
603 }
604
605 sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
606
607 if (sc->ps_flags & PS_BEACON_SYNC) {
608 sc->ps_flags &= ~PS_BEACON_SYNC;
609 ath_dbg(common, ATH_DBG_PS,
610 "Reconfigure Beacon timers based on timestamp from the AP\n");
611 ath_set_beacon(sc);
612 }
613
614 if (ath_beacon_dtim_pending_cab(skb)) {
615 /*
616 * Remain awake waiting for buffered broadcast/multicast
617 * frames. If the last broadcast/multicast frame is not
618 * received properly, the next beacon frame will work as
619 * a backup trigger for returning into NETWORK SLEEP state,
620 * so we are waiting for it as well.
621 */
622 ath_dbg(common, ATH_DBG_PS,
623 "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n");
624 sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
625 return;
626 }
627
628 if (sc->ps_flags & PS_WAIT_FOR_CAB) {
629 /*
630 * This can happen if a broadcast frame is dropped or the AP
631 * fails to send a frame indicating that all CAB frames have
632 * been delivered.
633 */
634 sc->ps_flags &= ~PS_WAIT_FOR_CAB;
635 ath_dbg(common, ATH_DBG_PS,
636 "PS wait for CAB frames timed out\n");
637 }
638 }
639
640 static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
641 {
642 struct ieee80211_hdr *hdr;
643 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
644
645 hdr = (struct ieee80211_hdr *)skb->data;
646
647 /* Process Beacon and CAB receive in PS state */
648 if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc))
649 && ieee80211_is_beacon(hdr->frame_control))
650 ath_rx_ps_beacon(sc, skb);
651 else if ((sc->ps_flags & PS_WAIT_FOR_CAB) &&
652 (ieee80211_is_data(hdr->frame_control) ||
653 ieee80211_is_action(hdr->frame_control)) &&
654 is_multicast_ether_addr(hdr->addr1) &&
655 !ieee80211_has_moredata(hdr->frame_control)) {
656 /*
657 * No more broadcast/multicast frames to be received at this
658 * point.
659 */
660 sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON);
661 ath_dbg(common, ATH_DBG_PS,
662 "All PS CAB frames received, back to sleep\n");
663 } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
664 !is_multicast_ether_addr(hdr->addr1) &&
665 !ieee80211_has_morefrags(hdr->frame_control)) {
666 sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
667 ath_dbg(common, ATH_DBG_PS,
668 "Going back to sleep after having received PS-Poll data (0x%lx)\n",
669 sc->ps_flags & (PS_WAIT_FOR_BEACON |
670 PS_WAIT_FOR_CAB |
671 PS_WAIT_FOR_PSPOLL_DATA |
672 PS_WAIT_FOR_TX_ACK));
673 }
674 }
675
676 static bool ath_edma_get_buffers(struct ath_softc *sc,
677 enum ath9k_rx_qtype qtype)
678 {
679 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
680 struct ath_hw *ah = sc->sc_ah;
681 struct ath_common *common = ath9k_hw_common(ah);
682 struct sk_buff *skb;
683 struct ath_buf *bf;
684 int ret;
685
686 skb = skb_peek(&rx_edma->rx_fifo);
687 if (!skb)
688 return false;
689
690 bf = SKB_CB_ATHBUF(skb);
691 BUG_ON(!bf);
692
693 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
694 common->rx_bufsize, DMA_FROM_DEVICE);
695
696 ret = ath9k_hw_process_rxdesc_edma(ah, NULL, skb->data);
697 if (ret == -EINPROGRESS) {
698 /*let device gain the buffer again*/
699 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
700 common->rx_bufsize, DMA_FROM_DEVICE);
701 return false;
702 }
703
704 __skb_unlink(skb, &rx_edma->rx_fifo);
705 if (ret == -EINVAL) {
706 /* corrupt descriptor, skip this one and the following one */
707 list_add_tail(&bf->list, &sc->rx.rxbuf);
708 ath_rx_edma_buf_link(sc, qtype);
709 skb = skb_peek(&rx_edma->rx_fifo);
710 if (!skb)
711 return true;
712
713 bf = SKB_CB_ATHBUF(skb);
714 BUG_ON(!bf);
715
716 __skb_unlink(skb, &rx_edma->rx_fifo);
717 list_add_tail(&bf->list, &sc->rx.rxbuf);
718 ath_rx_edma_buf_link(sc, qtype);
719 return true;
720 }
721 skb_queue_tail(&rx_edma->rx_buffers, skb);
722
723 return true;
724 }
725
726 static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
727 struct ath_rx_status *rs,
728 enum ath9k_rx_qtype qtype)
729 {
730 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
731 struct sk_buff *skb;
732 struct ath_buf *bf;
733
734 while (ath_edma_get_buffers(sc, qtype));
735 skb = __skb_dequeue(&rx_edma->rx_buffers);
736 if (!skb)
737 return NULL;
738
739 bf = SKB_CB_ATHBUF(skb);
740 ath9k_hw_process_rxdesc_edma(sc->sc_ah, rs, skb->data);
741 return bf;
742 }
743
744 static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc,
745 struct ath_rx_status *rs)
746 {
747 struct ath_hw *ah = sc->sc_ah;
748 struct ath_common *common = ath9k_hw_common(ah);
749 struct ath_desc *ds;
750 struct ath_buf *bf;
751 int ret;
752
753 if (list_empty(&sc->rx.rxbuf)) {
754 sc->rx.rxlink = NULL;
755 return NULL;
756 }
757
758 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
759 ds = bf->bf_desc;
760
761 /*
762 * Must provide the virtual address of the current
763 * descriptor, the physical address, and the virtual
764 * address of the next descriptor in the h/w chain.
765 * This allows the HAL to look ahead to see if the
766 * hardware is done with a descriptor by checking the
767 * done bit in the following descriptor and the address
768 * of the current descriptor the DMA engine is working
769 * on. All this is necessary because of our use of
770 * a self-linked list to avoid rx overruns.
771 */
772 ret = ath9k_hw_rxprocdesc(ah, ds, rs);
773 if (ret == -EINPROGRESS) {
774 struct ath_rx_status trs;
775 struct ath_buf *tbf;
776 struct ath_desc *tds;
777
778 memset(&trs, 0, sizeof(trs));
779 if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
780 sc->rx.rxlink = NULL;
781 return NULL;
782 }
783
784 tbf = list_entry(bf->list.next, struct ath_buf, list);
785
786 /*
787 * On some hardware the descriptor status words could
788 * get corrupted, including the done bit. Because of
789 * this, check if the next descriptor's done bit is
790 * set or not.
791 *
792 * If the next descriptor's done bit is set, the current
793 * descriptor has been corrupted. Force s/w to discard
794 * this descriptor and continue...
795 */
796
797 tds = tbf->bf_desc;
798 ret = ath9k_hw_rxprocdesc(ah, tds, &trs);
799 if (ret == -EINPROGRESS)
800 return NULL;
801 }
802
803 if (!bf->bf_mpdu)
804 return bf;
805
806 /*
807 * Synchronize the DMA transfer with CPU before
808 * 1. accessing the frame
809 * 2. requeueing the same buffer to h/w
810 */
811 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
812 common->rx_bufsize,
813 DMA_FROM_DEVICE);
814
815 return bf;
816 }
817
818 /* Assumes you've already done the endian to CPU conversion */
819 static bool ath9k_rx_accept(struct ath_common *common,
820 struct ieee80211_hdr *hdr,
821 struct ieee80211_rx_status *rxs,
822 struct ath_rx_status *rx_stats,
823 bool *decrypt_error)
824 {
825 bool is_mc, is_valid_tkip, strip_mic, mic_error;
826 struct ath_hw *ah = common->ah;
827 __le16 fc;
828 u8 rx_status_len = ah->caps.rx_status_len;
829
830 fc = hdr->frame_control;
831
832 is_mc = !!is_multicast_ether_addr(hdr->addr1);
833 is_valid_tkip = rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID &&
834 test_bit(rx_stats->rs_keyix, common->tkip_keymap);
835 strip_mic = is_valid_tkip && ieee80211_is_data(fc) &&
836 !(rx_stats->rs_status &
837 (ATH9K_RXERR_DECRYPT | ATH9K_RXERR_CRC | ATH9K_RXERR_MIC));
838
839 if (!rx_stats->rs_datalen)
840 return false;
841 /*
842 * rs_status follows rs_datalen so if rs_datalen is too large
843 * we can take a hint that hardware corrupted it, so ignore
844 * those frames.
845 */
846 if (rx_stats->rs_datalen > (common->rx_bufsize - rx_status_len))
847 return false;
848
849 /* Only use error bits from the last fragment */
850 if (rx_stats->rs_more)
851 return true;
852
853 mic_error = is_valid_tkip && !ieee80211_is_ctl(fc) &&
854 !ieee80211_has_morefrags(fc) &&
855 !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) &&
856 (rx_stats->rs_status & ATH9K_RXERR_MIC);
857
858 /*
859 * The rx_stats->rs_status will not be set until the end of the
860 * chained descriptors so it can be ignored if rs_more is set. The
861 * rs_more will be false at the last element of the chained
862 * descriptors.
863 */
864 if (rx_stats->rs_status != 0) {
865 if (rx_stats->rs_status & ATH9K_RXERR_CRC) {
866 rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
867 mic_error = false;
868 }
869 if (rx_stats->rs_status & ATH9K_RXERR_PHY)
870 return false;
871
872 if (rx_stats->rs_status & ATH9K_RXERR_DECRYPT) {
873 *decrypt_error = true;
874 mic_error = false;
875 }
876
877 /*
878 * Reject error frames with the exception of
879 * decryption and MIC failures. For monitor mode,
880 * we also ignore the CRC error.
881 */
882 if (ah->is_monitoring) {
883 if (rx_stats->rs_status &
884 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
885 ATH9K_RXERR_CRC))
886 return false;
887 } else {
888 if (rx_stats->rs_status &
889 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) {
890 return false;
891 }
892 }
893 }
894
895 /*
896 * For unicast frames the MIC error bit can have false positives,
897 * so all MIC error reports need to be validated in software.
898 * False negatives are not common, so skip software verification
899 * if the hardware considers the MIC valid.
900 */
901 if (strip_mic)
902 rxs->flag |= RX_FLAG_MMIC_STRIPPED;
903 else if (is_mc && mic_error)
904 rxs->flag |= RX_FLAG_MMIC_ERROR;
905
906 return true;
907 }
908
909 static int ath9k_process_rate(struct ath_common *common,
910 struct ieee80211_hw *hw,
911 struct ath_rx_status *rx_stats,
912 struct ieee80211_rx_status *rxs)
913 {
914 struct ieee80211_supported_band *sband;
915 enum ieee80211_band band;
916 unsigned int i = 0;
917
918 band = hw->conf.channel->band;
919 sband = hw->wiphy->bands[band];
920
921 if (rx_stats->rs_rate & 0x80) {
922 /* HT rate */
923 rxs->flag |= RX_FLAG_HT;
924 if (rx_stats->rs_flags & ATH9K_RX_2040)
925 rxs->flag |= RX_FLAG_40MHZ;
926 if (rx_stats->rs_flags & ATH9K_RX_GI)
927 rxs->flag |= RX_FLAG_SHORT_GI;
928 rxs->rate_idx = rx_stats->rs_rate & 0x7f;
929 return 0;
930 }
931
932 for (i = 0; i < sband->n_bitrates; i++) {
933 if (sband->bitrates[i].hw_value == rx_stats->rs_rate) {
934 rxs->rate_idx = i;
935 return 0;
936 }
937 if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) {
938 rxs->flag |= RX_FLAG_SHORTPRE;
939 rxs->rate_idx = i;
940 return 0;
941 }
942 }
943
944 /*
945 * No valid hardware bitrate found -- we should not get here
946 * because hardware has already validated this frame as OK.
947 */
948 ath_dbg(common, ATH_DBG_ANY,
949 "unsupported hw bitrate detected 0x%02x using 1 Mbit\n",
950 rx_stats->rs_rate);
951
952 return -EINVAL;
953 }
954
955 static void ath9k_process_rssi(struct ath_common *common,
956 struct ieee80211_hw *hw,
957 struct ieee80211_hdr *hdr,
958 struct ath_rx_status *rx_stats)
959 {
960 struct ath_softc *sc = hw->priv;
961 struct ath_hw *ah = common->ah;
962 int last_rssi;
963
964 if (!rx_stats->is_mybeacon ||
965 ((ah->opmode != NL80211_IFTYPE_STATION) &&
966 (ah->opmode != NL80211_IFTYPE_ADHOC)))
967 return;
968
969 if (rx_stats->rs_rssi != ATH9K_RSSI_BAD && !rx_stats->rs_moreaggr)
970 ATH_RSSI_LPF(sc->last_rssi, rx_stats->rs_rssi);
971
972 last_rssi = sc->last_rssi;
973 if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
974 rx_stats->rs_rssi = ATH_EP_RND(last_rssi,
975 ATH_RSSI_EP_MULTIPLIER);
976 if (rx_stats->rs_rssi < 0)
977 rx_stats->rs_rssi = 0;
978
979 /* Update Beacon RSSI, this is used by ANI. */
980 ah->stats.avgbrssi = rx_stats->rs_rssi;
981 }
982
983 /*
984 * For Decrypt or Demic errors, we only mark packet status here and always push
985 * up the frame up to let mac80211 handle the actual error case, be it no
986 * decryption key or real decryption error. This let us keep statistics there.
987 */
988 static int ath9k_rx_skb_preprocess(struct ath_common *common,
989 struct ieee80211_hw *hw,
990 struct ieee80211_hdr *hdr,
991 struct ath_rx_status *rx_stats,
992 struct ieee80211_rx_status *rx_status,
993 bool *decrypt_error)
994 {
995 struct ath_hw *ah = common->ah;
996
997 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
998
999 /*
1000 * everything but the rate is checked here, the rate check is done
1001 * separately to avoid doing two lookups for a rate for each frame.
1002 */
1003 if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error))
1004 return -EINVAL;
1005
1006 /* Only use status info from the last fragment */
1007 if (rx_stats->rs_more)
1008 return 0;
1009
1010 ath9k_process_rssi(common, hw, hdr, rx_stats);
1011
1012 if (ath9k_process_rate(common, hw, rx_stats, rx_status))
1013 return -EINVAL;
1014
1015 rx_status->band = hw->conf.channel->band;
1016 rx_status->freq = hw->conf.channel->center_freq;
1017 rx_status->signal = ah->noise + rx_stats->rs_rssi;
1018 rx_status->antenna = rx_stats->rs_antenna;
1019 rx_status->flag |= RX_FLAG_MACTIME_MPDU;
1020
1021 return 0;
1022 }
1023
1024 static void ath9k_rx_skb_postprocess(struct ath_common *common,
1025 struct sk_buff *skb,
1026 struct ath_rx_status *rx_stats,
1027 struct ieee80211_rx_status *rxs,
1028 bool decrypt_error)
1029 {
1030 struct ath_hw *ah = common->ah;
1031 struct ieee80211_hdr *hdr;
1032 int hdrlen, padpos, padsize;
1033 u8 keyix;
1034 __le16 fc;
1035
1036 /* see if any padding is done by the hw and remove it */
1037 hdr = (struct ieee80211_hdr *) skb->data;
1038 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1039 fc = hdr->frame_control;
1040 padpos = ath9k_cmn_padpos(hdr->frame_control);
1041
1042 /* The MAC header is padded to have 32-bit boundary if the
1043 * packet payload is non-zero. The general calculation for
1044 * padsize would take into account odd header lengths:
1045 * padsize = (4 - padpos % 4) % 4; However, since only
1046 * even-length headers are used, padding can only be 0 or 2
1047 * bytes and we can optimize this a bit. In addition, we must
1048 * not try to remove padding from short control frames that do
1049 * not have payload. */
1050 padsize = padpos & 3;
1051 if (padsize && skb->len>=padpos+padsize+FCS_LEN) {
1052 memmove(skb->data + padsize, skb->data, padpos);
1053 skb_pull(skb, padsize);
1054 }
1055
1056 keyix = rx_stats->rs_keyix;
1057
1058 if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error &&
1059 ieee80211_has_protected(fc)) {
1060 rxs->flag |= RX_FLAG_DECRYPTED;
1061 } else if (ieee80211_has_protected(fc)
1062 && !decrypt_error && skb->len >= hdrlen + 4) {
1063 keyix = skb->data[hdrlen + 3] >> 6;
1064
1065 if (test_bit(keyix, common->keymap))
1066 rxs->flag |= RX_FLAG_DECRYPTED;
1067 }
1068 if (ah->sw_mgmt_crypto &&
1069 (rxs->flag & RX_FLAG_DECRYPTED) &&
1070 ieee80211_is_mgmt(fc))
1071 /* Use software decrypt for management frames. */
1072 rxs->flag &= ~RX_FLAG_DECRYPTED;
1073 }
1074
1075 static void ath_lnaconf_alt_good_scan(struct ath_ant_comb *antcomb,
1076 struct ath_hw_antcomb_conf ant_conf,
1077 int main_rssi_avg)
1078 {
1079 antcomb->quick_scan_cnt = 0;
1080
1081 if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA2)
1082 antcomb->rssi_lna2 = main_rssi_avg;
1083 else if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA1)
1084 antcomb->rssi_lna1 = main_rssi_avg;
1085
1086 switch ((ant_conf.main_lna_conf << 4) | ant_conf.alt_lna_conf) {
1087 case 0x10: /* LNA2 A-B */
1088 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1089 antcomb->first_quick_scan_conf =
1090 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1091 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1092 break;
1093 case 0x20: /* LNA1 A-B */
1094 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1095 antcomb->first_quick_scan_conf =
1096 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1097 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1098 break;
1099 case 0x21: /* LNA1 LNA2 */
1100 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA2;
1101 antcomb->first_quick_scan_conf =
1102 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1103 antcomb->second_quick_scan_conf =
1104 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1105 break;
1106 case 0x12: /* LNA2 LNA1 */
1107 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1;
1108 antcomb->first_quick_scan_conf =
1109 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1110 antcomb->second_quick_scan_conf =
1111 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1112 break;
1113 case 0x13: /* LNA2 A+B */
1114 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1115 antcomb->first_quick_scan_conf =
1116 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1117 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1118 break;
1119 case 0x23: /* LNA1 A+B */
1120 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1121 antcomb->first_quick_scan_conf =
1122 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1123 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1124 break;
1125 default:
1126 break;
1127 }
1128 }
1129
1130 static void ath_select_ant_div_from_quick_scan(struct ath_ant_comb *antcomb,
1131 struct ath_hw_antcomb_conf *div_ant_conf,
1132 int main_rssi_avg, int alt_rssi_avg,
1133 int alt_ratio)
1134 {
1135 /* alt_good */
1136 switch (antcomb->quick_scan_cnt) {
1137 case 0:
1138 /* set alt to main, and alt to first conf */
1139 div_ant_conf->main_lna_conf = antcomb->main_conf;
1140 div_ant_conf->alt_lna_conf = antcomb->first_quick_scan_conf;
1141 break;
1142 case 1:
1143 /* set alt to main, and alt to first conf */
1144 div_ant_conf->main_lna_conf = antcomb->main_conf;
1145 div_ant_conf->alt_lna_conf = antcomb->second_quick_scan_conf;
1146 antcomb->rssi_first = main_rssi_avg;
1147 antcomb->rssi_second = alt_rssi_avg;
1148
1149 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1150 /* main is LNA1 */
1151 if (ath_is_alt_ant_ratio_better(alt_ratio,
1152 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1153 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1154 main_rssi_avg, alt_rssi_avg,
1155 antcomb->total_pkt_count))
1156 antcomb->first_ratio = true;
1157 else
1158 antcomb->first_ratio = false;
1159 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1160 if (ath_is_alt_ant_ratio_better(alt_ratio,
1161 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1162 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1163 main_rssi_avg, alt_rssi_avg,
1164 antcomb->total_pkt_count))
1165 antcomb->first_ratio = true;
1166 else
1167 antcomb->first_ratio = false;
1168 } else {
1169 if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1170 (alt_rssi_avg > main_rssi_avg +
1171 ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1172 (alt_rssi_avg > main_rssi_avg)) &&
1173 (antcomb->total_pkt_count > 50))
1174 antcomb->first_ratio = true;
1175 else
1176 antcomb->first_ratio = false;
1177 }
1178 break;
1179 case 2:
1180 antcomb->alt_good = false;
1181 antcomb->scan_not_start = false;
1182 antcomb->scan = false;
1183 antcomb->rssi_first = main_rssi_avg;
1184 antcomb->rssi_third = alt_rssi_avg;
1185
1186 if (antcomb->second_quick_scan_conf == ATH_ANT_DIV_COMB_LNA1)
1187 antcomb->rssi_lna1 = alt_rssi_avg;
1188 else if (antcomb->second_quick_scan_conf ==
1189 ATH_ANT_DIV_COMB_LNA2)
1190 antcomb->rssi_lna2 = alt_rssi_avg;
1191 else if (antcomb->second_quick_scan_conf ==
1192 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2) {
1193 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2)
1194 antcomb->rssi_lna2 = main_rssi_avg;
1195 else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1)
1196 antcomb->rssi_lna1 = main_rssi_avg;
1197 }
1198
1199 if (antcomb->rssi_lna2 > antcomb->rssi_lna1 +
1200 ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)
1201 div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1202 else
1203 div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA1;
1204
1205 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1206 if (ath_is_alt_ant_ratio_better(alt_ratio,
1207 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1208 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1209 main_rssi_avg, alt_rssi_avg,
1210 antcomb->total_pkt_count))
1211 antcomb->second_ratio = true;
1212 else
1213 antcomb->second_ratio = false;
1214 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1215 if (ath_is_alt_ant_ratio_better(alt_ratio,
1216 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1217 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1218 main_rssi_avg, alt_rssi_avg,
1219 antcomb->total_pkt_count))
1220 antcomb->second_ratio = true;
1221 else
1222 antcomb->second_ratio = false;
1223 } else {
1224 if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1225 (alt_rssi_avg > main_rssi_avg +
1226 ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1227 (alt_rssi_avg > main_rssi_avg)) &&
1228 (antcomb->total_pkt_count > 50))
1229 antcomb->second_ratio = true;
1230 else
1231 antcomb->second_ratio = false;
1232 }
1233
1234 /* set alt to the conf with maximun ratio */
1235 if (antcomb->first_ratio && antcomb->second_ratio) {
1236 if (antcomb->rssi_second > antcomb->rssi_third) {
1237 /* first alt*/
1238 if ((antcomb->first_quick_scan_conf ==
1239 ATH_ANT_DIV_COMB_LNA1) ||
1240 (antcomb->first_quick_scan_conf ==
1241 ATH_ANT_DIV_COMB_LNA2))
1242 /* Set alt LNA1 or LNA2*/
1243 if (div_ant_conf->main_lna_conf ==
1244 ATH_ANT_DIV_COMB_LNA2)
1245 div_ant_conf->alt_lna_conf =
1246 ATH_ANT_DIV_COMB_LNA1;
1247 else
1248 div_ant_conf->alt_lna_conf =
1249 ATH_ANT_DIV_COMB_LNA2;
1250 else
1251 /* Set alt to A+B or A-B */
1252 div_ant_conf->alt_lna_conf =
1253 antcomb->first_quick_scan_conf;
1254 } else if ((antcomb->second_quick_scan_conf ==
1255 ATH_ANT_DIV_COMB_LNA1) ||
1256 (antcomb->second_quick_scan_conf ==
1257 ATH_ANT_DIV_COMB_LNA2)) {
1258 /* Set alt LNA1 or LNA2 */
1259 if (div_ant_conf->main_lna_conf ==
1260 ATH_ANT_DIV_COMB_LNA2)
1261 div_ant_conf->alt_lna_conf =
1262 ATH_ANT_DIV_COMB_LNA1;
1263 else
1264 div_ant_conf->alt_lna_conf =
1265 ATH_ANT_DIV_COMB_LNA2;
1266 } else {
1267 /* Set alt to A+B or A-B */
1268 div_ant_conf->alt_lna_conf =
1269 antcomb->second_quick_scan_conf;
1270 }
1271 } else if (antcomb->first_ratio) {
1272 /* first alt */
1273 if ((antcomb->first_quick_scan_conf ==
1274 ATH_ANT_DIV_COMB_LNA1) ||
1275 (antcomb->first_quick_scan_conf ==
1276 ATH_ANT_DIV_COMB_LNA2))
1277 /* Set alt LNA1 or LNA2 */
1278 if (div_ant_conf->main_lna_conf ==
1279 ATH_ANT_DIV_COMB_LNA2)
1280 div_ant_conf->alt_lna_conf =
1281 ATH_ANT_DIV_COMB_LNA1;
1282 else
1283 div_ant_conf->alt_lna_conf =
1284 ATH_ANT_DIV_COMB_LNA2;
1285 else
1286 /* Set alt to A+B or A-B */
1287 div_ant_conf->alt_lna_conf =
1288 antcomb->first_quick_scan_conf;
1289 } else if (antcomb->second_ratio) {
1290 /* second alt */
1291 if ((antcomb->second_quick_scan_conf ==
1292 ATH_ANT_DIV_COMB_LNA1) ||
1293 (antcomb->second_quick_scan_conf ==
1294 ATH_ANT_DIV_COMB_LNA2))
1295 /* Set alt LNA1 or LNA2 */
1296 if (div_ant_conf->main_lna_conf ==
1297 ATH_ANT_DIV_COMB_LNA2)
1298 div_ant_conf->alt_lna_conf =
1299 ATH_ANT_DIV_COMB_LNA1;
1300 else
1301 div_ant_conf->alt_lna_conf =
1302 ATH_ANT_DIV_COMB_LNA2;
1303 else
1304 /* Set alt to A+B or A-B */
1305 div_ant_conf->alt_lna_conf =
1306 antcomb->second_quick_scan_conf;
1307 } else {
1308 /* main is largest */
1309 if ((antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) ||
1310 (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2))
1311 /* Set alt LNA1 or LNA2 */
1312 if (div_ant_conf->main_lna_conf ==
1313 ATH_ANT_DIV_COMB_LNA2)
1314 div_ant_conf->alt_lna_conf =
1315 ATH_ANT_DIV_COMB_LNA1;
1316 else
1317 div_ant_conf->alt_lna_conf =
1318 ATH_ANT_DIV_COMB_LNA2;
1319 else
1320 /* Set alt to A+B or A-B */
1321 div_ant_conf->alt_lna_conf = antcomb->main_conf;
1322 }
1323 break;
1324 default:
1325 break;
1326 }
1327 }
1328
1329 static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
1330 struct ath_ant_comb *antcomb, int alt_ratio)
1331 {
1332 if (ant_conf->div_group == 0) {
1333 /* Adjust the fast_div_bias based on main and alt lna conf */
1334 switch ((ant_conf->main_lna_conf << 4) |
1335 ant_conf->alt_lna_conf) {
1336 case 0x01: /* A-B LNA2 */
1337 ant_conf->fast_div_bias = 0x3b;
1338 break;
1339 case 0x02: /* A-B LNA1 */
1340 ant_conf->fast_div_bias = 0x3d;
1341 break;
1342 case 0x03: /* A-B A+B */
1343 ant_conf->fast_div_bias = 0x1;
1344 break;
1345 case 0x10: /* LNA2 A-B */
1346 ant_conf->fast_div_bias = 0x7;
1347 break;
1348 case 0x12: /* LNA2 LNA1 */
1349 ant_conf->fast_div_bias = 0x2;
1350 break;
1351 case 0x13: /* LNA2 A+B */
1352 ant_conf->fast_div_bias = 0x7;
1353 break;
1354 case 0x20: /* LNA1 A-B */
1355 ant_conf->fast_div_bias = 0x6;
1356 break;
1357 case 0x21: /* LNA1 LNA2 */
1358 ant_conf->fast_div_bias = 0x0;
1359 break;
1360 case 0x23: /* LNA1 A+B */
1361 ant_conf->fast_div_bias = 0x6;
1362 break;
1363 case 0x30: /* A+B A-B */
1364 ant_conf->fast_div_bias = 0x1;
1365 break;
1366 case 0x31: /* A+B LNA2 */
1367 ant_conf->fast_div_bias = 0x3b;
1368 break;
1369 case 0x32: /* A+B LNA1 */
1370 ant_conf->fast_div_bias = 0x3d;
1371 break;
1372 default:
1373 break;
1374 }
1375 } else if (ant_conf->div_group == 1) {
1376 /* Adjust the fast_div_bias based on main and alt_lna_conf */
1377 switch ((ant_conf->main_lna_conf << 4) |
1378 ant_conf->alt_lna_conf) {
1379 case 0x01: /* A-B LNA2 */
1380 ant_conf->fast_div_bias = 0x1;
1381 ant_conf->main_gaintb = 0;
1382 ant_conf->alt_gaintb = 0;
1383 break;
1384 case 0x02: /* A-B LNA1 */
1385 ant_conf->fast_div_bias = 0x1;
1386 ant_conf->main_gaintb = 0;
1387 ant_conf->alt_gaintb = 0;
1388 break;
1389 case 0x03: /* A-B A+B */
1390 ant_conf->fast_div_bias = 0x1;
1391 ant_conf->main_gaintb = 0;
1392 ant_conf->alt_gaintb = 0;
1393 break;
1394 case 0x10: /* LNA2 A-B */
1395 if (!(antcomb->scan) &&
1396 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1397 ant_conf->fast_div_bias = 0x3f;
1398 else
1399 ant_conf->fast_div_bias = 0x1;
1400 ant_conf->main_gaintb = 0;
1401 ant_conf->alt_gaintb = 0;
1402 break;
1403 case 0x12: /* LNA2 LNA1 */
1404 ant_conf->fast_div_bias = 0x1;
1405 ant_conf->main_gaintb = 0;
1406 ant_conf->alt_gaintb = 0;
1407 break;
1408 case 0x13: /* LNA2 A+B */
1409 if (!(antcomb->scan) &&
1410 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1411 ant_conf->fast_div_bias = 0x3f;
1412 else
1413 ant_conf->fast_div_bias = 0x1;
1414 ant_conf->main_gaintb = 0;
1415 ant_conf->alt_gaintb = 0;
1416 break;
1417 case 0x20: /* LNA1 A-B */
1418 if (!(antcomb->scan) &&
1419 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1420 ant_conf->fast_div_bias = 0x3f;
1421 else
1422 ant_conf->fast_div_bias = 0x1;
1423 ant_conf->main_gaintb = 0;
1424 ant_conf->alt_gaintb = 0;
1425 break;
1426 case 0x21: /* LNA1 LNA2 */
1427 ant_conf->fast_div_bias = 0x1;
1428 ant_conf->main_gaintb = 0;
1429 ant_conf->alt_gaintb = 0;
1430 break;
1431 case 0x23: /* LNA1 A+B */
1432 if (!(antcomb->scan) &&
1433 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1434 ant_conf->fast_div_bias = 0x3f;
1435 else
1436 ant_conf->fast_div_bias = 0x1;
1437 ant_conf->main_gaintb = 0;
1438 ant_conf->alt_gaintb = 0;
1439 break;
1440 case 0x30: /* A+B A-B */
1441 ant_conf->fast_div_bias = 0x1;
1442 ant_conf->main_gaintb = 0;
1443 ant_conf->alt_gaintb = 0;
1444 break;
1445 case 0x31: /* A+B LNA2 */
1446 ant_conf->fast_div_bias = 0x1;
1447 ant_conf->main_gaintb = 0;
1448 ant_conf->alt_gaintb = 0;
1449 break;
1450 case 0x32: /* A+B LNA1 */
1451 ant_conf->fast_div_bias = 0x1;
1452 ant_conf->main_gaintb = 0;
1453 ant_conf->alt_gaintb = 0;
1454 break;
1455 default:
1456 break;
1457 }
1458 } else if (ant_conf->div_group == 2) {
1459 /* Adjust the fast_div_bias based on main and alt_lna_conf */
1460 switch ((ant_conf->main_lna_conf << 4) |
1461 ant_conf->alt_lna_conf) {
1462 case 0x01: /* A-B LNA2 */
1463 ant_conf->fast_div_bias = 0x1;
1464 ant_conf->main_gaintb = 0;
1465 ant_conf->alt_gaintb = 0;
1466 break;
1467 case 0x02: /* A-B LNA1 */
1468 ant_conf->fast_div_bias = 0x1;
1469 ant_conf->main_gaintb = 0;
1470 ant_conf->alt_gaintb = 0;
1471 break;
1472 case 0x03: /* A-B A+B */
1473 ant_conf->fast_div_bias = 0x1;
1474 ant_conf->main_gaintb = 0;
1475 ant_conf->alt_gaintb = 0;
1476 break;
1477 case 0x10: /* LNA2 A-B */
1478 if (!(antcomb->scan) &&
1479 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1480 ant_conf->fast_div_bias = 0x1;
1481 else
1482 ant_conf->fast_div_bias = 0x2;
1483 ant_conf->main_gaintb = 0;
1484 ant_conf->alt_gaintb = 0;
1485 break;
1486 case 0x12: /* LNA2 LNA1 */
1487 ant_conf->fast_div_bias = 0x1;
1488 ant_conf->main_gaintb = 0;
1489 ant_conf->alt_gaintb = 0;
1490 break;
1491 case 0x13: /* LNA2 A+B */
1492 if (!(antcomb->scan) &&
1493 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1494 ant_conf->fast_div_bias = 0x1;
1495 else
1496 ant_conf->fast_div_bias = 0x2;
1497 ant_conf->main_gaintb = 0;
1498 ant_conf->alt_gaintb = 0;
1499 break;
1500 case 0x20: /* LNA1 A-B */
1501 if (!(antcomb->scan) &&
1502 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1503 ant_conf->fast_div_bias = 0x1;
1504 else
1505 ant_conf->fast_div_bias = 0x2;
1506 ant_conf->main_gaintb = 0;
1507 ant_conf->alt_gaintb = 0;
1508 break;
1509 case 0x21: /* LNA1 LNA2 */
1510 ant_conf->fast_div_bias = 0x1;
1511 ant_conf->main_gaintb = 0;
1512 ant_conf->alt_gaintb = 0;
1513 break;
1514 case 0x23: /* LNA1 A+B */
1515 if (!(antcomb->scan) &&
1516 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1517 ant_conf->fast_div_bias = 0x1;
1518 else
1519 ant_conf->fast_div_bias = 0x2;
1520 ant_conf->main_gaintb = 0;
1521 ant_conf->alt_gaintb = 0;
1522 break;
1523 case 0x30: /* A+B A-B */
1524 ant_conf->fast_div_bias = 0x1;
1525 ant_conf->main_gaintb = 0;
1526 ant_conf->alt_gaintb = 0;
1527 break;
1528 case 0x31: /* A+B LNA2 */
1529 ant_conf->fast_div_bias = 0x1;
1530 ant_conf->main_gaintb = 0;
1531 ant_conf->alt_gaintb = 0;
1532 break;
1533 case 0x32: /* A+B LNA1 */
1534 ant_conf->fast_div_bias = 0x1;
1535 ant_conf->main_gaintb = 0;
1536 ant_conf->alt_gaintb = 0;
1537 break;
1538 default:
1539 break;
1540 }
1541 }
1542 }
1543
1544 /* Antenna diversity and combining */
1545 static void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs)
1546 {
1547 struct ath_hw_antcomb_conf div_ant_conf;
1548 struct ath_ant_comb *antcomb = &sc->ant_comb;
1549 int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set;
1550 int curr_main_set;
1551 int main_rssi = rs->rs_rssi_ctl0;
1552 int alt_rssi = rs->rs_rssi_ctl1;
1553 int rx_ant_conf, main_ant_conf;
1554 bool short_scan = false;
1555
1556 rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) &
1557 ATH_ANT_RX_MASK;
1558 main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) &
1559 ATH_ANT_RX_MASK;
1560
1561 /* Record packet only when both main_rssi and alt_rssi is positive */
1562 if (main_rssi > 0 && alt_rssi > 0) {
1563 antcomb->total_pkt_count++;
1564 antcomb->main_total_rssi += main_rssi;
1565 antcomb->alt_total_rssi += alt_rssi;
1566 if (main_ant_conf == rx_ant_conf)
1567 antcomb->main_recv_cnt++;
1568 else
1569 antcomb->alt_recv_cnt++;
1570 }
1571
1572 /* Short scan check */
1573 if (antcomb->scan && antcomb->alt_good) {
1574 if (time_after(jiffies, antcomb->scan_start_time +
1575 msecs_to_jiffies(ATH_ANT_DIV_COMB_SHORT_SCAN_INTR)))
1576 short_scan = true;
1577 else
1578 if (antcomb->total_pkt_count ==
1579 ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT) {
1580 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1581 antcomb->total_pkt_count);
1582 if (alt_ratio < ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
1583 short_scan = true;
1584 }
1585 }
1586
1587 if (((antcomb->total_pkt_count < ATH_ANT_DIV_COMB_MAX_PKTCOUNT) ||
1588 rs->rs_moreaggr) && !short_scan)
1589 return;
1590
1591 if (antcomb->total_pkt_count) {
1592 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1593 antcomb->total_pkt_count);
1594 main_rssi_avg = (antcomb->main_total_rssi /
1595 antcomb->total_pkt_count);
1596 alt_rssi_avg = (antcomb->alt_total_rssi /
1597 antcomb->total_pkt_count);
1598 }
1599
1600
1601 ath9k_hw_antdiv_comb_conf_get(sc->sc_ah, &div_ant_conf);
1602 curr_alt_set = div_ant_conf.alt_lna_conf;
1603 curr_main_set = div_ant_conf.main_lna_conf;
1604
1605 antcomb->count++;
1606
1607 if (antcomb->count == ATH_ANT_DIV_COMB_MAX_COUNT) {
1608 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) {
1609 ath_lnaconf_alt_good_scan(antcomb, div_ant_conf,
1610 main_rssi_avg);
1611 antcomb->alt_good = true;
1612 } else {
1613 antcomb->alt_good = false;
1614 }
1615
1616 antcomb->count = 0;
1617 antcomb->scan = true;
1618 antcomb->scan_not_start = true;
1619 }
1620
1621 if (!antcomb->scan) {
1622 if (ath_ant_div_comb_alt_check(div_ant_conf.div_group,
1623 alt_ratio, curr_main_set, curr_alt_set,
1624 alt_rssi_avg, main_rssi_avg)) {
1625 if (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) {
1626 /* Switch main and alt LNA */
1627 div_ant_conf.main_lna_conf =
1628 ATH_ANT_DIV_COMB_LNA2;
1629 div_ant_conf.alt_lna_conf =
1630 ATH_ANT_DIV_COMB_LNA1;
1631 } else if (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) {
1632 div_ant_conf.main_lna_conf =
1633 ATH_ANT_DIV_COMB_LNA1;
1634 div_ant_conf.alt_lna_conf =
1635 ATH_ANT_DIV_COMB_LNA2;
1636 }
1637
1638 goto div_comb_done;
1639 } else if ((curr_alt_set != ATH_ANT_DIV_COMB_LNA1) &&
1640 (curr_alt_set != ATH_ANT_DIV_COMB_LNA2)) {
1641 /* Set alt to another LNA */
1642 if (curr_main_set == ATH_ANT_DIV_COMB_LNA2)
1643 div_ant_conf.alt_lna_conf =
1644 ATH_ANT_DIV_COMB_LNA1;
1645 else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1)
1646 div_ant_conf.alt_lna_conf =
1647 ATH_ANT_DIV_COMB_LNA2;
1648
1649 goto div_comb_done;
1650 }
1651
1652 if ((alt_rssi_avg < (main_rssi_avg +
1653 div_ant_conf.lna1_lna2_delta)))
1654 goto div_comb_done;
1655 }
1656
1657 if (!antcomb->scan_not_start) {
1658 switch (curr_alt_set) {
1659 case ATH_ANT_DIV_COMB_LNA2:
1660 antcomb->rssi_lna2 = alt_rssi_avg;
1661 antcomb->rssi_lna1 = main_rssi_avg;
1662 antcomb->scan = true;
1663 /* set to A+B */
1664 div_ant_conf.main_lna_conf =
1665 ATH_ANT_DIV_COMB_LNA1;
1666 div_ant_conf.alt_lna_conf =
1667 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1668 break;
1669 case ATH_ANT_DIV_COMB_LNA1:
1670 antcomb->rssi_lna1 = alt_rssi_avg;
1671 antcomb->rssi_lna2 = main_rssi_avg;
1672 antcomb->scan = true;
1673 /* set to A+B */
1674 div_ant_conf.main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1675 div_ant_conf.alt_lna_conf =
1676 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1677 break;
1678 case ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2:
1679 antcomb->rssi_add = alt_rssi_avg;
1680 antcomb->scan = true;
1681 /* set to A-B */
1682 div_ant_conf.alt_lna_conf =
1683 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1684 break;
1685 case ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2:
1686 antcomb->rssi_sub = alt_rssi_avg;
1687 antcomb->scan = false;
1688 if (antcomb->rssi_lna2 >
1689 (antcomb->rssi_lna1 +
1690 ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)) {
1691 /* use LNA2 as main LNA */
1692 if ((antcomb->rssi_add > antcomb->rssi_lna1) &&
1693 (antcomb->rssi_add > antcomb->rssi_sub)) {
1694 /* set to A+B */
1695 div_ant_conf.main_lna_conf =
1696 ATH_ANT_DIV_COMB_LNA2;
1697 div_ant_conf.alt_lna_conf =
1698 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1699 } else if (antcomb->rssi_sub >
1700 antcomb->rssi_lna1) {
1701 /* set to A-B */
1702 div_ant_conf.main_lna_conf =
1703 ATH_ANT_DIV_COMB_LNA2;
1704 div_ant_conf.alt_lna_conf =
1705 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1706 } else {
1707 /* set to LNA1 */
1708 div_ant_conf.main_lna_conf =
1709 ATH_ANT_DIV_COMB_LNA2;
1710 div_ant_conf.alt_lna_conf =
1711 ATH_ANT_DIV_COMB_LNA1;
1712 }
1713 } else {
1714 /* use LNA1 as main LNA */
1715 if ((antcomb->rssi_add > antcomb->rssi_lna2) &&
1716 (antcomb->rssi_add > antcomb->rssi_sub)) {
1717 /* set to A+B */
1718 div_ant_conf.main_lna_conf =
1719 ATH_ANT_DIV_COMB_LNA1;
1720 div_ant_conf.alt_lna_conf =
1721 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1722 } else if (antcomb->rssi_sub >
1723 antcomb->rssi_lna1) {
1724 /* set to A-B */
1725 div_ant_conf.main_lna_conf =
1726 ATH_ANT_DIV_COMB_LNA1;
1727 div_ant_conf.alt_lna_conf =
1728 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1729 } else {
1730 /* set to LNA2 */
1731 div_ant_conf.main_lna_conf =
1732 ATH_ANT_DIV_COMB_LNA1;
1733 div_ant_conf.alt_lna_conf =
1734 ATH_ANT_DIV_COMB_LNA2;
1735 }
1736 }
1737 break;
1738 default:
1739 break;
1740 }
1741 } else {
1742 if (!antcomb->alt_good) {
1743 antcomb->scan_not_start = false;
1744 /* Set alt to another LNA */
1745 if (curr_main_set == ATH_ANT_DIV_COMB_LNA2) {
1746 div_ant_conf.main_lna_conf =
1747 ATH_ANT_DIV_COMB_LNA2;
1748 div_ant_conf.alt_lna_conf =
1749 ATH_ANT_DIV_COMB_LNA1;
1750 } else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1) {
1751 div_ant_conf.main_lna_conf =
1752 ATH_ANT_DIV_COMB_LNA1;
1753 div_ant_conf.alt_lna_conf =
1754 ATH_ANT_DIV_COMB_LNA2;
1755 }
1756 goto div_comb_done;
1757 }
1758 }
1759
1760 ath_select_ant_div_from_quick_scan(antcomb, &div_ant_conf,
1761 main_rssi_avg, alt_rssi_avg,
1762 alt_ratio);
1763
1764 antcomb->quick_scan_cnt++;
1765
1766 div_comb_done:
1767 ath_ant_div_conf_fast_divbias(&div_ant_conf, antcomb, alt_ratio);
1768 ath9k_hw_antdiv_comb_conf_set(sc->sc_ah, &div_ant_conf);
1769
1770 antcomb->scan_start_time = jiffies;
1771 antcomb->total_pkt_count = 0;
1772 antcomb->main_total_rssi = 0;
1773 antcomb->alt_total_rssi = 0;
1774 antcomb->main_recv_cnt = 0;
1775 antcomb->alt_recv_cnt = 0;
1776 }
1777
1778 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
1779 {
1780 struct ath_buf *bf;
1781 struct sk_buff *skb = NULL, *requeue_skb, *hdr_skb;
1782 struct ieee80211_rx_status *rxs;
1783 struct ath_hw *ah = sc->sc_ah;
1784 struct ath_common *common = ath9k_hw_common(ah);
1785 struct ieee80211_hw *hw = sc->hw;
1786 struct ieee80211_hdr *hdr;
1787 int retval;
1788 bool decrypt_error = false;
1789 struct ath_rx_status rs;
1790 enum ath9k_rx_qtype qtype;
1791 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1792 int dma_type;
1793 u8 rx_status_len = ah->caps.rx_status_len;
1794 u64 tsf = 0;
1795 u32 tsf_lower = 0;
1796 unsigned long flags;
1797
1798 if (edma)
1799 dma_type = DMA_BIDIRECTIONAL;
1800 else
1801 dma_type = DMA_FROM_DEVICE;
1802
1803 qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
1804 spin_lock_bh(&sc->rx.rxbuflock);
1805
1806 tsf = ath9k_hw_gettsf64(ah);
1807 tsf_lower = tsf & 0xffffffff;
1808
1809 do {
1810 /* If handling rx interrupt and flush is in progress => exit */
1811 if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
1812 break;
1813
1814 memset(&rs, 0, sizeof(rs));
1815 if (edma)
1816 bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
1817 else
1818 bf = ath_get_next_rx_buf(sc, &rs);
1819
1820 if (!bf)
1821 break;
1822
1823 skb = bf->bf_mpdu;
1824 if (!skb)
1825 continue;
1826
1827 /*
1828 * Take frame header from the first fragment and RX status from
1829 * the last one.
1830 */
1831 if (sc->rx.frag)
1832 hdr_skb = sc->rx.frag;
1833 else
1834 hdr_skb = skb;
1835
1836 hdr = (struct ieee80211_hdr *) (hdr_skb->data + rx_status_len);
1837 rxs = IEEE80211_SKB_RXCB(hdr_skb);
1838 if (ieee80211_is_beacon(hdr->frame_control) &&
1839 !compare_ether_addr(hdr->addr3, common->curbssid))
1840 rs.is_mybeacon = true;
1841 else
1842 rs.is_mybeacon = false;
1843
1844 ath_debug_stat_rx(sc, &rs);
1845
1846 /*
1847 * If we're asked to flush receive queue, directly
1848 * chain it back at the queue without processing it.
1849 */
1850 if (sc->sc_flags & SC_OP_RXFLUSH)
1851 goto requeue_drop_frag;
1852
1853 retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs,
1854 rxs, &decrypt_error);
1855 if (retval)
1856 goto requeue_drop_frag;
1857
1858 rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp;
1859 if (rs.rs_tstamp > tsf_lower &&
1860 unlikely(rs.rs_tstamp - tsf_lower > 0x10000000))
1861 rxs->mactime -= 0x100000000ULL;
1862
1863 if (rs.rs_tstamp < tsf_lower &&
1864 unlikely(tsf_lower - rs.rs_tstamp > 0x10000000))
1865 rxs->mactime += 0x100000000ULL;
1866
1867 /* Ensure we always have an skb to requeue once we are done
1868 * processing the current buffer's skb */
1869 requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC);
1870
1871 /* If there is no memory we ignore the current RX'd frame,
1872 * tell hardware it can give us a new frame using the old
1873 * skb and put it at the tail of the sc->rx.rxbuf list for
1874 * processing. */
1875 if (!requeue_skb)
1876 goto requeue_drop_frag;
1877
1878 /* Unmap the frame */
1879 dma_unmap_single(sc->dev, bf->bf_buf_addr,
1880 common->rx_bufsize,
1881 dma_type);
1882
1883 skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
1884 if (ah->caps.rx_status_len)
1885 skb_pull(skb, ah->caps.rx_status_len);
1886
1887 if (!rs.rs_more)
1888 ath9k_rx_skb_postprocess(common, hdr_skb, &rs,
1889 rxs, decrypt_error);
1890
1891 /* We will now give hardware our shiny new allocated skb */
1892 bf->bf_mpdu = requeue_skb;
1893 bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
1894 common->rx_bufsize,
1895 dma_type);
1896 if (unlikely(dma_mapping_error(sc->dev,
1897 bf->bf_buf_addr))) {
1898 dev_kfree_skb_any(requeue_skb);
1899 bf->bf_mpdu = NULL;
1900 bf->bf_buf_addr = 0;
1901 ath_err(common, "dma_mapping_error() on RX\n");
1902 ieee80211_rx(hw, skb);
1903 break;
1904 }
1905
1906 if (rs.rs_more) {
1907 /*
1908 * rs_more indicates chained descriptors which can be
1909 * used to link buffers together for a sort of
1910 * scatter-gather operation.
1911 */
1912 if (sc->rx.frag) {
1913 /* too many fragments - cannot handle frame */
1914 dev_kfree_skb_any(sc->rx.frag);
1915 dev_kfree_skb_any(skb);
1916 skb = NULL;
1917 }
1918 sc->rx.frag = skb;
1919 goto requeue;
1920 }
1921
1922 if (sc->rx.frag) {
1923 int space = skb->len - skb_tailroom(hdr_skb);
1924
1925 sc->rx.frag = NULL;
1926
1927 if (pskb_expand_head(hdr_skb, 0, space, GFP_ATOMIC) < 0) {
1928 dev_kfree_skb(skb);
1929 goto requeue_drop_frag;
1930 }
1931
1932 skb_copy_from_linear_data(skb, skb_put(hdr_skb, skb->len),
1933 skb->len);
1934 dev_kfree_skb_any(skb);
1935 skb = hdr_skb;
1936 }
1937
1938 /*
1939 * change the default rx antenna if rx diversity chooses the
1940 * other antenna 3 times in a row.
1941 */
1942 if (sc->rx.defant != rs.rs_antenna) {
1943 if (++sc->rx.rxotherant >= 3)
1944 ath_setdefantenna(sc, rs.rs_antenna);
1945 } else {
1946 sc->rx.rxotherant = 0;
1947 }
1948
1949 if (rxs->flag & RX_FLAG_MMIC_STRIPPED)
1950 skb_trim(skb, skb->len - 8);
1951
1952 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1953
1954 if ((sc->ps_flags & (PS_WAIT_FOR_BEACON |
1955 PS_WAIT_FOR_CAB |
1956 PS_WAIT_FOR_PSPOLL_DATA)) ||
1957 ath9k_check_auto_sleep(sc))
1958 ath_rx_ps(sc, skb);
1959 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1960
1961 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx == 3)
1962 ath_ant_comb_scan(sc, &rs);
1963
1964 ieee80211_rx(hw, skb);
1965
1966 requeue_drop_frag:
1967 if (sc->rx.frag) {
1968 dev_kfree_skb_any(sc->rx.frag);
1969 sc->rx.frag = NULL;
1970 }
1971 requeue:
1972 if (edma) {
1973 list_add_tail(&bf->list, &sc->rx.rxbuf);
1974 ath_rx_edma_buf_link(sc, qtype);
1975 } else {
1976 list_move_tail(&bf->list, &sc->rx.rxbuf);
1977 ath_rx_buf_link(sc, bf);
1978 if (!flush)
1979 ath9k_hw_rxena(ah);
1980 }
1981 } while (1);
1982
1983 spin_unlock_bh(&sc->rx.rxbuflock);
1984
1985 if (!(ah->imask & ATH9K_INT_RXEOL)) {
1986 ah->imask |= (ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
1987 ath9k_hw_set_interrupts(ah, ah->imask);
1988 }
1989
1990 return 0;
1991 }
Linus' kernel tree