drivers/staging/dt3155/dt3155_io.h

   1 /*
   2
   3 Copyright 1996,2002 Gregory D. Hager, Alfred A. Rizzi, Noah J. Cowan,
   4                     Jason Lapenta, Scott Smedley
   5
   6 This file is part of the DT3155 Device Driver.
   7
   8 The DT3155 Device Driver is free software; you can redistribute it
   9 and/or modify it under the terms of the GNU General Public License as
  10 published by the Free Software Foundation; either version 2 of the
  11 License, or (at your option) any later version.
  12
  13 The DT3155 Device Driver is distributed in the hope that it will be
  14 useful, but WITHOUT ANY WARRANTY; without even the implied warranty
  15 of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with the DT3155 Device Driver; if not, write to the Free
  20 Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 MA 02111-1307 USA
  22
  23
  24 -- Changes --
  25
  26   Date     Programmer  Description of changes made
  27   -------------------------------------------------------------------
  28   24-Jul-2002 SS       GPL licence.
  29
  30 */
  31
  32 /* This code is a modified version of examples provided by Data Translations.*/
  33
  34 #ifndef DT3155_IO_INC
  35 #define DT3155_IO_INC
  36
  37 /***************** 32 bit register globals  **************/
  38
  39 /*  offsets for 32-bit memory mapped registers */
  40
  41 #define EVEN_DMA_START          0x000
  42 #define ODD_DMA_START           0x00C
  43 #define EVEN_DMA_STRIDE         0x018
  44 #define ODD_DMA_STRIDE          0x024
  45 #define EVEN_PIXEL_FMT          0x030
  46 #define ODD_PIXEL_FMT           0x034
  47 #define FIFO_TRIGGER            0x038
  48 #define XFER_MODE               0x03C
  49 #define CSR1                    0x040
  50 #define RETRY_WAIT_CNT          0x044
  51 #define INT_CSR                 0x048
  52 #define EVEN_FLD_MASK           0x04C
  53 #define ODD_FLD_MASK            0x050
  54 #define MASK_LENGTH             0x054
  55 #define FIFO_FLAG_CNT           0x058
  56 #define IIC_CLK_DUR             0x05C
  57 #define IIC_CSR1                0x060
  58 #define IIC_CSR2                0x064
  59 #define EVEN_DMA_UPPR_LMT       0x08C
  60 #define ODD_DMA_UPPR_LMT        0x090
  61
  62 #define CLK_DUR_VAL             0x01010101
  63
  64
  65
  66 /******** Assignments and Typedefs for 32 bit Memory Mapped Registers ********/
  67
  68 typedef union fifo_trigger_tag {
  69         u32   reg;
  70         struct {
  71                 u32 PACKED:6;
  72                 u32       :9;
  73                 u32 PLANER:7;
  74                 u32       :9;
  75         } fld;
  76 } FIFO_TRIGGER_R;
  77
  78 typedef union xfer_mode_tag {
  79         u32   reg;
  80         struct {
  81                 u32             :2;
  82                 u32 FIELD_TOGGLE:1;
  83                 u32             :5;
  84                 u32             :2;
  85                 u32             :22;
  86         } fld;
  87 } XFER_MODE_R;
  88
  89 typedef union csr1_tag {
  90         u32   reg;
  91         struct {
  92                 u32 CAP_CONT_EVE:1;
  93                 u32 CAP_CONT_ODD:1;
  94                 u32 CAP_SNGL_EVE:1;
  95                 u32 CAP_SNGL_ODD:1;
  96                 u32 FLD_DN_EVE  :1;
  97                 u32 FLD_DN_ODD  :1;
  98                 u32 SRST        :1;
  99                 u32 FIFO_EN     :1;
 100                 u32 FLD_CRPT_EVE:1;
 101                 u32 FLD_CRPT_ODD:1;
 102                 u32 ADDR_ERR_EVE:1;
 103                 u32 ADDR_ERR_ODD:1;
 104                 u32 CRPT_DIS    :1;
 105                 u32 RANGE_EN    :1;
 106                 u32             :16;
 107         } fld;
 108 } CSR1_R;
 109
 110 typedef union retry_wait_cnt_tag {
 111         u32   reg;
 112         struct {
 113                 u32 RTRY_WAIT_CNT:8;
 114                 u32              :24;
 115         } fld;
 116 } RETRY_WAIT_CNT_R;
 117
 118 typedef union int_csr_tag {
 119         u32   reg;
 120         struct {
 121                 u32 FLD_END_EVE   :1;
 122                 u32 FLD_END_ODD   :1;
 123                 u32 FLD_START     :1;
 124                 u32               :5;
 125                 u32 FLD_END_EVE_EN:1;
 126                 u32 FLD_END_ODD_EN:1;
 127                 u32 FLD_START_EN  :1;
 128                 u32               :21;
 129         } fld;
 130 } INT_CSR_R;
 131
 132 typedef union mask_length_tag {
 133         u32   reg;
 134         struct {
 135                 u32 MASK_LEN_EVE:5;
 136                 u32             :11;
 137                 u32 MASK_LEN_ODD:5;
 138                 u32             :11;
 139         } fld;
 140 } MASK_LENGTH_R;
 141
 142 typedef union fifo_flag_cnt_tag {
 143         u32   reg;
 144         struct {
 145                 u32 AF_COUNT:7;
 146                 u32         :9;
 147                 u32 AE_COUNT:7;
 148                 u32         :9;
 149         } fld;
 150 } FIFO_FLAG_CNT_R;
 151
 152 typedef union iic_clk_dur {
 153         u32   reg;
 154         struct {
 155                 u32 PHASE_1:8;
 156                 u32 PHASE_2:8;
 157                 u32 PHASE_3:8;
 158                 u32 PHASE_4:8;
 159         } fld;
 160 } IIC_CLK_DUR_R;
 161
 162 typedef union iic_csr1_tag {
 163         u32   reg;
 164         struct {
 165                 u32 AUTO_EN     :1;
 166                 u32 BYPASS      :1;
 167                 u32 SDA_OUT     :1;
 168                 u32 SCL_OUT     :1;
 169                 u32             :4;
 170                 u32 AUTO_ABORT  :1;
 171                 u32 DIRECT_ABORT:1;
 172                 u32 SDA_IN      :1;
 173                 u32 SCL_IN      :1;
 174                 u32             :4;
 175                 u32 AUTO_ADDR   :8;
 176                 u32 RD_DATA     :8;
 177         } fld;
 178 } IIC_CSR1_R;
 179
 180 /**********************************
 181  * iic_csr2_tag
 182  */
 183 typedef union iic_csr2_tag {
 184         u32   reg;
 185         struct {
 186                 u32 DIR_WR_DATA :8;
 187                 u32 DIR_SUB_ADDR:8;
 188                 u32 DIR_RD      :1;
 189                 u32 DIR_ADDR    :7;
 190                 u32 NEW_CYCLE   :1;
 191                 u32             :7;
 192         } fld;
 193 }  IIC_CSR2_R;
 194
 195 /* use for both EVEN and ODD DMA UPPER LIMITS */
 196
 197 /*
 198  * dma_upper_lmt_tag
 199  */
 200 typedef union dma_upper_lmt_tag   {
 201         u32 reg;
 202         struct {
 203                 u32 DMA_UPPER_LMT_VAL:24;
 204                 u32                  :8;
 205         } fld;
 206 } DMA_UPPER_LMT_R;
 207
 208
 209 /***************** 8 bit I2C register globals  ***********/
 210 #define CSR2            0x010   /* indices of 8-bit I2C mapped reg's*/
 211 #define EVEN_CSR        0x011
 212 #define ODD_CSR         0x012
 213 #define CONFIG          0x013
 214 #define DT_ID           0x01F
 215 #define X_CLIP_START    0x020
 216 #define Y_CLIP_START    0x022
 217 #define X_CLIP_END      0x024
 218 #define Y_CLIP_END      0x026
 219 #define AD_ADDR         0x030
 220 #define AD_LUT          0x031
 221 #define AD_CMD          0x032
 222 #define DIG_OUT         0x040
 223 #define PM_LUT_ADDR     0x050
 224 #define PM_LUT_DATA     0x051
 225
 226
 227 /******** Assignments and Typedefs for 8 bit I2C Registers********************/
 228
 229 typedef union i2c_csr2_tag {
 230         u8 reg;
 231         struct {
 232                 u8 CHROM_FIL:1;
 233                 u8 SYNC_SNTL:1;
 234                 u8 HZ50:1;
 235                 u8 SYNC_PRESENT:1;
 236                 u8 BUSY_EVE:1;
 237                 u8 BUSY_ODD:1;
 238                 u8 DISP_PASS:1;
 239         } fld;
 240 } I2C_CSR2;
 241
 242 typedef union i2c_even_csr_tag {
 243         u8    reg;
 244         struct {
 245                 u8 DONE_EVE :1;
 246                 u8 SNGL_EVE :1;
 247                 u8 ERROR_EVE:1;
 248                 u8          :5;
 249         } fld;
 250 } I2C_EVEN_CSR;
 251
 252 typedef union i2c_odd_csr_tag {
 253         u8 reg;
 254         struct {
 255                 u8 DONE_ODD:1;
 256                 u8 SNGL_ODD:1;
 257                 u8 ERROR_ODD:1;
 258                 u8 :5;
 259         } fld;
 260 } I2C_ODD_CSR;
 261
 262 typedef union i2c_config_tag {
 263         u8 reg;
 264         struct {
 265                 u8 ACQ_MODE:2;
 266                 u8 EXT_TRIG_EN:1;
 267                 u8 EXT_TRIG_POL:1;
 268                 u8 H_SCALE:1;
 269                 u8 CLIP:1;
 270                 u8 PM_LUT_SEL:1;
 271                 u8 PM_LUT_PGM:1;
 272         } fld;
 273 } I2C_CONFIG;
 274
 275
 276 typedef union i2c_ad_cmd_tag {
 277         /* bits can have 3 different meanings depending on value of AD_ADDR */
 278         u8 reg;
 279         /* Bt252 Command Register if AD_ADDR = 00h */
 280         struct {
 281                 u8             :2;
 282                 u8 SYNC_LVL_SEL:2;
 283                 u8 SYNC_CNL_SEL:2;
 284                 u8 DIGITIZE_CNL_SEL1:2;
 285                 } bt252_command;
 286
 287         /* Bt252 IOUT0 register if AD_ADDR = 01h */
 288         struct {
 289                 u8 IOUT_DATA:8;
 290         } bt252_iout0;
 291
 292         /* BT252 IOUT1 register if AD_ADDR = 02h */
 293         struct {
 294                 u8 IOUT_DATA:8;
 295         } bt252_iout1;
 296 } I2C_AD_CMD;
 297
 298
 299 /* access 8-bit IIC registers */
 300
 301 extern int ReadI2C(void __iomem *mmio, u_short wIregIndex, u8 *byVal);
 302 extern int WriteI2C(void __iomem *mmio, u_short wIregIndex, u8 byVal);
 303
 304 #endif