2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
54 #include <net/ieee80211_radiotap.h>
56 #include <asm/unaligned.h>
62 static int ath5k_calinterval
= 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63 static int modparam_nohwcrypt
;
64 module_param_named(nohwcrypt
, modparam_nohwcrypt
, int, 0444);
65 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
73 MODULE_AUTHOR("Jiri Slaby");
74 MODULE_AUTHOR("Nick Kossifidis");
75 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
76 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
77 MODULE_LICENSE("Dual BSD/GPL");
78 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
82 static struct pci_device_id ath5k_pci_id_table
[] __devinitdata
= {
83 { PCI_VDEVICE(ATHEROS
, 0x0207), .driver_data
= AR5K_AR5210
}, /* 5210 early */
84 { PCI_VDEVICE(ATHEROS
, 0x0007), .driver_data
= AR5K_AR5210
}, /* 5210 */
85 { PCI_VDEVICE(ATHEROS
, 0x0011), .driver_data
= AR5K_AR5211
}, /* 5311 - this is on AHB bus !*/
86 { PCI_VDEVICE(ATHEROS
, 0x0012), .driver_data
= AR5K_AR5211
}, /* 5211 */
87 { PCI_VDEVICE(ATHEROS
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 5212 */
88 { PCI_VDEVICE(3COM_2
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 3com 5212 */
89 { PCI_VDEVICE(3COM
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 3com 3CRDAG675 5212 */
90 { PCI_VDEVICE(ATHEROS
, 0x1014), .driver_data
= AR5K_AR5212
}, /* IBM minipci 5212 */
91 { PCI_VDEVICE(ATHEROS
, 0x0014), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS
, 0x0015), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS
, 0x0016), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS
, 0x0017), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
95 { PCI_VDEVICE(ATHEROS
, 0x0018), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS
, 0x0019), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS
, 0x001a), .driver_data
= AR5K_AR5212
}, /* 2413 Griffin-lite */
98 { PCI_VDEVICE(ATHEROS
, 0x001b), .driver_data
= AR5K_AR5212
}, /* 5413 Eagle */
99 { PCI_VDEVICE(ATHEROS
, 0x001c), .driver_data
= AR5K_AR5212
}, /* PCI-E cards */
100 { PCI_VDEVICE(ATHEROS
, 0x001d), .driver_data
= AR5K_AR5212
}, /* 2417 Nala */
103 MODULE_DEVICE_TABLE(pci
, ath5k_pci_id_table
);
106 static struct ath5k_srev_name srev_names
[] = {
107 { "5210", AR5K_VERSION_MAC
, AR5K_SREV_AR5210
},
108 { "5311", AR5K_VERSION_MAC
, AR5K_SREV_AR5311
},
109 { "5311A", AR5K_VERSION_MAC
, AR5K_SREV_AR5311A
},
110 { "5311B", AR5K_VERSION_MAC
, AR5K_SREV_AR5311B
},
111 { "5211", AR5K_VERSION_MAC
, AR5K_SREV_AR5211
},
112 { "5212", AR5K_VERSION_MAC
, AR5K_SREV_AR5212
},
113 { "5213", AR5K_VERSION_MAC
, AR5K_SREV_AR5213
},
114 { "5213A", AR5K_VERSION_MAC
, AR5K_SREV_AR5213A
},
115 { "2413", AR5K_VERSION_MAC
, AR5K_SREV_AR2413
},
116 { "2414", AR5K_VERSION_MAC
, AR5K_SREV_AR2414
},
117 { "5424", AR5K_VERSION_MAC
, AR5K_SREV_AR5424
},
118 { "5413", AR5K_VERSION_MAC
, AR5K_SREV_AR5413
},
119 { "5414", AR5K_VERSION_MAC
, AR5K_SREV_AR5414
},
120 { "2415", AR5K_VERSION_MAC
, AR5K_SREV_AR2415
},
121 { "5416", AR5K_VERSION_MAC
, AR5K_SREV_AR5416
},
122 { "5418", AR5K_VERSION_MAC
, AR5K_SREV_AR5418
},
123 { "2425", AR5K_VERSION_MAC
, AR5K_SREV_AR2425
},
124 { "2417", AR5K_VERSION_MAC
, AR5K_SREV_AR2417
},
125 { "xxxxx", AR5K_VERSION_MAC
, AR5K_SREV_UNKNOWN
},
126 { "5110", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5110
},
127 { "5111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111
},
128 { "5111A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111A
},
129 { "2111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2111
},
130 { "5112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112
},
131 { "5112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112A
},
132 { "5112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112B
},
133 { "2112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112
},
134 { "2112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112A
},
135 { "2112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112B
},
136 { "2413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2413
},
137 { "5413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5413
},
138 { "2316", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2316
},
139 { "2317", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2317
},
140 { "5424", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5424
},
141 { "5133", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5133
},
142 { "xxxxx", AR5K_VERSION_RAD
, AR5K_SREV_UNKNOWN
},
145 static struct ieee80211_rate ath5k_rates
[] = {
147 .hw_value
= ATH5K_RATE_CODE_1M
, },
149 .hw_value
= ATH5K_RATE_CODE_2M
,
150 .hw_value_short
= ATH5K_RATE_CODE_2M
| AR5K_SET_SHORT_PREAMBLE
,
151 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
153 .hw_value
= ATH5K_RATE_CODE_5_5M
,
154 .hw_value_short
= ATH5K_RATE_CODE_5_5M
| AR5K_SET_SHORT_PREAMBLE
,
155 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
157 .hw_value
= ATH5K_RATE_CODE_11M
,
158 .hw_value_short
= ATH5K_RATE_CODE_11M
| AR5K_SET_SHORT_PREAMBLE
,
159 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
161 .hw_value
= ATH5K_RATE_CODE_6M
,
164 .hw_value
= ATH5K_RATE_CODE_9M
,
167 .hw_value
= ATH5K_RATE_CODE_12M
,
170 .hw_value
= ATH5K_RATE_CODE_18M
,
173 .hw_value
= ATH5K_RATE_CODE_24M
,
176 .hw_value
= ATH5K_RATE_CODE_36M
,
179 .hw_value
= ATH5K_RATE_CODE_48M
,
182 .hw_value
= ATH5K_RATE_CODE_54M
,
188 * Prototypes - PCI stack related functions
190 static int __devinit
ath5k_pci_probe(struct pci_dev
*pdev
,
191 const struct pci_device_id
*id
);
192 static void __devexit
ath5k_pci_remove(struct pci_dev
*pdev
);
194 static int ath5k_pci_suspend(struct pci_dev
*pdev
,
196 static int ath5k_pci_resume(struct pci_dev
*pdev
);
198 #define ath5k_pci_suspend NULL
199 #define ath5k_pci_resume NULL
200 #endif /* CONFIG_PM */
202 static struct pci_driver ath5k_pci_driver
= {
203 .name
= KBUILD_MODNAME
,
204 .id_table
= ath5k_pci_id_table
,
205 .probe
= ath5k_pci_probe
,
206 .remove
= __devexit_p(ath5k_pci_remove
),
207 .suspend
= ath5k_pci_suspend
,
208 .resume
= ath5k_pci_resume
,
214 * Prototypes - MAC 802.11 stack related functions
216 static int ath5k_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
);
217 static int ath5k_reset(struct ath5k_softc
*sc
, bool stop
, bool change_channel
);
218 static int ath5k_reset_wake(struct ath5k_softc
*sc
);
219 static int ath5k_start(struct ieee80211_hw
*hw
);
220 static void ath5k_stop(struct ieee80211_hw
*hw
);
221 static int ath5k_add_interface(struct ieee80211_hw
*hw
,
222 struct ieee80211_if_init_conf
*conf
);
223 static void ath5k_remove_interface(struct ieee80211_hw
*hw
,
224 struct ieee80211_if_init_conf
*conf
);
225 static int ath5k_config(struct ieee80211_hw
*hw
, u32 changed
);
226 static int ath5k_config_interface(struct ieee80211_hw
*hw
,
227 struct ieee80211_vif
*vif
,
228 struct ieee80211_if_conf
*conf
);
229 static void ath5k_configure_filter(struct ieee80211_hw
*hw
,
230 unsigned int changed_flags
,
231 unsigned int *new_flags
,
232 int mc_count
, struct dev_mc_list
*mclist
);
233 static int ath5k_set_key(struct ieee80211_hw
*hw
,
234 enum set_key_cmd cmd
,
235 struct ieee80211_vif
*vif
, struct ieee80211_sta
*sta
,
236 struct ieee80211_key_conf
*key
);
237 static int ath5k_get_stats(struct ieee80211_hw
*hw
,
238 struct ieee80211_low_level_stats
*stats
);
239 static int ath5k_get_tx_stats(struct ieee80211_hw
*hw
,
240 struct ieee80211_tx_queue_stats
*stats
);
241 static u64
ath5k_get_tsf(struct ieee80211_hw
*hw
);
242 static void ath5k_reset_tsf(struct ieee80211_hw
*hw
);
243 static int ath5k_beacon_update(struct ath5k_softc
*sc
,
244 struct sk_buff
*skb
);
245 static void ath5k_bss_info_changed(struct ieee80211_hw
*hw
,
246 struct ieee80211_vif
*vif
,
247 struct ieee80211_bss_conf
*bss_conf
,
250 static struct ieee80211_ops ath5k_hw_ops
= {
252 .start
= ath5k_start
,
254 .add_interface
= ath5k_add_interface
,
255 .remove_interface
= ath5k_remove_interface
,
256 .config
= ath5k_config
,
257 .config_interface
= ath5k_config_interface
,
258 .configure_filter
= ath5k_configure_filter
,
259 .set_key
= ath5k_set_key
,
260 .get_stats
= ath5k_get_stats
,
262 .get_tx_stats
= ath5k_get_tx_stats
,
263 .get_tsf
= ath5k_get_tsf
,
264 .reset_tsf
= ath5k_reset_tsf
,
265 .bss_info_changed
= ath5k_bss_info_changed
,
269 * Prototypes - Internal functions
272 static int ath5k_attach(struct pci_dev
*pdev
,
273 struct ieee80211_hw
*hw
);
274 static void ath5k_detach(struct pci_dev
*pdev
,
275 struct ieee80211_hw
*hw
);
276 /* Channel/mode setup */
277 static inline short ath5k_ieee2mhz(short chan
);
278 static unsigned int ath5k_copy_channels(struct ath5k_hw
*ah
,
279 struct ieee80211_channel
*channels
,
282 static int ath5k_setup_bands(struct ieee80211_hw
*hw
);
283 static int ath5k_chan_set(struct ath5k_softc
*sc
,
284 struct ieee80211_channel
*chan
);
285 static void ath5k_setcurmode(struct ath5k_softc
*sc
,
287 static void ath5k_mode_setup(struct ath5k_softc
*sc
);
289 /* Descriptor setup */
290 static int ath5k_desc_alloc(struct ath5k_softc
*sc
,
291 struct pci_dev
*pdev
);
292 static void ath5k_desc_free(struct ath5k_softc
*sc
,
293 struct pci_dev
*pdev
);
295 static int ath5k_rxbuf_setup(struct ath5k_softc
*sc
,
296 struct ath5k_buf
*bf
);
297 static int ath5k_txbuf_setup(struct ath5k_softc
*sc
,
298 struct ath5k_buf
*bf
);
299 static inline void ath5k_txbuf_free(struct ath5k_softc
*sc
,
300 struct ath5k_buf
*bf
)
305 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, bf
->skb
->len
,
307 dev_kfree_skb_any(bf
->skb
);
312 static struct ath5k_txq
*ath5k_txq_setup(struct ath5k_softc
*sc
,
313 int qtype
, int subtype
);
314 static int ath5k_beaconq_setup(struct ath5k_hw
*ah
);
315 static int ath5k_beaconq_config(struct ath5k_softc
*sc
);
316 static void ath5k_txq_drainq(struct ath5k_softc
*sc
,
317 struct ath5k_txq
*txq
);
318 static void ath5k_txq_cleanup(struct ath5k_softc
*sc
);
319 static void ath5k_txq_release(struct ath5k_softc
*sc
);
321 static int ath5k_rx_start(struct ath5k_softc
*sc
);
322 static void ath5k_rx_stop(struct ath5k_softc
*sc
);
323 static unsigned int ath5k_rx_decrypted(struct ath5k_softc
*sc
,
324 struct ath5k_desc
*ds
,
326 struct ath5k_rx_status
*rs
);
327 static void ath5k_tasklet_rx(unsigned long data
);
329 static void ath5k_tx_processq(struct ath5k_softc
*sc
,
330 struct ath5k_txq
*txq
);
331 static void ath5k_tasklet_tx(unsigned long data
);
332 /* Beacon handling */
333 static int ath5k_beacon_setup(struct ath5k_softc
*sc
,
334 struct ath5k_buf
*bf
);
335 static void ath5k_beacon_send(struct ath5k_softc
*sc
);
336 static void ath5k_beacon_config(struct ath5k_softc
*sc
);
337 static void ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
);
339 static inline u64
ath5k_extend_tsf(struct ath5k_hw
*ah
, u32 rstamp
)
341 u64 tsf
= ath5k_hw_get_tsf64(ah
);
343 if ((tsf
& 0x7fff) < rstamp
)
346 return (tsf
& ~0x7fff) | rstamp
;
349 /* Interrupt handling */
350 static int ath5k_init(struct ath5k_softc
*sc
);
351 static int ath5k_stop_locked(struct ath5k_softc
*sc
);
352 static int ath5k_stop_hw(struct ath5k_softc
*sc
);
353 static irqreturn_t
ath5k_intr(int irq
, void *dev_id
);
354 static void ath5k_tasklet_reset(unsigned long data
);
356 static void ath5k_calibrate(unsigned long data
);
358 static int ath5k_init_leds(struct ath5k_softc
*sc
);
359 static void ath5k_led_enable(struct ath5k_softc
*sc
);
360 static void ath5k_led_off(struct ath5k_softc
*sc
);
361 static void ath5k_unregister_leds(struct ath5k_softc
*sc
);
364 * Module init/exit functions
373 ret
= pci_register_driver(&ath5k_pci_driver
);
375 printk(KERN_ERR
"ath5k_pci: can't register pci driver\n");
385 pci_unregister_driver(&ath5k_pci_driver
);
387 ath5k_debug_finish();
390 module_init(init_ath5k_pci
);
391 module_exit(exit_ath5k_pci
);
394 /********************\
395 * PCI Initialization *
396 \********************/
399 ath5k_chip_name(enum ath5k_srev_type type
, u_int16_t val
)
401 const char *name
= "xxxxx";
404 for (i
= 0; i
< ARRAY_SIZE(srev_names
); i
++) {
405 if (srev_names
[i
].sr_type
!= type
)
408 if ((val
& 0xf0) == srev_names
[i
].sr_val
)
409 name
= srev_names
[i
].sr_name
;
411 if ((val
& 0xff) == srev_names
[i
].sr_val
) {
412 name
= srev_names
[i
].sr_name
;
421 ath5k_pci_probe(struct pci_dev
*pdev
,
422 const struct pci_device_id
*id
)
425 struct ath5k_softc
*sc
;
426 struct ieee80211_hw
*hw
;
430 ret
= pci_enable_device(pdev
);
432 dev_err(&pdev
->dev
, "can't enable device\n");
436 /* XXX 32-bit addressing only */
437 ret
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
439 dev_err(&pdev
->dev
, "32-bit DMA not available\n");
444 * Cache line size is used to size and align various
445 * structures used to communicate with the hardware.
447 pci_read_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, &csz
);
450 * Linux 2.4.18 (at least) writes the cache line size
451 * register as a 16-bit wide register which is wrong.
452 * We must have this setup properly for rx buffer
453 * DMA to work so force a reasonable value here if it
456 csz
= L1_CACHE_BYTES
/ sizeof(u32
);
457 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, csz
);
460 * The default setting of latency timer yields poor results,
461 * set it to the value used by other systems. It may be worth
462 * tweaking this setting more.
464 pci_write_config_byte(pdev
, PCI_LATENCY_TIMER
, 0xa8);
466 /* Enable bus mastering */
467 pci_set_master(pdev
);
470 * Disable the RETRY_TIMEOUT register (0x41) to keep
471 * PCI Tx retries from interfering with C3 CPU state.
473 pci_write_config_byte(pdev
, 0x41, 0);
475 ret
= pci_request_region(pdev
, 0, "ath5k");
477 dev_err(&pdev
->dev
, "cannot reserve PCI memory region\n");
481 mem
= pci_iomap(pdev
, 0, 0);
483 dev_err(&pdev
->dev
, "cannot remap PCI memory region\n") ;
489 * Allocate hw (mac80211 main struct)
490 * and hw->priv (driver private data)
492 hw
= ieee80211_alloc_hw(sizeof(*sc
), &ath5k_hw_ops
);
494 dev_err(&pdev
->dev
, "cannot allocate ieee80211_hw\n");
499 dev_info(&pdev
->dev
, "registered as '%s'\n", wiphy_name(hw
->wiphy
));
501 /* Initialize driver private data */
502 SET_IEEE80211_DEV(hw
, &pdev
->dev
);
503 hw
->flags
= IEEE80211_HW_RX_INCLUDES_FCS
|
504 IEEE80211_HW_SIGNAL_DBM
|
505 IEEE80211_HW_NOISE_DBM
;
507 hw
->wiphy
->interface_modes
=
508 BIT(NL80211_IFTYPE_STATION
) |
509 BIT(NL80211_IFTYPE_ADHOC
) |
510 BIT(NL80211_IFTYPE_MESH_POINT
);
512 hw
->extra_tx_headroom
= 2;
513 hw
->channel_change_time
= 5000;
518 ath5k_debug_init_device(sc
);
521 * Mark the device as detached to avoid processing
522 * interrupts until setup is complete.
524 __set_bit(ATH_STAT_INVALID
, sc
->status
);
526 sc
->iobase
= mem
; /* So we can unmap it on detach */
527 sc
->cachelsz
= csz
* sizeof(u32
); /* convert to bytes */
528 sc
->opmode
= NL80211_IFTYPE_STATION
;
529 mutex_init(&sc
->lock
);
530 spin_lock_init(&sc
->rxbuflock
);
531 spin_lock_init(&sc
->txbuflock
);
532 spin_lock_init(&sc
->block
);
534 /* Set private data */
535 pci_set_drvdata(pdev
, hw
);
537 /* Setup interrupt handler */
538 ret
= request_irq(pdev
->irq
, ath5k_intr
, IRQF_SHARED
, "ath", sc
);
540 ATH5K_ERR(sc
, "request_irq failed\n");
544 /* Initialize device */
545 sc
->ah
= ath5k_hw_attach(sc
, id
->driver_data
);
546 if (IS_ERR(sc
->ah
)) {
547 ret
= PTR_ERR(sc
->ah
);
551 /* set up multi-rate retry capabilities */
552 if (sc
->ah
->ah_version
== AR5K_AR5212
) {
554 hw
->max_rate_tries
= 11;
557 /* Finish private driver data initialization */
558 ret
= ath5k_attach(pdev
, hw
);
562 ATH5K_INFO(sc
, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
563 ath5k_chip_name(AR5K_VERSION_MAC
, sc
->ah
->ah_mac_srev
),
565 sc
->ah
->ah_phy_revision
);
567 if (!sc
->ah
->ah_single_chip
) {
568 /* Single chip radio (!RF5111) */
569 if (sc
->ah
->ah_radio_5ghz_revision
&&
570 !sc
->ah
->ah_radio_2ghz_revision
) {
571 /* No 5GHz support -> report 2GHz radio */
572 if (!test_bit(AR5K_MODE_11A
,
573 sc
->ah
->ah_capabilities
.cap_mode
)) {
574 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
575 ath5k_chip_name(AR5K_VERSION_RAD
,
576 sc
->ah
->ah_radio_5ghz_revision
),
577 sc
->ah
->ah_radio_5ghz_revision
);
578 /* No 2GHz support (5110 and some
579 * 5Ghz only cards) -> report 5Ghz radio */
580 } else if (!test_bit(AR5K_MODE_11B
,
581 sc
->ah
->ah_capabilities
.cap_mode
)) {
582 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
583 ath5k_chip_name(AR5K_VERSION_RAD
,
584 sc
->ah
->ah_radio_5ghz_revision
),
585 sc
->ah
->ah_radio_5ghz_revision
);
586 /* Multiband radio */
588 ATH5K_INFO(sc
, "RF%s multiband radio found"
590 ath5k_chip_name(AR5K_VERSION_RAD
,
591 sc
->ah
->ah_radio_5ghz_revision
),
592 sc
->ah
->ah_radio_5ghz_revision
);
595 /* Multi chip radio (RF5111 - RF2111) ->
596 * report both 2GHz/5GHz radios */
597 else if (sc
->ah
->ah_radio_5ghz_revision
&&
598 sc
->ah
->ah_radio_2ghz_revision
){
599 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
600 ath5k_chip_name(AR5K_VERSION_RAD
,
601 sc
->ah
->ah_radio_5ghz_revision
),
602 sc
->ah
->ah_radio_5ghz_revision
);
603 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
604 ath5k_chip_name(AR5K_VERSION_RAD
,
605 sc
->ah
->ah_radio_2ghz_revision
),
606 sc
->ah
->ah_radio_2ghz_revision
);
611 /* ready to process interrupts */
612 __clear_bit(ATH_STAT_INVALID
, sc
->status
);
616 ath5k_hw_detach(sc
->ah
);
618 free_irq(pdev
->irq
, sc
);
620 ieee80211_free_hw(hw
);
622 pci_iounmap(pdev
, mem
);
624 pci_release_region(pdev
, 0);
626 pci_disable_device(pdev
);
631 static void __devexit
632 ath5k_pci_remove(struct pci_dev
*pdev
)
634 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
635 struct ath5k_softc
*sc
= hw
->priv
;
637 ath5k_debug_finish_device(sc
);
638 ath5k_detach(pdev
, hw
);
639 ath5k_hw_detach(sc
->ah
);
640 free_irq(pdev
->irq
, sc
);
641 pci_iounmap(pdev
, sc
->iobase
);
642 pci_release_region(pdev
, 0);
643 pci_disable_device(pdev
);
644 ieee80211_free_hw(hw
);
649 ath5k_pci_suspend(struct pci_dev
*pdev
, pm_message_t state
)
651 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
652 struct ath5k_softc
*sc
= hw
->priv
;
656 free_irq(pdev
->irq
, sc
);
657 pci_save_state(pdev
);
658 pci_disable_device(pdev
);
659 pci_set_power_state(pdev
, PCI_D3hot
);
665 ath5k_pci_resume(struct pci_dev
*pdev
)
667 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
668 struct ath5k_softc
*sc
= hw
->priv
;
671 pci_restore_state(pdev
);
673 err
= pci_enable_device(pdev
);
678 * Suspend/Resume resets the PCI configuration space, so we have to
679 * re-disable the RETRY_TIMEOUT register (0x41) to keep
680 * PCI Tx retries from interfering with C3 CPU state
682 pci_write_config_byte(pdev
, 0x41, 0);
684 err
= request_irq(pdev
->irq
, ath5k_intr
, IRQF_SHARED
, "ath", sc
);
686 ATH5K_ERR(sc
, "request_irq failed\n");
690 ath5k_led_enable(sc
);
694 pci_disable_device(pdev
);
697 #endif /* CONFIG_PM */
700 /***********************\
701 * Driver Initialization *
702 \***********************/
705 ath5k_attach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
707 struct ath5k_softc
*sc
= hw
->priv
;
708 struct ath5k_hw
*ah
= sc
->ah
;
709 u8 mac
[ETH_ALEN
] = {};
712 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "devid 0x%x\n", pdev
->device
);
715 * Check if the MAC has multi-rate retry support.
716 * We do this by trying to setup a fake extended
717 * descriptor. MAC's that don't have support will
718 * return false w/o doing anything. MAC's that do
719 * support it will return true w/o doing anything.
721 ret
= ah
->ah_setup_mrr_tx_desc(ah
, NULL
, 0, 0, 0, 0, 0, 0);
725 __set_bit(ATH_STAT_MRRETRY
, sc
->status
);
728 * Collect the channel list. The 802.11 layer
729 * is resposible for filtering this list based
730 * on settings like the phy mode and regulatory
731 * domain restrictions.
733 ret
= ath5k_setup_bands(hw
);
735 ATH5K_ERR(sc
, "can't get channels\n");
739 /* NB: setup here so ath5k_rate_update is happy */
740 if (test_bit(AR5K_MODE_11A
, ah
->ah_modes
))
741 ath5k_setcurmode(sc
, AR5K_MODE_11A
);
743 ath5k_setcurmode(sc
, AR5K_MODE_11B
);
746 * Allocate tx+rx descriptors and populate the lists.
748 ret
= ath5k_desc_alloc(sc
, pdev
);
750 ATH5K_ERR(sc
, "can't allocate descriptors\n");
755 * Allocate hardware transmit queues: one queue for
756 * beacon frames and one data queue for each QoS
757 * priority. Note that hw functions handle reseting
758 * these queues at the needed time.
760 ret
= ath5k_beaconq_setup(ah
);
762 ATH5K_ERR(sc
, "can't setup a beacon xmit queue\n");
767 sc
->txq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BK
);
768 if (IS_ERR(sc
->txq
)) {
769 ATH5K_ERR(sc
, "can't setup xmit queue\n");
770 ret
= PTR_ERR(sc
->txq
);
774 tasklet_init(&sc
->rxtq
, ath5k_tasklet_rx
, (unsigned long)sc
);
775 tasklet_init(&sc
->txtq
, ath5k_tasklet_tx
, (unsigned long)sc
);
776 tasklet_init(&sc
->restq
, ath5k_tasklet_reset
, (unsigned long)sc
);
777 setup_timer(&sc
->calib_tim
, ath5k_calibrate
, (unsigned long)sc
);
779 ret
= ath5k_eeprom_read_mac(ah
, mac
);
781 ATH5K_ERR(sc
, "unable to read address from EEPROM: 0x%04x\n",
786 SET_IEEE80211_PERM_ADDR(hw
, mac
);
787 /* All MAC address bits matter for ACKs */
788 memset(sc
->bssidmask
, 0xff, ETH_ALEN
);
789 ath5k_hw_set_bssid_mask(sc
->ah
, sc
->bssidmask
);
791 ret
= ieee80211_register_hw(hw
);
793 ATH5K_ERR(sc
, "can't register ieee80211 hw\n");
801 ath5k_txq_release(sc
);
803 ath5k_hw_release_tx_queue(ah
, sc
->bhalq
);
805 ath5k_desc_free(sc
, pdev
);
811 ath5k_detach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
813 struct ath5k_softc
*sc
= hw
->priv
;
816 * NB: the order of these is important:
817 * o call the 802.11 layer before detaching ath5k_hw to
818 * insure callbacks into the driver to delete global
819 * key cache entries can be handled
820 * o reclaim the tx queue data structures after calling
821 * the 802.11 layer as we'll get called back to reclaim
822 * node state and potentially want to use them
823 * o to cleanup the tx queues the hal is called, so detach
825 * XXX: ??? detach ath5k_hw ???
826 * Other than that, it's straightforward...
828 ieee80211_unregister_hw(hw
);
829 ath5k_desc_free(sc
, pdev
);
830 ath5k_txq_release(sc
);
831 ath5k_hw_release_tx_queue(sc
->ah
, sc
->bhalq
);
832 ath5k_unregister_leds(sc
);
835 * NB: can't reclaim these until after ieee80211_ifdetach
836 * returns because we'll get called back to reclaim node
837 * state and potentially want to use them.
844 /********************\
845 * Channel/mode setup *
846 \********************/
849 * Convert IEEE channel number to MHz frequency.
852 ath5k_ieee2mhz(short chan
)
854 if (chan
<= 14 || chan
>= 27)
855 return ieee80211chan2mhz(chan
);
857 return 2212 + chan
* 20;
861 ath5k_copy_channels(struct ath5k_hw
*ah
,
862 struct ieee80211_channel
*channels
,
866 unsigned int i
, count
, size
, chfreq
, freq
, ch
;
868 if (!test_bit(mode
, ah
->ah_modes
))
873 case AR5K_MODE_11A_TURBO
:
874 /* 1..220, but 2GHz frequencies are filtered by check_channel */
876 chfreq
= CHANNEL_5GHZ
;
880 case AR5K_MODE_11G_TURBO
:
882 chfreq
= CHANNEL_2GHZ
;
885 ATH5K_WARN(ah
->ah_sc
, "bad mode, not copying channels\n");
889 for (i
= 0, count
= 0; i
< size
&& max
> 0; i
++) {
891 freq
= ath5k_ieee2mhz(ch
);
893 /* Check if channel is supported by the chipset */
894 if (!ath5k_channel_ok(ah
, freq
, chfreq
))
897 /* Write channel info and increment counter */
898 channels
[count
].center_freq
= freq
;
899 channels
[count
].band
= (chfreq
== CHANNEL_2GHZ
) ?
900 IEEE80211_BAND_2GHZ
: IEEE80211_BAND_5GHZ
;
904 channels
[count
].hw_value
= chfreq
| CHANNEL_OFDM
;
906 case AR5K_MODE_11A_TURBO
:
907 case AR5K_MODE_11G_TURBO
:
908 channels
[count
].hw_value
= chfreq
|
909 CHANNEL_OFDM
| CHANNEL_TURBO
;
912 channels
[count
].hw_value
= CHANNEL_B
;
923 ath5k_setup_rate_idx(struct ath5k_softc
*sc
, struct ieee80211_supported_band
*b
)
927 for (i
= 0; i
< AR5K_MAX_RATES
; i
++)
928 sc
->rate_idx
[b
->band
][i
] = -1;
930 for (i
= 0; i
< b
->n_bitrates
; i
++) {
931 sc
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value
] = i
;
932 if (b
->bitrates
[i
].hw_value_short
)
933 sc
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value_short
] = i
;
938 ath5k_setup_bands(struct ieee80211_hw
*hw
)
940 struct ath5k_softc
*sc
= hw
->priv
;
941 struct ath5k_hw
*ah
= sc
->ah
;
942 struct ieee80211_supported_band
*sband
;
943 int max_c
, count_c
= 0;
946 BUILD_BUG_ON(ARRAY_SIZE(sc
->sbands
) < IEEE80211_NUM_BANDS
);
947 max_c
= ARRAY_SIZE(sc
->channels
);
950 sband
= &sc
->sbands
[IEEE80211_BAND_2GHZ
];
951 sband
->band
= IEEE80211_BAND_2GHZ
;
952 sband
->bitrates
= &sc
->rates
[IEEE80211_BAND_2GHZ
][0];
954 if (test_bit(AR5K_MODE_11G
, sc
->ah
->ah_capabilities
.cap_mode
)) {
956 memcpy(sband
->bitrates
, &ath5k_rates
[0],
957 sizeof(struct ieee80211_rate
) * 12);
958 sband
->n_bitrates
= 12;
960 sband
->channels
= sc
->channels
;
961 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
962 AR5K_MODE_11G
, max_c
);
964 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
965 count_c
= sband
->n_channels
;
967 } else if (test_bit(AR5K_MODE_11B
, sc
->ah
->ah_capabilities
.cap_mode
)) {
969 memcpy(sband
->bitrates
, &ath5k_rates
[0],
970 sizeof(struct ieee80211_rate
) * 4);
971 sband
->n_bitrates
= 4;
973 /* 5211 only supports B rates and uses 4bit rate codes
974 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
977 if (ah
->ah_version
== AR5K_AR5211
) {
978 for (i
= 0; i
< 4; i
++) {
979 sband
->bitrates
[i
].hw_value
=
980 sband
->bitrates
[i
].hw_value
& 0xF;
981 sband
->bitrates
[i
].hw_value_short
=
982 sband
->bitrates
[i
].hw_value_short
& 0xF;
986 sband
->channels
= sc
->channels
;
987 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
988 AR5K_MODE_11B
, max_c
);
990 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
991 count_c
= sband
->n_channels
;
994 ath5k_setup_rate_idx(sc
, sband
);
996 /* 5GHz band, A mode */
997 if (test_bit(AR5K_MODE_11A
, sc
->ah
->ah_capabilities
.cap_mode
)) {
998 sband
= &sc
->sbands
[IEEE80211_BAND_5GHZ
];
999 sband
->band
= IEEE80211_BAND_5GHZ
;
1000 sband
->bitrates
= &sc
->rates
[IEEE80211_BAND_5GHZ
][0];
1002 memcpy(sband
->bitrates
, &ath5k_rates
[4],
1003 sizeof(struct ieee80211_rate
) * 8);
1004 sband
->n_bitrates
= 8;
1006 sband
->channels
= &sc
->channels
[count_c
];
1007 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
1008 AR5K_MODE_11A
, max_c
);
1010 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] = sband
;
1012 ath5k_setup_rate_idx(sc
, sband
);
1014 ath5k_debug_dump_bands(sc
);
1020 * Set/change channels. If the channel is really being changed,
1021 * it's done by reseting the chip. To accomplish this we must
1022 * first cleanup any pending DMA, then restart stuff after a la
1026 ath5k_chan_set(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
)
1028 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "(%u MHz) -> (%u MHz)\n",
1029 sc
->curchan
->center_freq
, chan
->center_freq
);
1031 if (chan
->center_freq
!= sc
->curchan
->center_freq
||
1032 chan
->hw_value
!= sc
->curchan
->hw_value
) {
1035 sc
->curband
= &sc
->sbands
[chan
->band
];
1038 * To switch channels clear any pending DMA operations;
1039 * wait long enough for the RX fifo to drain, reset the
1040 * hardware at the new frequency, and then re-enable
1041 * the relevant bits of the h/w.
1043 return ath5k_reset(sc
, true, true);
1050 ath5k_setcurmode(struct ath5k_softc
*sc
, unsigned int mode
)
1054 if (mode
== AR5K_MODE_11A
) {
1055 sc
->curband
= &sc
->sbands
[IEEE80211_BAND_5GHZ
];
1057 sc
->curband
= &sc
->sbands
[IEEE80211_BAND_2GHZ
];
1062 ath5k_mode_setup(struct ath5k_softc
*sc
)
1064 struct ath5k_hw
*ah
= sc
->ah
;
1067 /* configure rx filter */
1068 rfilt
= sc
->filter_flags
;
1069 ath5k_hw_set_rx_filter(ah
, rfilt
);
1071 if (ath5k_hw_hasbssidmask(ah
))
1072 ath5k_hw_set_bssid_mask(ah
, sc
->bssidmask
);
1074 /* configure operational mode */
1075 ath5k_hw_set_opmode(ah
);
1077 ath5k_hw_set_mcast_filter(ah
, 0, 0);
1078 ATH5K_DBG(sc
, ATH5K_DEBUG_MODE
, "RX filter 0x%x\n", rfilt
);
1082 ath5k_hw_to_driver_rix(struct ath5k_softc
*sc
, int hw_rix
)
1084 WARN_ON(hw_rix
< 0 || hw_rix
> AR5K_MAX_RATES
);
1085 return sc
->rate_idx
[sc
->curband
->band
][hw_rix
];
1093 struct sk_buff
*ath5k_rx_skb_alloc(struct ath5k_softc
*sc
, dma_addr_t
*skb_addr
)
1095 struct sk_buff
*skb
;
1099 * Allocate buffer with headroom_needed space for the
1100 * fake physical layer header at the start.
1102 skb
= dev_alloc_skb(sc
->rxbufsize
+ sc
->cachelsz
- 1);
1105 ATH5K_ERR(sc
, "can't alloc skbuff of size %u\n",
1106 sc
->rxbufsize
+ sc
->cachelsz
- 1);
1110 * Cache-line-align. This is important (for the
1111 * 5210 at least) as not doing so causes bogus data
1114 off
= ((unsigned long)skb
->data
) % sc
->cachelsz
;
1116 skb_reserve(skb
, sc
->cachelsz
- off
);
1118 *skb_addr
= pci_map_single(sc
->pdev
,
1119 skb
->data
, sc
->rxbufsize
, PCI_DMA_FROMDEVICE
);
1120 if (unlikely(pci_dma_mapping_error(sc
->pdev
, *skb_addr
))) {
1121 ATH5K_ERR(sc
, "%s: DMA mapping failed\n", __func__
);
1129 ath5k_rxbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1131 struct ath5k_hw
*ah
= sc
->ah
;
1132 struct sk_buff
*skb
= bf
->skb
;
1133 struct ath5k_desc
*ds
;
1136 skb
= ath5k_rx_skb_alloc(sc
, &bf
->skbaddr
);
1143 * Setup descriptors. For receive we always terminate
1144 * the descriptor list with a self-linked entry so we'll
1145 * not get overrun under high load (as can happen with a
1146 * 5212 when ANI processing enables PHY error frames).
1148 * To insure the last descriptor is self-linked we create
1149 * each descriptor as self-linked and add it to the end. As
1150 * each additional descriptor is added the previous self-linked
1151 * entry is ``fixed'' naturally. This should be safe even
1152 * if DMA is happening. When processing RX interrupts we
1153 * never remove/process the last, self-linked, entry on the
1154 * descriptor list. This insures the hardware always has
1155 * someplace to write a new frame.
1158 ds
->ds_link
= bf
->daddr
; /* link to self */
1159 ds
->ds_data
= bf
->skbaddr
;
1160 ah
->ah_setup_rx_desc(ah
, ds
,
1161 skb_tailroom(skb
), /* buffer size */
1164 if (sc
->rxlink
!= NULL
)
1165 *sc
->rxlink
= bf
->daddr
;
1166 sc
->rxlink
= &ds
->ds_link
;
1171 ath5k_txbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1173 struct ath5k_hw
*ah
= sc
->ah
;
1174 struct ath5k_txq
*txq
= sc
->txq
;
1175 struct ath5k_desc
*ds
= bf
->desc
;
1176 struct sk_buff
*skb
= bf
->skb
;
1177 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1178 unsigned int pktlen
, flags
, keyidx
= AR5K_TXKEYIX_INVALID
;
1179 struct ieee80211_rate
*rate
;
1180 unsigned int mrr_rate
[3], mrr_tries
[3];
1187 flags
= AR5K_TXDESC_INTREQ
| AR5K_TXDESC_CLRDMASK
;
1189 /* XXX endianness */
1190 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
1193 rate
= ieee80211_get_tx_rate(sc
->hw
, info
);
1195 if (info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
1196 flags
|= AR5K_TXDESC_NOACK
;
1198 rc_flags
= info
->control
.rates
[0].flags
;
1199 hw_rate
= (rc_flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
) ?
1200 rate
->hw_value_short
: rate
->hw_value
;
1204 if (rc_flags
& IEEE80211_TX_RC_USE_RTS_CTS
) {
1205 flags
|= AR5K_TXDESC_RTSENA
;
1206 cts_rate
= ieee80211_get_rts_cts_rate(sc
->hw
, info
)->hw_value
;
1207 duration
= le16_to_cpu(ieee80211_rts_duration(sc
->hw
,
1208 sc
->vif
, pktlen
, info
));
1210 if (rc_flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
) {
1211 flags
|= AR5K_TXDESC_CTSENA
;
1212 cts_rate
= ieee80211_get_rts_cts_rate(sc
->hw
, info
)->hw_value
;
1213 duration
= le16_to_cpu(ieee80211_ctstoself_duration(sc
->hw
,
1214 sc
->vif
, pktlen
, info
));
1217 if (info
->control
.hw_key
) {
1218 keyidx
= info
->control
.hw_key
->hw_key_idx
;
1219 pktlen
+= info
->control
.hw_key
->icv_len
;
1221 ret
= ah
->ah_setup_tx_desc(ah
, ds
, pktlen
,
1222 ieee80211_get_hdrlen_from_skb(skb
), AR5K_PKT_TYPE_NORMAL
,
1223 (sc
->power_level
* 2),
1225 info
->control
.rates
[0].count
, keyidx
, 0, flags
,
1226 cts_rate
, duration
);
1230 memset(mrr_rate
, 0, sizeof(mrr_rate
));
1231 memset(mrr_tries
, 0, sizeof(mrr_tries
));
1232 for (i
= 0; i
< 3; i
++) {
1233 rate
= ieee80211_get_alt_retry_rate(sc
->hw
, info
, i
);
1237 mrr_rate
[i
] = rate
->hw_value
;
1238 mrr_tries
[i
] = info
->control
.rates
[i
+ 1].count
;
1241 ah
->ah_setup_mrr_tx_desc(ah
, ds
,
1242 mrr_rate
[0], mrr_tries
[0],
1243 mrr_rate
[1], mrr_tries
[1],
1244 mrr_rate
[2], mrr_tries
[2]);
1247 ds
->ds_data
= bf
->skbaddr
;
1249 spin_lock_bh(&txq
->lock
);
1250 list_add_tail(&bf
->list
, &txq
->q
);
1251 sc
->tx_stats
[txq
->qnum
].len
++;
1252 if (txq
->link
== NULL
) /* is this first packet? */
1253 ath5k_hw_set_txdp(ah
, txq
->qnum
, bf
->daddr
);
1254 else /* no, so only link it */
1255 *txq
->link
= bf
->daddr
;
1257 txq
->link
= &ds
->ds_link
;
1258 ath5k_hw_start_tx_dma(ah
, txq
->qnum
);
1260 spin_unlock_bh(&txq
->lock
);
1264 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
1268 /*******************\
1269 * Descriptors setup *
1270 \*******************/
1273 ath5k_desc_alloc(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
1275 struct ath5k_desc
*ds
;
1276 struct ath5k_buf
*bf
;
1281 /* allocate descriptors */
1282 sc
->desc_len
= sizeof(struct ath5k_desc
) *
1283 (ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
+ 1);
1284 sc
->desc
= pci_alloc_consistent(pdev
, sc
->desc_len
, &sc
->desc_daddr
);
1285 if (sc
->desc
== NULL
) {
1286 ATH5K_ERR(sc
, "can't allocate descriptors\n");
1291 da
= sc
->desc_daddr
;
1292 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "DMA map: %p (%zu) -> %llx\n",
1293 ds
, sc
->desc_len
, (unsigned long long)sc
->desc_daddr
);
1295 bf
= kcalloc(1 + ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
,
1296 sizeof(struct ath5k_buf
), GFP_KERNEL
);
1298 ATH5K_ERR(sc
, "can't allocate bufptr\n");
1304 INIT_LIST_HEAD(&sc
->rxbuf
);
1305 for (i
= 0; i
< ATH_RXBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
1308 list_add_tail(&bf
->list
, &sc
->rxbuf
);
1311 INIT_LIST_HEAD(&sc
->txbuf
);
1312 sc
->txbuf_len
= ATH_TXBUF
;
1313 for (i
= 0; i
< ATH_TXBUF
; i
++, bf
++, ds
++,
1314 da
+= sizeof(*ds
)) {
1317 list_add_tail(&bf
->list
, &sc
->txbuf
);
1327 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
1334 ath5k_desc_free(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
1336 struct ath5k_buf
*bf
;
1338 ath5k_txbuf_free(sc
, sc
->bbuf
);
1339 list_for_each_entry(bf
, &sc
->txbuf
, list
)
1340 ath5k_txbuf_free(sc
, bf
);
1341 list_for_each_entry(bf
, &sc
->rxbuf
, list
)
1342 ath5k_txbuf_free(sc
, bf
);
1344 /* Free memory associated with all descriptors */
1345 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
1359 static struct ath5k_txq
*
1360 ath5k_txq_setup(struct ath5k_softc
*sc
,
1361 int qtype
, int subtype
)
1363 struct ath5k_hw
*ah
= sc
->ah
;
1364 struct ath5k_txq
*txq
;
1365 struct ath5k_txq_info qi
= {
1366 .tqi_subtype
= subtype
,
1367 .tqi_aifs
= AR5K_TXQ_USEDEFAULT
,
1368 .tqi_cw_min
= AR5K_TXQ_USEDEFAULT
,
1369 .tqi_cw_max
= AR5K_TXQ_USEDEFAULT
1374 * Enable interrupts only for EOL and DESC conditions.
1375 * We mark tx descriptors to receive a DESC interrupt
1376 * when a tx queue gets deep; otherwise waiting for the
1377 * EOL to reap descriptors. Note that this is done to
1378 * reduce interrupt load and this only defers reaping
1379 * descriptors, never transmitting frames. Aside from
1380 * reducing interrupts this also permits more concurrency.
1381 * The only potential downside is if the tx queue backs
1382 * up in which case the top half of the kernel may backup
1383 * due to a lack of tx descriptors.
1385 qi
.tqi_flags
= AR5K_TXQ_FLAG_TXEOLINT_ENABLE
|
1386 AR5K_TXQ_FLAG_TXDESCINT_ENABLE
;
1387 qnum
= ath5k_hw_setup_tx_queue(ah
, qtype
, &qi
);
1390 * NB: don't print a message, this happens
1391 * normally on parts with too few tx queues
1393 return ERR_PTR(qnum
);
1395 if (qnum
>= ARRAY_SIZE(sc
->txqs
)) {
1396 ATH5K_ERR(sc
, "hw qnum %u out of range, max %tu!\n",
1397 qnum
, ARRAY_SIZE(sc
->txqs
));
1398 ath5k_hw_release_tx_queue(ah
, qnum
);
1399 return ERR_PTR(-EINVAL
);
1401 txq
= &sc
->txqs
[qnum
];
1405 INIT_LIST_HEAD(&txq
->q
);
1406 spin_lock_init(&txq
->lock
);
1409 return &sc
->txqs
[qnum
];
1413 ath5k_beaconq_setup(struct ath5k_hw
*ah
)
1415 struct ath5k_txq_info qi
= {
1416 .tqi_aifs
= AR5K_TXQ_USEDEFAULT
,
1417 .tqi_cw_min
= AR5K_TXQ_USEDEFAULT
,
1418 .tqi_cw_max
= AR5K_TXQ_USEDEFAULT
,
1419 /* NB: for dynamic turbo, don't enable any other interrupts */
1420 .tqi_flags
= AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1423 return ath5k_hw_setup_tx_queue(ah
, AR5K_TX_QUEUE_BEACON
, &qi
);
1427 ath5k_beaconq_config(struct ath5k_softc
*sc
)
1429 struct ath5k_hw
*ah
= sc
->ah
;
1430 struct ath5k_txq_info qi
;
1433 ret
= ath5k_hw_get_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1436 if (sc
->opmode
== NL80211_IFTYPE_AP
||
1437 sc
->opmode
== NL80211_IFTYPE_MESH_POINT
) {
1439 * Always burst out beacon and CAB traffic
1440 * (aifs = cwmin = cwmax = 0)
1445 } else if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
1447 * Adhoc mode; backoff between 0 and (2 * cw_min).
1451 qi
.tqi_cw_max
= 2 * ah
->ah_cw_min
;
1454 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1455 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1456 qi
.tqi_aifs
, qi
.tqi_cw_min
, qi
.tqi_cw_max
);
1458 ret
= ath5k_hw_set_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1460 ATH5K_ERR(sc
, "%s: unable to update parameters for beacon "
1461 "hardware queue!\n", __func__
);
1465 return ath5k_hw_reset_tx_queue(ah
, sc
->bhalq
); /* push to h/w */;
1469 ath5k_txq_drainq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
1471 struct ath5k_buf
*bf
, *bf0
;
1474 * NB: this assumes output has been stopped and
1475 * we do not need to block ath5k_tx_tasklet
1477 spin_lock_bh(&txq
->lock
);
1478 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1479 ath5k_debug_printtxbuf(sc
, bf
);
1481 ath5k_txbuf_free(sc
, bf
);
1483 spin_lock_bh(&sc
->txbuflock
);
1484 sc
->tx_stats
[txq
->qnum
].len
--;
1485 list_move_tail(&bf
->list
, &sc
->txbuf
);
1487 spin_unlock_bh(&sc
->txbuflock
);
1490 spin_unlock_bh(&txq
->lock
);
1494 * Drain the transmit queues and reclaim resources.
1497 ath5k_txq_cleanup(struct ath5k_softc
*sc
)
1499 struct ath5k_hw
*ah
= sc
->ah
;
1502 /* XXX return value */
1503 if (likely(!test_bit(ATH_STAT_INVALID
, sc
->status
))) {
1504 /* don't touch the hardware if marked invalid */
1505 ath5k_hw_stop_tx_dma(ah
, sc
->bhalq
);
1506 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "beacon queue %x\n",
1507 ath5k_hw_get_txdp(ah
, sc
->bhalq
));
1508 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++)
1509 if (sc
->txqs
[i
].setup
) {
1510 ath5k_hw_stop_tx_dma(ah
, sc
->txqs
[i
].qnum
);
1511 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "txq [%u] %x, "
1514 ath5k_hw_get_txdp(ah
,
1519 ieee80211_wake_queues(sc
->hw
); /* XXX move to callers */
1521 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++)
1522 if (sc
->txqs
[i
].setup
)
1523 ath5k_txq_drainq(sc
, &sc
->txqs
[i
]);
1527 ath5k_txq_release(struct ath5k_softc
*sc
)
1529 struct ath5k_txq
*txq
= sc
->txqs
;
1532 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++, txq
++)
1534 ath5k_hw_release_tx_queue(sc
->ah
, txq
->qnum
);
1547 * Enable the receive h/w following a reset.
1550 ath5k_rx_start(struct ath5k_softc
*sc
)
1552 struct ath5k_hw
*ah
= sc
->ah
;
1553 struct ath5k_buf
*bf
;
1556 sc
->rxbufsize
= roundup(IEEE80211_MAX_LEN
, sc
->cachelsz
);
1558 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "cachelsz %u rxbufsize %u\n",
1559 sc
->cachelsz
, sc
->rxbufsize
);
1563 spin_lock_bh(&sc
->rxbuflock
);
1564 list_for_each_entry(bf
, &sc
->rxbuf
, list
) {
1565 ret
= ath5k_rxbuf_setup(sc
, bf
);
1567 spin_unlock_bh(&sc
->rxbuflock
);
1571 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1572 spin_unlock_bh(&sc
->rxbuflock
);
1574 ath5k_hw_set_rxdp(ah
, bf
->daddr
);
1575 ath5k_hw_start_rx_dma(ah
); /* enable recv descriptors */
1576 ath5k_mode_setup(sc
); /* set filters, etc. */
1577 ath5k_hw_start_rx_pcu(ah
); /* re-enable PCU/DMA engine */
1585 * Disable the receive h/w in preparation for a reset.
1588 ath5k_rx_stop(struct ath5k_softc
*sc
)
1590 struct ath5k_hw
*ah
= sc
->ah
;
1592 ath5k_hw_stop_rx_pcu(ah
); /* disable PCU */
1593 ath5k_hw_set_rx_filter(ah
, 0); /* clear recv filter */
1594 ath5k_hw_stop_rx_dma(ah
); /* disable DMA engine */
1596 ath5k_debug_printrxbuffs(sc
, ah
);
1598 sc
->rxlink
= NULL
; /* just in case */
1602 ath5k_rx_decrypted(struct ath5k_softc
*sc
, struct ath5k_desc
*ds
,
1603 struct sk_buff
*skb
, struct ath5k_rx_status
*rs
)
1605 struct ieee80211_hdr
*hdr
= (void *)skb
->data
;
1606 unsigned int keyix
, hlen
;
1608 if (!(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1609 rs
->rs_keyix
!= AR5K_RXKEYIX_INVALID
)
1610 return RX_FLAG_DECRYPTED
;
1612 /* Apparently when a default key is used to decrypt the packet
1613 the hw does not set the index used to decrypt. In such cases
1614 get the index from the packet. */
1615 hlen
= ieee80211_hdrlen(hdr
->frame_control
);
1616 if (ieee80211_has_protected(hdr
->frame_control
) &&
1617 !(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1618 skb
->len
>= hlen
+ 4) {
1619 keyix
= skb
->data
[hlen
+ 3] >> 6;
1621 if (test_bit(keyix
, sc
->keymap
))
1622 return RX_FLAG_DECRYPTED
;
1630 ath5k_check_ibss_tsf(struct ath5k_softc
*sc
, struct sk_buff
*skb
,
1631 struct ieee80211_rx_status
*rxs
)
1635 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1637 if (ieee80211_is_beacon(mgmt
->frame_control
) &&
1638 le16_to_cpu(mgmt
->u
.beacon
.capab_info
) & WLAN_CAPABILITY_IBSS
&&
1639 memcmp(mgmt
->bssid
, sc
->ah
->ah_bssid
, ETH_ALEN
) == 0) {
1641 * Received an IBSS beacon with the same BSSID. Hardware *must*
1642 * have updated the local TSF. We have to work around various
1643 * hardware bugs, though...
1645 tsf
= ath5k_hw_get_tsf64(sc
->ah
);
1646 bc_tstamp
= le64_to_cpu(mgmt
->u
.beacon
.timestamp
);
1647 hw_tu
= TSF_TO_TU(tsf
);
1649 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1650 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1651 (unsigned long long)bc_tstamp
,
1652 (unsigned long long)rxs
->mactime
,
1653 (unsigned long long)(rxs
->mactime
- bc_tstamp
),
1654 (unsigned long long)tsf
);
1657 * Sometimes the HW will give us a wrong tstamp in the rx
1658 * status, causing the timestamp extension to go wrong.
1659 * (This seems to happen especially with beacon frames bigger
1660 * than 78 byte (incl. FCS))
1661 * But we know that the receive timestamp must be later than the
1662 * timestamp of the beacon since HW must have synced to that.
1664 * NOTE: here we assume mactime to be after the frame was
1665 * received, not like mac80211 which defines it at the start.
1667 if (bc_tstamp
> rxs
->mactime
) {
1668 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1669 "fixing mactime from %llx to %llx\n",
1670 (unsigned long long)rxs
->mactime
,
1671 (unsigned long long)tsf
);
1676 * Local TSF might have moved higher than our beacon timers,
1677 * in that case we have to update them to continue sending
1678 * beacons. This also takes care of synchronizing beacon sending
1679 * times with other stations.
1681 if (hw_tu
>= sc
->nexttbtt
)
1682 ath5k_beacon_update_timers(sc
, bc_tstamp
);
1688 ath5k_tasklet_rx(unsigned long data
)
1690 struct ieee80211_rx_status rxs
= {};
1691 struct ath5k_rx_status rs
= {};
1692 struct sk_buff
*skb
, *next_skb
;
1693 dma_addr_t next_skb_addr
;
1694 struct ath5k_softc
*sc
= (void *)data
;
1695 struct ath5k_buf
*bf
, *bf_last
;
1696 struct ath5k_desc
*ds
;
1701 spin_lock(&sc
->rxbuflock
);
1702 if (list_empty(&sc
->rxbuf
)) {
1703 ATH5K_WARN(sc
, "empty rx buf pool\n");
1706 bf_last
= list_entry(sc
->rxbuf
.prev
, struct ath5k_buf
, list
);
1710 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1711 BUG_ON(bf
->skb
== NULL
);
1716 * last buffer must not be freed to ensure proper hardware
1717 * function. When the hardware finishes also a packet next to
1718 * it, we are sure, it doesn't use it anymore and we can go on.
1723 struct ath5k_buf
*bf_next
= list_entry(bf
->list
.next
,
1724 struct ath5k_buf
, list
);
1725 ret
= sc
->ah
->ah_proc_rx_desc(sc
->ah
, bf_next
->desc
,
1730 /* skip the overwritten one (even status is martian) */
1734 ret
= sc
->ah
->ah_proc_rx_desc(sc
->ah
, ds
, &rs
);
1735 if (unlikely(ret
== -EINPROGRESS
))
1737 else if (unlikely(ret
)) {
1738 ATH5K_ERR(sc
, "error in processing rx descriptor\n");
1739 spin_unlock(&sc
->rxbuflock
);
1743 if (unlikely(rs
.rs_more
)) {
1744 ATH5K_WARN(sc
, "unsupported jumbo\n");
1748 if (unlikely(rs
.rs_status
)) {
1749 if (rs
.rs_status
& AR5K_RXERR_PHY
)
1751 if (rs
.rs_status
& AR5K_RXERR_DECRYPT
) {
1753 * Decrypt error. If the error occurred
1754 * because there was no hardware key, then
1755 * let the frame through so the upper layers
1756 * can process it. This is necessary for 5210
1757 * parts which have no way to setup a ``clear''
1760 * XXX do key cache faulting
1762 if (rs
.rs_keyix
== AR5K_RXKEYIX_INVALID
&&
1763 !(rs
.rs_status
& AR5K_RXERR_CRC
))
1766 if (rs
.rs_status
& AR5K_RXERR_MIC
) {
1767 rxs
.flag
|= RX_FLAG_MMIC_ERROR
;
1771 /* let crypto-error packets fall through in MNTR */
1773 ~(AR5K_RXERR_DECRYPT
|AR5K_RXERR_MIC
)) ||
1774 sc
->opmode
!= NL80211_IFTYPE_MONITOR
)
1778 next_skb
= ath5k_rx_skb_alloc(sc
, &next_skb_addr
);
1781 * If we can't replace bf->skb with a new skb under memory
1782 * pressure, just skip this packet
1787 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, sc
->rxbufsize
,
1788 PCI_DMA_FROMDEVICE
);
1789 skb_put(skb
, rs
.rs_datalen
);
1791 /* The MAC header is padded to have 32-bit boundary if the
1792 * packet payload is non-zero. The general calculation for
1793 * padsize would take into account odd header lengths:
1794 * padsize = (4 - hdrlen % 4) % 4; However, since only
1795 * even-length headers are used, padding can only be 0 or 2
1796 * bytes and we can optimize this a bit. In addition, we must
1797 * not try to remove padding from short control frames that do
1798 * not have payload. */
1799 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
1800 padsize
= ath5k_pad_size(hdrlen
);
1802 memmove(skb
->data
+ padsize
, skb
->data
, hdrlen
);
1803 skb_pull(skb
, padsize
);
1807 * always extend the mac timestamp, since this information is
1808 * also needed for proper IBSS merging.
1810 * XXX: it might be too late to do it here, since rs_tstamp is
1811 * 15bit only. that means TSF extension has to be done within
1812 * 32768usec (about 32ms). it might be necessary to move this to
1813 * the interrupt handler, like it is done in madwifi.
1815 * Unfortunately we don't know when the hardware takes the rx
1816 * timestamp (beginning of phy frame, data frame, end of rx?).
1817 * The only thing we know is that it is hardware specific...
1818 * On AR5213 it seems the rx timestamp is at the end of the
1819 * frame, but i'm not sure.
1821 * NOTE: mac80211 defines mactime at the beginning of the first
1822 * data symbol. Since we don't have any time references it's
1823 * impossible to comply to that. This affects IBSS merge only
1824 * right now, so it's not too bad...
1826 rxs
.mactime
= ath5k_extend_tsf(sc
->ah
, rs
.rs_tstamp
);
1827 rxs
.flag
|= RX_FLAG_TSFT
;
1829 rxs
.freq
= sc
->curchan
->center_freq
;
1830 rxs
.band
= sc
->curband
->band
;
1832 rxs
.noise
= sc
->ah
->ah_noise_floor
;
1833 rxs
.signal
= rxs
.noise
+ rs
.rs_rssi
;
1835 /* An rssi of 35 indicates you should be able use
1836 * 54 Mbps reliably. A more elaborate scheme can be used
1837 * here but it requires a map of SNR/throughput for each
1838 * possible mode used */
1839 rxs
.qual
= rs
.rs_rssi
* 100 / 35;
1841 /* rssi can be more than 35 though, anything above that
1842 * should be considered at 100% */
1846 rxs
.antenna
= rs
.rs_antenna
;
1847 rxs
.rate_idx
= ath5k_hw_to_driver_rix(sc
, rs
.rs_rate
);
1848 rxs
.flag
|= ath5k_rx_decrypted(sc
, ds
, skb
, &rs
);
1850 if (rxs
.rate_idx
>= 0 && rs
.rs_rate
==
1851 sc
->curband
->bitrates
[rxs
.rate_idx
].hw_value_short
)
1852 rxs
.flag
|= RX_FLAG_SHORTPRE
;
1854 ath5k_debug_dump_skb(sc
, skb
, "RX ", 0);
1856 /* check beacons in IBSS mode */
1857 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
)
1858 ath5k_check_ibss_tsf(sc
, skb
, &rxs
);
1860 __ieee80211_rx(sc
->hw
, skb
, &rxs
);
1863 bf
->skbaddr
= next_skb_addr
;
1865 list_move_tail(&bf
->list
, &sc
->rxbuf
);
1866 } while (ath5k_rxbuf_setup(sc
, bf
) == 0);
1868 spin_unlock(&sc
->rxbuflock
);
1879 ath5k_tx_processq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
1881 struct ath5k_tx_status ts
= {};
1882 struct ath5k_buf
*bf
, *bf0
;
1883 struct ath5k_desc
*ds
;
1884 struct sk_buff
*skb
;
1885 struct ieee80211_tx_info
*info
;
1888 spin_lock(&txq
->lock
);
1889 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1892 ret
= sc
->ah
->ah_proc_tx_desc(sc
->ah
, ds
, &ts
);
1893 if (unlikely(ret
== -EINPROGRESS
))
1895 else if (unlikely(ret
)) {
1896 ATH5K_ERR(sc
, "error %d while processing queue %u\n",
1902 info
= IEEE80211_SKB_CB(skb
);
1905 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
,
1908 ieee80211_tx_info_clear_status(info
);
1909 for (i
= 0; i
< 4; i
++) {
1910 struct ieee80211_tx_rate
*r
=
1911 &info
->status
.rates
[i
];
1913 if (ts
.ts_rate
[i
]) {
1914 r
->idx
= ath5k_hw_to_driver_rix(sc
, ts
.ts_rate
[i
]);
1915 r
->count
= ts
.ts_retry
[i
];
1922 /* count the successful attempt as well */
1923 info
->status
.rates
[ts
.ts_final_idx
].count
++;
1925 if (unlikely(ts
.ts_status
)) {
1926 sc
->ll_stats
.dot11ACKFailureCount
++;
1927 if (ts
.ts_status
& AR5K_TXERR_FILT
)
1928 info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
1930 info
->flags
|= IEEE80211_TX_STAT_ACK
;
1931 info
->status
.ack_signal
= ts
.ts_rssi
;
1934 ieee80211_tx_status(sc
->hw
, skb
);
1935 sc
->tx_stats
[txq
->qnum
].count
++;
1937 spin_lock(&sc
->txbuflock
);
1938 sc
->tx_stats
[txq
->qnum
].len
--;
1939 list_move_tail(&bf
->list
, &sc
->txbuf
);
1941 spin_unlock(&sc
->txbuflock
);
1943 if (likely(list_empty(&txq
->q
)))
1945 spin_unlock(&txq
->lock
);
1946 if (sc
->txbuf_len
> ATH_TXBUF
/ 5)
1947 ieee80211_wake_queues(sc
->hw
);
1951 ath5k_tasklet_tx(unsigned long data
)
1953 struct ath5k_softc
*sc
= (void *)data
;
1955 ath5k_tx_processq(sc
, sc
->txq
);
1964 * Setup the beacon frame for transmit.
1967 ath5k_beacon_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1969 struct sk_buff
*skb
= bf
->skb
;
1970 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1971 struct ath5k_hw
*ah
= sc
->ah
;
1972 struct ath5k_desc
*ds
;
1973 int ret
, antenna
= 0;
1976 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
1978 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "skb %p [data %p len %u] "
1979 "skbaddr %llx\n", skb
, skb
->data
, skb
->len
,
1980 (unsigned long long)bf
->skbaddr
);
1981 if (pci_dma_mapping_error(sc
->pdev
, bf
->skbaddr
)) {
1982 ATH5K_ERR(sc
, "beacon DMA mapping failed\n");
1988 flags
= AR5K_TXDESC_NOACK
;
1989 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
&& ath5k_hw_hasveol(ah
)) {
1990 ds
->ds_link
= bf
->daddr
; /* self-linked */
1991 flags
|= AR5K_TXDESC_VEOL
;
1993 * Let hardware handle antenna switching if txantenna is not set
1998 * Switch antenna every 4 beacons if txantenna is not set
1999 * XXX assumes two antennas
2002 antenna
= sc
->bsent
& 4 ? 2 : 1;
2005 ds
->ds_data
= bf
->skbaddr
;
2006 ret
= ah
->ah_setup_tx_desc(ah
, ds
, skb
->len
,
2007 ieee80211_get_hdrlen_from_skb(skb
),
2008 AR5K_PKT_TYPE_BEACON
, (sc
->power_level
* 2),
2009 ieee80211_get_tx_rate(sc
->hw
, info
)->hw_value
,
2010 1, AR5K_TXKEYIX_INVALID
,
2011 antenna
, flags
, 0, 0);
2017 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
2022 * Transmit a beacon frame at SWBA. Dynamic updates to the
2023 * frame contents are done as needed and the slot time is
2024 * also adjusted based on current state.
2026 * this is usually called from interrupt context (ath5k_intr())
2027 * but also from ath5k_beacon_config() in IBSS mode which in turn
2028 * can be called from a tasklet and user context
2031 ath5k_beacon_send(struct ath5k_softc
*sc
)
2033 struct ath5k_buf
*bf
= sc
->bbuf
;
2034 struct ath5k_hw
*ah
= sc
->ah
;
2036 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "in beacon_send\n");
2038 if (unlikely(bf
->skb
== NULL
|| sc
->opmode
== NL80211_IFTYPE_STATION
||
2039 sc
->opmode
== NL80211_IFTYPE_MONITOR
)) {
2040 ATH5K_WARN(sc
, "bf=%p bf_skb=%p\n", bf
, bf
? bf
->skb
: NULL
);
2044 * Check if the previous beacon has gone out. If
2045 * not don't don't try to post another, skip this
2046 * period and wait for the next. Missed beacons
2047 * indicate a problem and should not occur. If we
2048 * miss too many consecutive beacons reset the device.
2050 if (unlikely(ath5k_hw_num_tx_pending(ah
, sc
->bhalq
) != 0)) {
2052 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2053 "missed %u consecutive beacons\n", sc
->bmisscount
);
2054 if (sc
->bmisscount
> 3) { /* NB: 3 is a guess */
2055 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2056 "stuck beacon time (%u missed)\n",
2058 tasklet_schedule(&sc
->restq
);
2062 if (unlikely(sc
->bmisscount
!= 0)) {
2063 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2064 "resume beacon xmit after %u misses\n",
2070 * Stop any current dma and put the new frame on the queue.
2071 * This should never fail since we check above that no frames
2072 * are still pending on the queue.
2074 if (unlikely(ath5k_hw_stop_tx_dma(ah
, sc
->bhalq
))) {
2075 ATH5K_WARN(sc
, "beacon queue %u didn't stop?\n", sc
->bhalq
);
2076 /* NB: hw still stops DMA, so proceed */
2079 ath5k_hw_set_txdp(ah
, sc
->bhalq
, bf
->daddr
);
2080 ath5k_hw_start_tx_dma(ah
, sc
->bhalq
);
2081 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "TXDP[%u] = %llx (%p)\n",
2082 sc
->bhalq
, (unsigned long long)bf
->daddr
, bf
->desc
);
2089 * ath5k_beacon_update_timers - update beacon timers
2091 * @sc: struct ath5k_softc pointer we are operating on
2092 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2093 * beacon timer update based on the current HW TSF.
2095 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2096 * of a received beacon or the current local hardware TSF and write it to the
2097 * beacon timer registers.
2099 * This is called in a variety of situations, e.g. when a beacon is received,
2100 * when a TSF update has been detected, but also when an new IBSS is created or
2101 * when we otherwise know we have to update the timers, but we keep it in this
2102 * function to have it all together in one place.
2105 ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
)
2107 struct ath5k_hw
*ah
= sc
->ah
;
2108 u32 nexttbtt
, intval
, hw_tu
, bc_tu
;
2111 intval
= sc
->bintval
& AR5K_BEACON_PERIOD
;
2112 if (WARN_ON(!intval
))
2115 /* beacon TSF converted to TU */
2116 bc_tu
= TSF_TO_TU(bc_tsf
);
2118 /* current TSF converted to TU */
2119 hw_tsf
= ath5k_hw_get_tsf64(ah
);
2120 hw_tu
= TSF_TO_TU(hw_tsf
);
2123 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2126 * no beacons received, called internally.
2127 * just need to refresh timers based on HW TSF.
2129 nexttbtt
= roundup(hw_tu
+ FUDGE
, intval
);
2130 } else if (bc_tsf
== 0) {
2132 * no beacon received, probably called by ath5k_reset_tsf().
2133 * reset TSF to start with 0.
2136 intval
|= AR5K_BEACON_RESET_TSF
;
2137 } else if (bc_tsf
> hw_tsf
) {
2139 * beacon received, SW merge happend but HW TSF not yet updated.
2140 * not possible to reconfigure timers yet, but next time we
2141 * receive a beacon with the same BSSID, the hardware will
2142 * automatically update the TSF and then we need to reconfigure
2145 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2146 "need to wait for HW TSF sync\n");
2150 * most important case for beacon synchronization between STA.
2152 * beacon received and HW TSF has been already updated by HW.
2153 * update next TBTT based on the TSF of the beacon, but make
2154 * sure it is ahead of our local TSF timer.
2156 nexttbtt
= bc_tu
+ roundup(hw_tu
+ FUDGE
- bc_tu
, intval
);
2160 sc
->nexttbtt
= nexttbtt
;
2162 intval
|= AR5K_BEACON_ENA
;
2163 ath5k_hw_init_beacon(ah
, nexttbtt
, intval
);
2166 * debugging output last in order to preserve the time critical aspect
2170 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2171 "reconfigured timers based on HW TSF\n");
2172 else if (bc_tsf
== 0)
2173 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2174 "reset HW TSF and timers\n");
2176 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2177 "updated timers based on beacon TSF\n");
2179 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2180 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2181 (unsigned long long) bc_tsf
,
2182 (unsigned long long) hw_tsf
, bc_tu
, hw_tu
, nexttbtt
);
2183 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "intval %u %s %s\n",
2184 intval
& AR5K_BEACON_PERIOD
,
2185 intval
& AR5K_BEACON_ENA
? "AR5K_BEACON_ENA" : "",
2186 intval
& AR5K_BEACON_RESET_TSF
? "AR5K_BEACON_RESET_TSF" : "");
2191 * ath5k_beacon_config - Configure the beacon queues and interrupts
2193 * @sc: struct ath5k_softc pointer we are operating on
2195 * When operating in station mode we want to receive a BMISS interrupt when we
2196 * stop seeing beacons from the AP we've associated with so we can look for
2197 * another AP to associate with.
2199 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2200 * interrupts to detect TSF updates only.
2203 ath5k_beacon_config(struct ath5k_softc
*sc
)
2205 struct ath5k_hw
*ah
= sc
->ah
;
2207 ath5k_hw_set_imr(ah
, 0);
2209 sc
->imask
&= ~(AR5K_INT_BMISS
| AR5K_INT_SWBA
);
2211 if (sc
->opmode
== NL80211_IFTYPE_STATION
) {
2212 sc
->imask
|= AR5K_INT_BMISS
;
2213 } else if (sc
->opmode
== NL80211_IFTYPE_ADHOC
||
2214 sc
->opmode
== NL80211_IFTYPE_MESH_POINT
||
2215 sc
->opmode
== NL80211_IFTYPE_AP
) {
2217 * In IBSS mode we use a self-linked tx descriptor and let the
2218 * hardware send the beacons automatically. We have to load it
2220 * We use the SWBA interrupt only to keep track of the beacon
2221 * timers in order to detect automatic TSF updates.
2223 ath5k_beaconq_config(sc
);
2225 sc
->imask
|= AR5K_INT_SWBA
;
2227 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
2228 if (ath5k_hw_hasveol(ah
)) {
2229 spin_lock(&sc
->block
);
2230 ath5k_beacon_send(sc
);
2231 spin_unlock(&sc
->block
);
2234 ath5k_beacon_update_timers(sc
, -1);
2237 ath5k_hw_set_imr(ah
, sc
->imask
);
2241 /********************\
2242 * Interrupt handling *
2243 \********************/
2246 ath5k_init(struct ath5k_softc
*sc
)
2248 struct ath5k_hw
*ah
= sc
->ah
;
2251 mutex_lock(&sc
->lock
);
2253 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "mode %d\n", sc
->opmode
);
2256 * Stop anything previously setup. This is safe
2257 * no matter this is the first time through or not.
2259 ath5k_stop_locked(sc
);
2262 * The basic interface to setting the hardware in a good
2263 * state is ``reset''. On return the hardware is known to
2264 * be powered up and with interrupts disabled. This must
2265 * be followed by initialization of the appropriate bits
2266 * and then setup of the interrupt mask.
2268 sc
->curchan
= sc
->hw
->conf
.channel
;
2269 sc
->curband
= &sc
->sbands
[sc
->curchan
->band
];
2270 sc
->imask
= AR5K_INT_RXOK
| AR5K_INT_RXERR
| AR5K_INT_RXEOL
|
2271 AR5K_INT_RXORN
| AR5K_INT_TXDESC
| AR5K_INT_TXEOL
|
2272 AR5K_INT_FATAL
| AR5K_INT_GLOBAL
| AR5K_INT_MIB
;
2273 ret
= ath5k_reset(sc
, false, false);
2278 * Reset the key cache since some parts do not reset the
2279 * contents on initial power up or resume from suspend.
2281 for (i
= 0; i
< AR5K_KEYTABLE_SIZE
; i
++)
2282 ath5k_hw_reset_key(ah
, i
);
2284 /* Set ack to be sent at low bit-rates */
2285 ath5k_hw_set_ack_bitrate_high(ah
, false);
2287 mod_timer(&sc
->calib_tim
, round_jiffies(jiffies
+
2288 msecs_to_jiffies(ath5k_calinterval
* 1000)));
2293 mutex_unlock(&sc
->lock
);
2298 ath5k_stop_locked(struct ath5k_softc
*sc
)
2300 struct ath5k_hw
*ah
= sc
->ah
;
2302 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "invalid %u\n",
2303 test_bit(ATH_STAT_INVALID
, sc
->status
));
2306 * Shutdown the hardware and driver:
2307 * stop output from above
2308 * disable interrupts
2310 * turn off the radio
2311 * clear transmit machinery
2312 * clear receive machinery
2313 * drain and release tx queues
2314 * reclaim beacon resources
2315 * power down hardware
2317 * Note that some of this work is not possible if the
2318 * hardware is gone (invalid).
2320 ieee80211_stop_queues(sc
->hw
);
2322 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2324 ath5k_hw_set_imr(ah
, 0);
2325 synchronize_irq(sc
->pdev
->irq
);
2327 ath5k_txq_cleanup(sc
);
2328 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2330 ath5k_hw_phy_disable(ah
);
2338 * Stop the device, grabbing the top-level lock to protect
2339 * against concurrent entry through ath5k_init (which can happen
2340 * if another thread does a system call and the thread doing the
2341 * stop is preempted).
2344 ath5k_stop_hw(struct ath5k_softc
*sc
)
2348 mutex_lock(&sc
->lock
);
2349 ret
= ath5k_stop_locked(sc
);
2350 if (ret
== 0 && !test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2352 * Set the chip in full sleep mode. Note that we are
2353 * careful to do this only when bringing the interface
2354 * completely to a stop. When the chip is in this state
2355 * it must be carefully woken up or references to
2356 * registers in the PCI clock domain may freeze the bus
2357 * (and system). This varies by chip and is mostly an
2358 * issue with newer parts that go to sleep more quickly.
2360 if (sc
->ah
->ah_mac_srev
>= 0x78) {
2363 * don't put newer MAC revisions > 7.8 to sleep because
2364 * of the above mentioned problems
2366 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "mac version > 7.8, "
2367 "not putting device to sleep\n");
2369 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
2370 "putting device to full sleep\n");
2371 ath5k_hw_set_power(sc
->ah
, AR5K_PM_FULL_SLEEP
, true, 0);
2374 ath5k_txbuf_free(sc
, sc
->bbuf
);
2377 mutex_unlock(&sc
->lock
);
2379 del_timer_sync(&sc
->calib_tim
);
2380 tasklet_kill(&sc
->rxtq
);
2381 tasklet_kill(&sc
->txtq
);
2382 tasklet_kill(&sc
->restq
);
2388 ath5k_intr(int irq
, void *dev_id
)
2390 struct ath5k_softc
*sc
= dev_id
;
2391 struct ath5k_hw
*ah
= sc
->ah
;
2392 enum ath5k_int status
;
2393 unsigned int counter
= 1000;
2395 if (unlikely(test_bit(ATH_STAT_INVALID
, sc
->status
) ||
2396 !ath5k_hw_is_intr_pending(ah
)))
2401 * Figure out the reason(s) for the interrupt. Note
2402 * that get_isr returns a pseudo-ISR that may include
2403 * bits we haven't explicitly enabled so we mask the
2404 * value to insure we only process bits we requested.
2406 ath5k_hw_get_isr(ah
, &status
); /* NB: clears IRQ too */
2407 ATH5K_DBG(sc
, ATH5K_DEBUG_INTR
, "status 0x%x/0x%x\n",
2409 status
&= sc
->imask
; /* discard unasked for bits */
2410 if (unlikely(status
& AR5K_INT_FATAL
)) {
2412 * Fatal errors are unrecoverable.
2413 * Typically these are caused by DMA errors.
2415 tasklet_schedule(&sc
->restq
);
2416 } else if (unlikely(status
& AR5K_INT_RXORN
)) {
2417 tasklet_schedule(&sc
->restq
);
2419 if (status
& AR5K_INT_SWBA
) {
2421 * Software beacon alert--time to send a beacon.
2422 * Handle beacon transmission directly; deferring
2423 * this is too slow to meet timing constraints
2426 * In IBSS mode we use this interrupt just to
2427 * keep track of the next TBTT (target beacon
2428 * transmission time) in order to detect wether
2429 * automatic TSF updates happened.
2431 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
2432 /* XXX: only if VEOL suppported */
2433 u64 tsf
= ath5k_hw_get_tsf64(ah
);
2434 sc
->nexttbtt
+= sc
->bintval
;
2435 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2436 "SWBA nexttbtt: %x hw_tu: %x "
2440 (unsigned long long) tsf
);
2442 spin_lock(&sc
->block
);
2443 ath5k_beacon_send(sc
);
2444 spin_unlock(&sc
->block
);
2447 if (status
& AR5K_INT_RXEOL
) {
2449 * NB: the hardware should re-read the link when
2450 * RXE bit is written, but it doesn't work at
2451 * least on older hardware revs.
2455 if (status
& AR5K_INT_TXURN
) {
2456 /* bump tx trigger level */
2457 ath5k_hw_update_tx_triglevel(ah
, true);
2459 if (status
& (AR5K_INT_RXOK
| AR5K_INT_RXERR
))
2460 tasklet_schedule(&sc
->rxtq
);
2461 if (status
& (AR5K_INT_TXOK
| AR5K_INT_TXDESC
2462 | AR5K_INT_TXERR
| AR5K_INT_TXEOL
))
2463 tasklet_schedule(&sc
->txtq
);
2464 if (status
& AR5K_INT_BMISS
) {
2466 if (status
& AR5K_INT_MIB
) {
2468 * These stats are also used for ANI i think
2469 * so how about updating them more often ?
2471 ath5k_hw_update_mib_counters(ah
, &sc
->ll_stats
);
2474 } while (ath5k_hw_is_intr_pending(ah
) && counter
-- > 0);
2476 if (unlikely(!counter
))
2477 ATH5K_WARN(sc
, "too many interrupts, giving up for now\n");
2483 ath5k_tasklet_reset(unsigned long data
)
2485 struct ath5k_softc
*sc
= (void *)data
;
2487 ath5k_reset_wake(sc
);
2491 * Periodically recalibrate the PHY to account
2492 * for temperature/environment changes.
2495 ath5k_calibrate(unsigned long data
)
2497 struct ath5k_softc
*sc
= (void *)data
;
2498 struct ath5k_hw
*ah
= sc
->ah
;
2500 ATH5K_DBG(sc
, ATH5K_DEBUG_CALIBRATE
, "channel %u/%x\n",
2501 ieee80211_frequency_to_channel(sc
->curchan
->center_freq
),
2502 sc
->curchan
->hw_value
);
2504 if (ath5k_hw_get_rf_gain(ah
) == AR5K_RFGAIN_NEED_CHANGE
) {
2506 * Rfgain is out of bounds, reset the chip
2507 * to load new gain values.
2509 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "calibration, resetting\n");
2510 ath5k_reset_wake(sc
);
2512 if (ath5k_hw_phy_calibrate(ah
, sc
->curchan
))
2513 ATH5K_ERR(sc
, "calibration of channel %u failed\n",
2514 ieee80211_frequency_to_channel(
2515 sc
->curchan
->center_freq
));
2517 mod_timer(&sc
->calib_tim
, round_jiffies(jiffies
+
2518 msecs_to_jiffies(ath5k_calinterval
* 1000)));
2528 ath5k_led_enable(struct ath5k_softc
*sc
)
2530 if (test_bit(ATH_STAT_LEDSOFT
, sc
->status
)) {
2531 ath5k_hw_set_gpio_output(sc
->ah
, sc
->led_pin
);
2537 ath5k_led_on(struct ath5k_softc
*sc
)
2539 if (!test_bit(ATH_STAT_LEDSOFT
, sc
->status
))
2541 ath5k_hw_set_gpio(sc
->ah
, sc
->led_pin
, sc
->led_on
);
2545 ath5k_led_off(struct ath5k_softc
*sc
)
2547 if (!test_bit(ATH_STAT_LEDSOFT
, sc
->status
))
2549 ath5k_hw_set_gpio(sc
->ah
, sc
->led_pin
, !sc
->led_on
);
2553 ath5k_led_brightness_set(struct led_classdev
*led_dev
,
2554 enum led_brightness brightness
)
2556 struct ath5k_led
*led
= container_of(led_dev
, struct ath5k_led
,
2559 if (brightness
== LED_OFF
)
2560 ath5k_led_off(led
->sc
);
2562 ath5k_led_on(led
->sc
);
2566 ath5k_register_led(struct ath5k_softc
*sc
, struct ath5k_led
*led
,
2567 const char *name
, char *trigger
)
2572 strncpy(led
->name
, name
, sizeof(led
->name
));
2573 led
->led_dev
.name
= led
->name
;
2574 led
->led_dev
.default_trigger
= trigger
;
2575 led
->led_dev
.brightness_set
= ath5k_led_brightness_set
;
2577 err
= led_classdev_register(&sc
->pdev
->dev
, &led
->led_dev
);
2579 ATH5K_WARN(sc
, "could not register LED %s\n", name
);
2586 ath5k_unregister_led(struct ath5k_led
*led
)
2590 led_classdev_unregister(&led
->led_dev
);
2591 ath5k_led_off(led
->sc
);
2596 ath5k_unregister_leds(struct ath5k_softc
*sc
)
2598 ath5k_unregister_led(&sc
->rx_led
);
2599 ath5k_unregister_led(&sc
->tx_led
);
2604 ath5k_init_leds(struct ath5k_softc
*sc
)
2607 struct ieee80211_hw
*hw
= sc
->hw
;
2608 struct pci_dev
*pdev
= sc
->pdev
;
2609 char name
[ATH5K_LED_MAX_NAME_LEN
+ 1];
2612 * Auto-enable soft led processing for IBM cards and for
2613 * 5211 minipci cards.
2615 if (pdev
->device
== PCI_DEVICE_ID_ATHEROS_AR5212_IBM
||
2616 pdev
->device
== PCI_DEVICE_ID_ATHEROS_AR5211
) {
2617 __set_bit(ATH_STAT_LEDSOFT
, sc
->status
);
2619 sc
->led_on
= 0; /* active low */
2621 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2622 if (pdev
->subsystem_vendor
== PCI_VENDOR_ID_COMPAQ
) {
2623 __set_bit(ATH_STAT_LEDSOFT
, sc
->status
);
2625 sc
->led_on
= 1; /* active high */
2627 /* Pin 3 on Foxconn chips used in Acer Aspire One (0x105b:e008) */
2628 if (pdev
->subsystem_vendor
== PCI_VENDOR_ID_FOXCONN
) {
2629 __set_bit(ATH_STAT_LEDSOFT
, sc
->status
);
2631 sc
->led_on
= 0; /* active low */
2634 if (!test_bit(ATH_STAT_LEDSOFT
, sc
->status
))
2637 ath5k_led_enable(sc
);
2639 snprintf(name
, sizeof(name
), "ath5k-%s::rx", wiphy_name(hw
->wiphy
));
2640 ret
= ath5k_register_led(sc
, &sc
->rx_led
, name
,
2641 ieee80211_get_rx_led_name(hw
));
2645 snprintf(name
, sizeof(name
), "ath5k-%s::tx", wiphy_name(hw
->wiphy
));
2646 ret
= ath5k_register_led(sc
, &sc
->tx_led
, name
,
2647 ieee80211_get_tx_led_name(hw
));
2653 /********************\
2654 * Mac80211 functions *
2655 \********************/
2658 ath5k_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
)
2660 struct ath5k_softc
*sc
= hw
->priv
;
2661 struct ath5k_buf
*bf
;
2662 unsigned long flags
;
2666 ath5k_debug_dump_skb(sc
, skb
, "TX ", 1);
2668 if (sc
->opmode
== NL80211_IFTYPE_MONITOR
)
2669 ATH5K_DBG(sc
, ATH5K_DEBUG_XMIT
, "tx in monitor (scan?)\n");
2672 * the hardware expects the header padded to 4 byte boundaries
2673 * if this is not the case we add the padding after the header
2675 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
2676 padsize
= ath5k_pad_size(hdrlen
);
2679 if (skb_headroom(skb
) < padsize
) {
2680 ATH5K_ERR(sc
, "tx hdrlen not %%4: %d not enough"
2681 " headroom to pad %d\n", hdrlen
, padsize
);
2682 return NETDEV_TX_BUSY
;
2684 skb_push(skb
, padsize
);
2685 memmove(skb
->data
, skb
->data
+padsize
, hdrlen
);
2688 spin_lock_irqsave(&sc
->txbuflock
, flags
);
2689 if (list_empty(&sc
->txbuf
)) {
2690 ATH5K_ERR(sc
, "no further txbuf available, dropping packet\n");
2691 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2692 ieee80211_stop_queue(hw
, skb_get_queue_mapping(skb
));
2693 return NETDEV_TX_BUSY
;
2695 bf
= list_first_entry(&sc
->txbuf
, struct ath5k_buf
, list
);
2696 list_del(&bf
->list
);
2698 if (list_empty(&sc
->txbuf
))
2699 ieee80211_stop_queues(hw
);
2700 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2704 if (ath5k_txbuf_setup(sc
, bf
)) {
2706 spin_lock_irqsave(&sc
->txbuflock
, flags
);
2707 list_add_tail(&bf
->list
, &sc
->txbuf
);
2709 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2710 dev_kfree_skb_any(skb
);
2711 return NETDEV_TX_OK
;
2714 return NETDEV_TX_OK
;
2718 ath5k_reset(struct ath5k_softc
*sc
, bool stop
, bool change_channel
)
2720 struct ath5k_hw
*ah
= sc
->ah
;
2723 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "resetting\n");
2726 ath5k_hw_set_imr(ah
, 0);
2727 ath5k_txq_cleanup(sc
);
2730 ret
= ath5k_hw_reset(ah
, sc
->opmode
, sc
->curchan
, true);
2732 ATH5K_ERR(sc
, "can't reset hardware (%d)\n", ret
);
2737 * This is needed only to setup initial state
2738 * but it's best done after a reset.
2740 ath5k_hw_set_txpower_limit(sc
->ah
, 0);
2742 ret
= ath5k_rx_start(sc
);
2744 ATH5K_ERR(sc
, "can't start recv logic\n");
2749 * Change channels and update the h/w rate map if we're switching;
2750 * e.g. 11a to 11b/g.
2752 * We may be doing a reset in response to an ioctl that changes the
2753 * channel so update any state that might change as a result.
2757 /* ath5k_chan_change(sc, c); */
2759 ath5k_beacon_config(sc
);
2760 /* intrs are enabled by ath5k_beacon_config */
2768 ath5k_reset_wake(struct ath5k_softc
*sc
)
2772 ret
= ath5k_reset(sc
, true, true);
2774 ieee80211_wake_queues(sc
->hw
);
2779 static int ath5k_start(struct ieee80211_hw
*hw
)
2781 return ath5k_init(hw
->priv
);
2784 static void ath5k_stop(struct ieee80211_hw
*hw
)
2786 ath5k_stop_hw(hw
->priv
);
2789 static int ath5k_add_interface(struct ieee80211_hw
*hw
,
2790 struct ieee80211_if_init_conf
*conf
)
2792 struct ath5k_softc
*sc
= hw
->priv
;
2795 mutex_lock(&sc
->lock
);
2801 sc
->vif
= conf
->vif
;
2803 switch (conf
->type
) {
2804 case NL80211_IFTYPE_AP
:
2805 case NL80211_IFTYPE_STATION
:
2806 case NL80211_IFTYPE_ADHOC
:
2807 case NL80211_IFTYPE_MESH_POINT
:
2808 case NL80211_IFTYPE_MONITOR
:
2809 sc
->opmode
= conf
->type
;
2816 /* Set to a reasonable value. Note that this will
2817 * be set to mac80211's value at ath5k_config(). */
2819 ath5k_hw_set_lladdr(sc
->ah
, conf
->mac_addr
);
2823 mutex_unlock(&sc
->lock
);
2828 ath5k_remove_interface(struct ieee80211_hw
*hw
,
2829 struct ieee80211_if_init_conf
*conf
)
2831 struct ath5k_softc
*sc
= hw
->priv
;
2832 u8 mac
[ETH_ALEN
] = {};
2834 mutex_lock(&sc
->lock
);
2835 if (sc
->vif
!= conf
->vif
)
2838 ath5k_hw_set_lladdr(sc
->ah
, mac
);
2841 mutex_unlock(&sc
->lock
);
2845 * TODO: Phy disable/diversity etc
2848 ath5k_config(struct ieee80211_hw
*hw
, u32 changed
)
2850 struct ath5k_softc
*sc
= hw
->priv
;
2851 struct ieee80211_conf
*conf
= &hw
->conf
;
2853 sc
->bintval
= conf
->beacon_int
;
2854 sc
->power_level
= conf
->power_level
;
2856 return ath5k_chan_set(sc
, conf
->channel
);
2860 ath5k_config_interface(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
2861 struct ieee80211_if_conf
*conf
)
2863 struct ath5k_softc
*sc
= hw
->priv
;
2864 struct ath5k_hw
*ah
= sc
->ah
;
2867 mutex_lock(&sc
->lock
);
2868 if (sc
->vif
!= vif
) {
2872 if (conf
->changed
& IEEE80211_IFCC_BSSID
&& conf
->bssid
) {
2873 /* Cache for later use during resets */
2874 memcpy(ah
->ah_bssid
, conf
->bssid
, ETH_ALEN
);
2875 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2876 * a clean way of letting us retrieve this yet. */
2877 ath5k_hw_set_associd(ah
, ah
->ah_bssid
, 0);
2880 if (conf
->changed
& IEEE80211_IFCC_BEACON
&&
2881 (vif
->type
== NL80211_IFTYPE_ADHOC
||
2882 vif
->type
== NL80211_IFTYPE_MESH_POINT
||
2883 vif
->type
== NL80211_IFTYPE_AP
)) {
2884 struct sk_buff
*beacon
= ieee80211_beacon_get(hw
, vif
);
2889 ath5k_beacon_update(sc
, beacon
);
2891 mutex_unlock(&sc
->lock
);
2893 return ath5k_reset_wake(sc
);
2895 mutex_unlock(&sc
->lock
);
2899 #define SUPPORTED_FIF_FLAGS \
2900 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2901 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2902 FIF_BCN_PRBRESP_PROMISC
2904 * o always accept unicast, broadcast, and multicast traffic
2905 * o multicast traffic for all BSSIDs will be enabled if mac80211
2907 * o maintain current state of phy ofdm or phy cck error reception.
2908 * If the hardware detects any of these type of errors then
2909 * ath5k_hw_get_rx_filter() will pass to us the respective
2910 * hardware filters to be able to receive these type of frames.
2911 * o probe request frames are accepted only when operating in
2912 * hostap, adhoc, or monitor modes
2913 * o enable promiscuous mode according to the interface state
2915 * - when operating in adhoc mode so the 802.11 layer creates
2916 * node table entries for peers,
2917 * - when operating in station mode for collecting rssi data when
2918 * the station is otherwise quiet, or
2921 static void ath5k_configure_filter(struct ieee80211_hw
*hw
,
2922 unsigned int changed_flags
,
2923 unsigned int *new_flags
,
2924 int mc_count
, struct dev_mc_list
*mclist
)
2926 struct ath5k_softc
*sc
= hw
->priv
;
2927 struct ath5k_hw
*ah
= sc
->ah
;
2928 u32 mfilt
[2], val
, rfilt
;
2935 /* Only deal with supported flags */
2936 changed_flags
&= SUPPORTED_FIF_FLAGS
;
2937 *new_flags
&= SUPPORTED_FIF_FLAGS
;
2939 /* If HW detects any phy or radar errors, leave those filters on.
2940 * Also, always enable Unicast, Broadcasts and Multicast
2941 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2942 rfilt
= (ath5k_hw_get_rx_filter(ah
) & (AR5K_RX_FILTER_PHYERR
)) |
2943 (AR5K_RX_FILTER_UCAST
| AR5K_RX_FILTER_BCAST
|
2944 AR5K_RX_FILTER_MCAST
);
2946 if (changed_flags
& (FIF_PROMISC_IN_BSS
| FIF_OTHER_BSS
)) {
2947 if (*new_flags
& FIF_PROMISC_IN_BSS
) {
2948 rfilt
|= AR5K_RX_FILTER_PROM
;
2949 __set_bit(ATH_STAT_PROMISC
, sc
->status
);
2951 __clear_bit(ATH_STAT_PROMISC
, sc
->status
);
2955 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2956 if (*new_flags
& FIF_ALLMULTI
) {
2960 for (i
= 0; i
< mc_count
; i
++) {
2963 /* calculate XOR of eight 6-bit values */
2964 val
= get_unaligned_le32(mclist
->dmi_addr
+ 0);
2965 pos
= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
2966 val
= get_unaligned_le32(mclist
->dmi_addr
+ 3);
2967 pos
^= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
2969 mfilt
[pos
/ 32] |= (1 << (pos
% 32));
2970 /* XXX: we might be able to just do this instead,
2971 * but not sure, needs testing, if we do use this we'd
2972 * neet to inform below to not reset the mcast */
2973 /* ath5k_hw_set_mcast_filterindex(ah,
2974 * mclist->dmi_addr[5]); */
2975 mclist
= mclist
->next
;
2979 /* This is the best we can do */
2980 if (*new_flags
& (FIF_FCSFAIL
| FIF_PLCPFAIL
))
2981 rfilt
|= AR5K_RX_FILTER_PHYERR
;
2983 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2984 * and probes for any BSSID, this needs testing */
2985 if (*new_flags
& FIF_BCN_PRBRESP_PROMISC
)
2986 rfilt
|= AR5K_RX_FILTER_BEACON
| AR5K_RX_FILTER_PROBEREQ
;
2988 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2989 * set we should only pass on control frames for this
2990 * station. This needs testing. I believe right now this
2991 * enables *all* control frames, which is OK.. but
2992 * but we should see if we can improve on granularity */
2993 if (*new_flags
& FIF_CONTROL
)
2994 rfilt
|= AR5K_RX_FILTER_CONTROL
;
2996 /* Additional settings per mode -- this is per ath5k */
2998 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3000 if (sc
->opmode
== NL80211_IFTYPE_MONITOR
)
3001 rfilt
|= AR5K_RX_FILTER_CONTROL
| AR5K_RX_FILTER_BEACON
|
3002 AR5K_RX_FILTER_PROBEREQ
| AR5K_RX_FILTER_PROM
;
3003 if (sc
->opmode
!= NL80211_IFTYPE_STATION
)
3004 rfilt
|= AR5K_RX_FILTER_PROBEREQ
;
3005 if (sc
->opmode
!= NL80211_IFTYPE_AP
&&
3006 sc
->opmode
!= NL80211_IFTYPE_MESH_POINT
&&
3007 test_bit(ATH_STAT_PROMISC
, sc
->status
))
3008 rfilt
|= AR5K_RX_FILTER_PROM
;
3009 if ((sc
->opmode
== NL80211_IFTYPE_STATION
&& sc
->assoc
) ||
3010 sc
->opmode
== NL80211_IFTYPE_ADHOC
||
3011 sc
->opmode
== NL80211_IFTYPE_AP
)
3012 rfilt
|= AR5K_RX_FILTER_BEACON
;
3013 if (sc
->opmode
== NL80211_IFTYPE_MESH_POINT
)
3014 rfilt
|= AR5K_RX_FILTER_CONTROL
| AR5K_RX_FILTER_BEACON
|
3015 AR5K_RX_FILTER_PROBEREQ
| AR5K_RX_FILTER_PROM
;
3018 ath5k_hw_set_rx_filter(ah
, rfilt
);
3020 /* Set multicast bits */
3021 ath5k_hw_set_mcast_filter(ah
, mfilt
[0], mfilt
[1]);
3022 /* Set the cached hw filter flags, this will alter actually
3024 sc
->filter_flags
= rfilt
;
3028 ath5k_set_key(struct ieee80211_hw
*hw
, enum set_key_cmd cmd
,
3029 struct ieee80211_vif
*vif
, struct ieee80211_sta
*sta
,
3030 struct ieee80211_key_conf
*key
)
3032 struct ath5k_softc
*sc
= hw
->priv
;
3035 if (modparam_nohwcrypt
)
3049 mutex_lock(&sc
->lock
);
3053 ret
= ath5k_hw_set_key(sc
->ah
, key
->keyidx
, key
,
3054 sta
? sta
->addr
: NULL
);
3056 ATH5K_ERR(sc
, "can't set the key\n");
3059 __set_bit(key
->keyidx
, sc
->keymap
);
3060 key
->hw_key_idx
= key
->keyidx
;
3061 key
->flags
|= (IEEE80211_KEY_FLAG_GENERATE_IV
|
3062 IEEE80211_KEY_FLAG_GENERATE_MMIC
);
3065 ath5k_hw_reset_key(sc
->ah
, key
->keyidx
);
3066 __clear_bit(key
->keyidx
, sc
->keymap
);
3075 mutex_unlock(&sc
->lock
);
3080 ath5k_get_stats(struct ieee80211_hw
*hw
,
3081 struct ieee80211_low_level_stats
*stats
)
3083 struct ath5k_softc
*sc
= hw
->priv
;
3084 struct ath5k_hw
*ah
= sc
->ah
;
3087 ath5k_hw_update_mib_counters(ah
, &sc
->ll_stats
);
3089 memcpy(stats
, &sc
->ll_stats
, sizeof(sc
->ll_stats
));
3095 ath5k_get_tx_stats(struct ieee80211_hw
*hw
,
3096 struct ieee80211_tx_queue_stats
*stats
)
3098 struct ath5k_softc
*sc
= hw
->priv
;
3100 memcpy(stats
, &sc
->tx_stats
, sizeof(sc
->tx_stats
));
3106 ath5k_get_tsf(struct ieee80211_hw
*hw
)
3108 struct ath5k_softc
*sc
= hw
->priv
;
3110 return ath5k_hw_get_tsf64(sc
->ah
);
3114 ath5k_reset_tsf(struct ieee80211_hw
*hw
)
3116 struct ath5k_softc
*sc
= hw
->priv
;
3119 * in IBSS mode we need to update the beacon timers too.
3120 * this will also reset the TSF if we call it with 0
3122 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
)
3123 ath5k_beacon_update_timers(sc
, 0);
3125 ath5k_hw_reset_tsf(sc
->ah
);
3129 ath5k_beacon_update(struct ath5k_softc
*sc
, struct sk_buff
*skb
)
3131 unsigned long flags
;
3134 ath5k_debug_dump_skb(sc
, skb
, "BC ", 1);
3136 spin_lock_irqsave(&sc
->block
, flags
);
3137 ath5k_txbuf_free(sc
, sc
->bbuf
);
3138 sc
->bbuf
->skb
= skb
;
3139 ret
= ath5k_beacon_setup(sc
, sc
->bbuf
);
3141 sc
->bbuf
->skb
= NULL
;
3142 spin_unlock_irqrestore(&sc
->block
, flags
);
3144 ath5k_beacon_config(sc
);
3151 set_beacon_filter(struct ieee80211_hw
*hw
, bool enable
)
3153 struct ath5k_softc
*sc
= hw
->priv
;
3154 struct ath5k_hw
*ah
= sc
->ah
;
3156 rfilt
= ath5k_hw_get_rx_filter(ah
);
3158 rfilt
|= AR5K_RX_FILTER_BEACON
;
3160 rfilt
&= ~AR5K_RX_FILTER_BEACON
;
3161 ath5k_hw_set_rx_filter(ah
, rfilt
);
3162 sc
->filter_flags
= rfilt
;
3165 static void ath5k_bss_info_changed(struct ieee80211_hw
*hw
,
3166 struct ieee80211_vif
*vif
,
3167 struct ieee80211_bss_conf
*bss_conf
,
3170 struct ath5k_softc
*sc
= hw
->priv
;
3171 if (changes
& BSS_CHANGED_ASSOC
) {
3172 mutex_lock(&sc
->lock
);
3173 sc
->assoc
= bss_conf
->assoc
;
3174 if (sc
->opmode
== NL80211_IFTYPE_STATION
)
3175 set_beacon_filter(hw
, sc
->assoc
);
3176 mutex_unlock(&sc
->lock
);