1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/module.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/vmalloc.h>
32 #include <linux/pagemap.h>
33 #include <linux/netdevice.h>
34 #include <linux/ipv6.h>
35 #include <net/checksum.h>
36 #include <net/ip6_checksum.h>
37 #include <linux/net_tstamp.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40 #include <linux/if_vlan.h>
41 #include <linux/pci.h>
42 #include <linux/pci-aspm.h>
43 #include <linux/delay.h>
44 #include <linux/interrupt.h>
45 #include <linux/if_ether.h>
46 #include <linux/aer.h>
48 #include <linux/dca.h>
52 #define DRV_VERSION "1.3.16-k2"
53 char igb_driver_name
[] = "igb";
54 char igb_driver_version
[] = DRV_VERSION
;
55 static const char igb_driver_string
[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
57 static const char igb_copyright
[] = "Copyright (c) 2007-2009 Intel Corporation.";
59 static const struct e1000_info
*igb_info_tbl
[] = {
60 [board_82575
] = &e1000_82575_info
,
63 static struct pci_device_id igb_pci_tbl
[] = {
64 { PCI_VDEVICE(INTEL
, E1000_DEV_ID_82576
), board_82575
},
65 { PCI_VDEVICE(INTEL
, E1000_DEV_ID_82576_NS
), board_82575
},
66 { PCI_VDEVICE(INTEL
, E1000_DEV_ID_82576_NS_SERDES
), board_82575
},
67 { PCI_VDEVICE(INTEL
, E1000_DEV_ID_82576_FIBER
), board_82575
},
68 { PCI_VDEVICE(INTEL
, E1000_DEV_ID_82576_SERDES
), board_82575
},
69 { PCI_VDEVICE(INTEL
, E1000_DEV_ID_82576_SERDES_QUAD
), board_82575
},
70 { PCI_VDEVICE(INTEL
, E1000_DEV_ID_82576_QUAD_COPPER
), board_82575
},
71 { PCI_VDEVICE(INTEL
, E1000_DEV_ID_82575EB_COPPER
), board_82575
},
72 { PCI_VDEVICE(INTEL
, E1000_DEV_ID_82575EB_FIBER_SERDES
), board_82575
},
73 { PCI_VDEVICE(INTEL
, E1000_DEV_ID_82575GB_QUAD_COPPER
), board_82575
},
74 /* required last entry */
78 MODULE_DEVICE_TABLE(pci
, igb_pci_tbl
);
80 void igb_reset(struct igb_adapter
*);
81 static int igb_setup_all_tx_resources(struct igb_adapter
*);
82 static int igb_setup_all_rx_resources(struct igb_adapter
*);
83 static void igb_free_all_tx_resources(struct igb_adapter
*);
84 static void igb_free_all_rx_resources(struct igb_adapter
*);
85 void igb_update_stats(struct igb_adapter
*);
86 static int igb_probe(struct pci_dev
*, const struct pci_device_id
*);
87 static void __devexit
igb_remove(struct pci_dev
*pdev
);
88 static int igb_sw_init(struct igb_adapter
*);
89 static int igb_open(struct net_device
*);
90 static int igb_close(struct net_device
*);
91 static void igb_configure_tx(struct igb_adapter
*);
92 static void igb_configure_rx(struct igb_adapter
*);
93 static void igb_setup_rctl(struct igb_adapter
*);
94 static void igb_clean_all_tx_rings(struct igb_adapter
*);
95 static void igb_clean_all_rx_rings(struct igb_adapter
*);
96 static void igb_clean_tx_ring(struct igb_ring
*);
97 static void igb_clean_rx_ring(struct igb_ring
*);
98 static void igb_set_rx_mode(struct net_device
*);
99 static void igb_update_phy_info(unsigned long);
100 static void igb_watchdog(unsigned long);
101 static void igb_watchdog_task(struct work_struct
*);
102 static netdev_tx_t
igb_xmit_frame_ring_adv(struct sk_buff
*,
105 static netdev_tx_t
igb_xmit_frame_adv(struct sk_buff
*skb
,
106 struct net_device
*);
107 static struct net_device_stats
*igb_get_stats(struct net_device
*);
108 static int igb_change_mtu(struct net_device
*, int);
109 static int igb_set_mac(struct net_device
*, void *);
110 static void igb_set_uta(struct igb_adapter
*adapter
);
111 static irqreturn_t
igb_intr(int irq
, void *);
112 static irqreturn_t
igb_intr_msi(int irq
, void *);
113 static irqreturn_t
igb_msix_other(int irq
, void *);
114 static irqreturn_t
igb_msix_ring(int irq
, void *);
115 #ifdef CONFIG_IGB_DCA
116 static void igb_update_dca(struct igb_q_vector
*);
117 static void igb_setup_dca(struct igb_adapter
*);
118 #endif /* CONFIG_IGB_DCA */
119 static bool igb_clean_tx_irq(struct igb_q_vector
*);
120 static int igb_poll(struct napi_struct
*, int);
121 static bool igb_clean_rx_irq_adv(struct igb_q_vector
*, int *, int);
122 static void igb_alloc_rx_buffers_adv(struct igb_ring
*, int);
123 static int igb_ioctl(struct net_device
*, struct ifreq
*, int cmd
);
124 static void igb_tx_timeout(struct net_device
*);
125 static void igb_reset_task(struct work_struct
*);
126 static void igb_vlan_rx_register(struct net_device
*, struct vlan_group
*);
127 static void igb_vlan_rx_add_vid(struct net_device
*, u16
);
128 static void igb_vlan_rx_kill_vid(struct net_device
*, u16
);
129 static void igb_restore_vlan(struct igb_adapter
*);
130 static void igb_rar_set_qsel(struct igb_adapter
*, u8
*, u32
, u8
);
131 static void igb_ping_all_vfs(struct igb_adapter
*);
132 static void igb_msg_task(struct igb_adapter
*);
133 static int igb_rcv_msg_from_vf(struct igb_adapter
*, u32
);
134 static void igb_vmm_control(struct igb_adapter
*);
135 static int igb_set_vf_mac(struct igb_adapter
*adapter
, int, unsigned char *);
136 static void igb_restore_vf_multicasts(struct igb_adapter
*adapter
);
138 static inline void igb_set_vmolr(struct e1000_hw
*hw
, int vfn
)
142 reg_data
= rd32(E1000_VMOLR(vfn
));
143 reg_data
|= E1000_VMOLR_BAM
| /* Accept broadcast */
144 E1000_VMOLR_ROMPE
| /* Accept packets matched in MTA */
145 E1000_VMOLR_AUPE
| /* Accept untagged packets */
146 E1000_VMOLR_STRVLAN
; /* Strip vlan tags */
147 wr32(E1000_VMOLR(vfn
), reg_data
);
150 static inline int igb_set_vf_rlpml(struct igb_adapter
*adapter
, int size
,
153 struct e1000_hw
*hw
= &adapter
->hw
;
156 /* if it isn't the PF check to see if VFs are enabled and
157 * increase the size to support vlan tags */
158 if (vfn
< adapter
->vfs_allocated_count
&&
159 adapter
->vf_data
[vfn
].vlans_enabled
)
160 size
+= VLAN_TAG_SIZE
;
162 vmolr
= rd32(E1000_VMOLR(vfn
));
163 vmolr
&= ~E1000_VMOLR_RLPML_MASK
;
164 vmolr
|= size
| E1000_VMOLR_LPE
;
165 wr32(E1000_VMOLR(vfn
), vmolr
);
171 static int igb_suspend(struct pci_dev
*, pm_message_t
);
172 static int igb_resume(struct pci_dev
*);
174 static void igb_shutdown(struct pci_dev
*);
175 #ifdef CONFIG_IGB_DCA
176 static int igb_notify_dca(struct notifier_block
*, unsigned long, void *);
177 static struct notifier_block dca_notifier
= {
178 .notifier_call
= igb_notify_dca
,
183 #ifdef CONFIG_NET_POLL_CONTROLLER
184 /* for netdump / net console */
185 static void igb_netpoll(struct net_device
*);
187 #ifdef CONFIG_PCI_IOV
188 static unsigned int max_vfs
= 0;
189 module_param(max_vfs
, uint
, 0);
190 MODULE_PARM_DESC(max_vfs
, "Maximum number of virtual functions to allocate "
191 "per physical function");
192 #endif /* CONFIG_PCI_IOV */
194 static pci_ers_result_t
igb_io_error_detected(struct pci_dev
*,
195 pci_channel_state_t
);
196 static pci_ers_result_t
igb_io_slot_reset(struct pci_dev
*);
197 static void igb_io_resume(struct pci_dev
*);
199 static struct pci_error_handlers igb_err_handler
= {
200 .error_detected
= igb_io_error_detected
,
201 .slot_reset
= igb_io_slot_reset
,
202 .resume
= igb_io_resume
,
206 static struct pci_driver igb_driver
= {
207 .name
= igb_driver_name
,
208 .id_table
= igb_pci_tbl
,
210 .remove
= __devexit_p(igb_remove
),
212 /* Power Managment Hooks */
213 .suspend
= igb_suspend
,
214 .resume
= igb_resume
,
216 .shutdown
= igb_shutdown
,
217 .err_handler
= &igb_err_handler
220 static int global_quad_port_a
; /* global quad port a indication */
222 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
223 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
224 MODULE_LICENSE("GPL");
225 MODULE_VERSION(DRV_VERSION
);
228 * Scale the NIC clock cycle by a large factor so that
229 * relatively small clock corrections can be added or
230 * substracted at each clock tick. The drawbacks of a
231 * large factor are a) that the clock register overflows
232 * more quickly (not such a big deal) and b) that the
233 * increment per tick has to fit into 24 bits.
236 * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
238 * TIMINCA += TIMINCA * adjustment [ppm] / 1e9
240 * The base scale factor is intentionally a power of two
241 * so that the division in %struct timecounter can be done with
244 #define IGB_TSYNC_SHIFT (19)
245 #define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
248 * The duration of one clock cycle of the NIC.
250 * @todo This hard-coded value is part of the specification and might change
251 * in future hardware revisions. Add revision check.
253 #define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
255 #if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
256 # error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
260 * igb_read_clock - read raw cycle counter (to be used by time counter)
262 static cycle_t
igb_read_clock(const struct cyclecounter
*tc
)
264 struct igb_adapter
*adapter
=
265 container_of(tc
, struct igb_adapter
, cycles
);
266 struct e1000_hw
*hw
= &adapter
->hw
;
269 stamp
= rd32(E1000_SYSTIML
);
270 stamp
|= (u64
)rd32(E1000_SYSTIMH
) << 32ULL;
277 * igb_get_hw_dev_name - return device name string
278 * used by hardware layer to print debugging information
280 char *igb_get_hw_dev_name(struct e1000_hw
*hw
)
282 struct igb_adapter
*adapter
= hw
->back
;
283 return adapter
->netdev
->name
;
287 * igb_get_time_str - format current NIC and system time as string
289 static char *igb_get_time_str(struct igb_adapter
*adapter
,
292 cycle_t hw
= adapter
->cycles
.read(&adapter
->cycles
);
293 struct timespec nic
= ns_to_timespec(timecounter_read(&adapter
->clock
));
295 struct timespec delta
;
296 getnstimeofday(&sys
);
298 delta
= timespec_sub(nic
, sys
);
301 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
303 (long)nic
.tv_sec
, nic
.tv_nsec
,
304 (long)sys
.tv_sec
, sys
.tv_nsec
,
305 (long)delta
.tv_sec
, delta
.tv_nsec
);
312 * igb_desc_unused - calculate if we have unused descriptors
314 static int igb_desc_unused(struct igb_ring
*ring
)
316 if (ring
->next_to_clean
> ring
->next_to_use
)
317 return ring
->next_to_clean
- ring
->next_to_use
- 1;
319 return ring
->count
+ ring
->next_to_clean
- ring
->next_to_use
- 1;
323 * igb_init_module - Driver Registration Routine
325 * igb_init_module is the first routine called when the driver is
326 * loaded. All it does is register with the PCI subsystem.
328 static int __init
igb_init_module(void)
331 printk(KERN_INFO
"%s - version %s\n",
332 igb_driver_string
, igb_driver_version
);
334 printk(KERN_INFO
"%s\n", igb_copyright
);
336 global_quad_port_a
= 0;
338 #ifdef CONFIG_IGB_DCA
339 dca_register_notify(&dca_notifier
);
342 ret
= pci_register_driver(&igb_driver
);
346 module_init(igb_init_module
);
349 * igb_exit_module - Driver Exit Cleanup Routine
351 * igb_exit_module is called just before the driver is removed
354 static void __exit
igb_exit_module(void)
356 #ifdef CONFIG_IGB_DCA
357 dca_unregister_notify(&dca_notifier
);
359 pci_unregister_driver(&igb_driver
);
362 module_exit(igb_exit_module
);
364 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
366 * igb_cache_ring_register - Descriptor ring to register mapping
367 * @adapter: board private structure to initialize
369 * Once we know the feature-set enabled for the device, we'll cache
370 * the register offset the descriptor ring is assigned to.
372 static void igb_cache_ring_register(struct igb_adapter
*adapter
)
375 u32 rbase_offset
= adapter
->vfs_allocated_count
;
377 switch (adapter
->hw
.mac
.type
) {
379 /* The queues are allocated for virtualization such that VF 0
380 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
381 * In order to avoid collision we start at the first free queue
382 * and continue consuming queues in the same sequence
384 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
385 adapter
->rx_ring
[i
].reg_idx
= rbase_offset
+
387 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
388 adapter
->tx_ring
[i
].reg_idx
= rbase_offset
+
393 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
394 adapter
->rx_ring
[i
].reg_idx
= i
;
395 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
396 adapter
->tx_ring
[i
].reg_idx
= i
;
401 static void igb_free_queues(struct igb_adapter
*adapter
)
403 kfree(adapter
->tx_ring
);
404 kfree(adapter
->rx_ring
);
406 adapter
->tx_ring
= NULL
;
407 adapter
->rx_ring
= NULL
;
409 adapter
->num_rx_queues
= 0;
410 adapter
->num_tx_queues
= 0;
414 * igb_alloc_queues - Allocate memory for all rings
415 * @adapter: board private structure to initialize
417 * We allocate one ring per queue at run-time since we don't know the
418 * number of queues at compile-time.
420 static int igb_alloc_queues(struct igb_adapter
*adapter
)
424 adapter
->tx_ring
= kcalloc(adapter
->num_tx_queues
,
425 sizeof(struct igb_ring
), GFP_KERNEL
);
426 if (!adapter
->tx_ring
)
429 adapter
->rx_ring
= kcalloc(adapter
->num_rx_queues
,
430 sizeof(struct igb_ring
), GFP_KERNEL
);
431 if (!adapter
->rx_ring
)
434 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
435 struct igb_ring
*ring
= &(adapter
->tx_ring
[i
]);
436 ring
->count
= adapter
->tx_ring_count
;
437 ring
->queue_index
= i
;
439 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
440 struct igb_ring
*ring
= &(adapter
->rx_ring
[i
]);
441 ring
->count
= adapter
->rx_ring_count
;
442 ring
->queue_index
= i
;
445 igb_cache_ring_register(adapter
);
450 igb_free_queues(adapter
);
455 #define IGB_N0_QUEUE -1
456 static void igb_assign_vector(struct igb_q_vector
*q_vector
, int msix_vector
)
459 struct igb_adapter
*adapter
= q_vector
->adapter
;
460 struct e1000_hw
*hw
= &adapter
->hw
;
462 int rx_queue
= IGB_N0_QUEUE
;
463 int tx_queue
= IGB_N0_QUEUE
;
465 if (q_vector
->rx_ring
)
466 rx_queue
= q_vector
->rx_ring
->reg_idx
;
467 if (q_vector
->tx_ring
)
468 tx_queue
= q_vector
->tx_ring
->reg_idx
;
470 switch (hw
->mac
.type
) {
472 /* The 82575 assigns vectors using a bitmask, which matches the
473 bitmask for the EICR/EIMS/EIMC registers. To assign one
474 or more queues to a vector, we write the appropriate bits
475 into the MSIXBM register for that vector. */
476 if (rx_queue
> IGB_N0_QUEUE
)
477 msixbm
= E1000_EICR_RX_QUEUE0
<< rx_queue
;
478 if (tx_queue
> IGB_N0_QUEUE
)
479 msixbm
|= E1000_EICR_TX_QUEUE0
<< tx_queue
;
480 array_wr32(E1000_MSIXBM(0), msix_vector
, msixbm
);
481 q_vector
->eims_value
= msixbm
;
484 /* 82576 uses a table-based method for assigning vectors.
485 Each queue has a single entry in the table to which we write
486 a vector number along with a "valid" bit. Sadly, the layout
487 of the table is somewhat counterintuitive. */
488 if (rx_queue
> IGB_N0_QUEUE
) {
489 index
= (rx_queue
& 0x7);
490 ivar
= array_rd32(E1000_IVAR0
, index
);
492 /* vector goes into low byte of register */
493 ivar
= ivar
& 0xFFFFFF00;
494 ivar
|= msix_vector
| E1000_IVAR_VALID
;
496 /* vector goes into third byte of register */
497 ivar
= ivar
& 0xFF00FFFF;
498 ivar
|= (msix_vector
| E1000_IVAR_VALID
) << 16;
500 array_wr32(E1000_IVAR0
, index
, ivar
);
502 if (tx_queue
> IGB_N0_QUEUE
) {
503 index
= (tx_queue
& 0x7);
504 ivar
= array_rd32(E1000_IVAR0
, index
);
506 /* vector goes into second byte of register */
507 ivar
= ivar
& 0xFFFF00FF;
508 ivar
|= (msix_vector
| E1000_IVAR_VALID
) << 8;
510 /* vector goes into high byte of register */
511 ivar
= ivar
& 0x00FFFFFF;
512 ivar
|= (msix_vector
| E1000_IVAR_VALID
) << 24;
514 array_wr32(E1000_IVAR0
, index
, ivar
);
516 q_vector
->eims_value
= 1 << msix_vector
;
525 * igb_configure_msix - Configure MSI-X hardware
527 * igb_configure_msix sets up the hardware to properly
528 * generate MSI-X interrupts.
530 static void igb_configure_msix(struct igb_adapter
*adapter
)
534 struct e1000_hw
*hw
= &adapter
->hw
;
536 adapter
->eims_enable_mask
= 0;
538 /* set vector for other causes, i.e. link changes */
539 switch (hw
->mac
.type
) {
541 tmp
= rd32(E1000_CTRL_EXT
);
542 /* enable MSI-X PBA support*/
543 tmp
|= E1000_CTRL_EXT_PBA_CLR
;
545 /* Auto-Mask interrupts upon ICR read. */
546 tmp
|= E1000_CTRL_EXT_EIAME
;
547 tmp
|= E1000_CTRL_EXT_IRCA
;
549 wr32(E1000_CTRL_EXT
, tmp
);
551 /* enable msix_other interrupt */
552 array_wr32(E1000_MSIXBM(0), vector
++,
554 adapter
->eims_other
= E1000_EIMS_OTHER
;
559 /* Turn on MSI-X capability first, or our settings
560 * won't stick. And it will take days to debug. */
561 wr32(E1000_GPIE
, E1000_GPIE_MSIX_MODE
|
562 E1000_GPIE_PBA
| E1000_GPIE_EIAME
|
565 /* enable msix_other interrupt */
566 adapter
->eims_other
= 1 << vector
;
567 tmp
= (vector
++ | E1000_IVAR_VALID
) << 8;
569 wr32(E1000_IVAR_MISC
, tmp
);
572 /* do nothing, since nothing else supports MSI-X */
574 } /* switch (hw->mac.type) */
576 adapter
->eims_enable_mask
|= adapter
->eims_other
;
578 for (i
= 0; i
< adapter
->num_q_vectors
; i
++) {
579 struct igb_q_vector
*q_vector
= adapter
->q_vector
[i
];
580 igb_assign_vector(q_vector
, vector
++);
581 adapter
->eims_enable_mask
|= q_vector
->eims_value
;
588 * igb_request_msix - Initialize MSI-X interrupts
590 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
593 static int igb_request_msix(struct igb_adapter
*adapter
)
595 struct net_device
*netdev
= adapter
->netdev
;
596 struct e1000_hw
*hw
= &adapter
->hw
;
597 int i
, err
= 0, vector
= 0;
599 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
600 &igb_msix_other
, 0, netdev
->name
, adapter
);
605 for (i
= 0; i
< adapter
->num_q_vectors
; i
++) {
606 struct igb_q_vector
*q_vector
= adapter
->q_vector
[i
];
608 q_vector
->itr_register
= hw
->hw_addr
+ E1000_EITR(vector
);
610 if (q_vector
->rx_ring
&& q_vector
->tx_ring
)
611 sprintf(q_vector
->name
, "%s-TxRx-%u", netdev
->name
,
612 q_vector
->rx_ring
->queue_index
);
613 else if (q_vector
->tx_ring
)
614 sprintf(q_vector
->name
, "%s-tx-%u", netdev
->name
,
615 q_vector
->tx_ring
->queue_index
);
616 else if (q_vector
->rx_ring
)
617 sprintf(q_vector
->name
, "%s-rx-%u", netdev
->name
,
618 q_vector
->rx_ring
->queue_index
);
620 sprintf(q_vector
->name
, "%s-unused", netdev
->name
);
622 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
623 &igb_msix_ring
, 0, q_vector
->name
,
630 igb_configure_msix(adapter
);
636 static void igb_reset_interrupt_capability(struct igb_adapter
*adapter
)
638 if (adapter
->msix_entries
) {
639 pci_disable_msix(adapter
->pdev
);
640 kfree(adapter
->msix_entries
);
641 adapter
->msix_entries
= NULL
;
642 } else if (adapter
->flags
& IGB_FLAG_HAS_MSI
) {
643 pci_disable_msi(adapter
->pdev
);
648 * igb_free_q_vectors - Free memory allocated for interrupt vectors
649 * @adapter: board private structure to initialize
651 * This function frees the memory allocated to the q_vectors. In addition if
652 * NAPI is enabled it will delete any references to the NAPI struct prior
653 * to freeing the q_vector.
655 static void igb_free_q_vectors(struct igb_adapter
*adapter
)
659 for (v_idx
= 0; v_idx
< adapter
->num_q_vectors
; v_idx
++) {
660 struct igb_q_vector
*q_vector
= adapter
->q_vector
[v_idx
];
661 adapter
->q_vector
[v_idx
] = NULL
;
662 netif_napi_del(&q_vector
->napi
);
665 adapter
->num_q_vectors
= 0;
669 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
671 * This function resets the device so that it has 0 rx queues, tx queues, and
672 * MSI-X interrupts allocated.
674 static void igb_clear_interrupt_scheme(struct igb_adapter
*adapter
)
676 igb_free_queues(adapter
);
677 igb_free_q_vectors(adapter
);
678 igb_reset_interrupt_capability(adapter
);
682 * igb_set_interrupt_capability - set MSI or MSI-X if supported
684 * Attempt to configure interrupts using the best available
685 * capabilities of the hardware and kernel.
687 static void igb_set_interrupt_capability(struct igb_adapter
*adapter
)
692 /* Number of supported queues. */
693 adapter
->num_rx_queues
= min_t(u32
, IGB_MAX_RX_QUEUES
, num_online_cpus());
694 adapter
->num_tx_queues
= min_t(u32
, IGB_MAX_TX_QUEUES
, num_online_cpus());
696 /* start with one vector for every rx queue */
697 numvecs
= adapter
->num_rx_queues
;
699 /* if tx handler is seperate add 1 for every tx queue */
700 numvecs
+= adapter
->num_tx_queues
;
702 /* store the number of vectors reserved for queues */
703 adapter
->num_q_vectors
= numvecs
;
705 /* add 1 vector for link status interrupts */
707 adapter
->msix_entries
= kcalloc(numvecs
, sizeof(struct msix_entry
),
709 if (!adapter
->msix_entries
)
712 for (i
= 0; i
< numvecs
; i
++)
713 adapter
->msix_entries
[i
].entry
= i
;
715 err
= pci_enable_msix(adapter
->pdev
,
716 adapter
->msix_entries
,
721 igb_reset_interrupt_capability(adapter
);
723 /* If we can't do MSI-X, try MSI */
725 #ifdef CONFIG_PCI_IOV
726 /* disable SR-IOV for non MSI-X configurations */
727 if (adapter
->vf_data
) {
728 struct e1000_hw
*hw
= &adapter
->hw
;
729 /* disable iov and allow time for transactions to clear */
730 pci_disable_sriov(adapter
->pdev
);
733 kfree(adapter
->vf_data
);
734 adapter
->vf_data
= NULL
;
735 wr32(E1000_IOVCTL
, E1000_IOVCTL_REUSE_VFQ
);
737 dev_info(&adapter
->pdev
->dev
, "IOV Disabled\n");
740 adapter
->num_rx_queues
= 1;
741 adapter
->num_tx_queues
= 1;
742 adapter
->num_q_vectors
= 1;
743 if (!pci_enable_msi(adapter
->pdev
))
744 adapter
->flags
|= IGB_FLAG_HAS_MSI
;
746 /* Notify the stack of the (possibly) reduced Tx Queue count. */
747 adapter
->netdev
->real_num_tx_queues
= adapter
->num_tx_queues
;
752 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
753 * @adapter: board private structure to initialize
755 * We allocate one q_vector per queue interrupt. If allocation fails we
758 static int igb_alloc_q_vectors(struct igb_adapter
*adapter
)
760 struct igb_q_vector
*q_vector
;
761 struct e1000_hw
*hw
= &adapter
->hw
;
764 for (v_idx
= 0; v_idx
< adapter
->num_q_vectors
; v_idx
++) {
765 q_vector
= kzalloc(sizeof(struct igb_q_vector
), GFP_KERNEL
);
768 q_vector
->adapter
= adapter
;
769 q_vector
->itr_shift
= (hw
->mac
.type
== e1000_82575
) ? 16 : 0;
770 q_vector
->itr_register
= hw
->hw_addr
+ E1000_EITR(0);
771 q_vector
->itr_val
= IGB_START_ITR
;
772 q_vector
->set_itr
= 1;
773 netif_napi_add(adapter
->netdev
, &q_vector
->napi
, igb_poll
, 64);
774 adapter
->q_vector
[v_idx
] = q_vector
;
781 q_vector
= adapter
->q_vector
[v_idx
];
782 netif_napi_del(&q_vector
->napi
);
784 adapter
->q_vector
[v_idx
] = NULL
;
789 static void igb_map_rx_ring_to_vector(struct igb_adapter
*adapter
,
790 int ring_idx
, int v_idx
)
792 struct igb_q_vector
*q_vector
;
794 q_vector
= adapter
->q_vector
[v_idx
];
795 q_vector
->rx_ring
= &adapter
->rx_ring
[ring_idx
];
796 q_vector
->rx_ring
->q_vector
= q_vector
;
797 q_vector
->itr_val
= adapter
->itr
;
800 static void igb_map_tx_ring_to_vector(struct igb_adapter
*adapter
,
801 int ring_idx
, int v_idx
)
803 struct igb_q_vector
*q_vector
;
805 q_vector
= adapter
->q_vector
[v_idx
];
806 q_vector
->tx_ring
= &adapter
->tx_ring
[ring_idx
];
807 q_vector
->tx_ring
->q_vector
= q_vector
;
808 q_vector
->itr_val
= adapter
->itr
;
812 * igb_map_ring_to_vector - maps allocated queues to vectors
814 * This function maps the recently allocated queues to vectors.
816 static int igb_map_ring_to_vector(struct igb_adapter
*adapter
)
821 if ((adapter
->num_q_vectors
< adapter
->num_rx_queues
) ||
822 (adapter
->num_q_vectors
< adapter
->num_tx_queues
))
825 if (adapter
->num_q_vectors
>=
826 (adapter
->num_rx_queues
+ adapter
->num_tx_queues
)) {
827 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
828 igb_map_rx_ring_to_vector(adapter
, i
, v_idx
++);
829 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
830 igb_map_tx_ring_to_vector(adapter
, i
, v_idx
++);
832 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
833 if (i
< adapter
->num_tx_queues
)
834 igb_map_tx_ring_to_vector(adapter
, i
, v_idx
);
835 igb_map_rx_ring_to_vector(adapter
, i
, v_idx
++);
837 for (; i
< adapter
->num_tx_queues
; i
++)
838 igb_map_tx_ring_to_vector(adapter
, i
, v_idx
++);
844 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
846 * This function initializes the interrupts and allocates all of the queues.
848 static int igb_init_interrupt_scheme(struct igb_adapter
*adapter
)
850 struct pci_dev
*pdev
= adapter
->pdev
;
853 igb_set_interrupt_capability(adapter
);
855 err
= igb_alloc_q_vectors(adapter
);
857 dev_err(&pdev
->dev
, "Unable to allocate memory for vectors\n");
858 goto err_alloc_q_vectors
;
861 err
= igb_alloc_queues(adapter
);
863 dev_err(&pdev
->dev
, "Unable to allocate memory for queues\n");
864 goto err_alloc_queues
;
867 err
= igb_map_ring_to_vector(adapter
);
869 dev_err(&pdev
->dev
, "Invalid q_vector to ring mapping\n");
876 igb_free_queues(adapter
);
878 igb_free_q_vectors(adapter
);
880 igb_reset_interrupt_capability(adapter
);
885 * igb_request_irq - initialize interrupts
887 * Attempts to configure interrupts using the best available
888 * capabilities of the hardware and kernel.
890 static int igb_request_irq(struct igb_adapter
*adapter
)
892 struct net_device
*netdev
= adapter
->netdev
;
893 struct pci_dev
*pdev
= adapter
->pdev
;
894 struct e1000_hw
*hw
= &adapter
->hw
;
897 if (adapter
->msix_entries
) {
898 err
= igb_request_msix(adapter
);
901 /* fall back to MSI */
902 igb_clear_interrupt_scheme(adapter
);
903 if (!pci_enable_msi(adapter
->pdev
))
904 adapter
->flags
|= IGB_FLAG_HAS_MSI
;
905 igb_free_all_tx_resources(adapter
);
906 igb_free_all_rx_resources(adapter
);
907 adapter
->num_tx_queues
= 1;
908 adapter
->num_rx_queues
= 1;
909 adapter
->num_q_vectors
= 1;
910 err
= igb_alloc_q_vectors(adapter
);
913 "Unable to allocate memory for vectors\n");
916 err
= igb_alloc_queues(adapter
);
919 "Unable to allocate memory for queues\n");
920 igb_free_q_vectors(adapter
);
923 igb_setup_all_tx_resources(adapter
);
924 igb_setup_all_rx_resources(adapter
);
926 switch (hw
->mac
.type
) {
928 wr32(E1000_MSIXBM(0),
929 (E1000_EICR_RX_QUEUE0
|
930 E1000_EICR_TX_QUEUE0
|
934 wr32(E1000_IVAR0
, E1000_IVAR_VALID
);
941 if (adapter
->flags
& IGB_FLAG_HAS_MSI
) {
942 err
= request_irq(adapter
->pdev
->irq
, &igb_intr_msi
, 0,
943 netdev
->name
, adapter
);
947 /* fall back to legacy interrupts */
948 igb_reset_interrupt_capability(adapter
);
949 adapter
->flags
&= ~IGB_FLAG_HAS_MSI
;
952 err
= request_irq(adapter
->pdev
->irq
, &igb_intr
, IRQF_SHARED
,
953 netdev
->name
, adapter
);
956 dev_err(&adapter
->pdev
->dev
, "Error %d getting interrupt\n",
963 static void igb_free_irq(struct igb_adapter
*adapter
)
965 if (adapter
->msix_entries
) {
968 free_irq(adapter
->msix_entries
[vector
++].vector
, adapter
);
970 for (i
= 0; i
< adapter
->num_q_vectors
; i
++) {
971 struct igb_q_vector
*q_vector
= adapter
->q_vector
[i
];
972 free_irq(adapter
->msix_entries
[vector
++].vector
,
976 free_irq(adapter
->pdev
->irq
, adapter
);
981 * igb_irq_disable - Mask off interrupt generation on the NIC
982 * @adapter: board private structure
984 static void igb_irq_disable(struct igb_adapter
*adapter
)
986 struct e1000_hw
*hw
= &adapter
->hw
;
988 if (adapter
->msix_entries
) {
989 u32 regval
= rd32(E1000_EIAM
);
990 wr32(E1000_EIAM
, regval
& ~adapter
->eims_enable_mask
);
991 wr32(E1000_EIMC
, adapter
->eims_enable_mask
);
992 regval
= rd32(E1000_EIAC
);
993 wr32(E1000_EIAC
, regval
& ~adapter
->eims_enable_mask
);
999 synchronize_irq(adapter
->pdev
->irq
);
1003 * igb_irq_enable - Enable default interrupt generation settings
1004 * @adapter: board private structure
1006 static void igb_irq_enable(struct igb_adapter
*adapter
)
1008 struct e1000_hw
*hw
= &adapter
->hw
;
1010 if (adapter
->msix_entries
) {
1011 u32 regval
= rd32(E1000_EIAC
);
1012 wr32(E1000_EIAC
, regval
| adapter
->eims_enable_mask
);
1013 regval
= rd32(E1000_EIAM
);
1014 wr32(E1000_EIAM
, regval
| adapter
->eims_enable_mask
);
1015 wr32(E1000_EIMS
, adapter
->eims_enable_mask
);
1016 if (adapter
->vfs_allocated_count
)
1017 wr32(E1000_MBVFIMR
, 0xFF);
1018 wr32(E1000_IMS
, (E1000_IMS_LSC
| E1000_IMS_VMMB
|
1019 E1000_IMS_DOUTSYNC
));
1021 wr32(E1000_IMS
, IMS_ENABLE_MASK
);
1022 wr32(E1000_IAM
, IMS_ENABLE_MASK
);
1026 static void igb_update_mng_vlan(struct igb_adapter
*adapter
)
1028 struct net_device
*netdev
= adapter
->netdev
;
1029 u16 vid
= adapter
->hw
.mng_cookie
.vlan_id
;
1030 u16 old_vid
= adapter
->mng_vlan_id
;
1031 if (adapter
->vlgrp
) {
1032 if (!vlan_group_get_device(adapter
->vlgrp
, vid
)) {
1033 if (adapter
->hw
.mng_cookie
.status
&
1034 E1000_MNG_DHCP_COOKIE_STATUS_VLAN
) {
1035 igb_vlan_rx_add_vid(netdev
, vid
);
1036 adapter
->mng_vlan_id
= vid
;
1038 adapter
->mng_vlan_id
= IGB_MNG_VLAN_NONE
;
1040 if ((old_vid
!= (u16
)IGB_MNG_VLAN_NONE
) &&
1042 !vlan_group_get_device(adapter
->vlgrp
, old_vid
))
1043 igb_vlan_rx_kill_vid(netdev
, old_vid
);
1045 adapter
->mng_vlan_id
= vid
;
1050 * igb_release_hw_control - release control of the h/w to f/w
1051 * @adapter: address of board private structure
1053 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1054 * For ASF and Pass Through versions of f/w this means that the
1055 * driver is no longer loaded.
1058 static void igb_release_hw_control(struct igb_adapter
*adapter
)
1060 struct e1000_hw
*hw
= &adapter
->hw
;
1063 /* Let firmware take over control of h/w */
1064 ctrl_ext
= rd32(E1000_CTRL_EXT
);
1065 wr32(E1000_CTRL_EXT
,
1066 ctrl_ext
& ~E1000_CTRL_EXT_DRV_LOAD
);
1071 * igb_get_hw_control - get control of the h/w from f/w
1072 * @adapter: address of board private structure
1074 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1075 * For ASF and Pass Through versions of f/w this means that
1076 * the driver is loaded.
1079 static void igb_get_hw_control(struct igb_adapter
*adapter
)
1081 struct e1000_hw
*hw
= &adapter
->hw
;
1084 /* Let firmware know the driver has taken over */
1085 ctrl_ext
= rd32(E1000_CTRL_EXT
);
1086 wr32(E1000_CTRL_EXT
,
1087 ctrl_ext
| E1000_CTRL_EXT_DRV_LOAD
);
1091 * igb_configure - configure the hardware for RX and TX
1092 * @adapter: private board structure
1094 static void igb_configure(struct igb_adapter
*adapter
)
1096 struct net_device
*netdev
= adapter
->netdev
;
1099 igb_get_hw_control(adapter
);
1100 igb_set_rx_mode(netdev
);
1102 igb_restore_vlan(adapter
);
1104 igb_configure_tx(adapter
);
1105 igb_setup_rctl(adapter
);
1106 igb_configure_rx(adapter
);
1108 igb_rx_fifo_flush_82575(&adapter
->hw
);
1110 /* call igb_desc_unused which always leaves
1111 * at least 1 descriptor unused to make sure
1112 * next_to_use != next_to_clean */
1113 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
1114 struct igb_ring
*ring
= &adapter
->rx_ring
[i
];
1115 igb_alloc_rx_buffers_adv(ring
, igb_desc_unused(ring
));
1119 adapter
->tx_queue_len
= netdev
->tx_queue_len
;
1124 * igb_up - Open the interface and prepare it to handle traffic
1125 * @adapter: board private structure
1128 int igb_up(struct igb_adapter
*adapter
)
1130 struct e1000_hw
*hw
= &adapter
->hw
;
1133 /* hardware has been reset, we need to reload some things */
1134 igb_configure(adapter
);
1136 clear_bit(__IGB_DOWN
, &adapter
->state
);
1138 for (i
= 0; i
< adapter
->num_q_vectors
; i
++) {
1139 struct igb_q_vector
*q_vector
= adapter
->q_vector
[i
];
1140 napi_enable(&q_vector
->napi
);
1142 if (adapter
->msix_entries
)
1143 igb_configure_msix(adapter
);
1145 igb_vmm_control(adapter
);
1146 igb_set_vmolr(hw
, adapter
->vfs_allocated_count
);
1148 /* Clear any pending interrupts. */
1150 igb_irq_enable(adapter
);
1152 netif_tx_start_all_queues(adapter
->netdev
);
1154 /* Fire a link change interrupt to start the watchdog. */
1155 wr32(E1000_ICS
, E1000_ICS_LSC
);
1159 void igb_down(struct igb_adapter
*adapter
)
1161 struct e1000_hw
*hw
= &adapter
->hw
;
1162 struct net_device
*netdev
= adapter
->netdev
;
1166 /* signal that we're down so the interrupt handler does not
1167 * reschedule our watchdog timer */
1168 set_bit(__IGB_DOWN
, &adapter
->state
);
1170 /* disable receives in the hardware */
1171 rctl
= rd32(E1000_RCTL
);
1172 wr32(E1000_RCTL
, rctl
& ~E1000_RCTL_EN
);
1173 /* flush and sleep below */
1175 netif_tx_stop_all_queues(netdev
);
1177 /* disable transmits in the hardware */
1178 tctl
= rd32(E1000_TCTL
);
1179 tctl
&= ~E1000_TCTL_EN
;
1180 wr32(E1000_TCTL
, tctl
);
1181 /* flush both disables and wait for them to finish */
1185 for (i
= 0; i
< adapter
->num_q_vectors
; i
++) {
1186 struct igb_q_vector
*q_vector
= adapter
->q_vector
[i
];
1187 napi_disable(&q_vector
->napi
);
1190 igb_irq_disable(adapter
);
1192 del_timer_sync(&adapter
->watchdog_timer
);
1193 del_timer_sync(&adapter
->phy_info_timer
);
1195 netdev
->tx_queue_len
= adapter
->tx_queue_len
;
1196 netif_carrier_off(netdev
);
1198 /* record the stats before reset*/
1199 igb_update_stats(adapter
);
1201 adapter
->link_speed
= 0;
1202 adapter
->link_duplex
= 0;
1204 if (!pci_channel_offline(adapter
->pdev
))
1206 igb_clean_all_tx_rings(adapter
);
1207 igb_clean_all_rx_rings(adapter
);
1208 #ifdef CONFIG_IGB_DCA
1210 /* since we reset the hardware DCA settings were cleared */
1211 igb_setup_dca(adapter
);
1215 void igb_reinit_locked(struct igb_adapter
*adapter
)
1217 WARN_ON(in_interrupt());
1218 while (test_and_set_bit(__IGB_RESETTING
, &adapter
->state
))
1222 clear_bit(__IGB_RESETTING
, &adapter
->state
);
1225 void igb_reset(struct igb_adapter
*adapter
)
1227 struct e1000_hw
*hw
= &adapter
->hw
;
1228 struct e1000_mac_info
*mac
= &hw
->mac
;
1229 struct e1000_fc_info
*fc
= &hw
->fc
;
1230 u32 pba
= 0, tx_space
, min_tx_space
, min_rx_space
;
1233 /* Repartition Pba for greater than 9k mtu
1234 * To take effect CTRL.RST is required.
1236 switch (mac
->type
) {
1238 pba
= E1000_PBA_64K
;
1242 pba
= E1000_PBA_34K
;
1246 if ((adapter
->max_frame_size
> ETH_FRAME_LEN
+ ETH_FCS_LEN
) &&
1247 (mac
->type
< e1000_82576
)) {
1248 /* adjust PBA for jumbo frames */
1249 wr32(E1000_PBA
, pba
);
1251 /* To maintain wire speed transmits, the Tx FIFO should be
1252 * large enough to accommodate two full transmit packets,
1253 * rounded up to the next 1KB and expressed in KB. Likewise,
1254 * the Rx FIFO should be large enough to accommodate at least
1255 * one full receive packet and is similarly rounded up and
1256 * expressed in KB. */
1257 pba
= rd32(E1000_PBA
);
1258 /* upper 16 bits has Tx packet buffer allocation size in KB */
1259 tx_space
= pba
>> 16;
1260 /* lower 16 bits has Rx packet buffer allocation size in KB */
1262 /* the tx fifo also stores 16 bytes of information about the tx
1263 * but don't include ethernet FCS because hardware appends it */
1264 min_tx_space
= (adapter
->max_frame_size
+
1265 sizeof(union e1000_adv_tx_desc
) -
1267 min_tx_space
= ALIGN(min_tx_space
, 1024);
1268 min_tx_space
>>= 10;
1269 /* software strips receive CRC, so leave room for it */
1270 min_rx_space
= adapter
->max_frame_size
;
1271 min_rx_space
= ALIGN(min_rx_space
, 1024);
1272 min_rx_space
>>= 10;
1274 /* If current Tx allocation is less than the min Tx FIFO size,
1275 * and the min Tx FIFO size is less than the current Rx FIFO
1276 * allocation, take space away from current Rx allocation */
1277 if (tx_space
< min_tx_space
&&
1278 ((min_tx_space
- tx_space
) < pba
)) {
1279 pba
= pba
- (min_tx_space
- tx_space
);
1281 /* if short on rx space, rx wins and must trump tx
1283 if (pba
< min_rx_space
)
1286 wr32(E1000_PBA
, pba
);
1289 /* flow control settings */
1290 /* The high water mark must be low enough to fit one full frame
1291 * (or the size used for early receive) above it in the Rx FIFO.
1292 * Set it to the lower of:
1293 * - 90% of the Rx FIFO size, or
1294 * - the full Rx FIFO size minus one full frame */
1295 hwm
= min(((pba
<< 10) * 9 / 10),
1296 ((pba
<< 10) - 2 * adapter
->max_frame_size
));
1298 if (mac
->type
< e1000_82576
) {
1299 fc
->high_water
= hwm
& 0xFFF8; /* 8-byte granularity */
1300 fc
->low_water
= fc
->high_water
- 8;
1302 fc
->high_water
= hwm
& 0xFFF0; /* 16-byte granularity */
1303 fc
->low_water
= fc
->high_water
- 16;
1305 fc
->pause_time
= 0xFFFF;
1307 fc
->current_mode
= fc
->requested_mode
;
1309 /* disable receive for all VFs and wait one second */
1310 if (adapter
->vfs_allocated_count
) {
1312 for (i
= 0 ; i
< adapter
->vfs_allocated_count
; i
++)
1313 adapter
->vf_data
[i
].clear_to_send
= false;
1315 /* ping all the active vfs to let them know we are going down */
1316 igb_ping_all_vfs(adapter
);
1318 /* disable transmits and receives */
1319 wr32(E1000_VFRE
, 0);
1320 wr32(E1000_VFTE
, 0);
1323 /* Allow time for pending master requests to run */
1324 adapter
->hw
.mac
.ops
.reset_hw(&adapter
->hw
);
1327 if (adapter
->hw
.mac
.ops
.init_hw(&adapter
->hw
))
1328 dev_err(&adapter
->pdev
->dev
, "Hardware Error\n");
1330 igb_update_mng_vlan(adapter
);
1332 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1333 wr32(E1000_VET
, ETHERNET_IEEE_VLAN_TYPE
);
1335 igb_reset_adaptive(&adapter
->hw
);
1336 igb_get_phy_info(&adapter
->hw
);
1339 static const struct net_device_ops igb_netdev_ops
= {
1340 .ndo_open
= igb_open
,
1341 .ndo_stop
= igb_close
,
1342 .ndo_start_xmit
= igb_xmit_frame_adv
,
1343 .ndo_get_stats
= igb_get_stats
,
1344 .ndo_set_rx_mode
= igb_set_rx_mode
,
1345 .ndo_set_multicast_list
= igb_set_rx_mode
,
1346 .ndo_set_mac_address
= igb_set_mac
,
1347 .ndo_change_mtu
= igb_change_mtu
,
1348 .ndo_do_ioctl
= igb_ioctl
,
1349 .ndo_tx_timeout
= igb_tx_timeout
,
1350 .ndo_validate_addr
= eth_validate_addr
,
1351 .ndo_vlan_rx_register
= igb_vlan_rx_register
,
1352 .ndo_vlan_rx_add_vid
= igb_vlan_rx_add_vid
,
1353 .ndo_vlan_rx_kill_vid
= igb_vlan_rx_kill_vid
,
1354 #ifdef CONFIG_NET_POLL_CONTROLLER
1355 .ndo_poll_controller
= igb_netpoll
,
1360 * igb_probe - Device Initialization Routine
1361 * @pdev: PCI device information struct
1362 * @ent: entry in igb_pci_tbl
1364 * Returns 0 on success, negative on failure
1366 * igb_probe initializes an adapter identified by a pci_dev structure.
1367 * The OS initialization, configuring of the adapter private structure,
1368 * and a hardware reset occur.
1370 static int __devinit
igb_probe(struct pci_dev
*pdev
,
1371 const struct pci_device_id
*ent
)
1373 struct net_device
*netdev
;
1374 struct igb_adapter
*adapter
;
1375 struct e1000_hw
*hw
;
1376 const struct e1000_info
*ei
= igb_info_tbl
[ent
->driver_data
];
1377 unsigned long mmio_start
, mmio_len
;
1378 int err
, pci_using_dac
;
1379 u16 eeprom_data
= 0;
1380 u16 eeprom_apme_mask
= IGB_EEPROM_APME
;
1383 err
= pci_enable_device_mem(pdev
);
1388 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64));
1390 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
1394 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
1396 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
1398 dev_err(&pdev
->dev
, "No usable DMA "
1399 "configuration, aborting\n");
1405 err
= pci_request_selected_regions(pdev
, pci_select_bars(pdev
,
1411 pci_enable_pcie_error_reporting(pdev
);
1413 pci_set_master(pdev
);
1414 pci_save_state(pdev
);
1417 netdev
= alloc_etherdev_mq(sizeof(struct igb_adapter
),
1418 IGB_ABS_MAX_TX_QUEUES
);
1420 goto err_alloc_etherdev
;
1422 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
1424 pci_set_drvdata(pdev
, netdev
);
1425 adapter
= netdev_priv(netdev
);
1426 adapter
->netdev
= netdev
;
1427 adapter
->pdev
= pdev
;
1430 adapter
->msg_enable
= NETIF_MSG_DRV
| NETIF_MSG_PROBE
;
1432 mmio_start
= pci_resource_start(pdev
, 0);
1433 mmio_len
= pci_resource_len(pdev
, 0);
1436 hw
->hw_addr
= ioremap(mmio_start
, mmio_len
);
1440 netdev
->netdev_ops
= &igb_netdev_ops
;
1441 igb_set_ethtool_ops(netdev
);
1442 netdev
->watchdog_timeo
= 5 * HZ
;
1444 strncpy(netdev
->name
, pci_name(pdev
), sizeof(netdev
->name
) - 1);
1446 netdev
->mem_start
= mmio_start
;
1447 netdev
->mem_end
= mmio_start
+ mmio_len
;
1449 /* PCI config space info */
1450 hw
->vendor_id
= pdev
->vendor
;
1451 hw
->device_id
= pdev
->device
;
1452 hw
->revision_id
= pdev
->revision
;
1453 hw
->subsystem_vendor_id
= pdev
->subsystem_vendor
;
1454 hw
->subsystem_device_id
= pdev
->subsystem_device
;
1456 /* setup the private structure */
1458 /* Copy the default MAC, PHY and NVM function pointers */
1459 memcpy(&hw
->mac
.ops
, ei
->mac_ops
, sizeof(hw
->mac
.ops
));
1460 memcpy(&hw
->phy
.ops
, ei
->phy_ops
, sizeof(hw
->phy
.ops
));
1461 memcpy(&hw
->nvm
.ops
, ei
->nvm_ops
, sizeof(hw
->nvm
.ops
));
1462 /* Initialize skew-specific constants */
1463 err
= ei
->get_invariants(hw
);
1467 #ifdef CONFIG_PCI_IOV
1468 /* since iov functionality isn't critical to base device function we
1469 * can accept failure. If it fails we don't allow iov to be enabled */
1470 if (hw
->mac
.type
== e1000_82576
) {
1471 /* 82576 supports a maximum of 7 VFs in addition to the PF */
1472 unsigned int num_vfs
= (max_vfs
> 7) ? 7 : max_vfs
;
1474 unsigned char mac_addr
[ETH_ALEN
];
1477 adapter
->vf_data
= kcalloc(num_vfs
,
1478 sizeof(struct vf_data_storage
),
1480 if (!adapter
->vf_data
) {
1482 "Could not allocate VF private data - "
1483 "IOV enable failed\n");
1485 err
= pci_enable_sriov(pdev
, num_vfs
);
1487 adapter
->vfs_allocated_count
= num_vfs
;
1488 dev_info(&pdev
->dev
,
1489 "%d vfs allocated\n",
1492 i
< adapter
->vfs_allocated_count
;
1494 random_ether_addr(mac_addr
);
1495 igb_set_vf_mac(adapter
, i
,
1499 kfree(adapter
->vf_data
);
1500 adapter
->vf_data
= NULL
;
1507 /* setup the private structure */
1508 err
= igb_sw_init(adapter
);
1512 igb_get_bus_info_pcie(hw
);
1515 switch (hw
->mac
.type
) {
1517 adapter
->flags
|= IGB_FLAG_NEED_CTX_IDX
;
1524 hw
->phy
.autoneg_wait_to_complete
= false;
1525 hw
->mac
.adaptive_ifs
= true;
1527 /* Copper options */
1528 if (hw
->phy
.media_type
== e1000_media_type_copper
) {
1529 hw
->phy
.mdix
= AUTO_ALL_MODES
;
1530 hw
->phy
.disable_polarity_correction
= false;
1531 hw
->phy
.ms_type
= e1000_ms_hw_default
;
1534 if (igb_check_reset_block(hw
))
1535 dev_info(&pdev
->dev
,
1536 "PHY reset is blocked due to SOL/IDER session.\n");
1538 netdev
->features
= NETIF_F_SG
|
1540 NETIF_F_HW_VLAN_TX
|
1541 NETIF_F_HW_VLAN_RX
|
1542 NETIF_F_HW_VLAN_FILTER
;
1544 netdev
->features
|= NETIF_F_IPV6_CSUM
;
1545 netdev
->features
|= NETIF_F_TSO
;
1546 netdev
->features
|= NETIF_F_TSO6
;
1548 netdev
->features
|= NETIF_F_GRO
;
1550 netdev
->vlan_features
|= NETIF_F_TSO
;
1551 netdev
->vlan_features
|= NETIF_F_TSO6
;
1552 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
1553 netdev
->vlan_features
|= NETIF_F_IPV6_CSUM
;
1554 netdev
->vlan_features
|= NETIF_F_SG
;
1557 netdev
->features
|= NETIF_F_HIGHDMA
;
1559 if (adapter
->hw
.mac
.type
== e1000_82576
)
1560 netdev
->features
|= NETIF_F_SCTP_CSUM
;
1562 adapter
->en_mng_pt
= igb_enable_mng_pass_thru(&adapter
->hw
);
1564 /* before reading the NVM, reset the controller to put the device in a
1565 * known good starting state */
1566 hw
->mac
.ops
.reset_hw(hw
);
1568 /* make sure the NVM is good */
1569 if (igb_validate_nvm_checksum(hw
) < 0) {
1570 dev_err(&pdev
->dev
, "The NVM Checksum Is Not Valid\n");
1575 /* copy the MAC address out of the NVM */
1576 if (hw
->mac
.ops
.read_mac_addr(hw
))
1577 dev_err(&pdev
->dev
, "NVM Read Error\n");
1579 memcpy(netdev
->dev_addr
, hw
->mac
.addr
, netdev
->addr_len
);
1580 memcpy(netdev
->perm_addr
, hw
->mac
.addr
, netdev
->addr_len
);
1582 if (!is_valid_ether_addr(netdev
->perm_addr
)) {
1583 dev_err(&pdev
->dev
, "Invalid MAC Address\n");
1588 setup_timer(&adapter
->watchdog_timer
, &igb_watchdog
,
1589 (unsigned long) adapter
);
1590 setup_timer(&adapter
->phy_info_timer
, &igb_update_phy_info
,
1591 (unsigned long) adapter
);
1593 INIT_WORK(&adapter
->reset_task
, igb_reset_task
);
1594 INIT_WORK(&adapter
->watchdog_task
, igb_watchdog_task
);
1596 /* Initialize link properties that are user-changeable */
1597 adapter
->fc_autoneg
= true;
1598 hw
->mac
.autoneg
= true;
1599 hw
->phy
.autoneg_advertised
= 0x2f;
1601 hw
->fc
.requested_mode
= e1000_fc_default
;
1602 hw
->fc
.current_mode
= e1000_fc_default
;
1604 adapter
->itr_setting
= IGB_DEFAULT_ITR
;
1605 adapter
->itr
= IGB_START_ITR
;
1607 igb_validate_mdi_setting(hw
);
1609 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1610 * enable the ACPI Magic Packet filter
1613 if (hw
->bus
.func
== 0)
1614 hw
->nvm
.ops
.read(hw
, NVM_INIT_CONTROL3_PORT_A
, 1, &eeprom_data
);
1615 else if (hw
->bus
.func
== 1)
1616 hw
->nvm
.ops
.read(hw
, NVM_INIT_CONTROL3_PORT_B
, 1, &eeprom_data
);
1618 if (eeprom_data
& eeprom_apme_mask
)
1619 adapter
->eeprom_wol
|= E1000_WUFC_MAG
;
1621 /* now that we have the eeprom settings, apply the special cases where
1622 * the eeprom may be wrong or the board simply won't support wake on
1623 * lan on a particular port */
1624 switch (pdev
->device
) {
1625 case E1000_DEV_ID_82575GB_QUAD_COPPER
:
1626 adapter
->eeprom_wol
= 0;
1628 case E1000_DEV_ID_82575EB_FIBER_SERDES
:
1629 case E1000_DEV_ID_82576_FIBER
:
1630 case E1000_DEV_ID_82576_SERDES
:
1631 /* Wake events only supported on port A for dual fiber
1632 * regardless of eeprom setting */
1633 if (rd32(E1000_STATUS
) & E1000_STATUS_FUNC_1
)
1634 adapter
->eeprom_wol
= 0;
1636 case E1000_DEV_ID_82576_QUAD_COPPER
:
1637 /* if quad port adapter, disable WoL on all but port A */
1638 if (global_quad_port_a
!= 0)
1639 adapter
->eeprom_wol
= 0;
1641 adapter
->flags
|= IGB_FLAG_QUAD_PORT_A
;
1642 /* Reset for multiple quad port adapters */
1643 if (++global_quad_port_a
== 4)
1644 global_quad_port_a
= 0;
1648 /* initialize the wol settings based on the eeprom settings */
1649 adapter
->wol
= adapter
->eeprom_wol
;
1650 device_set_wakeup_enable(&adapter
->pdev
->dev
, adapter
->wol
);
1652 /* reset the hardware with the new settings */
1655 /* let the f/w know that the h/w is now under the control of the
1657 igb_get_hw_control(adapter
);
1659 strcpy(netdev
->name
, "eth%d");
1660 err
= register_netdev(netdev
);
1664 /* carrier off reporting is important to ethtool even BEFORE open */
1665 netif_carrier_off(netdev
);
1667 #ifdef CONFIG_IGB_DCA
1668 if (dca_add_requester(&pdev
->dev
) == 0) {
1669 adapter
->flags
|= IGB_FLAG_DCA_ENABLED
;
1670 dev_info(&pdev
->dev
, "DCA enabled\n");
1671 igb_setup_dca(adapter
);
1676 * Initialize hardware timer: we keep it running just in case
1677 * that some program needs it later on.
1679 memset(&adapter
->cycles
, 0, sizeof(adapter
->cycles
));
1680 adapter
->cycles
.read
= igb_read_clock
;
1681 adapter
->cycles
.mask
= CLOCKSOURCE_MASK(64);
1682 adapter
->cycles
.mult
= 1;
1683 adapter
->cycles
.shift
= IGB_TSYNC_SHIFT
;
1686 IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS
* IGB_TSYNC_SCALE
);
1689 * Avoid rollover while we initialize by resetting the time counter.
1691 wr32(E1000_SYSTIML
, 0x00000000);
1692 wr32(E1000_SYSTIMH
, 0x00000000);
1695 * Set registers so that rollover occurs soon to test this.
1697 wr32(E1000_SYSTIML
, 0x00000000);
1698 wr32(E1000_SYSTIMH
, 0xFF800000);
1701 timecounter_init(&adapter
->clock
,
1703 ktime_to_ns(ktime_get_real()));
1706 * Synchronize our NIC clock against system wall clock. NIC
1707 * time stamp reading requires ~3us per sample, each sample
1708 * was pretty stable even under load => only require 10
1709 * samples for each offset comparison.
1711 memset(&adapter
->compare
, 0, sizeof(adapter
->compare
));
1712 adapter
->compare
.source
= &adapter
->clock
;
1713 adapter
->compare
.target
= ktime_get_real
;
1714 adapter
->compare
.num_samples
= 10;
1715 timecompare_update(&adapter
->compare
, 0);
1721 "igb: %s: hw %p initialized timer\n",
1722 igb_get_time_str(adapter
, buffer
),
1727 dev_info(&pdev
->dev
, "Intel(R) Gigabit Ethernet Network Connection\n");
1728 /* print bus type/speed/width info */
1729 dev_info(&pdev
->dev
, "%s: (PCIe:%s:%s) %pM\n",
1731 ((hw
->bus
.speed
== e1000_bus_speed_2500
)
1732 ? "2.5Gb/s" : "unknown"),
1733 ((hw
->bus
.width
== e1000_bus_width_pcie_x4
) ? "Width x4" :
1734 (hw
->bus
.width
== e1000_bus_width_pcie_x2
) ? "Width x2" :
1735 (hw
->bus
.width
== e1000_bus_width_pcie_x1
) ? "Width x1" :
1739 igb_read_part_num(hw
, &part_num
);
1740 dev_info(&pdev
->dev
, "%s: PBA No: %06x-%03x\n", netdev
->name
,
1741 (part_num
>> 8), (part_num
& 0xff));
1743 dev_info(&pdev
->dev
,
1744 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1745 adapter
->msix_entries
? "MSI-X" :
1746 (adapter
->flags
& IGB_FLAG_HAS_MSI
) ? "MSI" : "legacy",
1747 adapter
->num_rx_queues
, adapter
->num_tx_queues
);
1752 igb_release_hw_control(adapter
);
1754 if (!igb_check_reset_block(hw
))
1757 if (hw
->flash_address
)
1758 iounmap(hw
->flash_address
);
1760 igb_clear_interrupt_scheme(adapter
);
1761 iounmap(hw
->hw_addr
);
1763 free_netdev(netdev
);
1765 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
1769 pci_disable_device(pdev
);
1774 * igb_remove - Device Removal Routine
1775 * @pdev: PCI device information struct
1777 * igb_remove is called by the PCI subsystem to alert the driver
1778 * that it should release a PCI device. The could be caused by a
1779 * Hot-Plug event, or because the driver is going to be removed from
1782 static void __devexit
igb_remove(struct pci_dev
*pdev
)
1784 struct net_device
*netdev
= pci_get_drvdata(pdev
);
1785 struct igb_adapter
*adapter
= netdev_priv(netdev
);
1786 struct e1000_hw
*hw
= &adapter
->hw
;
1788 /* flush_scheduled work may reschedule our watchdog task, so
1789 * explicitly disable watchdog tasks from being rescheduled */
1790 set_bit(__IGB_DOWN
, &adapter
->state
);
1791 del_timer_sync(&adapter
->watchdog_timer
);
1792 del_timer_sync(&adapter
->phy_info_timer
);
1794 flush_scheduled_work();
1796 #ifdef CONFIG_IGB_DCA
1797 if (adapter
->flags
& IGB_FLAG_DCA_ENABLED
) {
1798 dev_info(&pdev
->dev
, "DCA disabled\n");
1799 dca_remove_requester(&pdev
->dev
);
1800 adapter
->flags
&= ~IGB_FLAG_DCA_ENABLED
;
1801 wr32(E1000_DCA_CTRL
, E1000_DCA_CTRL_DCA_MODE_DISABLE
);
1805 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1806 * would have already happened in close and is redundant. */
1807 igb_release_hw_control(adapter
);
1809 unregister_netdev(netdev
);
1811 if (!igb_check_reset_block(&adapter
->hw
))
1812 igb_reset_phy(&adapter
->hw
);
1814 igb_clear_interrupt_scheme(adapter
);
1816 #ifdef CONFIG_PCI_IOV
1817 /* reclaim resources allocated to VFs */
1818 if (adapter
->vf_data
) {
1819 /* disable iov and allow time for transactions to clear */
1820 pci_disable_sriov(pdev
);
1823 kfree(adapter
->vf_data
);
1824 adapter
->vf_data
= NULL
;
1825 wr32(E1000_IOVCTL
, E1000_IOVCTL_REUSE_VFQ
);
1827 dev_info(&pdev
->dev
, "IOV Disabled\n");
1830 iounmap(hw
->hw_addr
);
1831 if (hw
->flash_address
)
1832 iounmap(hw
->flash_address
);
1833 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
1836 free_netdev(netdev
);
1838 pci_disable_pcie_error_reporting(pdev
);
1840 pci_disable_device(pdev
);
1844 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1845 * @adapter: board private structure to initialize
1847 * igb_sw_init initializes the Adapter private data structure.
1848 * Fields are initialized based on PCI device information and
1849 * OS network device settings (MTU size).
1851 static int __devinit
igb_sw_init(struct igb_adapter
*adapter
)
1853 struct e1000_hw
*hw
= &adapter
->hw
;
1854 struct net_device
*netdev
= adapter
->netdev
;
1855 struct pci_dev
*pdev
= adapter
->pdev
;
1857 pci_read_config_word(pdev
, PCI_COMMAND
, &hw
->bus
.pci_cmd_word
);
1859 adapter
->tx_ring_count
= IGB_DEFAULT_TXD
;
1860 adapter
->rx_ring_count
= IGB_DEFAULT_RXD
;
1861 adapter
->rx_buffer_len
= MAXIMUM_ETHERNET_VLAN_SIZE
;
1862 adapter
->rx_ps_hdr_size
= 0; /* disable packet split */
1863 adapter
->max_frame_size
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
1864 adapter
->min_frame_size
= ETH_ZLEN
+ ETH_FCS_LEN
;
1866 /* This call may decrease the number of queues depending on
1867 * interrupt mode. */
1868 if (igb_init_interrupt_scheme(adapter
)) {
1869 dev_err(&pdev
->dev
, "Unable to allocate memory for queues\n");
1873 /* Explicitly disable IRQ since the NIC can be in any state. */
1874 igb_irq_disable(adapter
);
1876 set_bit(__IGB_DOWN
, &adapter
->state
);
1881 * igb_open - Called when a network interface is made active
1882 * @netdev: network interface device structure
1884 * Returns 0 on success, negative value on failure
1886 * The open entry point is called when a network interface is made
1887 * active by the system (IFF_UP). At this point all resources needed
1888 * for transmit and receive operations are allocated, the interrupt
1889 * handler is registered with the OS, the watchdog timer is started,
1890 * and the stack is notified that the interface is ready.
1892 static int igb_open(struct net_device
*netdev
)
1894 struct igb_adapter
*adapter
= netdev_priv(netdev
);
1895 struct e1000_hw
*hw
= &adapter
->hw
;
1899 /* disallow open during test */
1900 if (test_bit(__IGB_TESTING
, &adapter
->state
))
1903 netif_carrier_off(netdev
);
1905 /* allocate transmit descriptors */
1906 err
= igb_setup_all_tx_resources(adapter
);
1910 /* allocate receive descriptors */
1911 err
= igb_setup_all_rx_resources(adapter
);
1915 /* e1000_power_up_phy(adapter); */
1917 adapter
->mng_vlan_id
= IGB_MNG_VLAN_NONE
;
1918 if ((adapter
->hw
.mng_cookie
.status
&
1919 E1000_MNG_DHCP_COOKIE_STATUS_VLAN
))
1920 igb_update_mng_vlan(adapter
);
1922 /* before we allocate an interrupt, we must be ready to handle it.
1923 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1924 * as soon as we call pci_request_irq, so we have to setup our
1925 * clean_rx handler before we do so. */
1926 igb_configure(adapter
);
1928 igb_vmm_control(adapter
);
1929 igb_set_vmolr(hw
, adapter
->vfs_allocated_count
);
1931 err
= igb_request_irq(adapter
);
1935 /* From here on the code is the same as igb_up() */
1936 clear_bit(__IGB_DOWN
, &adapter
->state
);
1938 for (i
= 0; i
< adapter
->num_q_vectors
; i
++) {
1939 struct igb_q_vector
*q_vector
= adapter
->q_vector
[i
];
1940 napi_enable(&q_vector
->napi
);
1943 /* Clear any pending interrupts. */
1946 igb_irq_enable(adapter
);
1948 netif_tx_start_all_queues(netdev
);
1950 /* Fire a link status change interrupt to start the watchdog. */
1951 wr32(E1000_ICS
, E1000_ICS_LSC
);
1956 igb_release_hw_control(adapter
);
1957 /* e1000_power_down_phy(adapter); */
1958 igb_free_all_rx_resources(adapter
);
1960 igb_free_all_tx_resources(adapter
);
1968 * igb_close - Disables a network interface
1969 * @netdev: network interface device structure
1971 * Returns 0, this is not allowed to fail
1973 * The close entry point is called when an interface is de-activated
1974 * by the OS. The hardware is still under the driver's control, but
1975 * needs to be disabled. A global MAC reset is issued to stop the
1976 * hardware, and all transmit and receive resources are freed.
1978 static int igb_close(struct net_device
*netdev
)
1980 struct igb_adapter
*adapter
= netdev_priv(netdev
);
1982 WARN_ON(test_bit(__IGB_RESETTING
, &adapter
->state
));
1985 igb_free_irq(adapter
);
1987 igb_free_all_tx_resources(adapter
);
1988 igb_free_all_rx_resources(adapter
);
1990 /* kill manageability vlan ID if supported, but not if a vlan with
1991 * the same ID is registered on the host OS (let 8021q kill it) */
1992 if ((adapter
->hw
.mng_cookie
.status
&
1993 E1000_MNG_DHCP_COOKIE_STATUS_VLAN
) &&
1995 vlan_group_get_device(adapter
->vlgrp
, adapter
->mng_vlan_id
)))
1996 igb_vlan_rx_kill_vid(netdev
, adapter
->mng_vlan_id
);
2002 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
2003 * @adapter: board private structure
2004 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2006 * Return 0 on success, negative on failure
2008 int igb_setup_tx_resources(struct igb_adapter
*adapter
,
2009 struct igb_ring
*tx_ring
)
2011 struct pci_dev
*pdev
= adapter
->pdev
;
2014 size
= sizeof(struct igb_buffer
) * tx_ring
->count
;
2015 tx_ring
->buffer_info
= vmalloc(size
);
2016 if (!tx_ring
->buffer_info
)
2018 memset(tx_ring
->buffer_info
, 0, size
);
2020 /* round up to nearest 4K */
2021 tx_ring
->size
= tx_ring
->count
* sizeof(union e1000_adv_tx_desc
);
2022 tx_ring
->size
= ALIGN(tx_ring
->size
, 4096);
2024 tx_ring
->desc
= pci_alloc_consistent(pdev
, tx_ring
->size
,
2030 tx_ring
->next_to_use
= 0;
2031 tx_ring
->next_to_clean
= 0;
2035 vfree(tx_ring
->buffer_info
);
2037 "Unable to allocate memory for the transmit descriptor ring\n");
2042 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2043 * (Descriptors) for all queues
2044 * @adapter: board private structure
2046 * Return 0 on success, negative on failure
2048 static int igb_setup_all_tx_resources(struct igb_adapter
*adapter
)
2053 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2054 err
= igb_setup_tx_resources(adapter
, &adapter
->tx_ring
[i
]);
2056 dev_err(&adapter
->pdev
->dev
,
2057 "Allocation for Tx Queue %u failed\n", i
);
2058 for (i
--; i
>= 0; i
--)
2059 igb_free_tx_resources(&adapter
->tx_ring
[i
]);
2064 for (i
= 0; i
< IGB_MAX_TX_QUEUES
; i
++) {
2065 r_idx
= i
% adapter
->num_tx_queues
;
2066 adapter
->multi_tx_table
[i
] = &adapter
->tx_ring
[r_idx
];
2072 * igb_configure_tx - Configure transmit Unit after Reset
2073 * @adapter: board private structure
2075 * Configure the Tx unit of the MAC after a reset.
2077 static void igb_configure_tx(struct igb_adapter
*adapter
)
2080 struct e1000_hw
*hw
= &adapter
->hw
;
2085 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2086 struct igb_ring
*ring
= &adapter
->tx_ring
[i
];
2088 wr32(E1000_TDLEN(j
),
2089 ring
->count
* sizeof(union e1000_adv_tx_desc
));
2091 wr32(E1000_TDBAL(j
),
2092 tdba
& 0x00000000ffffffffULL
);
2093 wr32(E1000_TDBAH(j
), tdba
>> 32);
2095 ring
->head
= E1000_TDH(j
);
2096 ring
->tail
= E1000_TDT(j
);
2097 writel(0, hw
->hw_addr
+ ring
->tail
);
2098 writel(0, hw
->hw_addr
+ ring
->head
);
2099 txdctl
= rd32(E1000_TXDCTL(j
));
2100 txdctl
|= E1000_TXDCTL_QUEUE_ENABLE
;
2101 wr32(E1000_TXDCTL(j
), txdctl
);
2103 /* Turn off Relaxed Ordering on head write-backs. The
2104 * writebacks MUST be delivered in order or it will
2105 * completely screw up our bookeeping.
2107 txctrl
= rd32(E1000_DCA_TXCTRL(j
));
2108 txctrl
&= ~E1000_DCA_TXCTRL_TX_WB_RO_EN
;
2109 wr32(E1000_DCA_TXCTRL(j
), txctrl
);
2112 /* disable queue 0 to prevent tail bump w/o re-configuration */
2113 if (adapter
->vfs_allocated_count
)
2114 wr32(E1000_TXDCTL(0), 0);
2116 /* Program the Transmit Control Register */
2117 tctl
= rd32(E1000_TCTL
);
2118 tctl
&= ~E1000_TCTL_CT
;
2119 tctl
|= E1000_TCTL_PSP
| E1000_TCTL_RTLC
|
2120 (E1000_COLLISION_THRESHOLD
<< E1000_CT_SHIFT
);
2122 igb_config_collision_dist(hw
);
2124 /* Setup Transmit Descriptor Settings for eop descriptor */
2125 adapter
->txd_cmd
= E1000_TXD_CMD_EOP
| E1000_TXD_CMD_RS
;
2127 /* Enable transmits */
2128 tctl
|= E1000_TCTL_EN
;
2130 wr32(E1000_TCTL
, tctl
);
2134 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
2135 * @adapter: board private structure
2136 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2138 * Returns 0 on success, negative on failure
2140 int igb_setup_rx_resources(struct igb_adapter
*adapter
,
2141 struct igb_ring
*rx_ring
)
2143 struct pci_dev
*pdev
= adapter
->pdev
;
2146 size
= sizeof(struct igb_buffer
) * rx_ring
->count
;
2147 rx_ring
->buffer_info
= vmalloc(size
);
2148 if (!rx_ring
->buffer_info
)
2150 memset(rx_ring
->buffer_info
, 0, size
);
2152 desc_len
= sizeof(union e1000_adv_rx_desc
);
2154 /* Round up to nearest 4K */
2155 rx_ring
->size
= rx_ring
->count
* desc_len
;
2156 rx_ring
->size
= ALIGN(rx_ring
->size
, 4096);
2158 rx_ring
->desc
= pci_alloc_consistent(pdev
, rx_ring
->size
,
2164 rx_ring
->next_to_clean
= 0;
2165 rx_ring
->next_to_use
= 0;
2170 vfree(rx_ring
->buffer_info
);
2171 dev_err(&adapter
->pdev
->dev
, "Unable to allocate memory for "
2172 "the receive descriptor ring\n");
2177 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2178 * (Descriptors) for all queues
2179 * @adapter: board private structure
2181 * Return 0 on success, negative on failure
2183 static int igb_setup_all_rx_resources(struct igb_adapter
*adapter
)
2187 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2188 err
= igb_setup_rx_resources(adapter
, &adapter
->rx_ring
[i
]);
2190 dev_err(&adapter
->pdev
->dev
,
2191 "Allocation for Rx Queue %u failed\n", i
);
2192 for (i
--; i
>= 0; i
--)
2193 igb_free_rx_resources(&adapter
->rx_ring
[i
]);
2202 * igb_setup_rctl - configure the receive control registers
2203 * @adapter: Board private structure
2205 static void igb_setup_rctl(struct igb_adapter
*adapter
)
2207 struct e1000_hw
*hw
= &adapter
->hw
;
2212 rctl
= rd32(E1000_RCTL
);
2214 rctl
&= ~(3 << E1000_RCTL_MO_SHIFT
);
2215 rctl
&= ~(E1000_RCTL_LBM_TCVR
| E1000_RCTL_LBM_MAC
);
2217 rctl
|= E1000_RCTL_EN
| E1000_RCTL_BAM
| E1000_RCTL_RDMTS_HALF
|
2218 (hw
->mac
.mc_filter_type
<< E1000_RCTL_MO_SHIFT
);
2221 * enable stripping of CRC. It's unlikely this will break BMC
2222 * redirection as it did with e1000. Newer features require
2223 * that the HW strips the CRC.
2225 rctl
|= E1000_RCTL_SECRC
;
2228 * disable store bad packets and clear size bits.
2230 rctl
&= ~(E1000_RCTL_SBP
| E1000_RCTL_SZ_256
);
2232 /* enable LPE when to prevent packets larger than max_frame_size */
2233 rctl
|= E1000_RCTL_LPE
;
2235 /* Setup buffer sizes */
2236 switch (adapter
->rx_buffer_len
) {
2237 case IGB_RXBUFFER_256
:
2238 rctl
|= E1000_RCTL_SZ_256
;
2240 case IGB_RXBUFFER_512
:
2241 rctl
|= E1000_RCTL_SZ_512
;
2244 srrctl
= ALIGN(adapter
->rx_buffer_len
, 1024)
2245 >> E1000_SRRCTL_BSIZEPKT_SHIFT
;
2249 /* 82575 and greater support packet-split where the protocol
2250 * header is placed in skb->data and the packet data is
2251 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2252 * In the case of a non-split, skb->data is linearly filled,
2253 * followed by the page buffers. Therefore, skb->data is
2254 * sized to hold the largest protocol header.
2256 /* allocations using alloc_page take too long for regular MTU
2257 * so only enable packet split for jumbo frames */
2258 if (adapter
->netdev
->mtu
> ETH_DATA_LEN
) {
2259 adapter
->rx_ps_hdr_size
= IGB_RXBUFFER_128
;
2260 srrctl
|= adapter
->rx_ps_hdr_size
<<
2261 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT
;
2262 srrctl
|= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS
;
2264 adapter
->rx_ps_hdr_size
= 0;
2265 srrctl
|= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF
;
2268 /* Attention!!! For SR-IOV PF driver operations you must enable
2269 * queue drop for all VF and PF queues to prevent head of line blocking
2270 * if an un-trusted VF does not provide descriptors to hardware.
2272 if (adapter
->vfs_allocated_count
) {
2275 /* set all queue drop enable bits */
2276 wr32(E1000_QDE
, ALL_QUEUES
);
2277 srrctl
|= E1000_SRRCTL_DROP_EN
;
2279 /* disable queue 0 to prevent tail write w/o re-config */
2280 wr32(E1000_RXDCTL(0), 0);
2282 vmolr
= rd32(E1000_VMOLR(adapter
->vfs_allocated_count
));
2283 if (rctl
& E1000_RCTL_LPE
)
2284 vmolr
|= E1000_VMOLR_LPE
;
2285 if (adapter
->num_rx_queues
> 1)
2286 vmolr
|= E1000_VMOLR_RSSE
;
2287 wr32(E1000_VMOLR(adapter
->vfs_allocated_count
), vmolr
);
2290 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2291 int j
= adapter
->rx_ring
[i
].reg_idx
;
2292 wr32(E1000_SRRCTL(j
), srrctl
);
2295 wr32(E1000_RCTL
, rctl
);
2299 * igb_rlpml_set - set maximum receive packet size
2300 * @adapter: board private structure
2302 * Configure maximum receivable packet size.
2304 static void igb_rlpml_set(struct igb_adapter
*adapter
)
2306 u32 max_frame_size
= adapter
->max_frame_size
;
2307 struct e1000_hw
*hw
= &adapter
->hw
;
2308 u16 pf_id
= adapter
->vfs_allocated_count
;
2311 max_frame_size
+= VLAN_TAG_SIZE
;
2313 /* if vfs are enabled we set RLPML to the largest possible request
2314 * size and set the VMOLR RLPML to the size we need */
2316 igb_set_vf_rlpml(adapter
, max_frame_size
, pf_id
);
2317 max_frame_size
= MAX_STD_JUMBO_FRAME_SIZE
+ VLAN_TAG_SIZE
;
2320 wr32(E1000_RLPML
, max_frame_size
);
2324 * igb_configure_vt_default_pool - Configure VT default pool
2325 * @adapter: board private structure
2327 * Configure the default pool
2329 static void igb_configure_vt_default_pool(struct igb_adapter
*adapter
)
2331 struct e1000_hw
*hw
= &adapter
->hw
;
2332 u16 pf_id
= adapter
->vfs_allocated_count
;
2335 /* not in sr-iov mode - do nothing */
2339 vtctl
= rd32(E1000_VT_CTL
);
2340 vtctl
&= ~(E1000_VT_CTL_DEFAULT_POOL_MASK
|
2341 E1000_VT_CTL_DISABLE_DEF_POOL
);
2342 vtctl
|= pf_id
<< E1000_VT_CTL_DEFAULT_POOL_SHIFT
;
2343 wr32(E1000_VT_CTL
, vtctl
);
2347 * igb_configure_rx - Configure receive Unit after Reset
2348 * @adapter: board private structure
2350 * Configure the Rx unit of the MAC after a reset.
2352 static void igb_configure_rx(struct igb_adapter
*adapter
)
2355 struct e1000_hw
*hw
= &adapter
->hw
;
2360 /* disable receives while setting up the descriptors */
2361 rctl
= rd32(E1000_RCTL
);
2362 wr32(E1000_RCTL
, rctl
& ~E1000_RCTL_EN
);
2366 if (adapter
->itr_setting
> 3)
2367 wr32(E1000_ITR
, adapter
->itr
);
2369 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2370 * the Base and Length of the Rx Descriptor Ring */
2371 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2372 struct igb_ring
*ring
= &adapter
->rx_ring
[i
];
2373 int j
= ring
->reg_idx
;
2375 wr32(E1000_RDBAL(j
),
2376 rdba
& 0x00000000ffffffffULL
);
2377 wr32(E1000_RDBAH(j
), rdba
>> 32);
2378 wr32(E1000_RDLEN(j
),
2379 ring
->count
* sizeof(union e1000_adv_rx_desc
));
2381 ring
->head
= E1000_RDH(j
);
2382 ring
->tail
= E1000_RDT(j
);
2383 writel(0, hw
->hw_addr
+ ring
->tail
);
2384 writel(0, hw
->hw_addr
+ ring
->head
);
2386 rxdctl
= rd32(E1000_RXDCTL(j
));
2387 rxdctl
|= E1000_RXDCTL_QUEUE_ENABLE
;
2388 rxdctl
&= 0xFFF00000;
2389 rxdctl
|= IGB_RX_PTHRESH
;
2390 rxdctl
|= IGB_RX_HTHRESH
<< 8;
2391 rxdctl
|= IGB_RX_WTHRESH
<< 16;
2392 wr32(E1000_RXDCTL(j
), rxdctl
);
2395 if (adapter
->num_rx_queues
> 1) {
2404 get_random_bytes(&random
[0], 40);
2406 if (hw
->mac
.type
>= e1000_82576
)
2410 for (j
= 0; j
< (32 * 4); j
++) {
2412 adapter
->rx_ring
[(j
% adapter
->num_rx_queues
)].reg_idx
<< shift
;
2415 hw
->hw_addr
+ E1000_RETA(0) + (j
& ~3));
2417 if (adapter
->vfs_allocated_count
)
2418 mrqc
= E1000_MRQC_ENABLE_VMDQ_RSS_2Q
;
2420 mrqc
= E1000_MRQC_ENABLE_RSS_4Q
;
2422 /* Fill out hash function seeds */
2423 for (j
= 0; j
< 10; j
++)
2424 array_wr32(E1000_RSSRK(0), j
, random
[j
]);
2426 mrqc
|= (E1000_MRQC_RSS_FIELD_IPV4
|
2427 E1000_MRQC_RSS_FIELD_IPV4_TCP
);
2428 mrqc
|= (E1000_MRQC_RSS_FIELD_IPV6
|
2429 E1000_MRQC_RSS_FIELD_IPV6_TCP
);
2430 mrqc
|= (E1000_MRQC_RSS_FIELD_IPV4_UDP
|
2431 E1000_MRQC_RSS_FIELD_IPV6_UDP
);
2432 mrqc
|= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX
|
2433 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX
);
2435 wr32(E1000_MRQC
, mrqc
);
2436 } else if (adapter
->vfs_allocated_count
) {
2437 /* Enable multi-queue for sr-iov */
2438 wr32(E1000_MRQC
, E1000_MRQC_ENABLE_VMDQ
);
2441 /* Enable Receive Checksum Offload for TCP and UDP */
2442 rxcsum
= rd32(E1000_RXCSUM
);
2443 /* Disable raw packet checksumming */
2444 rxcsum
|= E1000_RXCSUM_PCSD
;
2446 if (adapter
->hw
.mac
.type
== e1000_82576
)
2447 /* Enable Receive Checksum Offload for SCTP */
2448 rxcsum
|= E1000_RXCSUM_CRCOFL
;
2450 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2451 wr32(E1000_RXCSUM
, rxcsum
);
2453 /* Set the default pool for the PF's first queue */
2454 igb_configure_vt_default_pool(adapter
);
2456 /* set UTA to appropriate mode */
2457 igb_set_uta(adapter
);
2459 /* set the correct pool for the PF default MAC address in entry 0 */
2460 igb_rar_set_qsel(adapter
, adapter
->hw
.mac
.addr
, 0,
2461 adapter
->vfs_allocated_count
);
2463 igb_rlpml_set(adapter
);
2465 /* Enable Receives */
2466 wr32(E1000_RCTL
, rctl
);
2470 * igb_free_tx_resources - Free Tx Resources per Queue
2471 * @tx_ring: Tx descriptor ring for a specific queue
2473 * Free all transmit software resources
2475 void igb_free_tx_resources(struct igb_ring
*tx_ring
)
2477 struct pci_dev
*pdev
= tx_ring
->q_vector
->adapter
->pdev
;
2479 igb_clean_tx_ring(tx_ring
);
2481 vfree(tx_ring
->buffer_info
);
2482 tx_ring
->buffer_info
= NULL
;
2484 pci_free_consistent(pdev
, tx_ring
->size
, tx_ring
->desc
, tx_ring
->dma
);
2486 tx_ring
->desc
= NULL
;
2490 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2491 * @adapter: board private structure
2493 * Free all transmit software resources
2495 static void igb_free_all_tx_resources(struct igb_adapter
*adapter
)
2499 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
2500 igb_free_tx_resources(&adapter
->tx_ring
[i
]);
2503 static void igb_unmap_and_free_tx_resource(struct igb_adapter
*adapter
,
2504 struct igb_buffer
*buffer_info
)
2506 buffer_info
->dma
= 0;
2507 if (buffer_info
->skb
) {
2508 skb_dma_unmap(&adapter
->pdev
->dev
, buffer_info
->skb
,
2510 dev_kfree_skb_any(buffer_info
->skb
);
2511 buffer_info
->skb
= NULL
;
2513 buffer_info
->time_stamp
= 0;
2514 /* buffer_info must be completely set up in the transmit path */
2518 * igb_clean_tx_ring - Free Tx Buffers
2519 * @tx_ring: ring to be cleaned
2521 static void igb_clean_tx_ring(struct igb_ring
*tx_ring
)
2523 struct igb_adapter
*adapter
= tx_ring
->q_vector
->adapter
;
2524 struct igb_buffer
*buffer_info
;
2528 if (!tx_ring
->buffer_info
)
2530 /* Free all the Tx ring sk_buffs */
2532 for (i
= 0; i
< tx_ring
->count
; i
++) {
2533 buffer_info
= &tx_ring
->buffer_info
[i
];
2534 igb_unmap_and_free_tx_resource(adapter
, buffer_info
);
2537 size
= sizeof(struct igb_buffer
) * tx_ring
->count
;
2538 memset(tx_ring
->buffer_info
, 0, size
);
2540 /* Zero out the descriptor ring */
2542 memset(tx_ring
->desc
, 0, tx_ring
->size
);
2544 tx_ring
->next_to_use
= 0;
2545 tx_ring
->next_to_clean
= 0;
2547 writel(0, adapter
->hw
.hw_addr
+ tx_ring
->head
);
2548 writel(0, adapter
->hw
.hw_addr
+ tx_ring
->tail
);
2552 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2553 * @adapter: board private structure
2555 static void igb_clean_all_tx_rings(struct igb_adapter
*adapter
)
2559 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
2560 igb_clean_tx_ring(&adapter
->tx_ring
[i
]);
2564 * igb_free_rx_resources - Free Rx Resources
2565 * @rx_ring: ring to clean the resources from
2567 * Free all receive software resources
2569 void igb_free_rx_resources(struct igb_ring
*rx_ring
)
2571 struct pci_dev
*pdev
= rx_ring
->q_vector
->adapter
->pdev
;
2573 igb_clean_rx_ring(rx_ring
);
2575 vfree(rx_ring
->buffer_info
);
2576 rx_ring
->buffer_info
= NULL
;
2578 pci_free_consistent(pdev
, rx_ring
->size
, rx_ring
->desc
, rx_ring
->dma
);
2580 rx_ring
->desc
= NULL
;
2584 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2585 * @adapter: board private structure
2587 * Free all receive software resources
2589 static void igb_free_all_rx_resources(struct igb_adapter
*adapter
)
2593 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
2594 igb_free_rx_resources(&adapter
->rx_ring
[i
]);
2598 * igb_clean_rx_ring - Free Rx Buffers per Queue
2599 * @rx_ring: ring to free buffers from
2601 static void igb_clean_rx_ring(struct igb_ring
*rx_ring
)
2603 struct igb_adapter
*adapter
= rx_ring
->q_vector
->adapter
;
2604 struct igb_buffer
*buffer_info
;
2605 struct pci_dev
*pdev
= adapter
->pdev
;
2609 if (!rx_ring
->buffer_info
)
2611 /* Free all the Rx ring sk_buffs */
2612 for (i
= 0; i
< rx_ring
->count
; i
++) {
2613 buffer_info
= &rx_ring
->buffer_info
[i
];
2614 if (buffer_info
->dma
) {
2615 if (adapter
->rx_ps_hdr_size
)
2616 pci_unmap_single(pdev
, buffer_info
->dma
,
2617 adapter
->rx_ps_hdr_size
,
2618 PCI_DMA_FROMDEVICE
);
2620 pci_unmap_single(pdev
, buffer_info
->dma
,
2621 adapter
->rx_buffer_len
,
2622 PCI_DMA_FROMDEVICE
);
2623 buffer_info
->dma
= 0;
2626 if (buffer_info
->skb
) {
2627 dev_kfree_skb(buffer_info
->skb
);
2628 buffer_info
->skb
= NULL
;
2630 if (buffer_info
->page
) {
2631 if (buffer_info
->page_dma
)
2632 pci_unmap_page(pdev
, buffer_info
->page_dma
,
2634 PCI_DMA_FROMDEVICE
);
2635 put_page(buffer_info
->page
);
2636 buffer_info
->page
= NULL
;
2637 buffer_info
->page_dma
= 0;
2638 buffer_info
->page_offset
= 0;
2642 size
= sizeof(struct igb_buffer
) * rx_ring
->count
;
2643 memset(rx_ring
->buffer_info
, 0, size
);
2645 /* Zero out the descriptor ring */
2646 memset(rx_ring
->desc
, 0, rx_ring
->size
);
2648 rx_ring
->next_to_clean
= 0;
2649 rx_ring
->next_to_use
= 0;
2651 writel(0, adapter
->hw
.hw_addr
+ rx_ring
->head
);
2652 writel(0, adapter
->hw
.hw_addr
+ rx_ring
->tail
);
2656 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2657 * @adapter: board private structure
2659 static void igb_clean_all_rx_rings(struct igb_adapter
*adapter
)
2663 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
2664 igb_clean_rx_ring(&adapter
->rx_ring
[i
]);
2668 * igb_set_mac - Change the Ethernet Address of the NIC
2669 * @netdev: network interface device structure
2670 * @p: pointer to an address structure
2672 * Returns 0 on success, negative on failure
2674 static int igb_set_mac(struct net_device
*netdev
, void *p
)
2676 struct igb_adapter
*adapter
= netdev_priv(netdev
);
2677 struct e1000_hw
*hw
= &adapter
->hw
;
2678 struct sockaddr
*addr
= p
;
2680 if (!is_valid_ether_addr(addr
->sa_data
))
2681 return -EADDRNOTAVAIL
;
2683 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
2684 memcpy(hw
->mac
.addr
, addr
->sa_data
, netdev
->addr_len
);
2686 /* set the correct pool for the new PF MAC address in entry 0 */
2687 igb_rar_set_qsel(adapter
, hw
->mac
.addr
, 0,
2688 adapter
->vfs_allocated_count
);
2694 * igb_write_mc_addr_list - write multicast addresses to MTA
2695 * @netdev: network interface device structure
2697 * Writes multicast address list to the MTA hash table.
2698 * Returns: -ENOMEM on failure
2699 * 0 on no addresses written
2700 * X on writing X addresses to MTA
2702 static int igb_write_mc_addr_list(struct net_device
*netdev
)
2704 struct igb_adapter
*adapter
= netdev_priv(netdev
);
2705 struct e1000_hw
*hw
= &adapter
->hw
;
2706 struct dev_mc_list
*mc_ptr
= netdev
->mc_list
;
2711 if (!netdev
->mc_count
) {
2712 /* nothing to program, so clear mc list */
2713 igb_update_mc_addr_list(hw
, NULL
, 0);
2714 igb_restore_vf_multicasts(adapter
);
2718 mta_list
= kzalloc(netdev
->mc_count
* 6, GFP_ATOMIC
);
2722 /* set vmolr receive overflow multicast bit */
2723 vmolr
|= E1000_VMOLR_ROMPE
;
2725 /* The shared function expects a packed array of only addresses. */
2726 mc_ptr
= netdev
->mc_list
;
2728 for (i
= 0; i
< netdev
->mc_count
; i
++) {
2731 memcpy(mta_list
+ (i
*ETH_ALEN
), mc_ptr
->dmi_addr
, ETH_ALEN
);
2732 mc_ptr
= mc_ptr
->next
;
2734 igb_update_mc_addr_list(hw
, mta_list
, i
);
2737 return netdev
->mc_count
;
2741 * igb_write_uc_addr_list - write unicast addresses to RAR table
2742 * @netdev: network interface device structure
2744 * Writes unicast address list to the RAR table.
2745 * Returns: -ENOMEM on failure/insufficient address space
2746 * 0 on no addresses written
2747 * X on writing X addresses to the RAR table
2749 static int igb_write_uc_addr_list(struct net_device
*netdev
)
2751 struct igb_adapter
*adapter
= netdev_priv(netdev
);
2752 struct e1000_hw
*hw
= &adapter
->hw
;
2753 unsigned int vfn
= adapter
->vfs_allocated_count
;
2754 unsigned int rar_entries
= hw
->mac
.rar_entry_count
- (vfn
+ 1);
2757 /* return ENOMEM indicating insufficient memory for addresses */
2758 if (netdev
->uc
.count
> rar_entries
)
2761 if (netdev
->uc
.count
&& rar_entries
) {
2762 struct netdev_hw_addr
*ha
;
2763 list_for_each_entry(ha
, &netdev
->uc
.list
, list
) {
2766 igb_rar_set_qsel(adapter
, ha
->addr
,
2772 /* write the addresses in reverse order to avoid write combining */
2773 for (; rar_entries
> 0 ; rar_entries
--) {
2774 wr32(E1000_RAH(rar_entries
), 0);
2775 wr32(E1000_RAL(rar_entries
), 0);
2783 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
2784 * @netdev: network interface device structure
2786 * The set_rx_mode entry point is called whenever the unicast or multicast
2787 * address lists or the network interface flags are updated. This routine is
2788 * responsible for configuring the hardware for proper unicast, multicast,
2789 * promiscuous mode, and all-multi behavior.
2791 static void igb_set_rx_mode(struct net_device
*netdev
)
2793 struct igb_adapter
*adapter
= netdev_priv(netdev
);
2794 struct e1000_hw
*hw
= &adapter
->hw
;
2795 unsigned int vfn
= adapter
->vfs_allocated_count
;
2796 u32 rctl
, vmolr
= 0;
2799 /* Check for Promiscuous and All Multicast modes */
2800 rctl
= rd32(E1000_RCTL
);
2802 /* clear the effected bits */
2803 rctl
&= ~(E1000_RCTL_UPE
| E1000_RCTL_MPE
| E1000_RCTL_VFE
);
2805 if (netdev
->flags
& IFF_PROMISC
) {
2806 rctl
|= (E1000_RCTL_UPE
| E1000_RCTL_MPE
);
2807 vmolr
|= (E1000_VMOLR_ROPE
| E1000_VMOLR_MPME
);
2809 if (netdev
->flags
& IFF_ALLMULTI
) {
2810 rctl
|= E1000_RCTL_MPE
;
2811 vmolr
|= E1000_VMOLR_MPME
;
2814 * Write addresses to the MTA, if the attempt fails
2815 * then we should just turn on promiscous mode so
2816 * that we can at least receive multicast traffic
2818 count
= igb_write_mc_addr_list(netdev
);
2820 rctl
|= E1000_RCTL_MPE
;
2821 vmolr
|= E1000_VMOLR_MPME
;
2823 vmolr
|= E1000_VMOLR_ROMPE
;
2827 * Write addresses to available RAR registers, if there is not
2828 * sufficient space to store all the addresses then enable
2829 * unicast promiscous mode
2831 count
= igb_write_uc_addr_list(netdev
);
2833 rctl
|= E1000_RCTL_UPE
;
2834 vmolr
|= E1000_VMOLR_ROPE
;
2836 rctl
|= E1000_RCTL_VFE
;
2838 wr32(E1000_RCTL
, rctl
);
2841 * In order to support SR-IOV and eventually VMDq it is necessary to set
2842 * the VMOLR to enable the appropriate modes. Without this workaround
2843 * we will have issues with VLAN tag stripping not being done for frames
2844 * that are only arriving because we are the default pool
2846 if (hw
->mac
.type
< e1000_82576
)
2849 vmolr
|= rd32(E1000_VMOLR(vfn
)) &
2850 ~(E1000_VMOLR_ROPE
| E1000_VMOLR_MPME
| E1000_VMOLR_ROMPE
);
2851 wr32(E1000_VMOLR(vfn
), vmolr
);
2852 igb_restore_vf_multicasts(adapter
);
2855 /* Need to wait a few seconds after link up to get diagnostic information from
2857 static void igb_update_phy_info(unsigned long data
)
2859 struct igb_adapter
*adapter
= (struct igb_adapter
*) data
;
2860 igb_get_phy_info(&adapter
->hw
);
2864 * igb_has_link - check shared code for link and determine up/down
2865 * @adapter: pointer to driver private info
2867 static bool igb_has_link(struct igb_adapter
*adapter
)
2869 struct e1000_hw
*hw
= &adapter
->hw
;
2870 bool link_active
= false;
2873 /* get_link_status is set on LSC (link status) interrupt or
2874 * rx sequence error interrupt. get_link_status will stay
2875 * false until the e1000_check_for_link establishes link
2876 * for copper adapters ONLY
2878 switch (hw
->phy
.media_type
) {
2879 case e1000_media_type_copper
:
2880 if (hw
->mac
.get_link_status
) {
2881 ret_val
= hw
->mac
.ops
.check_for_link(hw
);
2882 link_active
= !hw
->mac
.get_link_status
;
2887 case e1000_media_type_internal_serdes
:
2888 ret_val
= hw
->mac
.ops
.check_for_link(hw
);
2889 link_active
= hw
->mac
.serdes_has_link
;
2892 case e1000_media_type_unknown
:
2900 * igb_watchdog - Timer Call-back
2901 * @data: pointer to adapter cast into an unsigned long
2903 static void igb_watchdog(unsigned long data
)
2905 struct igb_adapter
*adapter
= (struct igb_adapter
*)data
;
2906 /* Do the rest outside of interrupt context */
2907 schedule_work(&adapter
->watchdog_task
);
2910 static void igb_watchdog_task(struct work_struct
*work
)
2912 struct igb_adapter
*adapter
= container_of(work
,
2913 struct igb_adapter
, watchdog_task
);
2914 struct e1000_hw
*hw
= &adapter
->hw
;
2915 struct net_device
*netdev
= adapter
->netdev
;
2916 struct igb_ring
*tx_ring
= adapter
->tx_ring
;
2920 link
= igb_has_link(adapter
);
2921 if ((netif_carrier_ok(netdev
)) && link
)
2925 if (!netif_carrier_ok(netdev
)) {
2927 hw
->mac
.ops
.get_speed_and_duplex(&adapter
->hw
,
2928 &adapter
->link_speed
,
2929 &adapter
->link_duplex
);
2931 ctrl
= rd32(E1000_CTRL
);
2932 /* Links status message must follow this format */
2933 printk(KERN_INFO
"igb: %s NIC Link is Up %d Mbps %s, "
2934 "Flow Control: %s\n",
2936 adapter
->link_speed
,
2937 adapter
->link_duplex
== FULL_DUPLEX
?
2938 "Full Duplex" : "Half Duplex",
2939 ((ctrl
& E1000_CTRL_TFCE
) && (ctrl
&
2940 E1000_CTRL_RFCE
)) ? "RX/TX" : ((ctrl
&
2941 E1000_CTRL_RFCE
) ? "RX" : ((ctrl
&
2942 E1000_CTRL_TFCE
) ? "TX" : "None")));
2944 /* tweak tx_queue_len according to speed/duplex and
2945 * adjust the timeout factor */
2946 netdev
->tx_queue_len
= adapter
->tx_queue_len
;
2947 adapter
->tx_timeout_factor
= 1;
2948 switch (adapter
->link_speed
) {
2950 netdev
->tx_queue_len
= 10;
2951 adapter
->tx_timeout_factor
= 14;
2954 netdev
->tx_queue_len
= 100;
2955 /* maybe add some timeout factor ? */
2959 netif_carrier_on(netdev
);
2961 igb_ping_all_vfs(adapter
);
2963 /* link state has changed, schedule phy info update */
2964 if (!test_bit(__IGB_DOWN
, &adapter
->state
))
2965 mod_timer(&adapter
->phy_info_timer
,
2966 round_jiffies(jiffies
+ 2 * HZ
));
2969 if (netif_carrier_ok(netdev
)) {
2970 adapter
->link_speed
= 0;
2971 adapter
->link_duplex
= 0;
2972 /* Links status message must follow this format */
2973 printk(KERN_INFO
"igb: %s NIC Link is Down\n",
2975 netif_carrier_off(netdev
);
2977 igb_ping_all_vfs(adapter
);
2979 /* link state has changed, schedule phy info update */
2980 if (!test_bit(__IGB_DOWN
, &adapter
->state
))
2981 mod_timer(&adapter
->phy_info_timer
,
2982 round_jiffies(jiffies
+ 2 * HZ
));
2987 igb_update_stats(adapter
);
2989 hw
->mac
.tx_packet_delta
= adapter
->stats
.tpt
- adapter
->tpt_old
;
2990 adapter
->tpt_old
= adapter
->stats
.tpt
;
2991 hw
->mac
.collision_delta
= adapter
->stats
.colc
- adapter
->colc_old
;
2992 adapter
->colc_old
= adapter
->stats
.colc
;
2994 adapter
->gorc
= adapter
->stats
.gorc
- adapter
->gorc_old
;
2995 adapter
->gorc_old
= adapter
->stats
.gorc
;
2996 adapter
->gotc
= adapter
->stats
.gotc
- adapter
->gotc_old
;
2997 adapter
->gotc_old
= adapter
->stats
.gotc
;
2999 igb_update_adaptive(&adapter
->hw
);
3001 if (!netif_carrier_ok(netdev
)) {
3002 if (igb_desc_unused(tx_ring
) + 1 < tx_ring
->count
) {
3003 /* We've lost link, so the controller stops DMA,
3004 * but we've got queued Tx work that's never going
3005 * to get done, so reset controller to flush Tx.
3006 * (Do the reset outside of interrupt context). */
3007 adapter
->tx_timeout_count
++;
3008 schedule_work(&adapter
->reset_task
);
3009 /* return immediately since reset is imminent */
3014 /* Cause software interrupt to ensure rx ring is cleaned */
3015 if (adapter
->msix_entries
) {
3017 for (i
= 0; i
< adapter
->num_q_vectors
; i
++) {
3018 struct igb_q_vector
*q_vector
= adapter
->q_vector
[i
];
3019 eics
|= q_vector
->eims_value
;
3021 wr32(E1000_EICS
, eics
);
3023 wr32(E1000_ICS
, E1000_ICS_RXDMT0
);
3026 /* Force detection of hung controller every watchdog period */
3027 tx_ring
->detect_tx_hung
= true;
3029 /* Reset the timer */
3030 if (!test_bit(__IGB_DOWN
, &adapter
->state
))
3031 mod_timer(&adapter
->watchdog_timer
,
3032 round_jiffies(jiffies
+ 2 * HZ
));
3035 enum latency_range
{
3039 latency_invalid
= 255
3044 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3046 * Stores a new ITR value based on strictly on packet size. This
3047 * algorithm is less sophisticated than that used in igb_update_itr,
3048 * due to the difficulty of synchronizing statistics across multiple
3049 * receive rings. The divisors and thresholds used by this fuction
3050 * were determined based on theoretical maximum wire speed and testing
3051 * data, in order to minimize response time while increasing bulk
3053 * This functionality is controlled by the InterruptThrottleRate module
3054 * parameter (see igb_param.c)
3055 * NOTE: This function is called only when operating in a multiqueue
3056 * receive environment.
3057 * @q_vector: pointer to q_vector
3059 static void igb_update_ring_itr(struct igb_q_vector
*q_vector
)
3061 int new_val
= q_vector
->itr_val
;
3062 int avg_wire_size
= 0;
3063 struct igb_adapter
*adapter
= q_vector
->adapter
;
3065 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3066 * ints/sec - ITR timer value of 120 ticks.
3068 if (adapter
->link_speed
!= SPEED_1000
) {
3073 if (q_vector
->rx_ring
&& q_vector
->rx_ring
->total_packets
) {
3074 struct igb_ring
*ring
= q_vector
->rx_ring
;
3075 avg_wire_size
= ring
->total_bytes
/ ring
->total_packets
;
3078 if (q_vector
->tx_ring
&& q_vector
->tx_ring
->total_packets
) {
3079 struct igb_ring
*ring
= q_vector
->tx_ring
;
3080 avg_wire_size
= max_t(u32
, avg_wire_size
,
3081 (ring
->total_bytes
/
3082 ring
->total_packets
));
3085 /* if avg_wire_size isn't set no work was done */
3089 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3090 avg_wire_size
+= 24;
3092 /* Don't starve jumbo frames */
3093 avg_wire_size
= min(avg_wire_size
, 3000);
3095 /* Give a little boost to mid-size frames */
3096 if ((avg_wire_size
> 300) && (avg_wire_size
< 1200))
3097 new_val
= avg_wire_size
/ 3;
3099 new_val
= avg_wire_size
/ 2;
3102 if (new_val
!= q_vector
->itr_val
) {
3103 q_vector
->itr_val
= new_val
;
3104 q_vector
->set_itr
= 1;
3107 if (q_vector
->rx_ring
) {
3108 q_vector
->rx_ring
->total_bytes
= 0;
3109 q_vector
->rx_ring
->total_packets
= 0;
3111 if (q_vector
->tx_ring
) {
3112 q_vector
->tx_ring
->total_bytes
= 0;
3113 q_vector
->tx_ring
->total_packets
= 0;
3118 * igb_update_itr - update the dynamic ITR value based on statistics
3119 * Stores a new ITR value based on packets and byte
3120 * counts during the last interrupt. The advantage of per interrupt
3121 * computation is faster updates and more accurate ITR for the current
3122 * traffic pattern. Constants in this function were computed
3123 * based on theoretical maximum wire speed and thresholds were set based
3124 * on testing data as well as attempting to minimize response time
3125 * while increasing bulk throughput.
3126 * this functionality is controlled by the InterruptThrottleRate module
3127 * parameter (see igb_param.c)
3128 * NOTE: These calculations are only valid when operating in a single-
3129 * queue environment.
3130 * @adapter: pointer to adapter
3131 * @itr_setting: current q_vector->itr_val
3132 * @packets: the number of packets during this measurement interval
3133 * @bytes: the number of bytes during this measurement interval
3135 static unsigned int igb_update_itr(struct igb_adapter
*adapter
, u16 itr_setting
,
3136 int packets
, int bytes
)
3138 unsigned int retval
= itr_setting
;
3141 goto update_itr_done
;
3143 switch (itr_setting
) {
3144 case lowest_latency
:
3145 /* handle TSO and jumbo frames */
3146 if (bytes
/packets
> 8000)
3147 retval
= bulk_latency
;
3148 else if ((packets
< 5) && (bytes
> 512))
3149 retval
= low_latency
;
3151 case low_latency
: /* 50 usec aka 20000 ints/s */
3152 if (bytes
> 10000) {
3153 /* this if handles the TSO accounting */
3154 if (bytes
/packets
> 8000) {
3155 retval
= bulk_latency
;
3156 } else if ((packets
< 10) || ((bytes
/packets
) > 1200)) {
3157 retval
= bulk_latency
;
3158 } else if ((packets
> 35)) {
3159 retval
= lowest_latency
;
3161 } else if (bytes
/packets
> 2000) {
3162 retval
= bulk_latency
;
3163 } else if (packets
<= 2 && bytes
< 512) {
3164 retval
= lowest_latency
;
3167 case bulk_latency
: /* 250 usec aka 4000 ints/s */
3168 if (bytes
> 25000) {
3170 retval
= low_latency
;
3171 } else if (bytes
< 1500) {
3172 retval
= low_latency
;
3181 static void igb_set_itr(struct igb_adapter
*adapter
)
3183 struct igb_q_vector
*q_vector
= adapter
->q_vector
[0];
3185 u32 new_itr
= q_vector
->itr_val
;
3187 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3188 if (adapter
->link_speed
!= SPEED_1000
) {
3194 adapter
->rx_itr
= igb_update_itr(adapter
,
3196 adapter
->rx_ring
->total_packets
,
3197 adapter
->rx_ring
->total_bytes
);
3199 adapter
->tx_itr
= igb_update_itr(adapter
,
3201 adapter
->tx_ring
->total_packets
,
3202 adapter
->tx_ring
->total_bytes
);
3203 current_itr
= max(adapter
->rx_itr
, adapter
->tx_itr
);
3205 /* conservative mode (itr 3) eliminates the lowest_latency setting */
3206 if (adapter
->itr_setting
== 3 && current_itr
== lowest_latency
)
3207 current_itr
= low_latency
;
3209 switch (current_itr
) {
3210 /* counts and packets in update_itr are dependent on these numbers */
3211 case lowest_latency
:
3212 new_itr
= 56; /* aka 70,000 ints/sec */
3215 new_itr
= 196; /* aka 20,000 ints/sec */
3218 new_itr
= 980; /* aka 4,000 ints/sec */
3225 adapter
->rx_ring
->total_bytes
= 0;
3226 adapter
->rx_ring
->total_packets
= 0;
3227 adapter
->tx_ring
->total_bytes
= 0;
3228 adapter
->tx_ring
->total_packets
= 0;
3230 if (new_itr
!= q_vector
->itr_val
) {
3231 /* this attempts to bias the interrupt rate towards Bulk
3232 * by adding intermediate steps when interrupt rate is
3234 new_itr
= new_itr
> q_vector
->itr_val
?
3235 max((new_itr
* q_vector
->itr_val
) /
3236 (new_itr
+ (q_vector
->itr_val
>> 2)),
3239 /* Don't write the value here; it resets the adapter's
3240 * internal timer, and causes us to delay far longer than
3241 * we should between interrupts. Instead, we write the ITR
3242 * value at the beginning of the next interrupt so the timing
3243 * ends up being correct.
3245 q_vector
->itr_val
= new_itr
;
3246 q_vector
->set_itr
= 1;
3252 #define IGB_TX_FLAGS_CSUM 0x00000001
3253 #define IGB_TX_FLAGS_VLAN 0x00000002
3254 #define IGB_TX_FLAGS_TSO 0x00000004
3255 #define IGB_TX_FLAGS_IPV4 0x00000008
3256 #define IGB_TX_FLAGS_TSTAMP 0x00000010
3257 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
3258 #define IGB_TX_FLAGS_VLAN_SHIFT 16
3260 static inline int igb_tso_adv(struct igb_adapter
*adapter
,
3261 struct igb_ring
*tx_ring
,
3262 struct sk_buff
*skb
, u32 tx_flags
, u8
*hdr_len
)
3264 struct e1000_adv_tx_context_desc
*context_desc
;
3267 struct igb_buffer
*buffer_info
;
3268 u32 info
= 0, tu_cmd
= 0;
3269 u32 mss_l4len_idx
, l4len
;
3272 if (skb_header_cloned(skb
)) {
3273 err
= pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
);
3278 l4len
= tcp_hdrlen(skb
);
3281 if (skb
->protocol
== htons(ETH_P_IP
)) {
3282 struct iphdr
*iph
= ip_hdr(skb
);
3285 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
3289 } else if (skb_shinfo(skb
)->gso_type
== SKB_GSO_TCPV6
) {
3290 ipv6_hdr(skb
)->payload_len
= 0;
3291 tcp_hdr(skb
)->check
= ~csum_ipv6_magic(&ipv6_hdr(skb
)->saddr
,
3292 &ipv6_hdr(skb
)->daddr
,
3296 i
= tx_ring
->next_to_use
;
3298 buffer_info
= &tx_ring
->buffer_info
[i
];
3299 context_desc
= E1000_TX_CTXTDESC_ADV(*tx_ring
, i
);
3300 /* VLAN MACLEN IPLEN */
3301 if (tx_flags
& IGB_TX_FLAGS_VLAN
)
3302 info
|= (tx_flags
& IGB_TX_FLAGS_VLAN_MASK
);
3303 info
|= (skb_network_offset(skb
) << E1000_ADVTXD_MACLEN_SHIFT
);
3304 *hdr_len
+= skb_network_offset(skb
);
3305 info
|= skb_network_header_len(skb
);
3306 *hdr_len
+= skb_network_header_len(skb
);
3307 context_desc
->vlan_macip_lens
= cpu_to_le32(info
);
3309 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3310 tu_cmd
|= (E1000_TXD_CMD_DEXT
| E1000_ADVTXD_DTYP_CTXT
);
3312 if (skb
->protocol
== htons(ETH_P_IP
))
3313 tu_cmd
|= E1000_ADVTXD_TUCMD_IPV4
;
3314 tu_cmd
|= E1000_ADVTXD_TUCMD_L4T_TCP
;
3316 context_desc
->type_tucmd_mlhl
= cpu_to_le32(tu_cmd
);
3319 mss_l4len_idx
= (skb_shinfo(skb
)->gso_size
<< E1000_ADVTXD_MSS_SHIFT
);
3320 mss_l4len_idx
|= (l4len
<< E1000_ADVTXD_L4LEN_SHIFT
);
3322 /* For 82575, context index must be unique per ring. */
3323 if (adapter
->flags
& IGB_FLAG_NEED_CTX_IDX
)
3324 mss_l4len_idx
|= tx_ring
->queue_index
<< 4;
3326 context_desc
->mss_l4len_idx
= cpu_to_le32(mss_l4len_idx
);
3327 context_desc
->seqnum_seed
= 0;
3329 buffer_info
->time_stamp
= jiffies
;
3330 buffer_info
->next_to_watch
= i
;
3331 buffer_info
->dma
= 0;
3333 if (i
== tx_ring
->count
)
3336 tx_ring
->next_to_use
= i
;
3341 static inline bool igb_tx_csum_adv(struct igb_adapter
*adapter
,
3342 struct igb_ring
*tx_ring
,
3343 struct sk_buff
*skb
, u32 tx_flags
)
3345 struct e1000_adv_tx_context_desc
*context_desc
;
3347 struct igb_buffer
*buffer_info
;
3348 u32 info
= 0, tu_cmd
= 0;
3350 if ((skb
->ip_summed
== CHECKSUM_PARTIAL
) ||
3351 (tx_flags
& IGB_TX_FLAGS_VLAN
)) {
3352 i
= tx_ring
->next_to_use
;
3353 buffer_info
= &tx_ring
->buffer_info
[i
];
3354 context_desc
= E1000_TX_CTXTDESC_ADV(*tx_ring
, i
);
3356 if (tx_flags
& IGB_TX_FLAGS_VLAN
)
3357 info
|= (tx_flags
& IGB_TX_FLAGS_VLAN_MASK
);
3358 info
|= (skb_network_offset(skb
) << E1000_ADVTXD_MACLEN_SHIFT
);
3359 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
3360 info
|= skb_network_header_len(skb
);
3362 context_desc
->vlan_macip_lens
= cpu_to_le32(info
);
3364 tu_cmd
|= (E1000_TXD_CMD_DEXT
| E1000_ADVTXD_DTYP_CTXT
);
3366 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
3369 if (skb
->protocol
== cpu_to_be16(ETH_P_8021Q
)) {
3370 const struct vlan_ethhdr
*vhdr
=
3371 (const struct vlan_ethhdr
*)skb
->data
;
3373 protocol
= vhdr
->h_vlan_encapsulated_proto
;
3375 protocol
= skb
->protocol
;
3379 case cpu_to_be16(ETH_P_IP
):
3380 tu_cmd
|= E1000_ADVTXD_TUCMD_IPV4
;
3381 if (ip_hdr(skb
)->protocol
== IPPROTO_TCP
)
3382 tu_cmd
|= E1000_ADVTXD_TUCMD_L4T_TCP
;
3383 else if (ip_hdr(skb
)->protocol
== IPPROTO_SCTP
)
3384 tu_cmd
|= E1000_ADVTXD_TUCMD_L4T_SCTP
;
3386 case cpu_to_be16(ETH_P_IPV6
):
3387 /* XXX what about other V6 headers?? */
3388 if (ipv6_hdr(skb
)->nexthdr
== IPPROTO_TCP
)
3389 tu_cmd
|= E1000_ADVTXD_TUCMD_L4T_TCP
;
3390 else if (ipv6_hdr(skb
)->nexthdr
== IPPROTO_SCTP
)
3391 tu_cmd
|= E1000_ADVTXD_TUCMD_L4T_SCTP
;
3394 if (unlikely(net_ratelimit()))
3395 dev_warn(&adapter
->pdev
->dev
,
3396 "partial checksum but proto=%x!\n",
3402 context_desc
->type_tucmd_mlhl
= cpu_to_le32(tu_cmd
);
3403 context_desc
->seqnum_seed
= 0;
3404 if (adapter
->flags
& IGB_FLAG_NEED_CTX_IDX
)
3405 context_desc
->mss_l4len_idx
=
3406 cpu_to_le32(tx_ring
->queue_index
<< 4);
3408 context_desc
->mss_l4len_idx
= 0;
3410 buffer_info
->time_stamp
= jiffies
;
3411 buffer_info
->next_to_watch
= i
;
3412 buffer_info
->dma
= 0;
3415 if (i
== tx_ring
->count
)
3417 tx_ring
->next_to_use
= i
;
3424 #define IGB_MAX_TXD_PWR 16
3425 #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3427 static inline int igb_tx_map_adv(struct igb_adapter
*adapter
,
3428 struct igb_ring
*tx_ring
, struct sk_buff
*skb
,
3431 struct igb_buffer
*buffer_info
;
3432 unsigned int len
= skb_headlen(skb
);
3433 unsigned int count
= 0, i
;
3437 i
= tx_ring
->next_to_use
;
3439 if (skb_dma_map(&adapter
->pdev
->dev
, skb
, DMA_TO_DEVICE
)) {
3440 dev_err(&adapter
->pdev
->dev
, "TX DMA map failed\n");
3444 map
= skb_shinfo(skb
)->dma_maps
;
3446 buffer_info
= &tx_ring
->buffer_info
[i
];
3447 BUG_ON(len
>= IGB_MAX_DATA_PER_TXD
);
3448 buffer_info
->length
= len
;
3449 /* set time_stamp *before* dma to help avoid a possible race */
3450 buffer_info
->time_stamp
= jiffies
;
3451 buffer_info
->next_to_watch
= i
;
3452 buffer_info
->dma
= skb_shinfo(skb
)->dma_head
;
3454 for (f
= 0; f
< skb_shinfo(skb
)->nr_frags
; f
++) {
3455 struct skb_frag_struct
*frag
;
3458 if (i
== tx_ring
->count
)
3461 frag
= &skb_shinfo(skb
)->frags
[f
];
3464 buffer_info
= &tx_ring
->buffer_info
[i
];
3465 BUG_ON(len
>= IGB_MAX_DATA_PER_TXD
);
3466 buffer_info
->length
= len
;
3467 buffer_info
->time_stamp
= jiffies
;
3468 buffer_info
->next_to_watch
= i
;
3469 buffer_info
->dma
= map
[count
];
3473 tx_ring
->buffer_info
[i
].skb
= skb
;
3474 tx_ring
->buffer_info
[first
].next_to_watch
= i
;
3479 static inline void igb_tx_queue_adv(struct igb_adapter
*adapter
,
3480 struct igb_ring
*tx_ring
,
3481 int tx_flags
, int count
, u32 paylen
,
3484 union e1000_adv_tx_desc
*tx_desc
= NULL
;
3485 struct igb_buffer
*buffer_info
;
3486 u32 olinfo_status
= 0, cmd_type_len
;
3489 cmd_type_len
= (E1000_ADVTXD_DTYP_DATA
| E1000_ADVTXD_DCMD_IFCS
|
3490 E1000_ADVTXD_DCMD_DEXT
);
3492 if (tx_flags
& IGB_TX_FLAGS_VLAN
)
3493 cmd_type_len
|= E1000_ADVTXD_DCMD_VLE
;
3495 if (tx_flags
& IGB_TX_FLAGS_TSTAMP
)
3496 cmd_type_len
|= E1000_ADVTXD_MAC_TSTAMP
;
3498 if (tx_flags
& IGB_TX_FLAGS_TSO
) {
3499 cmd_type_len
|= E1000_ADVTXD_DCMD_TSE
;
3501 /* insert tcp checksum */
3502 olinfo_status
|= E1000_TXD_POPTS_TXSM
<< 8;
3504 /* insert ip checksum */
3505 if (tx_flags
& IGB_TX_FLAGS_IPV4
)
3506 olinfo_status
|= E1000_TXD_POPTS_IXSM
<< 8;
3508 } else if (tx_flags
& IGB_TX_FLAGS_CSUM
) {
3509 olinfo_status
|= E1000_TXD_POPTS_TXSM
<< 8;
3512 if ((adapter
->flags
& IGB_FLAG_NEED_CTX_IDX
) &&
3513 (tx_flags
& (IGB_TX_FLAGS_CSUM
| IGB_TX_FLAGS_TSO
|
3514 IGB_TX_FLAGS_VLAN
)))
3515 olinfo_status
|= tx_ring
->queue_index
<< 4;
3517 olinfo_status
|= ((paylen
- hdr_len
) << E1000_ADVTXD_PAYLEN_SHIFT
);
3519 i
= tx_ring
->next_to_use
;
3521 buffer_info
= &tx_ring
->buffer_info
[i
];
3522 tx_desc
= E1000_TX_DESC_ADV(*tx_ring
, i
);
3523 tx_desc
->read
.buffer_addr
= cpu_to_le64(buffer_info
->dma
);
3524 tx_desc
->read
.cmd_type_len
=
3525 cpu_to_le32(cmd_type_len
| buffer_info
->length
);
3526 tx_desc
->read
.olinfo_status
= cpu_to_le32(olinfo_status
);
3528 if (i
== tx_ring
->count
)
3532 tx_desc
->read
.cmd_type_len
|= cpu_to_le32(adapter
->txd_cmd
);
3533 /* Force memory writes to complete before letting h/w
3534 * know there are new descriptors to fetch. (Only
3535 * applicable for weak-ordered memory model archs,
3536 * such as IA-64). */
3539 tx_ring
->next_to_use
= i
;
3540 writel(i
, adapter
->hw
.hw_addr
+ tx_ring
->tail
);
3541 /* we need this if more than one processor can write to our tail
3542 * at a time, it syncronizes IO on IA64/Altix systems */
3546 static int __igb_maybe_stop_tx(struct net_device
*netdev
,
3547 struct igb_ring
*tx_ring
, int size
)
3549 struct igb_adapter
*adapter
= netdev_priv(netdev
);
3551 netif_stop_subqueue(netdev
, tx_ring
->queue_index
);
3553 /* Herbert's original patch had:
3554 * smp_mb__after_netif_stop_queue();
3555 * but since that doesn't exist yet, just open code it. */
3558 /* We need to check again in a case another CPU has just
3559 * made room available. */
3560 if (igb_desc_unused(tx_ring
) < size
)
3564 netif_wake_subqueue(netdev
, tx_ring
->queue_index
);
3565 ++adapter
->restart_queue
;
3569 static int igb_maybe_stop_tx(struct net_device
*netdev
,
3570 struct igb_ring
*tx_ring
, int size
)
3572 if (igb_desc_unused(tx_ring
) >= size
)
3574 return __igb_maybe_stop_tx(netdev
, tx_ring
, size
);
3577 static netdev_tx_t
igb_xmit_frame_ring_adv(struct sk_buff
*skb
,
3578 struct net_device
*netdev
,
3579 struct igb_ring
*tx_ring
)
3581 struct igb_adapter
*adapter
= netdev_priv(netdev
);
3583 unsigned int tx_flags
= 0;
3587 union skb_shared_tx
*shtx
;
3589 if (test_bit(__IGB_DOWN
, &adapter
->state
)) {
3590 dev_kfree_skb_any(skb
);
3591 return NETDEV_TX_OK
;
3594 if (skb
->len
<= 0) {
3595 dev_kfree_skb_any(skb
);
3596 return NETDEV_TX_OK
;
3599 /* need: 1 descriptor per page,
3600 * + 2 desc gap to keep tail from touching head,
3601 * + 1 desc for skb->data,
3602 * + 1 desc for context descriptor,
3603 * otherwise try next time */
3604 if (igb_maybe_stop_tx(netdev
, tx_ring
, skb_shinfo(skb
)->nr_frags
+ 4)) {
3605 /* this is a hard error */
3606 return NETDEV_TX_BUSY
;
3610 * TODO: check that there currently is no other packet with
3611 * time stamping in the queue
3613 * When doing time stamping, keep the connection to the socket
3614 * a while longer: it is still needed by skb_hwtstamp_tx(),
3615 * called either in igb_tx_hwtstamp() or by our caller when
3616 * doing software time stamping.
3619 if (unlikely(shtx
->hardware
)) {
3620 shtx
->in_progress
= 1;
3621 tx_flags
|= IGB_TX_FLAGS_TSTAMP
;
3624 if (adapter
->vlgrp
&& vlan_tx_tag_present(skb
)) {
3625 tx_flags
|= IGB_TX_FLAGS_VLAN
;
3626 tx_flags
|= (vlan_tx_tag_get(skb
) << IGB_TX_FLAGS_VLAN_SHIFT
);
3629 if (skb
->protocol
== htons(ETH_P_IP
))
3630 tx_flags
|= IGB_TX_FLAGS_IPV4
;
3632 first
= tx_ring
->next_to_use
;
3633 tso
= skb_is_gso(skb
) ? igb_tso_adv(adapter
, tx_ring
, skb
, tx_flags
,
3637 dev_kfree_skb_any(skb
);
3638 return NETDEV_TX_OK
;
3642 tx_flags
|= IGB_TX_FLAGS_TSO
;
3643 else if (igb_tx_csum_adv(adapter
, tx_ring
, skb
, tx_flags
) &&
3644 (skb
->ip_summed
== CHECKSUM_PARTIAL
))
3645 tx_flags
|= IGB_TX_FLAGS_CSUM
;
3648 * count reflects descriptors mapped, if 0 then mapping error
3649 * has occured and we need to rewind the descriptor queue
3651 count
= igb_tx_map_adv(adapter
, tx_ring
, skb
, first
);
3654 igb_tx_queue_adv(adapter
, tx_ring
, tx_flags
, count
,
3656 /* Make sure there is space in the ring for the next send. */
3657 igb_maybe_stop_tx(netdev
, tx_ring
, MAX_SKB_FRAGS
+ 4);
3659 dev_kfree_skb_any(skb
);
3660 tx_ring
->buffer_info
[first
].time_stamp
= 0;
3661 tx_ring
->next_to_use
= first
;
3664 return NETDEV_TX_OK
;
3667 static netdev_tx_t
igb_xmit_frame_adv(struct sk_buff
*skb
,
3668 struct net_device
*netdev
)
3670 struct igb_adapter
*adapter
= netdev_priv(netdev
);
3671 struct igb_ring
*tx_ring
;
3674 r_idx
= skb
->queue_mapping
& (IGB_ABS_MAX_TX_QUEUES
- 1);
3675 tx_ring
= adapter
->multi_tx_table
[r_idx
];
3677 /* This goes back to the question of how to logically map a tx queue
3678 * to a flow. Right now, performance is impacted slightly negatively
3679 * if using multiple tx queues. If the stack breaks away from a
3680 * single qdisc implementation, we can look at this again. */
3681 return igb_xmit_frame_ring_adv(skb
, netdev
, tx_ring
);
3685 * igb_tx_timeout - Respond to a Tx Hang
3686 * @netdev: network interface device structure
3688 static void igb_tx_timeout(struct net_device
*netdev
)
3690 struct igb_adapter
*adapter
= netdev_priv(netdev
);
3691 struct e1000_hw
*hw
= &adapter
->hw
;
3693 /* Do the reset outside of interrupt context */
3694 adapter
->tx_timeout_count
++;
3695 schedule_work(&adapter
->reset_task
);
3697 (adapter
->eims_enable_mask
& ~adapter
->eims_other
));
3700 static void igb_reset_task(struct work_struct
*work
)
3702 struct igb_adapter
*adapter
;
3703 adapter
= container_of(work
, struct igb_adapter
, reset_task
);
3705 igb_reinit_locked(adapter
);
3709 * igb_get_stats - Get System Network Statistics
3710 * @netdev: network interface device structure
3712 * Returns the address of the device statistics structure.
3713 * The statistics are actually updated from the timer callback.
3715 static struct net_device_stats
*igb_get_stats(struct net_device
*netdev
)
3717 /* only return the current stats */
3718 return &netdev
->stats
;
3722 * igb_change_mtu - Change the Maximum Transfer Unit
3723 * @netdev: network interface device structure
3724 * @new_mtu: new value for maximum frame size
3726 * Returns 0 on success, negative on failure
3728 static int igb_change_mtu(struct net_device
*netdev
, int new_mtu
)
3730 struct igb_adapter
*adapter
= netdev_priv(netdev
);
3731 int max_frame
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
3733 if ((max_frame
< ETH_ZLEN
+ ETH_FCS_LEN
) ||
3734 (max_frame
> MAX_JUMBO_FRAME_SIZE
)) {
3735 dev_err(&adapter
->pdev
->dev
, "Invalid MTU setting\n");
3739 if (max_frame
> MAX_STD_JUMBO_FRAME_SIZE
) {
3740 dev_err(&adapter
->pdev
->dev
, "MTU > 9216 not supported.\n");
3744 while (test_and_set_bit(__IGB_RESETTING
, &adapter
->state
))
3747 /* igb_down has a dependency on max_frame_size */
3748 adapter
->max_frame_size
= max_frame
;
3749 if (netif_running(netdev
))
3752 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3753 * means we reserve 2 more, this pushes us to allocate from the next
3755 * i.e. RXBUFFER_2048 --> size-4096 slab
3758 if (max_frame
<= IGB_RXBUFFER_256
)
3759 adapter
->rx_buffer_len
= IGB_RXBUFFER_256
;
3760 else if (max_frame
<= IGB_RXBUFFER_512
)
3761 adapter
->rx_buffer_len
= IGB_RXBUFFER_512
;
3762 else if (max_frame
<= IGB_RXBUFFER_1024
)
3763 adapter
->rx_buffer_len
= IGB_RXBUFFER_1024
;
3764 else if (max_frame
<= IGB_RXBUFFER_2048
)
3765 adapter
->rx_buffer_len
= IGB_RXBUFFER_2048
;
3767 #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3768 adapter
->rx_buffer_len
= IGB_RXBUFFER_16384
;
3770 adapter
->rx_buffer_len
= PAGE_SIZE
/ 2;
3773 /* if sr-iov is enabled we need to force buffer size to 1K or larger */
3774 if (adapter
->vfs_allocated_count
&&
3775 (adapter
->rx_buffer_len
< IGB_RXBUFFER_1024
))
3776 adapter
->rx_buffer_len
= IGB_RXBUFFER_1024
;
3778 /* adjust allocation if LPE protects us, and we aren't using SBP */
3779 if ((max_frame
== ETH_FRAME_LEN
+ ETH_FCS_LEN
) ||
3780 (max_frame
== MAXIMUM_ETHERNET_VLAN_SIZE
))
3781 adapter
->rx_buffer_len
= MAXIMUM_ETHERNET_VLAN_SIZE
;
3783 dev_info(&adapter
->pdev
->dev
, "changing MTU from %d to %d\n",
3784 netdev
->mtu
, new_mtu
);
3785 netdev
->mtu
= new_mtu
;
3787 if (netif_running(netdev
))
3792 clear_bit(__IGB_RESETTING
, &adapter
->state
);
3798 * igb_update_stats - Update the board statistics counters
3799 * @adapter: board private structure
3802 void igb_update_stats(struct igb_adapter
*adapter
)
3804 struct net_device
*netdev
= adapter
->netdev
;
3805 struct e1000_hw
*hw
= &adapter
->hw
;
3806 struct pci_dev
*pdev
= adapter
->pdev
;
3809 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3812 * Prevent stats update while adapter is being reset, or if the pci
3813 * connection is down.
3815 if (adapter
->link_speed
== 0)
3817 if (pci_channel_offline(pdev
))
3820 adapter
->stats
.crcerrs
+= rd32(E1000_CRCERRS
);
3821 adapter
->stats
.gprc
+= rd32(E1000_GPRC
);
3822 adapter
->stats
.gorc
+= rd32(E1000_GORCL
);
3823 rd32(E1000_GORCH
); /* clear GORCL */
3824 adapter
->stats
.bprc
+= rd32(E1000_BPRC
);
3825 adapter
->stats
.mprc
+= rd32(E1000_MPRC
);
3826 adapter
->stats
.roc
+= rd32(E1000_ROC
);
3828 adapter
->stats
.prc64
+= rd32(E1000_PRC64
);
3829 adapter
->stats
.prc127
+= rd32(E1000_PRC127
);
3830 adapter
->stats
.prc255
+= rd32(E1000_PRC255
);
3831 adapter
->stats
.prc511
+= rd32(E1000_PRC511
);
3832 adapter
->stats
.prc1023
+= rd32(E1000_PRC1023
);
3833 adapter
->stats
.prc1522
+= rd32(E1000_PRC1522
);
3834 adapter
->stats
.symerrs
+= rd32(E1000_SYMERRS
);
3835 adapter
->stats
.sec
+= rd32(E1000_SEC
);
3837 adapter
->stats
.mpc
+= rd32(E1000_MPC
);
3838 adapter
->stats
.scc
+= rd32(E1000_SCC
);
3839 adapter
->stats
.ecol
+= rd32(E1000_ECOL
);
3840 adapter
->stats
.mcc
+= rd32(E1000_MCC
);
3841 adapter
->stats
.latecol
+= rd32(E1000_LATECOL
);
3842 adapter
->stats
.dc
+= rd32(E1000_DC
);
3843 adapter
->stats
.rlec
+= rd32(E1000_RLEC
);
3844 adapter
->stats
.xonrxc
+= rd32(E1000_XONRXC
);
3845 adapter
->stats
.xontxc
+= rd32(E1000_XONTXC
);
3846 adapter
->stats
.xoffrxc
+= rd32(E1000_XOFFRXC
);
3847 adapter
->stats
.xofftxc
+= rd32(E1000_XOFFTXC
);
3848 adapter
->stats
.fcruc
+= rd32(E1000_FCRUC
);
3849 adapter
->stats
.gptc
+= rd32(E1000_GPTC
);
3850 adapter
->stats
.gotc
+= rd32(E1000_GOTCL
);
3851 rd32(E1000_GOTCH
); /* clear GOTCL */
3852 adapter
->stats
.rnbc
+= rd32(E1000_RNBC
);
3853 adapter
->stats
.ruc
+= rd32(E1000_RUC
);
3854 adapter
->stats
.rfc
+= rd32(E1000_RFC
);
3855 adapter
->stats
.rjc
+= rd32(E1000_RJC
);
3856 adapter
->stats
.tor
+= rd32(E1000_TORH
);
3857 adapter
->stats
.tot
+= rd32(E1000_TOTH
);
3858 adapter
->stats
.tpr
+= rd32(E1000_TPR
);
3860 adapter
->stats
.ptc64
+= rd32(E1000_PTC64
);
3861 adapter
->stats
.ptc127
+= rd32(E1000_PTC127
);
3862 adapter
->stats
.ptc255
+= rd32(E1000_PTC255
);
3863 adapter
->stats
.ptc511
+= rd32(E1000_PTC511
);
3864 adapter
->stats
.ptc1023
+= rd32(E1000_PTC1023
);
3865 adapter
->stats
.ptc1522
+= rd32(E1000_PTC1522
);
3867 adapter
->stats
.mptc
+= rd32(E1000_MPTC
);
3868 adapter
->stats
.bptc
+= rd32(E1000_BPTC
);
3870 /* used for adaptive IFS */
3872 hw
->mac
.tx_packet_delta
= rd32(E1000_TPT
);
3873 adapter
->stats
.tpt
+= hw
->mac
.tx_packet_delta
;
3874 hw
->mac
.collision_delta
= rd32(E1000_COLC
);
3875 adapter
->stats
.colc
+= hw
->mac
.collision_delta
;
3877 adapter
->stats
.algnerrc
+= rd32(E1000_ALGNERRC
);
3878 adapter
->stats
.rxerrc
+= rd32(E1000_RXERRC
);
3879 adapter
->stats
.tncrs
+= rd32(E1000_TNCRS
);
3880 adapter
->stats
.tsctc
+= rd32(E1000_TSCTC
);
3881 adapter
->stats
.tsctfc
+= rd32(E1000_TSCTFC
);
3883 adapter
->stats
.iac
+= rd32(E1000_IAC
);
3884 adapter
->stats
.icrxoc
+= rd32(E1000_ICRXOC
);
3885 adapter
->stats
.icrxptc
+= rd32(E1000_ICRXPTC
);
3886 adapter
->stats
.icrxatc
+= rd32(E1000_ICRXATC
);
3887 adapter
->stats
.ictxptc
+= rd32(E1000_ICTXPTC
);
3888 adapter
->stats
.ictxatc
+= rd32(E1000_ICTXATC
);
3889 adapter
->stats
.ictxqec
+= rd32(E1000_ICTXQEC
);
3890 adapter
->stats
.ictxqmtc
+= rd32(E1000_ICTXQMTC
);
3891 adapter
->stats
.icrxdmtc
+= rd32(E1000_ICRXDMTC
);
3893 /* Fill out the OS statistics structure */
3894 netdev
->stats
.multicast
= adapter
->stats
.mprc
;
3895 netdev
->stats
.collisions
= adapter
->stats
.colc
;
3899 if (hw
->mac
.type
!= e1000_82575
) {
3901 u64 rqdpc_total
= 0;
3903 /* Read out drops stats per RX queue. Notice RQDPC (Receive
3904 * Queue Drop Packet Count) stats only gets incremented, if
3905 * the DROP_EN but it set (in the SRRCTL register for that
3906 * queue). If DROP_EN bit is NOT set, then the some what
3907 * equivalent count is stored in RNBC (not per queue basis).
3908 * Also note the drop count is due to lack of available
3911 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3912 rqdpc_tmp
= rd32(E1000_RQDPC(i
)) & 0xFFF;
3913 adapter
->rx_ring
[i
].rx_stats
.drops
+= rqdpc_tmp
;
3914 rqdpc_total
+= adapter
->rx_ring
[i
].rx_stats
.drops
;
3916 netdev
->stats
.rx_fifo_errors
= rqdpc_total
;
3919 /* Note RNBC (Receive No Buffers Count) is an not an exact
3920 * drop count as the hardware FIFO might save the day. Thats
3921 * one of the reason for saving it in rx_fifo_errors, as its
3922 * potentially not a true drop.
3924 netdev
->stats
.rx_fifo_errors
+= adapter
->stats
.rnbc
;
3926 /* RLEC on some newer hardware can be incorrect so build
3927 * our own version based on RUC and ROC */
3928 netdev
->stats
.rx_errors
= adapter
->stats
.rxerrc
+
3929 adapter
->stats
.crcerrs
+ adapter
->stats
.algnerrc
+
3930 adapter
->stats
.ruc
+ adapter
->stats
.roc
+
3931 adapter
->stats
.cexterr
;
3932 netdev
->stats
.rx_length_errors
= adapter
->stats
.ruc
+
3934 netdev
->stats
.rx_crc_errors
= adapter
->stats
.crcerrs
;
3935 netdev
->stats
.rx_frame_errors
= adapter
->stats
.algnerrc
;
3936 netdev
->stats
.rx_missed_errors
= adapter
->stats
.mpc
;
3939 netdev
->stats
.tx_errors
= adapter
->stats
.ecol
+
3940 adapter
->stats
.latecol
;
3941 netdev
->stats
.tx_aborted_errors
= adapter
->stats
.ecol
;
3942 netdev
->stats
.tx_window_errors
= adapter
->stats
.latecol
;
3943 netdev
->stats
.tx_carrier_errors
= adapter
->stats
.tncrs
;
3945 /* Tx Dropped needs to be maintained elsewhere */
3948 if (hw
->phy
.media_type
== e1000_media_type_copper
) {
3949 if ((adapter
->link_speed
== SPEED_1000
) &&
3950 (!igb_read_phy_reg(hw
, PHY_1000T_STATUS
, &phy_tmp
))) {
3951 phy_tmp
&= PHY_IDLE_ERROR_COUNT_MASK
;
3952 adapter
->phy_stats
.idle_errors
+= phy_tmp
;
3956 /* Management Stats */
3957 adapter
->stats
.mgptc
+= rd32(E1000_MGTPTC
);
3958 adapter
->stats
.mgprc
+= rd32(E1000_MGTPRC
);
3959 adapter
->stats
.mgpdc
+= rd32(E1000_MGTPDC
);
3962 static irqreturn_t
igb_msix_other(int irq
, void *data
)
3964 struct igb_adapter
*adapter
= data
;
3965 struct e1000_hw
*hw
= &adapter
->hw
;
3966 u32 icr
= rd32(E1000_ICR
);
3967 /* reading ICR causes bit 31 of EICR to be cleared */
3969 if (icr
& E1000_ICR_DOUTSYNC
) {
3970 /* HW is reporting DMA is out of sync */
3971 adapter
->stats
.doosync
++;
3974 /* Check for a mailbox event */
3975 if (icr
& E1000_ICR_VMMB
)
3976 igb_msg_task(adapter
);
3978 if (icr
& E1000_ICR_LSC
) {
3979 hw
->mac
.get_link_status
= 1;
3980 /* guard against interrupt when we're going down */
3981 if (!test_bit(__IGB_DOWN
, &adapter
->state
))
3982 mod_timer(&adapter
->watchdog_timer
, jiffies
+ 1);
3985 wr32(E1000_IMS
, E1000_IMS_LSC
| E1000_IMS_DOUTSYNC
| E1000_IMS_VMMB
);
3986 wr32(E1000_EIMS
, adapter
->eims_other
);
3991 static void igb_write_itr(struct igb_q_vector
*q_vector
)
3993 u32 itr_val
= q_vector
->itr_val
& 0x7FFC;
3995 if (!q_vector
->set_itr
)
4001 if (q_vector
->itr_shift
)
4002 itr_val
|= itr_val
<< q_vector
->itr_shift
;
4004 itr_val
|= 0x8000000;
4006 writel(itr_val
, q_vector
->itr_register
);
4007 q_vector
->set_itr
= 0;
4010 static irqreturn_t
igb_msix_ring(int irq
, void *data
)
4012 struct igb_q_vector
*q_vector
= data
;
4014 /* Write the ITR value calculated from the previous interrupt. */
4015 igb_write_itr(q_vector
);
4017 napi_schedule(&q_vector
->napi
);
4022 #ifdef CONFIG_IGB_DCA
4023 static void igb_update_dca(struct igb_q_vector
*q_vector
)
4025 struct igb_adapter
*adapter
= q_vector
->adapter
;
4026 struct e1000_hw
*hw
= &adapter
->hw
;
4027 int cpu
= get_cpu();
4029 if (q_vector
->cpu
== cpu
)
4032 if (q_vector
->tx_ring
) {
4033 int q
= q_vector
->tx_ring
->reg_idx
;
4034 u32 dca_txctrl
= rd32(E1000_DCA_TXCTRL(q
));
4035 if (hw
->mac
.type
== e1000_82575
) {
4036 dca_txctrl
&= ~E1000_DCA_TXCTRL_CPUID_MASK
;
4037 dca_txctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
4039 dca_txctrl
&= ~E1000_DCA_TXCTRL_CPUID_MASK_82576
;
4040 dca_txctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
4041 E1000_DCA_TXCTRL_CPUID_SHIFT
;
4043 dca_txctrl
|= E1000_DCA_TXCTRL_DESC_DCA_EN
;
4044 wr32(E1000_DCA_TXCTRL(q
), dca_txctrl
);
4046 if (q_vector
->rx_ring
) {
4047 int q
= q_vector
->rx_ring
->reg_idx
;
4048 u32 dca_rxctrl
= rd32(E1000_DCA_RXCTRL(q
));
4049 if (hw
->mac
.type
== e1000_82575
) {
4050 dca_rxctrl
&= ~E1000_DCA_RXCTRL_CPUID_MASK
;
4051 dca_rxctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
4053 dca_rxctrl
&= ~E1000_DCA_RXCTRL_CPUID_MASK_82576
;
4054 dca_rxctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
4055 E1000_DCA_RXCTRL_CPUID_SHIFT
;
4057 dca_rxctrl
|= E1000_DCA_RXCTRL_DESC_DCA_EN
;
4058 dca_rxctrl
|= E1000_DCA_RXCTRL_HEAD_DCA_EN
;
4059 dca_rxctrl
|= E1000_DCA_RXCTRL_DATA_DCA_EN
;
4060 wr32(E1000_DCA_RXCTRL(q
), dca_rxctrl
);
4062 q_vector
->cpu
= cpu
;
4067 static void igb_setup_dca(struct igb_adapter
*adapter
)
4069 struct e1000_hw
*hw
= &adapter
->hw
;
4072 if (!(adapter
->flags
& IGB_FLAG_DCA_ENABLED
))
4075 /* Always use CB2 mode, difference is masked in the CB driver. */
4076 wr32(E1000_DCA_CTRL
, E1000_DCA_CTRL_DCA_MODE_CB2
);
4078 for (i
= 0; i
< adapter
->num_q_vectors
; i
++) {
4079 struct igb_q_vector
*q_vector
= adapter
->q_vector
[i
];
4081 igb_update_dca(q_vector
);
4085 static int __igb_notify_dca(struct device
*dev
, void *data
)
4087 struct net_device
*netdev
= dev_get_drvdata(dev
);
4088 struct igb_adapter
*adapter
= netdev_priv(netdev
);
4089 struct e1000_hw
*hw
= &adapter
->hw
;
4090 unsigned long event
= *(unsigned long *)data
;
4093 case DCA_PROVIDER_ADD
:
4094 /* if already enabled, don't do it again */
4095 if (adapter
->flags
& IGB_FLAG_DCA_ENABLED
)
4097 /* Always use CB2 mode, difference is masked
4098 * in the CB driver. */
4099 wr32(E1000_DCA_CTRL
, E1000_DCA_CTRL_DCA_MODE_CB2
);
4100 if (dca_add_requester(dev
) == 0) {
4101 adapter
->flags
|= IGB_FLAG_DCA_ENABLED
;
4102 dev_info(&adapter
->pdev
->dev
, "DCA enabled\n");
4103 igb_setup_dca(adapter
);
4106 /* Fall Through since DCA is disabled. */
4107 case DCA_PROVIDER_REMOVE
:
4108 if (adapter
->flags
& IGB_FLAG_DCA_ENABLED
) {
4109 /* without this a class_device is left
4110 * hanging around in the sysfs model */
4111 dca_remove_requester(dev
);
4112 dev_info(&adapter
->pdev
->dev
, "DCA disabled\n");
4113 adapter
->flags
&= ~IGB_FLAG_DCA_ENABLED
;
4114 wr32(E1000_DCA_CTRL
, E1000_DCA_CTRL_DCA_MODE_DISABLE
);
4122 static int igb_notify_dca(struct notifier_block
*nb
, unsigned long event
,
4127 ret_val
= driver_for_each_device(&igb_driver
.driver
, NULL
, &event
,
4130 return ret_val
? NOTIFY_BAD
: NOTIFY_DONE
;
4132 #endif /* CONFIG_IGB_DCA */
4134 static void igb_ping_all_vfs(struct igb_adapter
*adapter
)
4136 struct e1000_hw
*hw
= &adapter
->hw
;
4140 for (i
= 0 ; i
< adapter
->vfs_allocated_count
; i
++) {
4141 ping
= E1000_PF_CONTROL_MSG
;
4142 if (adapter
->vf_data
[i
].clear_to_send
)
4143 ping
|= E1000_VT_MSGTYPE_CTS
;
4144 igb_write_mbx(hw
, &ping
, 1, i
);
4148 static int igb_set_vf_multicasts(struct igb_adapter
*adapter
,
4149 u32
*msgbuf
, u32 vf
)
4151 int n
= (msgbuf
[0] & E1000_VT_MSGINFO_MASK
) >> E1000_VT_MSGINFO_SHIFT
;
4152 u16
*hash_list
= (u16
*)&msgbuf
[1];
4153 struct vf_data_storage
*vf_data
= &adapter
->vf_data
[vf
];
4156 /* only up to 30 hash values supported */
4160 /* salt away the number of multi cast addresses assigned
4161 * to this VF for later use to restore when the PF multi cast
4164 vf_data
->num_vf_mc_hashes
= n
;
4166 /* VFs are limited to using the MTA hash table for their multicast
4168 for (i
= 0; i
< n
; i
++)
4169 vf_data
->vf_mc_hashes
[i
] = hash_list
[i
];
4171 /* Flush and reset the mta with the new values */
4172 igb_set_rx_mode(adapter
->netdev
);
4177 static void igb_restore_vf_multicasts(struct igb_adapter
*adapter
)
4179 struct e1000_hw
*hw
= &adapter
->hw
;
4180 struct vf_data_storage
*vf_data
;
4183 for (i
= 0; i
< adapter
->vfs_allocated_count
; i
++) {
4184 vf_data
= &adapter
->vf_data
[i
];
4185 for (j
= 0; j
< vf_data
->num_vf_mc_hashes
; j
++)
4186 igb_mta_set(hw
, vf_data
->vf_mc_hashes
[j
]);
4190 static void igb_clear_vf_vfta(struct igb_adapter
*adapter
, u32 vf
)
4192 struct e1000_hw
*hw
= &adapter
->hw
;
4193 u32 pool_mask
, reg
, vid
;
4196 pool_mask
= 1 << (E1000_VLVF_POOLSEL_SHIFT
+ vf
);
4198 /* Find the vlan filter for this id */
4199 for (i
= 0; i
< E1000_VLVF_ARRAY_SIZE
; i
++) {
4200 reg
= rd32(E1000_VLVF(i
));
4202 /* remove the vf from the pool */
4205 /* if pool is empty then remove entry from vfta */
4206 if (!(reg
& E1000_VLVF_POOLSEL_MASK
) &&
4207 (reg
& E1000_VLVF_VLANID_ENABLE
)) {
4209 vid
= reg
& E1000_VLVF_VLANID_MASK
;
4210 igb_vfta_set(hw
, vid
, false);
4213 wr32(E1000_VLVF(i
), reg
);
4216 adapter
->vf_data
[vf
].vlans_enabled
= 0;
4219 static s32
igb_vlvf_set(struct igb_adapter
*adapter
, u32 vid
, bool add
, u32 vf
)
4221 struct e1000_hw
*hw
= &adapter
->hw
;
4224 /* It is an error to call this function when VFs are not enabled */
4225 if (!adapter
->vfs_allocated_count
)
4228 /* Find the vlan filter for this id */
4229 for (i
= 0; i
< E1000_VLVF_ARRAY_SIZE
; i
++) {
4230 reg
= rd32(E1000_VLVF(i
));
4231 if ((reg
& E1000_VLVF_VLANID_ENABLE
) &&
4232 vid
== (reg
& E1000_VLVF_VLANID_MASK
))
4237 if (i
== E1000_VLVF_ARRAY_SIZE
) {
4238 /* Did not find a matching VLAN ID entry that was
4239 * enabled. Search for a free filter entry, i.e.
4240 * one without the enable bit set
4242 for (i
= 0; i
< E1000_VLVF_ARRAY_SIZE
; i
++) {
4243 reg
= rd32(E1000_VLVF(i
));
4244 if (!(reg
& E1000_VLVF_VLANID_ENABLE
))
4248 if (i
< E1000_VLVF_ARRAY_SIZE
) {
4249 /* Found an enabled/available entry */
4250 reg
|= 1 << (E1000_VLVF_POOLSEL_SHIFT
+ vf
);
4252 /* if !enabled we need to set this up in vfta */
4253 if (!(reg
& E1000_VLVF_VLANID_ENABLE
)) {
4254 /* add VID to filter table, if bit already set
4255 * PF must have added it outside of table */
4256 if (igb_vfta_set(hw
, vid
, true))
4257 reg
|= 1 << (E1000_VLVF_POOLSEL_SHIFT
+
4258 adapter
->vfs_allocated_count
);
4259 reg
|= E1000_VLVF_VLANID_ENABLE
;
4261 reg
&= ~E1000_VLVF_VLANID_MASK
;
4264 wr32(E1000_VLVF(i
), reg
);
4266 /* do not modify RLPML for PF devices */
4267 if (vf
>= adapter
->vfs_allocated_count
)
4270 if (!adapter
->vf_data
[vf
].vlans_enabled
) {
4272 reg
= rd32(E1000_VMOLR(vf
));
4273 size
= reg
& E1000_VMOLR_RLPML_MASK
;
4275 reg
&= ~E1000_VMOLR_RLPML_MASK
;
4277 wr32(E1000_VMOLR(vf
), reg
);
4279 adapter
->vf_data
[vf
].vlans_enabled
++;
4284 if (i
< E1000_VLVF_ARRAY_SIZE
) {
4285 /* remove vf from the pool */
4286 reg
&= ~(1 << (E1000_VLVF_POOLSEL_SHIFT
+ vf
));
4287 /* if pool is empty then remove entry from vfta */
4288 if (!(reg
& E1000_VLVF_POOLSEL_MASK
)) {
4290 igb_vfta_set(hw
, vid
, false);
4292 wr32(E1000_VLVF(i
), reg
);
4294 /* do not modify RLPML for PF devices */
4295 if (vf
>= adapter
->vfs_allocated_count
)
4298 adapter
->vf_data
[vf
].vlans_enabled
--;
4299 if (!adapter
->vf_data
[vf
].vlans_enabled
) {
4301 reg
= rd32(E1000_VMOLR(vf
));
4302 size
= reg
& E1000_VMOLR_RLPML_MASK
;
4304 reg
&= ~E1000_VMOLR_RLPML_MASK
;
4306 wr32(E1000_VMOLR(vf
), reg
);
4314 static int igb_set_vf_vlan(struct igb_adapter
*adapter
, u32
*msgbuf
, u32 vf
)
4316 int add
= (msgbuf
[0] & E1000_VT_MSGINFO_MASK
) >> E1000_VT_MSGINFO_SHIFT
;
4317 int vid
= (msgbuf
[1] & E1000_VLVF_VLANID_MASK
);
4319 return igb_vlvf_set(adapter
, vid
, add
, vf
);
4322 static inline void igb_vf_reset_event(struct igb_adapter
*adapter
, u32 vf
)
4324 struct e1000_hw
*hw
= &adapter
->hw
;
4326 /* disable mailbox functionality for vf */
4327 adapter
->vf_data
[vf
].clear_to_send
= false;
4329 /* reset offloads to defaults */
4330 igb_set_vmolr(hw
, vf
);
4332 /* reset vlans for device */
4333 igb_clear_vf_vfta(adapter
, vf
);
4335 /* reset multicast table array for vf */
4336 adapter
->vf_data
[vf
].num_vf_mc_hashes
= 0;
4338 /* Flush and reset the mta with the new values */
4339 igb_set_rx_mode(adapter
->netdev
);
4342 static inline void igb_vf_reset_msg(struct igb_adapter
*adapter
, u32 vf
)
4344 struct e1000_hw
*hw
= &adapter
->hw
;
4345 unsigned char *vf_mac
= adapter
->vf_data
[vf
].vf_mac_addresses
;
4346 int rar_entry
= hw
->mac
.rar_entry_count
- (vf
+ 1);
4348 u8
*addr
= (u8
*)(&msgbuf
[1]);
4350 /* process all the same items cleared in a function level reset */
4351 igb_vf_reset_event(adapter
, vf
);
4353 /* set vf mac address */
4354 igb_rar_set_qsel(adapter
, vf_mac
, rar_entry
, vf
);
4356 /* enable transmit and receive for vf */
4357 reg
= rd32(E1000_VFTE
);
4358 wr32(E1000_VFTE
, reg
| (1 << vf
));
4359 reg
= rd32(E1000_VFRE
);
4360 wr32(E1000_VFRE
, reg
| (1 << vf
));
4362 /* enable mailbox functionality for vf */
4363 adapter
->vf_data
[vf
].clear_to_send
= true;
4365 /* reply to reset with ack and vf mac address */
4366 msgbuf
[0] = E1000_VF_RESET
| E1000_VT_MSGTYPE_ACK
;
4367 memcpy(addr
, vf_mac
, 6);
4368 igb_write_mbx(hw
, msgbuf
, 3, vf
);
4371 static int igb_set_vf_mac_addr(struct igb_adapter
*adapter
, u32
*msg
, int vf
)
4373 unsigned char *addr
= (char *)&msg
[1];
4376 if (is_valid_ether_addr(addr
))
4377 err
= igb_set_vf_mac(adapter
, vf
, addr
);
4383 static void igb_rcv_ack_from_vf(struct igb_adapter
*adapter
, u32 vf
)
4385 struct e1000_hw
*hw
= &adapter
->hw
;
4386 u32 msg
= E1000_VT_MSGTYPE_NACK
;
4388 /* if device isn't clear to send it shouldn't be reading either */
4389 if (!adapter
->vf_data
[vf
].clear_to_send
)
4390 igb_write_mbx(hw
, &msg
, 1, vf
);
4394 static void igb_msg_task(struct igb_adapter
*adapter
)
4396 struct e1000_hw
*hw
= &adapter
->hw
;
4399 for (vf
= 0; vf
< adapter
->vfs_allocated_count
; vf
++) {
4400 /* process any reset requests */
4401 if (!igb_check_for_rst(hw
, vf
)) {
4402 adapter
->vf_data
[vf
].clear_to_send
= false;
4403 igb_vf_reset_event(adapter
, vf
);
4406 /* process any messages pending */
4407 if (!igb_check_for_msg(hw
, vf
))
4408 igb_rcv_msg_from_vf(adapter
, vf
);
4410 /* process any acks */
4411 if (!igb_check_for_ack(hw
, vf
))
4412 igb_rcv_ack_from_vf(adapter
, vf
);
4417 static int igb_rcv_msg_from_vf(struct igb_adapter
*adapter
, u32 vf
)
4419 u32 mbx_size
= E1000_VFMAILBOX_SIZE
;
4420 u32 msgbuf
[mbx_size
];
4421 struct e1000_hw
*hw
= &adapter
->hw
;
4424 retval
= igb_read_mbx(hw
, msgbuf
, mbx_size
, vf
);
4427 dev_err(&adapter
->pdev
->dev
,
4428 "Error receiving message from VF\n");
4430 /* this is a message we already processed, do nothing */
4431 if (msgbuf
[0] & (E1000_VT_MSGTYPE_ACK
| E1000_VT_MSGTYPE_NACK
))
4435 * until the vf completes a reset it should not be
4436 * allowed to start any configuration.
4439 if (msgbuf
[0] == E1000_VF_RESET
) {
4440 igb_vf_reset_msg(adapter
, vf
);
4445 if (!adapter
->vf_data
[vf
].clear_to_send
) {
4446 msgbuf
[0] |= E1000_VT_MSGTYPE_NACK
;
4447 igb_write_mbx(hw
, msgbuf
, 1, vf
);
4451 switch ((msgbuf
[0] & 0xFFFF)) {
4452 case E1000_VF_SET_MAC_ADDR
:
4453 retval
= igb_set_vf_mac_addr(adapter
, msgbuf
, vf
);
4455 case E1000_VF_SET_MULTICAST
:
4456 retval
= igb_set_vf_multicasts(adapter
, msgbuf
, vf
);
4458 case E1000_VF_SET_LPE
:
4459 retval
= igb_set_vf_rlpml(adapter
, msgbuf
[1], vf
);
4461 case E1000_VF_SET_VLAN
:
4462 retval
= igb_set_vf_vlan(adapter
, msgbuf
, vf
);
4465 dev_err(&adapter
->pdev
->dev
, "Unhandled Msg %08x\n", msgbuf
[0]);
4470 /* notify the VF of the results of what it sent us */
4472 msgbuf
[0] |= E1000_VT_MSGTYPE_NACK
;
4474 msgbuf
[0] |= E1000_VT_MSGTYPE_ACK
;
4476 msgbuf
[0] |= E1000_VT_MSGTYPE_CTS
;
4478 igb_write_mbx(hw
, msgbuf
, 1, vf
);
4484 * igb_set_uta - Set unicast filter table address
4485 * @adapter: board private structure
4487 * The unicast table address is a register array of 32-bit registers.
4488 * The table is meant to be used in a way similar to how the MTA is used
4489 * however due to certain limitations in the hardware it is necessary to
4490 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscous
4491 * enable bit to allow vlan tag stripping when promiscous mode is enabled
4493 static void igb_set_uta(struct igb_adapter
*adapter
)
4495 struct e1000_hw
*hw
= &adapter
->hw
;
4498 /* The UTA table only exists on 82576 hardware and newer */
4499 if (hw
->mac
.type
< e1000_82576
)
4502 /* we only need to do this if VMDq is enabled */
4503 if (!adapter
->vfs_allocated_count
)
4506 for (i
= 0; i
< hw
->mac
.uta_reg_count
; i
++)
4507 array_wr32(E1000_UTA
, i
, ~0);
4511 * igb_intr_msi - Interrupt Handler
4512 * @irq: interrupt number
4513 * @data: pointer to a network interface device structure
4515 static irqreturn_t
igb_intr_msi(int irq
, void *data
)
4517 struct igb_adapter
*adapter
= data
;
4518 struct igb_q_vector
*q_vector
= adapter
->q_vector
[0];
4519 struct e1000_hw
*hw
= &adapter
->hw
;
4520 /* read ICR disables interrupts using IAM */
4521 u32 icr
= rd32(E1000_ICR
);
4523 igb_write_itr(q_vector
);
4525 if (icr
& E1000_ICR_DOUTSYNC
) {
4526 /* HW is reporting DMA is out of sync */
4527 adapter
->stats
.doosync
++;
4530 if (icr
& (E1000_ICR_RXSEQ
| E1000_ICR_LSC
)) {
4531 hw
->mac
.get_link_status
= 1;
4532 if (!test_bit(__IGB_DOWN
, &adapter
->state
))
4533 mod_timer(&adapter
->watchdog_timer
, jiffies
+ 1);
4536 napi_schedule(&q_vector
->napi
);
4542 * igb_intr - Legacy Interrupt Handler
4543 * @irq: interrupt number
4544 * @data: pointer to a network interface device structure
4546 static irqreturn_t
igb_intr(int irq
, void *data
)
4548 struct igb_adapter
*adapter
= data
;
4549 struct igb_q_vector
*q_vector
= adapter
->q_vector
[0];
4550 struct e1000_hw
*hw
= &adapter
->hw
;
4551 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
4552 * need for the IMC write */
4553 u32 icr
= rd32(E1000_ICR
);
4555 return IRQ_NONE
; /* Not our interrupt */
4557 igb_write_itr(q_vector
);
4559 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4560 * not set, then the adapter didn't send an interrupt */
4561 if (!(icr
& E1000_ICR_INT_ASSERTED
))
4564 if (icr
& E1000_ICR_DOUTSYNC
) {
4565 /* HW is reporting DMA is out of sync */
4566 adapter
->stats
.doosync
++;
4569 if (icr
& (E1000_ICR_RXSEQ
| E1000_ICR_LSC
)) {
4570 hw
->mac
.get_link_status
= 1;
4571 /* guard against interrupt when we're going down */
4572 if (!test_bit(__IGB_DOWN
, &adapter
->state
))
4573 mod_timer(&adapter
->watchdog_timer
, jiffies
+ 1);
4576 napi_schedule(&q_vector
->napi
);
4581 static inline void igb_ring_irq_enable(struct igb_q_vector
*q_vector
)
4583 struct igb_adapter
*adapter
= q_vector
->adapter
;
4584 struct e1000_hw
*hw
= &adapter
->hw
;
4586 if (adapter
->itr_setting
& 3) {
4587 if (!adapter
->msix_entries
)
4588 igb_set_itr(adapter
);
4590 igb_update_ring_itr(q_vector
);
4593 if (!test_bit(__IGB_DOWN
, &adapter
->state
)) {
4594 if (adapter
->msix_entries
)
4595 wr32(E1000_EIMS
, q_vector
->eims_value
);
4597 igb_irq_enable(adapter
);
4602 * igb_poll - NAPI Rx polling callback
4603 * @napi: napi polling structure
4604 * @budget: count of how many packets we should handle
4606 static int igb_poll(struct napi_struct
*napi
, int budget
)
4608 struct igb_q_vector
*q_vector
= container_of(napi
,
4609 struct igb_q_vector
,
4611 int tx_clean_complete
= 1, work_done
= 0;
4613 #ifdef CONFIG_IGB_DCA
4614 if (q_vector
->adapter
->flags
& IGB_FLAG_DCA_ENABLED
)
4615 igb_update_dca(q_vector
);
4617 if (q_vector
->tx_ring
)
4618 tx_clean_complete
= igb_clean_tx_irq(q_vector
);
4620 if (q_vector
->rx_ring
)
4621 igb_clean_rx_irq_adv(q_vector
, &work_done
, budget
);
4623 if (!tx_clean_complete
)
4626 /* If not enough Rx work done, exit the polling mode */
4627 if (work_done
< budget
) {
4628 napi_complete(napi
);
4629 igb_ring_irq_enable(q_vector
);
4636 * igb_hwtstamp - utility function which checks for TX time stamp
4637 * @adapter: board private structure
4638 * @skb: packet that was just sent
4640 * If we were asked to do hardware stamping and such a time stamp is
4641 * available, then it must have been for this skb here because we only
4642 * allow only one such packet into the queue.
4644 static void igb_tx_hwtstamp(struct igb_adapter
*adapter
, struct sk_buff
*skb
)
4646 union skb_shared_tx
*shtx
= skb_tx(skb
);
4647 struct e1000_hw
*hw
= &adapter
->hw
;
4649 if (unlikely(shtx
->hardware
)) {
4650 u32 valid
= rd32(E1000_TSYNCTXCTL
) & E1000_TSYNCTXCTL_VALID
;
4652 u64 regval
= rd32(E1000_TXSTMPL
);
4654 struct skb_shared_hwtstamps shhwtstamps
;
4656 memset(&shhwtstamps
, 0, sizeof(shhwtstamps
));
4657 regval
|= (u64
)rd32(E1000_TXSTMPH
) << 32;
4658 ns
= timecounter_cyc2time(&adapter
->clock
,
4660 timecompare_update(&adapter
->compare
, ns
);
4661 shhwtstamps
.hwtstamp
= ns_to_ktime(ns
);
4662 shhwtstamps
.syststamp
=
4663 timecompare_transform(&adapter
->compare
, ns
);
4664 skb_tstamp_tx(skb
, &shhwtstamps
);
4670 * igb_clean_tx_irq - Reclaim resources after transmit completes
4671 * @q_vector: pointer to q_vector containing needed info
4672 * returns true if ring is completely cleaned
4674 static bool igb_clean_tx_irq(struct igb_q_vector
*q_vector
)
4676 struct igb_adapter
*adapter
= q_vector
->adapter
;
4677 struct igb_ring
*tx_ring
= q_vector
->tx_ring
;
4678 struct net_device
*netdev
= adapter
->netdev
;
4679 struct e1000_hw
*hw
= &adapter
->hw
;
4680 struct igb_buffer
*buffer_info
;
4681 struct sk_buff
*skb
;
4682 union e1000_adv_tx_desc
*tx_desc
, *eop_desc
;
4683 unsigned int total_bytes
= 0, total_packets
= 0;
4684 unsigned int i
, eop
, count
= 0;
4685 bool cleaned
= false;
4687 i
= tx_ring
->next_to_clean
;
4688 eop
= tx_ring
->buffer_info
[i
].next_to_watch
;
4689 eop_desc
= E1000_TX_DESC_ADV(*tx_ring
, eop
);
4691 while ((eop_desc
->wb
.status
& cpu_to_le32(E1000_TXD_STAT_DD
)) &&
4692 (count
< tx_ring
->count
)) {
4693 for (cleaned
= false; !cleaned
; count
++) {
4694 tx_desc
= E1000_TX_DESC_ADV(*tx_ring
, i
);
4695 buffer_info
= &tx_ring
->buffer_info
[i
];
4696 cleaned
= (i
== eop
);
4697 skb
= buffer_info
->skb
;
4700 unsigned int segs
, bytecount
;
4701 /* gso_segs is currently only valid for tcp */
4702 segs
= skb_shinfo(skb
)->gso_segs
?: 1;
4703 /* multiply data chunks by size of headers */
4704 bytecount
= ((segs
- 1) * skb_headlen(skb
)) +
4706 total_packets
+= segs
;
4707 total_bytes
+= bytecount
;
4709 igb_tx_hwtstamp(adapter
, skb
);
4712 igb_unmap_and_free_tx_resource(adapter
, buffer_info
);
4713 tx_desc
->wb
.status
= 0;
4716 if (i
== tx_ring
->count
)
4719 eop
= tx_ring
->buffer_info
[i
].next_to_watch
;
4720 eop_desc
= E1000_TX_DESC_ADV(*tx_ring
, eop
);
4723 tx_ring
->next_to_clean
= i
;
4725 if (unlikely(count
&&
4726 netif_carrier_ok(netdev
) &&
4727 igb_desc_unused(tx_ring
) >= IGB_TX_QUEUE_WAKE
)) {
4728 /* Make sure that anybody stopping the queue after this
4729 * sees the new next_to_clean.
4732 if (__netif_subqueue_stopped(netdev
, tx_ring
->queue_index
) &&
4733 !(test_bit(__IGB_DOWN
, &adapter
->state
))) {
4734 netif_wake_subqueue(netdev
, tx_ring
->queue_index
);
4735 ++adapter
->restart_queue
;
4739 if (tx_ring
->detect_tx_hung
) {
4740 /* Detect a transmit hang in hardware, this serializes the
4741 * check with the clearing of time_stamp and movement of i */
4742 tx_ring
->detect_tx_hung
= false;
4743 if (tx_ring
->buffer_info
[i
].time_stamp
&&
4744 time_after(jiffies
, tx_ring
->buffer_info
[i
].time_stamp
+
4745 (adapter
->tx_timeout_factor
* HZ
))
4746 && !(rd32(E1000_STATUS
) &
4747 E1000_STATUS_TXOFF
)) {
4749 /* detected Tx unit hang */
4750 dev_err(&adapter
->pdev
->dev
,
4751 "Detected Tx Unit Hang\n"
4755 " next_to_use <%x>\n"
4756 " next_to_clean <%x>\n"
4757 "buffer_info[next_to_clean]\n"
4758 " time_stamp <%lx>\n"
4759 " next_to_watch <%x>\n"
4761 " desc.status <%x>\n",
4762 tx_ring
->queue_index
,
4763 readl(adapter
->hw
.hw_addr
+ tx_ring
->head
),
4764 readl(adapter
->hw
.hw_addr
+ tx_ring
->tail
),
4765 tx_ring
->next_to_use
,
4766 tx_ring
->next_to_clean
,
4767 tx_ring
->buffer_info
[i
].time_stamp
,
4770 eop_desc
->wb
.status
);
4771 netif_stop_subqueue(netdev
, tx_ring
->queue_index
);
4774 tx_ring
->total_bytes
+= total_bytes
;
4775 tx_ring
->total_packets
+= total_packets
;
4776 tx_ring
->tx_stats
.bytes
+= total_bytes
;
4777 tx_ring
->tx_stats
.packets
+= total_packets
;
4778 netdev
->stats
.tx_bytes
+= total_bytes
;
4779 netdev
->stats
.tx_packets
+= total_packets
;
4780 return (count
< tx_ring
->count
);
4784 * igb_receive_skb - helper function to handle rx indications
4785 * @q_vector: structure containing interrupt and ring information
4786 * @skb: packet to send up
4787 * @vlan_tag: vlan tag for packet
4789 static void igb_receive_skb(struct igb_q_vector
*q_vector
,
4790 struct sk_buff
*skb
,
4793 struct igb_adapter
*adapter
= q_vector
->adapter
;
4796 vlan_gro_receive(&q_vector
->napi
, adapter
->vlgrp
,
4799 napi_gro_receive(&q_vector
->napi
, skb
);
4802 static inline void igb_rx_checksum_adv(struct igb_adapter
*adapter
,
4803 u32 status_err
, struct sk_buff
*skb
)
4805 skb
->ip_summed
= CHECKSUM_NONE
;
4807 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
4808 if ((status_err
& E1000_RXD_STAT_IXSM
) ||
4809 (adapter
->flags
& IGB_FLAG_RX_CSUM_DISABLED
))
4811 /* TCP/UDP checksum error bit is set */
4813 (E1000_RXDEXT_STATERR_TCPE
| E1000_RXDEXT_STATERR_IPE
)) {
4815 * work around errata with sctp packets where the TCPE aka
4816 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
4817 * packets, (aka let the stack check the crc32c)
4819 if (!((adapter
->hw
.mac
.type
== e1000_82576
) &&
4821 adapter
->hw_csum_err
++;
4822 /* let the stack verify checksum errors */
4825 /* It must be a TCP or UDP packet with a valid checksum */
4826 if (status_err
& (E1000_RXD_STAT_TCPCS
| E1000_RXD_STAT_UDPCS
))
4827 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
4829 dev_dbg(&adapter
->pdev
->dev
, "cksum success: bits %08X\n", status_err
);
4830 adapter
->hw_csum_good
++;
4833 static inline u16
igb_get_hlen(struct igb_adapter
*adapter
,
4834 union e1000_adv_rx_desc
*rx_desc
)
4836 /* HW will not DMA in data larger than the given buffer, even if it
4837 * parses the (NFS, of course) header to be larger. In that case, it
4838 * fills the header buffer and spills the rest into the page.
4840 u16 hlen
= (le16_to_cpu(rx_desc
->wb
.lower
.lo_dword
.hdr_info
) &
4841 E1000_RXDADV_HDRBUFLEN_MASK
) >> E1000_RXDADV_HDRBUFLEN_SHIFT
;
4842 if (hlen
> adapter
->rx_ps_hdr_size
)
4843 hlen
= adapter
->rx_ps_hdr_size
;
4847 static bool igb_clean_rx_irq_adv(struct igb_q_vector
*q_vector
,
4848 int *work_done
, int budget
)
4850 struct igb_adapter
*adapter
= q_vector
->adapter
;
4851 struct net_device
*netdev
= adapter
->netdev
;
4852 struct igb_ring
*rx_ring
= q_vector
->rx_ring
;
4853 struct e1000_hw
*hw
= &adapter
->hw
;
4854 struct pci_dev
*pdev
= adapter
->pdev
;
4855 union e1000_adv_rx_desc
*rx_desc
, *next_rxd
;
4856 struct igb_buffer
*buffer_info
, *next_buffer
;
4857 struct sk_buff
*skb
;
4858 bool cleaned
= false;
4859 int cleaned_count
= 0;
4860 unsigned int total_bytes
= 0, total_packets
= 0;
4866 i
= rx_ring
->next_to_clean
;
4867 buffer_info
= &rx_ring
->buffer_info
[i
];
4868 rx_desc
= E1000_RX_DESC_ADV(*rx_ring
, i
);
4869 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
4871 while (staterr
& E1000_RXD_STAT_DD
) {
4872 if (*work_done
>= budget
)
4876 skb
= buffer_info
->skb
;
4877 prefetch(skb
->data
- NET_IP_ALIGN
);
4878 buffer_info
->skb
= NULL
;
4881 if (i
== rx_ring
->count
)
4883 next_rxd
= E1000_RX_DESC_ADV(*rx_ring
, i
);
4885 next_buffer
= &rx_ring
->buffer_info
[i
];
4887 length
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
4891 /* this is the fast path for the non-packet split case */
4892 if (!adapter
->rx_ps_hdr_size
) {
4893 pci_unmap_single(pdev
, buffer_info
->dma
,
4894 adapter
->rx_buffer_len
,
4895 PCI_DMA_FROMDEVICE
);
4896 buffer_info
->dma
= 0;
4897 skb_put(skb
, length
);
4901 if (buffer_info
->dma
) {
4902 u16 hlen
= igb_get_hlen(adapter
, rx_desc
);
4903 pci_unmap_single(pdev
, buffer_info
->dma
,
4904 adapter
->rx_ps_hdr_size
,
4905 PCI_DMA_FROMDEVICE
);
4906 buffer_info
->dma
= 0;
4911 pci_unmap_page(pdev
, buffer_info
->page_dma
,
4912 PAGE_SIZE
/ 2, PCI_DMA_FROMDEVICE
);
4913 buffer_info
->page_dma
= 0;
4915 skb_fill_page_desc(skb
, skb_shinfo(skb
)->nr_frags
++,
4917 buffer_info
->page_offset
,
4920 if ((adapter
->rx_buffer_len
> (PAGE_SIZE
/ 2)) ||
4921 (page_count(buffer_info
->page
) != 1))
4922 buffer_info
->page
= NULL
;
4924 get_page(buffer_info
->page
);
4927 skb
->data_len
+= length
;
4929 skb
->truesize
+= length
;
4932 if (!(staterr
& E1000_RXD_STAT_EOP
)) {
4933 buffer_info
->skb
= next_buffer
->skb
;
4934 buffer_info
->dma
= next_buffer
->dma
;
4935 next_buffer
->skb
= skb
;
4936 next_buffer
->dma
= 0;
4941 * If this bit is set, then the RX registers contain
4942 * the time stamp. No other packet will be time
4943 * stamped until we read these registers, so read the
4944 * registers to make them available again. Because
4945 * only one packet can be time stamped at a time, we
4946 * know that the register values must belong to this
4947 * one here and therefore we don't need to compare
4948 * any of the additional attributes stored for it.
4950 * If nothing went wrong, then it should have a
4951 * skb_shared_tx that we can turn into a
4952 * skb_shared_hwtstamps.
4954 * TODO: can time stamping be triggered (thus locking
4955 * the registers) without the packet reaching this point
4956 * here? In that case RX time stamping would get stuck.
4958 * TODO: in "time stamp all packets" mode this bit is
4959 * not set. Need a global flag for this mode and then
4960 * always read the registers. Cannot be done without
4963 if (unlikely(staterr
& E1000_RXD_STAT_TS
)) {
4966 struct skb_shared_hwtstamps
*shhwtstamps
=
4969 WARN(!(rd32(E1000_TSYNCRXCTL
) & E1000_TSYNCRXCTL_VALID
),
4970 "igb: no RX time stamp available for time stamped packet");
4971 regval
= rd32(E1000_RXSTMPL
);
4972 regval
|= (u64
)rd32(E1000_RXSTMPH
) << 32;
4973 ns
= timecounter_cyc2time(&adapter
->clock
, regval
);
4974 timecompare_update(&adapter
->compare
, ns
);
4975 memset(shhwtstamps
, 0, sizeof(*shhwtstamps
));
4976 shhwtstamps
->hwtstamp
= ns_to_ktime(ns
);
4977 shhwtstamps
->syststamp
=
4978 timecompare_transform(&adapter
->compare
, ns
);
4981 if (staterr
& E1000_RXDEXT_ERR_FRAME_ERR_MASK
) {
4982 dev_kfree_skb_irq(skb
);
4986 total_bytes
+= skb
->len
;
4989 igb_rx_checksum_adv(adapter
, staterr
, skb
);
4991 skb
->protocol
= eth_type_trans(skb
, netdev
);
4992 skb_record_rx_queue(skb
, rx_ring
->queue_index
);
4994 vlan_tag
= ((staterr
& E1000_RXD_STAT_VP
) ?
4995 le16_to_cpu(rx_desc
->wb
.upper
.vlan
) : 0);
4997 igb_receive_skb(q_vector
, skb
, vlan_tag
);
5000 rx_desc
->wb
.upper
.status_error
= 0;
5002 /* return some buffers to hardware, one at a time is too slow */
5003 if (cleaned_count
>= IGB_RX_BUFFER_WRITE
) {
5004 igb_alloc_rx_buffers_adv(rx_ring
, cleaned_count
);
5008 /* use prefetched values */
5010 buffer_info
= next_buffer
;
5011 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
5014 rx_ring
->next_to_clean
= i
;
5015 cleaned_count
= igb_desc_unused(rx_ring
);
5018 igb_alloc_rx_buffers_adv(rx_ring
, cleaned_count
);
5020 rx_ring
->total_packets
+= total_packets
;
5021 rx_ring
->total_bytes
+= total_bytes
;
5022 rx_ring
->rx_stats
.packets
+= total_packets
;
5023 rx_ring
->rx_stats
.bytes
+= total_bytes
;
5024 netdev
->stats
.rx_bytes
+= total_bytes
;
5025 netdev
->stats
.rx_packets
+= total_packets
;
5030 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
5031 * @adapter: address of board private structure
5033 static void igb_alloc_rx_buffers_adv(struct igb_ring
*rx_ring
,
5036 struct igb_adapter
*adapter
= rx_ring
->q_vector
->adapter
;
5037 struct net_device
*netdev
= adapter
->netdev
;
5038 struct pci_dev
*pdev
= adapter
->pdev
;
5039 union e1000_adv_rx_desc
*rx_desc
;
5040 struct igb_buffer
*buffer_info
;
5041 struct sk_buff
*skb
;
5045 i
= rx_ring
->next_to_use
;
5046 buffer_info
= &rx_ring
->buffer_info
[i
];
5048 if (adapter
->rx_ps_hdr_size
)
5049 bufsz
= adapter
->rx_ps_hdr_size
;
5051 bufsz
= adapter
->rx_buffer_len
;
5053 while (cleaned_count
--) {
5054 rx_desc
= E1000_RX_DESC_ADV(*rx_ring
, i
);
5056 if (adapter
->rx_ps_hdr_size
&& !buffer_info
->page_dma
) {
5057 if (!buffer_info
->page
) {
5058 buffer_info
->page
= alloc_page(GFP_ATOMIC
);
5059 if (!buffer_info
->page
) {
5060 adapter
->alloc_rx_buff_failed
++;
5063 buffer_info
->page_offset
= 0;
5065 buffer_info
->page_offset
^= PAGE_SIZE
/ 2;
5067 buffer_info
->page_dma
=
5068 pci_map_page(pdev
, buffer_info
->page
,
5069 buffer_info
->page_offset
,
5071 PCI_DMA_FROMDEVICE
);
5074 if (!buffer_info
->skb
) {
5075 skb
= netdev_alloc_skb_ip_align(netdev
, bufsz
);
5077 adapter
->alloc_rx_buff_failed
++;
5081 buffer_info
->skb
= skb
;
5082 buffer_info
->dma
= pci_map_single(pdev
, skb
->data
,
5084 PCI_DMA_FROMDEVICE
);
5086 /* Refresh the desc even if buffer_addrs didn't change because
5087 * each write-back erases this info. */
5088 if (adapter
->rx_ps_hdr_size
) {
5089 rx_desc
->read
.pkt_addr
=
5090 cpu_to_le64(buffer_info
->page_dma
);
5091 rx_desc
->read
.hdr_addr
= cpu_to_le64(buffer_info
->dma
);
5093 rx_desc
->read
.pkt_addr
=
5094 cpu_to_le64(buffer_info
->dma
);
5095 rx_desc
->read
.hdr_addr
= 0;
5099 if (i
== rx_ring
->count
)
5101 buffer_info
= &rx_ring
->buffer_info
[i
];
5105 if (rx_ring
->next_to_use
!= i
) {
5106 rx_ring
->next_to_use
= i
;
5108 i
= (rx_ring
->count
- 1);
5112 /* Force memory writes to complete before letting h/w
5113 * know there are new descriptors to fetch. (Only
5114 * applicable for weak-ordered memory model archs,
5115 * such as IA-64). */
5117 writel(i
, adapter
->hw
.hw_addr
+ rx_ring
->tail
);
5127 static int igb_mii_ioctl(struct net_device
*netdev
, struct ifreq
*ifr
, int cmd
)
5129 struct igb_adapter
*adapter
= netdev_priv(netdev
);
5130 struct mii_ioctl_data
*data
= if_mii(ifr
);
5132 if (adapter
->hw
.phy
.media_type
!= e1000_media_type_copper
)
5137 data
->phy_id
= adapter
->hw
.phy
.addr
;
5140 if (igb_read_phy_reg(&adapter
->hw
, data
->reg_num
& 0x1F,
5152 * igb_hwtstamp_ioctl - control hardware time stamping
5157 * Outgoing time stamping can be enabled and disabled. Play nice and
5158 * disable it when requested, although it shouldn't case any overhead
5159 * when no packet needs it. At most one packet in the queue may be
5160 * marked for time stamping, otherwise it would be impossible to tell
5161 * for sure to which packet the hardware time stamp belongs.
5163 * Incoming time stamping has to be configured via the hardware
5164 * filters. Not all combinations are supported, in particular event
5165 * type has to be specified. Matching the kind of event packet is
5166 * not supported, with the exception of "all V2 events regardless of
5170 static int igb_hwtstamp_ioctl(struct net_device
*netdev
,
5171 struct ifreq
*ifr
, int cmd
)
5173 struct igb_adapter
*adapter
= netdev_priv(netdev
);
5174 struct e1000_hw
*hw
= &adapter
->hw
;
5175 struct hwtstamp_config config
;
5176 u32 tsync_tx_ctl_bit
= E1000_TSYNCTXCTL_ENABLED
;
5177 u32 tsync_rx_ctl_bit
= E1000_TSYNCRXCTL_ENABLED
;
5178 u32 tsync_rx_ctl_type
= 0;
5179 u32 tsync_rx_cfg
= 0;
5182 short port
= 319; /* PTP */
5185 if (copy_from_user(&config
, ifr
->ifr_data
, sizeof(config
)))
5188 /* reserved for future extensions */
5192 switch (config
.tx_type
) {
5193 case HWTSTAMP_TX_OFF
:
5194 tsync_tx_ctl_bit
= 0;
5196 case HWTSTAMP_TX_ON
:
5197 tsync_tx_ctl_bit
= E1000_TSYNCTXCTL_ENABLED
;
5203 switch (config
.rx_filter
) {
5204 case HWTSTAMP_FILTER_NONE
:
5205 tsync_rx_ctl_bit
= 0;
5207 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
5208 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
5209 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT
:
5210 case HWTSTAMP_FILTER_ALL
:
5212 * register TSYNCRXCFG must be set, therefore it is not
5213 * possible to time stamp both Sync and Delay_Req messages
5214 * => fall back to time stamping all packets
5216 tsync_rx_ctl_type
= E1000_TSYNCRXCTL_TYPE_ALL
;
5217 config
.rx_filter
= HWTSTAMP_FILTER_ALL
;
5219 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
5220 tsync_rx_ctl_type
= E1000_TSYNCRXCTL_TYPE_L4_V1
;
5221 tsync_rx_cfg
= E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE
;
5224 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
5225 tsync_rx_ctl_type
= E1000_TSYNCRXCTL_TYPE_L4_V1
;
5226 tsync_rx_cfg
= E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE
;
5229 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC
:
5230 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
5231 tsync_rx_ctl_type
= E1000_TSYNCRXCTL_TYPE_L2_L4_V2
;
5232 tsync_rx_cfg
= E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE
;
5235 config
.rx_filter
= HWTSTAMP_FILTER_SOME
;
5237 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
:
5238 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
5239 tsync_rx_ctl_type
= E1000_TSYNCRXCTL_TYPE_L2_L4_V2
;
5240 tsync_rx_cfg
= E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE
;
5243 config
.rx_filter
= HWTSTAMP_FILTER_SOME
;
5245 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
5246 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
5247 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
5248 tsync_rx_ctl_type
= E1000_TSYNCRXCTL_TYPE_EVENT_V2
;
5249 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_EVENT
;
5256 /* enable/disable TX */
5257 regval
= rd32(E1000_TSYNCTXCTL
);
5258 regval
= (regval
& ~E1000_TSYNCTXCTL_ENABLED
) | tsync_tx_ctl_bit
;
5259 wr32(E1000_TSYNCTXCTL
, regval
);
5261 /* enable/disable RX, define which PTP packets are time stamped */
5262 regval
= rd32(E1000_TSYNCRXCTL
);
5263 regval
= (regval
& ~E1000_TSYNCRXCTL_ENABLED
) | tsync_rx_ctl_bit
;
5264 regval
= (regval
& ~0xE) | tsync_rx_ctl_type
;
5265 wr32(E1000_TSYNCRXCTL
, regval
);
5266 wr32(E1000_TSYNCRXCFG
, tsync_rx_cfg
);
5269 * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
5270 * (Ethertype to filter on)
5271 * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
5272 * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
5274 wr32(E1000_ETQF0
, is_l2
? 0x440088f7 : 0);
5276 /* L4 Queue Filter[0]: only filter by source and destination port */
5277 wr32(E1000_SPQF0
, htons(port
));
5278 wr32(E1000_IMIREXT(0), is_l4
?
5279 ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
5280 wr32(E1000_IMIR(0), is_l4
?
5282 | (0<<16) /* immediate interrupt disabled */
5283 | 0 /* (1<<17) bit cleared: do not bypass
5284 destination port check */)
5286 wr32(E1000_FTQF0
, is_l4
?
5288 | (1<<15) /* VF not compared */
5289 | (1<<27) /* Enable Timestamping */
5290 | (7<<28) /* only source port filter enabled,
5291 source/target address and protocol
5293 : ((1<<15) | (15<<28) /* all mask bits set = filter not
5298 adapter
->hwtstamp_config
= config
;
5300 /* clear TX/RX time stamp registers, just to be sure */
5301 regval
= rd32(E1000_TXSTMPH
);
5302 regval
= rd32(E1000_RXSTMPH
);
5304 return copy_to_user(ifr
->ifr_data
, &config
, sizeof(config
)) ?
5314 static int igb_ioctl(struct net_device
*netdev
, struct ifreq
*ifr
, int cmd
)
5320 return igb_mii_ioctl(netdev
, ifr
, cmd
);
5322 return igb_hwtstamp_ioctl(netdev
, ifr
, cmd
);
5328 s32
igb_read_pcie_cap_reg(struct e1000_hw
*hw
, u32 reg
, u16
*value
)
5330 struct igb_adapter
*adapter
= hw
->back
;
5333 cap_offset
= pci_find_capability(adapter
->pdev
, PCI_CAP_ID_EXP
);
5335 return -E1000_ERR_CONFIG
;
5337 pci_read_config_word(adapter
->pdev
, cap_offset
+ reg
, value
);
5342 s32
igb_write_pcie_cap_reg(struct e1000_hw
*hw
, u32 reg
, u16
*value
)
5344 struct igb_adapter
*adapter
= hw
->back
;
5347 cap_offset
= pci_find_capability(adapter
->pdev
, PCI_CAP_ID_EXP
);
5349 return -E1000_ERR_CONFIG
;
5351 pci_write_config_word(adapter
->pdev
, cap_offset
+ reg
, *value
);
5356 static void igb_vlan_rx_register(struct net_device
*netdev
,
5357 struct vlan_group
*grp
)
5359 struct igb_adapter
*adapter
= netdev_priv(netdev
);
5360 struct e1000_hw
*hw
= &adapter
->hw
;
5363 igb_irq_disable(adapter
);
5364 adapter
->vlgrp
= grp
;
5367 /* enable VLAN tag insert/strip */
5368 ctrl
= rd32(E1000_CTRL
);
5369 ctrl
|= E1000_CTRL_VME
;
5370 wr32(E1000_CTRL
, ctrl
);
5372 /* enable VLAN receive filtering */
5373 rctl
= rd32(E1000_RCTL
);
5374 rctl
&= ~E1000_RCTL_CFIEN
;
5375 wr32(E1000_RCTL
, rctl
);
5376 igb_update_mng_vlan(adapter
);
5378 /* disable VLAN tag insert/strip */
5379 ctrl
= rd32(E1000_CTRL
);
5380 ctrl
&= ~E1000_CTRL_VME
;
5381 wr32(E1000_CTRL
, ctrl
);
5383 if (adapter
->mng_vlan_id
!= (u16
)IGB_MNG_VLAN_NONE
) {
5384 igb_vlan_rx_kill_vid(netdev
, adapter
->mng_vlan_id
);
5385 adapter
->mng_vlan_id
= IGB_MNG_VLAN_NONE
;
5389 igb_rlpml_set(adapter
);
5391 if (!test_bit(__IGB_DOWN
, &adapter
->state
))
5392 igb_irq_enable(adapter
);
5395 static void igb_vlan_rx_add_vid(struct net_device
*netdev
, u16 vid
)
5397 struct igb_adapter
*adapter
= netdev_priv(netdev
);
5398 struct e1000_hw
*hw
= &adapter
->hw
;
5399 int pf_id
= adapter
->vfs_allocated_count
;
5401 if ((hw
->mng_cookie
.status
&
5402 E1000_MNG_DHCP_COOKIE_STATUS_VLAN
) &&
5403 (vid
== adapter
->mng_vlan_id
))
5406 /* add vid to vlvf if sr-iov is enabled,
5407 * if that fails add directly to filter table */
5408 if (igb_vlvf_set(adapter
, vid
, true, pf_id
))
5409 igb_vfta_set(hw
, vid
, true);
5413 static void igb_vlan_rx_kill_vid(struct net_device
*netdev
, u16 vid
)
5415 struct igb_adapter
*adapter
= netdev_priv(netdev
);
5416 struct e1000_hw
*hw
= &adapter
->hw
;
5417 int pf_id
= adapter
->vfs_allocated_count
;
5419 igb_irq_disable(adapter
);
5420 vlan_group_set_device(adapter
->vlgrp
, vid
, NULL
);
5422 if (!test_bit(__IGB_DOWN
, &adapter
->state
))
5423 igb_irq_enable(adapter
);
5425 if ((adapter
->hw
.mng_cookie
.status
&
5426 E1000_MNG_DHCP_COOKIE_STATUS_VLAN
) &&
5427 (vid
== adapter
->mng_vlan_id
)) {
5428 /* release control to f/w */
5429 igb_release_hw_control(adapter
);
5433 /* remove vid from vlvf if sr-iov is enabled,
5434 * if not in vlvf remove from vfta */
5435 if (igb_vlvf_set(adapter
, vid
, false, pf_id
))
5436 igb_vfta_set(hw
, vid
, false);
5439 static void igb_restore_vlan(struct igb_adapter
*adapter
)
5441 igb_vlan_rx_register(adapter
->netdev
, adapter
->vlgrp
);
5443 if (adapter
->vlgrp
) {
5445 for (vid
= 0; vid
< VLAN_GROUP_ARRAY_LEN
; vid
++) {
5446 if (!vlan_group_get_device(adapter
->vlgrp
, vid
))
5448 igb_vlan_rx_add_vid(adapter
->netdev
, vid
);
5453 int igb_set_spd_dplx(struct igb_adapter
*adapter
, u16 spddplx
)
5455 struct e1000_mac_info
*mac
= &adapter
->hw
.mac
;
5460 case SPEED_10
+ DUPLEX_HALF
:
5461 mac
->forced_speed_duplex
= ADVERTISE_10_HALF
;
5463 case SPEED_10
+ DUPLEX_FULL
:
5464 mac
->forced_speed_duplex
= ADVERTISE_10_FULL
;
5466 case SPEED_100
+ DUPLEX_HALF
:
5467 mac
->forced_speed_duplex
= ADVERTISE_100_HALF
;
5469 case SPEED_100
+ DUPLEX_FULL
:
5470 mac
->forced_speed_duplex
= ADVERTISE_100_FULL
;
5472 case SPEED_1000
+ DUPLEX_FULL
:
5474 adapter
->hw
.phy
.autoneg_advertised
= ADVERTISE_1000_FULL
;
5476 case SPEED_1000
+ DUPLEX_HALF
: /* not supported */
5478 dev_err(&adapter
->pdev
->dev
,
5479 "Unsupported Speed/Duplex configuration\n");
5485 static int __igb_shutdown(struct pci_dev
*pdev
, bool *enable_wake
)
5487 struct net_device
*netdev
= pci_get_drvdata(pdev
);
5488 struct igb_adapter
*adapter
= netdev_priv(netdev
);
5489 struct e1000_hw
*hw
= &adapter
->hw
;
5490 u32 ctrl
, rctl
, status
;
5491 u32 wufc
= adapter
->wol
;
5496 netif_device_detach(netdev
);
5498 if (netif_running(netdev
))
5501 igb_clear_interrupt_scheme(adapter
);
5504 retval
= pci_save_state(pdev
);
5509 status
= rd32(E1000_STATUS
);
5510 if (status
& E1000_STATUS_LU
)
5511 wufc
&= ~E1000_WUFC_LNKC
;
5514 igb_setup_rctl(adapter
);
5515 igb_set_rx_mode(netdev
);
5517 /* turn on all-multi mode if wake on multicast is enabled */
5518 if (wufc
& E1000_WUFC_MC
) {
5519 rctl
= rd32(E1000_RCTL
);
5520 rctl
|= E1000_RCTL_MPE
;
5521 wr32(E1000_RCTL
, rctl
);
5524 ctrl
= rd32(E1000_CTRL
);
5525 /* advertise wake from D3Cold */
5526 #define E1000_CTRL_ADVD3WUC 0x00100000
5527 /* phy power management enable */
5528 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5529 ctrl
|= E1000_CTRL_ADVD3WUC
;
5530 wr32(E1000_CTRL
, ctrl
);
5532 /* Allow time for pending master requests to run */
5533 igb_disable_pcie_master(&adapter
->hw
);
5535 wr32(E1000_WUC
, E1000_WUC_PME_EN
);
5536 wr32(E1000_WUFC
, wufc
);
5539 wr32(E1000_WUFC
, 0);
5542 *enable_wake
= wufc
|| adapter
->en_mng_pt
;
5544 igb_shutdown_serdes_link_82575(hw
);
5546 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5547 * would have already happened in close and is redundant. */
5548 igb_release_hw_control(adapter
);
5550 pci_disable_device(pdev
);
5556 static int igb_suspend(struct pci_dev
*pdev
, pm_message_t state
)
5561 retval
= __igb_shutdown(pdev
, &wake
);
5566 pci_prepare_to_sleep(pdev
);
5568 pci_wake_from_d3(pdev
, false);
5569 pci_set_power_state(pdev
, PCI_D3hot
);
5575 static int igb_resume(struct pci_dev
*pdev
)
5577 struct net_device
*netdev
= pci_get_drvdata(pdev
);
5578 struct igb_adapter
*adapter
= netdev_priv(netdev
);
5579 struct e1000_hw
*hw
= &adapter
->hw
;
5582 pci_set_power_state(pdev
, PCI_D0
);
5583 pci_restore_state(pdev
);
5585 err
= pci_enable_device_mem(pdev
);
5588 "igb: Cannot enable PCI device from suspend\n");
5591 pci_set_master(pdev
);
5593 pci_enable_wake(pdev
, PCI_D3hot
, 0);
5594 pci_enable_wake(pdev
, PCI_D3cold
, 0);
5596 if (igb_init_interrupt_scheme(adapter
)) {
5597 dev_err(&pdev
->dev
, "Unable to allocate memory for queues\n");
5601 /* e1000_power_up_phy(adapter); */
5605 /* let the f/w know that the h/w is now under the control of the
5607 igb_get_hw_control(adapter
);
5609 wr32(E1000_WUS
, ~0);
5611 if (netif_running(netdev
)) {
5612 err
= igb_open(netdev
);
5617 netif_device_attach(netdev
);
5623 static void igb_shutdown(struct pci_dev
*pdev
)
5627 __igb_shutdown(pdev
, &wake
);
5629 if (system_state
== SYSTEM_POWER_OFF
) {
5630 pci_wake_from_d3(pdev
, wake
);
5631 pci_set_power_state(pdev
, PCI_D3hot
);
5635 #ifdef CONFIG_NET_POLL_CONTROLLER
5637 * Polling 'interrupt' - used by things like netconsole to send skbs
5638 * without having to re-enable interrupts. It's not called while
5639 * the interrupt routine is executing.
5641 static void igb_netpoll(struct net_device
*netdev
)
5643 struct igb_adapter
*adapter
= netdev_priv(netdev
);
5644 struct e1000_hw
*hw
= &adapter
->hw
;
5647 if (!adapter
->msix_entries
) {
5648 struct igb_q_vector
*q_vector
= adapter
->q_vector
[0];
5649 igb_irq_disable(adapter
);
5650 napi_schedule(&q_vector
->napi
);
5654 for (i
= 0; i
< adapter
->num_q_vectors
; i
++) {
5655 struct igb_q_vector
*q_vector
= adapter
->q_vector
[i
];
5656 wr32(E1000_EIMC
, q_vector
->eims_value
);
5657 napi_schedule(&q_vector
->napi
);
5660 #endif /* CONFIG_NET_POLL_CONTROLLER */
5663 * igb_io_error_detected - called when PCI error is detected
5664 * @pdev: Pointer to PCI device
5665 * @state: The current pci connection state
5667 * This function is called after a PCI bus error affecting
5668 * this device has been detected.
5670 static pci_ers_result_t
igb_io_error_detected(struct pci_dev
*pdev
,
5671 pci_channel_state_t state
)
5673 struct net_device
*netdev
= pci_get_drvdata(pdev
);
5674 struct igb_adapter
*adapter
= netdev_priv(netdev
);
5676 netif_device_detach(netdev
);
5678 if (state
== pci_channel_io_perm_failure
)
5679 return PCI_ERS_RESULT_DISCONNECT
;
5681 if (netif_running(netdev
))
5683 pci_disable_device(pdev
);
5685 /* Request a slot slot reset. */
5686 return PCI_ERS_RESULT_NEED_RESET
;
5690 * igb_io_slot_reset - called after the pci bus has been reset.
5691 * @pdev: Pointer to PCI device
5693 * Restart the card from scratch, as if from a cold-boot. Implementation
5694 * resembles the first-half of the igb_resume routine.
5696 static pci_ers_result_t
igb_io_slot_reset(struct pci_dev
*pdev
)
5698 struct net_device
*netdev
= pci_get_drvdata(pdev
);
5699 struct igb_adapter
*adapter
= netdev_priv(netdev
);
5700 struct e1000_hw
*hw
= &adapter
->hw
;
5701 pci_ers_result_t result
;
5704 if (pci_enable_device_mem(pdev
)) {
5706 "Cannot re-enable PCI device after reset.\n");
5707 result
= PCI_ERS_RESULT_DISCONNECT
;
5709 pci_set_master(pdev
);
5710 pci_restore_state(pdev
);
5712 pci_enable_wake(pdev
, PCI_D3hot
, 0);
5713 pci_enable_wake(pdev
, PCI_D3cold
, 0);
5716 wr32(E1000_WUS
, ~0);
5717 result
= PCI_ERS_RESULT_RECOVERED
;
5720 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
5722 dev_err(&pdev
->dev
, "pci_cleanup_aer_uncorrect_error_status "
5723 "failed 0x%0x\n", err
);
5724 /* non-fatal, continue */
5731 * igb_io_resume - called when traffic can start flowing again.
5732 * @pdev: Pointer to PCI device
5734 * This callback is called when the error recovery driver tells us that
5735 * its OK to resume normal operation. Implementation resembles the
5736 * second-half of the igb_resume routine.
5738 static void igb_io_resume(struct pci_dev
*pdev
)
5740 struct net_device
*netdev
= pci_get_drvdata(pdev
);
5741 struct igb_adapter
*adapter
= netdev_priv(netdev
);
5743 if (netif_running(netdev
)) {
5744 if (igb_up(adapter
)) {
5745 dev_err(&pdev
->dev
, "igb_up failed after reset\n");
5750 netif_device_attach(netdev
);
5752 /* let the f/w know that the h/w is now under the control of the
5754 igb_get_hw_control(adapter
);
5757 static void igb_rar_set_qsel(struct igb_adapter
*adapter
, u8
*addr
, u32 index
,
5760 u32 rar_low
, rar_high
;
5761 struct e1000_hw
*hw
= &adapter
->hw
;
5763 /* HW expects these in little endian so we reverse the byte order
5764 * from network order (big endian) to little endian
5766 rar_low
= ((u32
) addr
[0] | ((u32
) addr
[1] << 8) |
5767 ((u32
) addr
[2] << 16) | ((u32
) addr
[3] << 24));
5768 rar_high
= ((u32
) addr
[4] | ((u32
) addr
[5] << 8));
5770 /* Indicate to hardware the Address is Valid. */
5771 rar_high
|= E1000_RAH_AV
;
5773 if (hw
->mac
.type
== e1000_82575
)
5774 rar_high
|= E1000_RAH_POOL_1
* qsel
;
5776 rar_high
|= E1000_RAH_POOL_1
<< qsel
;
5778 wr32(E1000_RAL(index
), rar_low
);
5780 wr32(E1000_RAH(index
), rar_high
);
5784 static int igb_set_vf_mac(struct igb_adapter
*adapter
,
5785 int vf
, unsigned char *mac_addr
)
5787 struct e1000_hw
*hw
= &adapter
->hw
;
5788 /* VF MAC addresses start at end of receive addresses and moves
5789 * torwards the first, as a result a collision should not be possible */
5790 int rar_entry
= hw
->mac
.rar_entry_count
- (vf
+ 1);
5792 memcpy(adapter
->vf_data
[vf
].vf_mac_addresses
, mac_addr
, ETH_ALEN
);
5794 igb_rar_set_qsel(adapter
, mac_addr
, rar_entry
, vf
);
5799 static void igb_vmm_control(struct igb_adapter
*adapter
)
5801 struct e1000_hw
*hw
= &adapter
->hw
;
5804 if (!adapter
->vfs_allocated_count
)
5807 /* VF's need PF reset indication before they
5808 * can send/receive mail */
5809 reg_data
= rd32(E1000_CTRL_EXT
);
5810 reg_data
|= E1000_CTRL_EXT_PFRSTD
;
5811 wr32(E1000_CTRL_EXT
, reg_data
);
5813 igb_vmdq_set_loopback_pf(hw
, true);
5814 igb_vmdq_set_replication_pf(hw
, true);