arch/tile/include/asm/io.h

   1 /*
   2  * Copyright 2010 Tilera Corporation. All Rights Reserved.
   3  *
   4  *   This program is free software; you can redistribute it and/or
   5  *   modify it under the terms of the GNU General Public License
   6  *   as published by the Free Software Foundation, version 2.
   7  *
   8  *   This program is distributed in the hope that it will be useful, but
   9  *   WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  11  *   NON INFRINGEMENT.  See the GNU General Public License for
  12  *   more details.
  13  */
  14
  15 #ifndef _ASM_TILE_IO_H
  16 #define _ASM_TILE_IO_H
  17
  18 #include <linux/kernel.h>
  19 #include <linux/bug.h>
  20 #include <asm/page.h>
  21
  22 #define IO_SPACE_LIMIT 0xfffffffful
  23
  24 /*
  25  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
  26  * access.
  27  */
  28 #define xlate_dev_mem_ptr(p)    __va(p)
  29
  30 /*
  31  * Convert a virtual cached pointer to an uncached pointer.
  32  */
  33 #define xlate_dev_kmem_ptr(p)   p
  34
  35 /*
  36  * Change "struct page" to physical address.
  37  */
  38 #define page_to_phys(page)    ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
  39
  40 /*
  41  * Some places try to pass in an loff_t for PHYSADDR (?!), so we cast it to
  42  * long before casting it to a pointer to avoid compiler warnings.
  43  */
  44 #if CHIP_HAS_MMIO()
  45 extern void __iomem *ioremap(resource_size_t offset, unsigned long size);
  46 extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size,
  47         pgprot_t pgprot);
  48 extern void iounmap(volatile void __iomem *addr);
  49 #else
  50 #define ioremap(physaddr, size) ((void __iomem *)(unsigned long)(physaddr))
  51 #define iounmap(addr)           ((void)0)
  52 #endif
  53
  54 #define ioremap_nocache(physaddr, size)         ioremap(physaddr, size)
  55 #define ioremap_wc(physaddr, size)              ioremap(physaddr, size)
  56 #define ioremap_writethrough(physaddr, size)    ioremap(physaddr, size)
  57 #define ioremap_fullcache(physaddr, size)       ioremap(physaddr, size)
  58
  59 #define mmiowb()
  60
  61 /* Conversion between virtual and physical mappings.  */
  62 #define mm_ptov(addr)           ((void *)phys_to_virt(addr))
  63 #define mm_vtop(addr)           ((unsigned long)virt_to_phys(addr))
  64
  65 #if CHIP_HAS_MMIO()
  66
  67 /*
  68  * We use inline assembly to guarantee that the compiler does not
  69  * split an access into multiple byte-sized accesses as it might
  70  * sometimes do if a register data structure is marked "packed".
  71  * Obviously on tile we can't tolerate such an access being
  72  * actually unaligned, but we want to avoid the case where the
  73  * compiler conservatively would generate multiple accesses even
  74  * for an aligned read or write.
  75  */
  76
  77 static inline u8 __raw_readb(const volatile void __iomem *addr)
  78 {
  79         return *(const volatile u8 __force *)addr;
  80 }
  81
  82 static inline u16 __raw_readw(const volatile void __iomem *addr)
  83 {
  84         u16 ret;
  85         asm volatile("ld2u %0, %1" : "=r" (ret) : "r" (addr));
  86         barrier();
  87         return le16_to_cpu(ret);
  88 }
  89
  90 static inline u32 __raw_readl(const volatile void __iomem *addr)
  91 {
  92         u32 ret;
  93         /* Sign-extend to conform to u32 ABI sign-extension convention. */
  94         asm volatile("ld4s %0, %1" : "=r" (ret) : "r" (addr));
  95         barrier();
  96         return le32_to_cpu(ret);
  97 }
  98
  99 static inline u64 __raw_readq(const volatile void __iomem *addr)
 100 {
 101         u64 ret;
 102         asm volatile("ld %0, %1" : "=r" (ret) : "r" (addr));
 103         barrier();
 104         return le64_to_cpu(ret);
 105 }
 106
 107 static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
 108 {
 109         *(volatile u8 __force *)addr = val;
 110 }
 111
 112 static inline void __raw_writew(u16 val, volatile void __iomem *addr)
 113 {
 114         asm volatile("st2 %0, %1" :: "r" (addr), "r" (cpu_to_le16(val)));
 115 }
 116
 117 static inline void __raw_writel(u32 val, volatile void __iomem *addr)
 118 {
 119         asm volatile("st4 %0, %1" :: "r" (addr), "r" (cpu_to_le32(val)));
 120 }
 121
 122 static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
 123 {
 124         asm volatile("st %0, %1" :: "r" (addr), "r" (cpu_to_le64(val)));
 125 }
 126
 127 /*
 128  * The on-chip I/O hardware on tilegx is configured with VA=PA for the
 129  * kernel's PA range.  The low-level APIs and field names use "va" and
 130  * "void *" nomenclature, to be consistent with the general notion
 131  * that the addresses in question are virtualizable, but in the kernel
 132  * context we are actually manipulating PA values.  (In other contexts,
 133  * e.g. access from user space, we do in fact use real virtual addresses
 134  * in the va fields.)  To allow readers of the code to understand what's
 135  * happening, we direct their attention to this comment by using the
 136  * following two functions that just duplicate __va() and __pa().
 137  */
 138 typedef unsigned long tile_io_addr_t;
 139 static inline tile_io_addr_t va_to_tile_io_addr(void *va)
 140 {
 141         BUILD_BUG_ON(sizeof(phys_addr_t) != sizeof(tile_io_addr_t));
 142         return __pa(va);
 143 }
 144 static inline void *tile_io_addr_to_va(tile_io_addr_t tile_io_addr)
 145 {
 146         return __va(tile_io_addr);
 147 }
 148
 149 #else /* CHIP_HAS_MMIO() */
 150
 151 #ifdef CONFIG_PCI
 152
 153 extern u8 _tile_readb(unsigned long addr);
 154 extern u16 _tile_readw(unsigned long addr);
 155 extern u32 _tile_readl(unsigned long addr);
 156 extern u64 _tile_readq(unsigned long addr);
 157 extern void _tile_writeb(u8  val, unsigned long addr);
 158 extern void _tile_writew(u16 val, unsigned long addr);
 159 extern void _tile_writel(u32 val, unsigned long addr);
 160 extern void _tile_writeq(u64 val, unsigned long addr);
 161
 162 #define __raw_readb(addr) _tile_readb((unsigned long)addr)
 163 #define __raw_readw(addr) _tile_readw((unsigned long)addr)
 164 #define __raw_readl(addr) _tile_readl((unsigned long)addr)
 165 #define __raw_readq(addr) _tile_readq((unsigned long)addr)
 166 #define __raw_writeb(val, addr) _tile_writeb(val, (unsigned long)addr)
 167 #define __raw_writew(val, addr) _tile_writew(val, (unsigned long)addr)
 168 #define __raw_writel(val, addr) _tile_writel(val, (unsigned long)addr)
 169 #define __raw_writeq(val, addr) _tile_writeq(val, (unsigned long)addr)
 170
 171 #else /* CONFIG_PCI */
 172
 173 /*
 174  * The tilepro architecture does not support IOMEM unless PCI is enabled.
 175  * Unfortunately we can't yet simply not declare these methods,
 176  * since some generic code that compiles into the kernel, but
 177  * we never run, uses them unconditionally.
 178  */
 179
 180 static inline int iomem_panic(void)
 181 {
 182         panic("readb/writeb and friends do not exist on tile without PCI");
 183         return 0;
 184 }
 185
 186 static inline u8 readb(unsigned long addr)
 187 {
 188         return iomem_panic();
 189 }
 190
 191 static inline u16 _readw(unsigned long addr)
 192 {
 193         return iomem_panic();
 194 }
 195
 196 static inline u32 readl(unsigned long addr)
 197 {
 198         return iomem_panic();
 199 }
 200
 201 static inline u64 readq(unsigned long addr)
 202 {
 203         return iomem_panic();
 204 }
 205
 206 static inline void writeb(u8  val, unsigned long addr)
 207 {
 208         iomem_panic();
 209 }
 210
 211 static inline void writew(u16 val, unsigned long addr)
 212 {
 213         iomem_panic();
 214 }
 215
 216 static inline void writel(u32 val, unsigned long addr)
 217 {
 218         iomem_panic();
 219 }
 220
 221 static inline void writeq(u64 val, unsigned long addr)
 222 {
 223         iomem_panic();
 224 }
 225
 226 #endif /* CONFIG_PCI */
 227
 228 #endif /* CHIP_HAS_MMIO() */
 229
 230 #define readb __raw_readb
 231 #define readw __raw_readw
 232 #define readl __raw_readl
 233 #define readq __raw_readq
 234 #define writeb __raw_writeb
 235 #define writew __raw_writew
 236 #define writel __raw_writel
 237 #define writeq __raw_writeq
 238
 239 #define readb_relaxed readb
 240 #define readw_relaxed readw
 241 #define readl_relaxed readl
 242 #define readq_relaxed readq
 243
 244 #define ioread8 readb
 245 #define ioread16 readw
 246 #define ioread32 readl
 247 #define ioread64 readq
 248 #define iowrite8 writeb
 249 #define iowrite16 writew
 250 #define iowrite32 writel
 251 #define iowrite64 writeq
 252
 253 static inline void memset_io(void *dst, int val, size_t len)
 254 {
 255         int x;
 256         BUG_ON((unsigned long)dst & 0x3);
 257         val = (val & 0xff) * 0x01010101;
 258         for (x = 0; x < len; x += 4)
 259                 writel(val, dst + x);
 260 }
 261
 262 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
 263                                  size_t len)
 264 {
 265         int x;
 266         BUG_ON((unsigned long)src & 0x3);
 267         for (x = 0; x < len; x += 4)
 268                 *(u32 *)(dst + x) = readl(src + x);
 269 }
 270
 271 static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
 272                                 size_t len)
 273 {
 274         int x;
 275         BUG_ON((unsigned long)dst & 0x3);
 276         for (x = 0; x < len; x += 4)
 277                 writel(*(u32 *)(src + x), dst + x);
 278 }
 279
 280 /*
 281  * The Tile architecture does not support IOPORT, even with PCI.
 282  * Unfortunately we can't yet simply not declare these methods,
 283  * since some generic code that compiles into the kernel, but
 284  * we never run, uses them unconditionally.
 285  */
 286
 287 static inline long ioport_panic(void)
 288 {
 289         panic("inb/outb and friends do not exist on tile");
 290         return 0;
 291 }
 292
 293 static inline void __iomem *ioport_map(unsigned long port, unsigned int len)
 294 {
 295         pr_info("ioport_map: mapping IO resources is unsupported on tile.\n");
 296         return NULL;
 297 }
 298
 299 static inline void ioport_unmap(void __iomem *addr)
 300 {
 301         ioport_panic();
 302 }
 303
 304 static inline u8 inb(unsigned long addr)
 305 {
 306         return ioport_panic();
 307 }
 308
 309 static inline u16 inw(unsigned long addr)
 310 {
 311         return ioport_panic();
 312 }
 313
 314 static inline u32 inl(unsigned long addr)
 315 {
 316         return ioport_panic();
 317 }
 318
 319 static inline void outb(u8 b, unsigned long addr)
 320 {
 321         ioport_panic();
 322 }
 323
 324 static inline void outw(u16 b, unsigned long addr)
 325 {
 326         ioport_panic();
 327 }
 328
 329 static inline void outl(u32 b, unsigned long addr)
 330 {
 331         ioport_panic();
 332 }
 333
 334 #define inb_p(addr)     inb(addr)
 335 #define inw_p(addr)     inw(addr)
 336 #define inl_p(addr)     inl(addr)
 337 #define outb_p(x, addr) outb((x), (addr))
 338 #define outw_p(x, addr) outw((x), (addr))
 339 #define outl_p(x, addr) outl((x), (addr))
 340
 341 static inline void insb(unsigned long addr, void *buffer, int count)
 342 {
 343         ioport_panic();
 344 }
 345
 346 static inline void insw(unsigned long addr, void *buffer, int count)
 347 {
 348         ioport_panic();
 349 }
 350
 351 static inline void insl(unsigned long addr, void *buffer, int count)
 352 {
 353         ioport_panic();
 354 }
 355
 356 static inline void outsb(unsigned long addr, const void *buffer, int count)
 357 {
 358         ioport_panic();
 359 }
 360
 361 static inline void outsw(unsigned long addr, const void *buffer, int count)
 362 {
 363         ioport_panic();
 364 }
 365
 366 static inline void outsl(unsigned long addr, const void *buffer, int count)
 367 {
 368         ioport_panic();
 369 }
 370
 371 #define ioread16be(addr)        be16_to_cpu(ioread16(addr))
 372 #define ioread32be(addr)        be32_to_cpu(ioread32(addr))
 373 #define iowrite16be(v, addr)    iowrite16(be16_to_cpu(v), (addr))
 374 #define iowrite32be(v, addr)    iowrite32(be32_to_cpu(v), (addr))
 375
 376 #define ioread8_rep(p, dst, count) \
 377         insb((unsigned long) (p), (dst), (count))
 378 #define ioread16_rep(p, dst, count) \
 379         insw((unsigned long) (p), (dst), (count))
 380 #define ioread32_rep(p, dst, count) \
 381         insl((unsigned long) (p), (dst), (count))
 382
 383 #define iowrite8_rep(p, src, count) \
 384         outsb((unsigned long) (p), (src), (count))
 385 #define iowrite16_rep(p, src, count) \
 386         outsw((unsigned long) (p), (src), (count))
 387 #define iowrite32_rep(p, src, count) \
 388         outsl((unsigned long) (p), (src), (count))
 389
 390 #define virt_to_bus     virt_to_phys
 391 #define bus_to_virt     phys_to_virt
 392
 393 #endif /* _ASM_TILE_IO_H */