2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004 MIPS Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/module.h>
24 #include <asm/mipsregs.h>
25 #include <asm/system.h>
26 #include <asm/watch.h>
27 #include <asm/spram.h>
29 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
30 * the implementation of the "wait" feature differs between CPU families. This
31 * points to the function that implements CPU specific wait.
32 * The wait instruction stops the pipeline and reduces the power consumption of
35 void (*cpu_wait
)(void);
36 EXPORT_SYMBOL(cpu_wait
);
38 static void r3081_wait(void)
40 unsigned long cfg
= read_c0_conf();
41 write_c0_conf(cfg
| R30XX_CONF_HALT
);
44 static void r39xx_wait(void)
48 write_c0_conf(read_c0_conf() | TX39_CONF_HALT
);
52 extern void r4k_wait(void);
55 * This variant is preferable as it allows testing need_resched and going to
56 * sleep depending on the outcome atomically. Unfortunately the "It is
57 * implementation-dependent whether the pipeline restarts when a non-enabled
58 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
59 * using this version a gamble.
61 void r4k_wait_irqoff(void)
65 __asm__(" .set push \n"
70 __asm__(" .globl __pastwait \n"
76 * The RM7000 variant has to handle erratum 38. The workaround is to not
77 * have any pending stores when the WAIT instruction is executed.
79 static void rm7k_wait_irqoff(void)
89 " mtc0 $1, $12 # stalls until W stage \n"
91 " mtc0 $1, $12 # stalls until W stage \n"
97 * The Au1xxx wait is available only if using 32khz counter or
98 * external timer source, but specifically not CP0 Counter.
99 * alchemy/common/time.c may override cpu_wait!
101 static void au1k_wait(void)
103 __asm__(" .set mips3 \n"
104 " cache 0x14, 0(%0) \n"
105 " cache 0x14, 32(%0) \n"
114 : : "r" (au1k_wait
));
117 static int __initdata nowait
;
119 static int __init
wait_disable(char *s
)
126 __setup("nowait", wait_disable
);
128 static int __cpuinitdata mips_fpu_disabled
;
130 static int __init
fpu_disable(char *s
)
132 cpu_data
[0].options
&= ~MIPS_CPU_FPU
;
133 mips_fpu_disabled
= 1;
138 __setup("nofpu", fpu_disable
);
140 int __cpuinitdata mips_dsp_disabled
;
142 static int __init
dsp_disable(char *s
)
144 cpu_data
[0].ases
&= ~MIPS_ASE_DSP
;
145 mips_dsp_disabled
= 1;
150 __setup("nodsp", dsp_disable
);
152 void __init
check_wait(void)
154 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
157 printk("Wait instruction disabled.\n");
161 switch (c
->cputype
) {
164 cpu_wait
= r3081_wait
;
167 cpu_wait
= r39xx_wait
;
170 /* case CPU_R4300: */
188 case CPU_CAVIUM_OCTEON
:
189 case CPU_CAVIUM_OCTEON_PLUS
:
194 cpu_wait
= rm7k_wait_irqoff
;
201 if (read_c0_config7() & MIPS_CONF7_WII
)
202 cpu_wait
= r4k_wait_irqoff
;
207 if ((c
->processor_id
& 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
208 cpu_wait
= r4k_wait_irqoff
;
212 cpu_wait
= r4k_wait_irqoff
;
215 cpu_wait
= au1k_wait
;
219 * WAIT on Rev1.0 has E1, E2, E3 and E16.
220 * WAIT on Rev2.0 and Rev3.0 has E16.
221 * Rev3.1 WAIT is nop, why bother
223 if ((c
->processor_id
& 0xff) <= 0x64)
227 * Another rev is incremeting c0_count at a reduced clock
228 * rate while in WAIT mode. So we basically have the choice
229 * between using the cp0 timer as clocksource or avoiding
230 * the WAIT instruction. Until more details are known,
231 * disable the use of WAIT for 20Kc entirely.
236 if ((c
->processor_id
& 0x00ff) >= 0x40)
244 static inline void check_errata(void)
246 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
248 switch (c
->cputype
) {
251 * Erratum "RPS May Cause Incorrect Instruction Execution"
252 * This code only handles VPE0, any SMP/SMTC/RTOS code
253 * making use of VPE1 will be responsable for that VPE.
255 if ((c
->processor_id
& PRID_REV_MASK
) <= PRID_REV_34K_V1_0_2
)
256 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS
);
263 void __init
check_bugs32(void)
269 * Probe whether cpu has config register by trying to play with
270 * alternate cache bit and see whether it matters.
271 * It's used by cpu_probe to distinguish between R3000A and R3081.
273 static inline int cpu_has_confreg(void)
275 #ifdef CONFIG_CPU_R3000
276 extern unsigned long r3k_cache_size(unsigned long);
277 unsigned long size1
, size2
;
278 unsigned long cfg
= read_c0_conf();
280 size1
= r3k_cache_size(ST0_ISC
);
281 write_c0_conf(cfg
^ R30XX_CONF_AC
);
282 size2
= r3k_cache_size(ST0_ISC
);
284 return size1
!= size2
;
291 * Get the FPU Implementation/Revision.
293 static inline unsigned long cpu_get_fpu_id(void)
295 unsigned long tmp
, fpu_id
;
297 tmp
= read_c0_status();
299 fpu_id
= read_32bit_cp1_register(CP1_REVISION
);
300 write_c0_status(tmp
);
305 * Check the CPU has an FPU the official way.
307 static inline int __cpu_has_fpu(void)
309 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE
);
312 static inline void cpu_probe_vmbits(struct cpuinfo_mips
*c
)
314 #ifdef __NEED_VMBITS_PROBE
315 write_c0_entryhi(0x3fffffffffffe000ULL
);
316 back_to_back_c0_hazard();
317 c
->vmbits
= fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL
);
321 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
324 static inline void cpu_probe_legacy(struct cpuinfo_mips
*c
, unsigned int cpu
)
326 switch (c
->processor_id
& 0xff00) {
328 c
->cputype
= CPU_R2000
;
329 __cpu_name
[cpu
] = "R2000";
330 c
->isa_level
= MIPS_CPU_ISA_I
;
331 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_3K_CACHE
|
334 c
->options
|= MIPS_CPU_FPU
;
338 if ((c
->processor_id
& 0xff) == PRID_REV_R3000A
) {
339 if (cpu_has_confreg()) {
340 c
->cputype
= CPU_R3081E
;
341 __cpu_name
[cpu
] = "R3081";
343 c
->cputype
= CPU_R3000A
;
344 __cpu_name
[cpu
] = "R3000A";
348 c
->cputype
= CPU_R3000
;
349 __cpu_name
[cpu
] = "R3000";
351 c
->isa_level
= MIPS_CPU_ISA_I
;
352 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_3K_CACHE
|
355 c
->options
|= MIPS_CPU_FPU
;
359 if (read_c0_config() & CONF_SC
) {
360 if ((c
->processor_id
& 0xff) >= PRID_REV_R4400
) {
361 c
->cputype
= CPU_R4400PC
;
362 __cpu_name
[cpu
] = "R4400PC";
364 c
->cputype
= CPU_R4000PC
;
365 __cpu_name
[cpu
] = "R4000PC";
368 if ((c
->processor_id
& 0xff) >= PRID_REV_R4400
) {
369 c
->cputype
= CPU_R4400SC
;
370 __cpu_name
[cpu
] = "R4400SC";
372 c
->cputype
= CPU_R4000SC
;
373 __cpu_name
[cpu
] = "R4000SC";
377 c
->isa_level
= MIPS_CPU_ISA_III
;
378 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
379 MIPS_CPU_WATCH
| MIPS_CPU_VCE
|
383 case PRID_IMP_VR41XX
:
384 switch (c
->processor_id
& 0xf0) {
385 case PRID_REV_VR4111
:
386 c
->cputype
= CPU_VR4111
;
387 __cpu_name
[cpu
] = "NEC VR4111";
389 case PRID_REV_VR4121
:
390 c
->cputype
= CPU_VR4121
;
391 __cpu_name
[cpu
] = "NEC VR4121";
393 case PRID_REV_VR4122
:
394 if ((c
->processor_id
& 0xf) < 0x3) {
395 c
->cputype
= CPU_VR4122
;
396 __cpu_name
[cpu
] = "NEC VR4122";
398 c
->cputype
= CPU_VR4181A
;
399 __cpu_name
[cpu
] = "NEC VR4181A";
402 case PRID_REV_VR4130
:
403 if ((c
->processor_id
& 0xf) < 0x4) {
404 c
->cputype
= CPU_VR4131
;
405 __cpu_name
[cpu
] = "NEC VR4131";
407 c
->cputype
= CPU_VR4133
;
408 __cpu_name
[cpu
] = "NEC VR4133";
412 printk(KERN_INFO
"Unexpected CPU of NEC VR4100 series\n");
413 c
->cputype
= CPU_VR41XX
;
414 __cpu_name
[cpu
] = "NEC Vr41xx";
417 c
->isa_level
= MIPS_CPU_ISA_III
;
418 c
->options
= R4K_OPTS
;
422 c
->cputype
= CPU_R4300
;
423 __cpu_name
[cpu
] = "R4300";
424 c
->isa_level
= MIPS_CPU_ISA_III
;
425 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
430 c
->cputype
= CPU_R4600
;
431 __cpu_name
[cpu
] = "R4600";
432 c
->isa_level
= MIPS_CPU_ISA_III
;
433 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
440 * This processor doesn't have an MMU, so it's not
441 * "real easy" to run Linux on it. It is left purely
442 * for documentation. Commented out because it shares
443 * it's c0_prid id number with the TX3900.
445 c
->cputype
= CPU_R4650
;
446 __cpu_name
[cpu
] = "R4650";
447 c
->isa_level
= MIPS_CPU_ISA_III
;
448 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_LLSC
;
453 c
->isa_level
= MIPS_CPU_ISA_I
;
454 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_TX39_CACHE
;
456 if ((c
->processor_id
& 0xf0) == (PRID_REV_TX3927
& 0xf0)) {
457 c
->cputype
= CPU_TX3927
;
458 __cpu_name
[cpu
] = "TX3927";
461 switch (c
->processor_id
& 0xff) {
462 case PRID_REV_TX3912
:
463 c
->cputype
= CPU_TX3912
;
464 __cpu_name
[cpu
] = "TX3912";
467 case PRID_REV_TX3922
:
468 c
->cputype
= CPU_TX3922
;
469 __cpu_name
[cpu
] = "TX3922";
476 c
->cputype
= CPU_R4700
;
477 __cpu_name
[cpu
] = "R4700";
478 c
->isa_level
= MIPS_CPU_ISA_III
;
479 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
484 c
->cputype
= CPU_TX49XX
;
485 __cpu_name
[cpu
] = "R49XX";
486 c
->isa_level
= MIPS_CPU_ISA_III
;
487 c
->options
= R4K_OPTS
| MIPS_CPU_LLSC
;
488 if (!(c
->processor_id
& 0x08))
489 c
->options
|= MIPS_CPU_FPU
| MIPS_CPU_32FPR
;
493 c
->cputype
= CPU_R5000
;
494 __cpu_name
[cpu
] = "R5000";
495 c
->isa_level
= MIPS_CPU_ISA_IV
;
496 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
501 c
->cputype
= CPU_R5432
;
502 __cpu_name
[cpu
] = "R5432";
503 c
->isa_level
= MIPS_CPU_ISA_IV
;
504 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
505 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
509 c
->cputype
= CPU_R5500
;
510 __cpu_name
[cpu
] = "R5500";
511 c
->isa_level
= MIPS_CPU_ISA_IV
;
512 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
513 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
516 case PRID_IMP_NEVADA
:
517 c
->cputype
= CPU_NEVADA
;
518 __cpu_name
[cpu
] = "Nevada";
519 c
->isa_level
= MIPS_CPU_ISA_IV
;
520 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
521 MIPS_CPU_DIVEC
| MIPS_CPU_LLSC
;
525 c
->cputype
= CPU_R6000
;
526 __cpu_name
[cpu
] = "R6000";
527 c
->isa_level
= MIPS_CPU_ISA_II
;
528 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
532 case PRID_IMP_R6000A
:
533 c
->cputype
= CPU_R6000A
;
534 __cpu_name
[cpu
] = "R6000A";
535 c
->isa_level
= MIPS_CPU_ISA_II
;
536 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
540 case PRID_IMP_RM7000
:
541 c
->cputype
= CPU_RM7000
;
542 __cpu_name
[cpu
] = "RM7000";
543 c
->isa_level
= MIPS_CPU_ISA_IV
;
544 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
547 * Undocumented RM7000: Bit 29 in the info register of
548 * the RM7000 v2.0 indicates if the TLB has 48 or 64
551 * 29 1 => 64 entry JTLB
554 c
->tlbsize
= (read_c0_info() & (1 << 29)) ? 64 : 48;
556 case PRID_IMP_RM9000
:
557 c
->cputype
= CPU_RM9000
;
558 __cpu_name
[cpu
] = "RM9000";
559 c
->isa_level
= MIPS_CPU_ISA_IV
;
560 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
563 * Bit 29 in the info register of the RM9000
564 * indicates if the TLB has 48 or 64 entries.
566 * 29 1 => 64 entry JTLB
569 c
->tlbsize
= (read_c0_info() & (1 << 29)) ? 64 : 48;
572 c
->cputype
= CPU_R8000
;
573 __cpu_name
[cpu
] = "RM8000";
574 c
->isa_level
= MIPS_CPU_ISA_IV
;
575 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4KEX
|
576 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
578 c
->tlbsize
= 384; /* has weird TLB: 3-way x 128 */
580 case PRID_IMP_R10000
:
581 c
->cputype
= CPU_R10000
;
582 __cpu_name
[cpu
] = "R10000";
583 c
->isa_level
= MIPS_CPU_ISA_IV
;
584 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
585 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
586 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
590 case PRID_IMP_R12000
:
591 c
->cputype
= CPU_R12000
;
592 __cpu_name
[cpu
] = "R12000";
593 c
->isa_level
= MIPS_CPU_ISA_IV
;
594 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
595 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
596 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
600 case PRID_IMP_R14000
:
601 c
->cputype
= CPU_R14000
;
602 __cpu_name
[cpu
] = "R14000";
603 c
->isa_level
= MIPS_CPU_ISA_IV
;
604 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
605 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
606 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
610 case PRID_IMP_LOONGSON2
:
611 c
->cputype
= CPU_LOONGSON2
;
612 __cpu_name
[cpu
] = "ICT Loongson-2";
613 c
->isa_level
= MIPS_CPU_ISA_III
;
614 c
->options
= R4K_OPTS
|
615 MIPS_CPU_FPU
| MIPS_CPU_LLSC
|
622 static char unknown_isa
[] __cpuinitdata
= KERN_ERR \
623 "Unsupported ISA type, c0.config0: %d.";
625 static inline unsigned int decode_config0(struct cpuinfo_mips
*c
)
627 unsigned int config0
;
630 config0
= read_c0_config();
632 if (((config0
& MIPS_CONF_MT
) >> 7) == 1)
633 c
->options
|= MIPS_CPU_TLB
;
634 isa
= (config0
& MIPS_CONF_AT
) >> 13;
637 switch ((config0
& MIPS_CONF_AR
) >> 10) {
639 c
->isa_level
= MIPS_CPU_ISA_M32R1
;
642 c
->isa_level
= MIPS_CPU_ISA_M32R2
;
649 switch ((config0
& MIPS_CONF_AR
) >> 10) {
651 c
->isa_level
= MIPS_CPU_ISA_M64R1
;
654 c
->isa_level
= MIPS_CPU_ISA_M64R2
;
664 return config0
& MIPS_CONF_M
;
667 panic(unknown_isa
, config0
);
670 static inline unsigned int decode_config1(struct cpuinfo_mips
*c
)
672 unsigned int config1
;
674 config1
= read_c0_config1();
676 if (config1
& MIPS_CONF1_MD
)
677 c
->ases
|= MIPS_ASE_MDMX
;
678 if (config1
& MIPS_CONF1_WR
)
679 c
->options
|= MIPS_CPU_WATCH
;
680 if (config1
& MIPS_CONF1_CA
)
681 c
->ases
|= MIPS_ASE_MIPS16
;
682 if (config1
& MIPS_CONF1_EP
)
683 c
->options
|= MIPS_CPU_EJTAG
;
684 if (config1
& MIPS_CONF1_FP
) {
685 c
->options
|= MIPS_CPU_FPU
;
686 c
->options
|= MIPS_CPU_32FPR
;
689 c
->tlbsize
= ((config1
& MIPS_CONF1_TLBS
) >> 25) + 1;
691 return config1
& MIPS_CONF_M
;
694 static inline unsigned int decode_config2(struct cpuinfo_mips
*c
)
696 unsigned int config2
;
698 config2
= read_c0_config2();
700 if (config2
& MIPS_CONF2_SL
)
701 c
->scache
.flags
&= ~MIPS_CACHE_NOT_PRESENT
;
703 return config2
& MIPS_CONF_M
;
706 static inline unsigned int decode_config3(struct cpuinfo_mips
*c
)
708 unsigned int config3
;
710 config3
= read_c0_config3();
712 if (config3
& MIPS_CONF3_SM
)
713 c
->ases
|= MIPS_ASE_SMARTMIPS
;
714 if (config3
& MIPS_CONF3_DSP
)
715 c
->ases
|= MIPS_ASE_DSP
;
716 if (config3
& MIPS_CONF3_VINT
)
717 c
->options
|= MIPS_CPU_VINT
;
718 if (config3
& MIPS_CONF3_VEIC
)
719 c
->options
|= MIPS_CPU_VEIC
;
720 if (config3
& MIPS_CONF3_MT
)
721 c
->ases
|= MIPS_ASE_MIPSMT
;
722 if (config3
& MIPS_CONF3_ULRI
)
723 c
->options
|= MIPS_CPU_ULRI
;
725 return config3
& MIPS_CONF_M
;
728 static inline unsigned int decode_config4(struct cpuinfo_mips
*c
)
730 unsigned int config4
;
732 config4
= read_c0_config4();
734 if ((config4
& MIPS_CONF4_MMUEXTDEF
) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
736 c
->tlbsize
+= (config4
& MIPS_CONF4_MMUSIZEEXT
) * 0x40;
738 return config4
& MIPS_CONF_M
;
741 static void __cpuinit
decode_configs(struct cpuinfo_mips
*c
)
745 /* MIPS32 or MIPS64 compliant CPU. */
746 c
->options
= MIPS_CPU_4KEX
| MIPS_CPU_4K_CACHE
| MIPS_CPU_COUNTER
|
747 MIPS_CPU_DIVEC
| MIPS_CPU_LLSC
| MIPS_CPU_MCHECK
;
749 c
->scache
.flags
= MIPS_CACHE_NOT_PRESENT
;
751 ok
= decode_config0(c
); /* Read Config registers. */
752 BUG_ON(!ok
); /* Arch spec violation! */
754 ok
= decode_config1(c
);
756 ok
= decode_config2(c
);
758 ok
= decode_config3(c
);
760 ok
= decode_config4(c
);
762 mips_probe_watch_registers(c
);
765 static inline void cpu_probe_mips(struct cpuinfo_mips
*c
, unsigned int cpu
)
768 switch (c
->processor_id
& 0xff00) {
770 c
->cputype
= CPU_4KC
;
771 __cpu_name
[cpu
] = "MIPS 4Kc";
774 case PRID_IMP_4KECR2
:
775 c
->cputype
= CPU_4KEC
;
776 __cpu_name
[cpu
] = "MIPS 4KEc";
780 c
->cputype
= CPU_4KSC
;
781 __cpu_name
[cpu
] = "MIPS 4KSc";
784 c
->cputype
= CPU_5KC
;
785 __cpu_name
[cpu
] = "MIPS 5Kc";
788 c
->cputype
= CPU_20KC
;
789 __cpu_name
[cpu
] = "MIPS 20Kc";
793 c
->cputype
= CPU_24K
;
794 __cpu_name
[cpu
] = "MIPS 24Kc";
797 c
->cputype
= CPU_25KF
;
798 __cpu_name
[cpu
] = "MIPS 25Kc";
801 c
->cputype
= CPU_34K
;
802 __cpu_name
[cpu
] = "MIPS 34Kc";
805 c
->cputype
= CPU_74K
;
806 __cpu_name
[cpu
] = "MIPS 74Kc";
809 c
->cputype
= CPU_1004K
;
810 __cpu_name
[cpu
] = "MIPS 1004Kc";
817 static inline void cpu_probe_alchemy(struct cpuinfo_mips
*c
, unsigned int cpu
)
820 switch (c
->processor_id
& 0xff00) {
821 case PRID_IMP_AU1_REV1
:
822 case PRID_IMP_AU1_REV2
:
823 c
->cputype
= CPU_ALCHEMY
;
824 switch ((c
->processor_id
>> 24) & 0xff) {
826 __cpu_name
[cpu
] = "Au1000";
829 __cpu_name
[cpu
] = "Au1500";
832 __cpu_name
[cpu
] = "Au1100";
835 __cpu_name
[cpu
] = "Au1550";
838 __cpu_name
[cpu
] = "Au1200";
839 if ((c
->processor_id
& 0xff) == 2)
840 __cpu_name
[cpu
] = "Au1250";
843 __cpu_name
[cpu
] = "Au1210";
846 __cpu_name
[cpu
] = "Au1xxx";
853 static inline void cpu_probe_sibyte(struct cpuinfo_mips
*c
, unsigned int cpu
)
857 switch (c
->processor_id
& 0xff00) {
859 c
->cputype
= CPU_SB1
;
860 __cpu_name
[cpu
] = "SiByte SB1";
861 /* FPU in pass1 is known to have issues. */
862 if ((c
->processor_id
& 0xff) < 0x02)
863 c
->options
&= ~(MIPS_CPU_FPU
| MIPS_CPU_32FPR
);
866 c
->cputype
= CPU_SB1A
;
867 __cpu_name
[cpu
] = "SiByte SB1A";
872 static inline void cpu_probe_sandcraft(struct cpuinfo_mips
*c
, unsigned int cpu
)
875 switch (c
->processor_id
& 0xff00) {
876 case PRID_IMP_SR71000
:
877 c
->cputype
= CPU_SR71000
;
878 __cpu_name
[cpu
] = "Sandcraft SR71000";
885 static inline void cpu_probe_nxp(struct cpuinfo_mips
*c
, unsigned int cpu
)
888 switch (c
->processor_id
& 0xff00) {
889 case PRID_IMP_PR4450
:
890 c
->cputype
= CPU_PR4450
;
891 __cpu_name
[cpu
] = "Philips PR4450";
892 c
->isa_level
= MIPS_CPU_ISA_M32R1
;
897 static inline void cpu_probe_broadcom(struct cpuinfo_mips
*c
, unsigned int cpu
)
900 switch (c
->processor_id
& 0xff00) {
901 case PRID_IMP_BCM3302
:
902 /* same as PRID_IMP_BCM6338 */
903 c
->cputype
= CPU_BCM3302
;
904 __cpu_name
[cpu
] = "Broadcom BCM3302";
906 case PRID_IMP_BCM4710
:
907 c
->cputype
= CPU_BCM4710
;
908 __cpu_name
[cpu
] = "Broadcom BCM4710";
910 case PRID_IMP_BCM6345
:
911 c
->cputype
= CPU_BCM6345
;
912 __cpu_name
[cpu
] = "Broadcom BCM6345";
914 case PRID_IMP_BCM6348
:
915 c
->cputype
= CPU_BCM6348
;
916 __cpu_name
[cpu
] = "Broadcom BCM6348";
918 case PRID_IMP_BCM4350
:
919 switch (c
->processor_id
& 0xf0) {
920 case PRID_REV_BCM6358
:
921 c
->cputype
= CPU_BCM6358
;
922 __cpu_name
[cpu
] = "Broadcom BCM6358";
925 c
->cputype
= CPU_UNKNOWN
;
932 static inline void cpu_probe_cavium(struct cpuinfo_mips
*c
, unsigned int cpu
)
935 switch (c
->processor_id
& 0xff00) {
936 case PRID_IMP_CAVIUM_CN38XX
:
937 case PRID_IMP_CAVIUM_CN31XX
:
938 case PRID_IMP_CAVIUM_CN30XX
:
939 c
->cputype
= CPU_CAVIUM_OCTEON
;
940 __cpu_name
[cpu
] = "Cavium Octeon";
942 case PRID_IMP_CAVIUM_CN58XX
:
943 case PRID_IMP_CAVIUM_CN56XX
:
944 case PRID_IMP_CAVIUM_CN50XX
:
945 case PRID_IMP_CAVIUM_CN52XX
:
946 c
->cputype
= CPU_CAVIUM_OCTEON_PLUS
;
947 __cpu_name
[cpu
] = "Cavium Octeon+";
950 __elf_platform
= "octeon";
953 printk(KERN_INFO
"Unknown Octeon chip!\n");
954 c
->cputype
= CPU_UNKNOWN
;
959 const char *__cpu_name
[NR_CPUS
];
960 const char *__elf_platform
;
962 __cpuinit
void cpu_probe(void)
964 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
965 unsigned int cpu
= smp_processor_id();
967 c
->processor_id
= PRID_IMP_UNKNOWN
;
968 c
->fpu_id
= FPIR_IMP_NONE
;
969 c
->cputype
= CPU_UNKNOWN
;
971 c
->processor_id
= read_c0_prid();
972 switch (c
->processor_id
& 0xff0000) {
973 case PRID_COMP_LEGACY
:
974 cpu_probe_legacy(c
, cpu
);
977 cpu_probe_mips(c
, cpu
);
979 case PRID_COMP_ALCHEMY
:
980 cpu_probe_alchemy(c
, cpu
);
982 case PRID_COMP_SIBYTE
:
983 cpu_probe_sibyte(c
, cpu
);
985 case PRID_COMP_BROADCOM
:
986 cpu_probe_broadcom(c
, cpu
);
988 case PRID_COMP_SANDCRAFT
:
989 cpu_probe_sandcraft(c
, cpu
);
992 cpu_probe_nxp(c
, cpu
);
994 case PRID_COMP_CAVIUM
:
995 cpu_probe_cavium(c
, cpu
);
999 BUG_ON(!__cpu_name
[cpu
]);
1000 BUG_ON(c
->cputype
== CPU_UNKNOWN
);
1003 * Platform code can force the cpu type to optimize code
1004 * generation. In that case be sure the cpu type is correctly
1005 * manually setup otherwise it could trigger some nasty bugs.
1007 BUG_ON(current_cpu_type() != c
->cputype
);
1009 if (mips_fpu_disabled
)
1010 c
->options
&= ~MIPS_CPU_FPU
;
1012 if (mips_dsp_disabled
)
1013 c
->ases
&= ~MIPS_ASE_DSP
;
1015 if (c
->options
& MIPS_CPU_FPU
) {
1016 c
->fpu_id
= cpu_get_fpu_id();
1018 if (c
->isa_level
== MIPS_CPU_ISA_M32R1
||
1019 c
->isa_level
== MIPS_CPU_ISA_M32R2
||
1020 c
->isa_level
== MIPS_CPU_ISA_M64R1
||
1021 c
->isa_level
== MIPS_CPU_ISA_M64R2
) {
1022 if (c
->fpu_id
& MIPS_FPIR_3D
)
1023 c
->ases
|= MIPS_ASE_MIPS3D
;
1027 if (cpu_has_mips_r2
)
1028 c
->srsets
= ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1032 cpu_probe_vmbits(c
);
1035 __cpuinit
void cpu_report(void)
1037 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1039 printk(KERN_INFO
"CPU revision is: %08x (%s)\n",
1040 c
->processor_id
, cpu_name_string());
1041 if (c
->options
& MIPS_CPU_FPU
)
1042 printk(KERN_INFO
"FPU revision is: %08x\n", c
->fpu_id
);