| blob | 35a26d42ef38f2137bbd411a3086353851077cd4 |
1 config ARM
2 bool
3 default y
4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_WANT_IPC_PARSE_VERSION
8 select CPU_PM if (SUSPEND || CPU_IDLE)
9 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
12 select GENERIC_IRQ_PROBE
13 select GENERIC_IRQ_SHOW
14 select GENERIC_KERNEL_THREAD
15 select GENERIC_KERNEL_EXECVE
16 select GENERIC_PCI_IOMAP
17 select GENERIC_SMP_IDLE_THREAD
18 select GENERIC_STRNCPY_FROM_USER
19 select GENERIC_STRNLEN_USER
20 select HARDIRQS_SW_RESEND
21 select HAVE_AOUT
22 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
23 select HAVE_ARCH_KGDB
24 select HAVE_ARCH_TRACEHOOK
25 select HAVE_BPF_JIT
26 select HAVE_C_RECORDMCOUNT
27 select HAVE_DEBUG_KMEMLEAK
28 select HAVE_DMA_API_DEBUG
29 select HAVE_DMA_ATTRS
30 select HAVE_DMA_CONTIGUOUS if MMU
31 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
32 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
33 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
34 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
35 select HAVE_GENERIC_DMA_COHERENT
36 select HAVE_GENERIC_HARDIRQS
37 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
38 select HAVE_IDE if PCI || ISA || PCMCIA
39 select HAVE_IRQ_WORK
40 select HAVE_KERNEL_GZIP
41 select HAVE_KERNEL_LZMA
42 select HAVE_KERNEL_LZO
43 select HAVE_KERNEL_XZ
44 select HAVE_KPROBES if !XIP_KERNEL
45 select HAVE_KRETPROBES if (HAVE_KPROBES)
46 select HAVE_MEMBLOCK
47 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
48 select HAVE_PERF_EVENTS
49 select HAVE_REGS_AND_STACK_ACCESS_API
50 select HAVE_SYSCALL_TRACEPOINTS
51 select HAVE_UID16
52 select KTIME_SCALAR
53 select PERF_USE_VMALLOC
54 select RTC_LIB
55 select SYS_SUPPORTS_APM_EMULATION
56 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
57 select MODULES_USE_ELF_REL
58 help
59 The ARM series is a line of low-power-consumption RISC chip designs
60 licensed by ARM Ltd and targeted at embedded applications and
61 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
62 manufactured, but legacy ARM-based PC hardware remains popular in
63 Europe. There is an ARM Linux project with a web page at
64 <http://www.arm.linux.org.uk/>.
66 config ARM_HAS_SG_CHAIN
67 bool
69 config NEED_SG_DMA_LENGTH
70 bool
72 config ARM_DMA_USE_IOMMU
73 bool
74 select ARM_HAS_SG_CHAIN
75 select NEED_SG_DMA_LENGTH
77 config HAVE_PWM
78 bool
80 config MIGHT_HAVE_PCI
81 bool
83 config SYS_SUPPORTS_APM_EMULATION
84 bool
86 config GENERIC_GPIO
87 bool
89 config HAVE_TCM
90 bool
91 select GENERIC_ALLOCATOR
93 config HAVE_PROC_CPU
94 bool
96 config NO_IOPORT
97 bool
99 config EISA
100 bool
101 ---help---
102 The Extended Industry Standard Architecture (EISA) bus was
103 developed as an open alternative to the IBM MicroChannel bus.
105 The EISA bus provided some of the features of the IBM MicroChannel
106 bus while maintaining backward compatibility with cards made for
107 the older ISA bus. The EISA bus saw limited use between 1988 and
108 1995 when it was made obsolete by the PCI bus.
110 Say Y here if you are building a kernel for an EISA-based machine.
112 Otherwise, say N.
114 config SBUS
115 bool
117 config STACKTRACE_SUPPORT
118 bool
119 default y
121 config HAVE_LATENCYTOP_SUPPORT
122 bool
123 depends on !SMP
124 default y
126 config LOCKDEP_SUPPORT
127 bool
128 default y
130 config TRACE_IRQFLAGS_SUPPORT
131 bool
132 default y
134 config RWSEM_GENERIC_SPINLOCK
135 bool
136 default y
138 config RWSEM_XCHGADD_ALGORITHM
139 bool
141 config ARCH_HAS_ILOG2_U32
142 bool
144 config ARCH_HAS_ILOG2_U64
145 bool
147 config ARCH_HAS_CPUFREQ
148 bool
149 help
150 Internal node to signify that the ARCH has CPUFREQ support
151 and that the relevant menu configurations are displayed for
152 it.
154 config GENERIC_HWEIGHT
155 bool
156 default y
158 config GENERIC_CALIBRATE_DELAY
159 bool
160 default y
162 config ARCH_MAY_HAVE_PC_FDC
163 bool
165 config ZONE_DMA
166 bool
168 config NEED_DMA_MAP_STATE
169 def_bool y
171 config ARCH_HAS_DMA_SET_COHERENT_MASK
172 bool
174 config GENERIC_ISA_DMA
175 bool
177 config FIQ
178 bool
180 config NEED_RET_TO_USER
181 bool
183 config ARCH_MTD_XIP
184 bool
186 config VECTORS_BASE
187 hex
188 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
189 default DRAM_BASE if REMAP_VECTORS_TO_RAM
190 default 0x00000000
191 help
192 The base address of exception vectors.
194 config ARM_PATCH_PHYS_VIRT
195 bool "Patch physical to virtual translations at runtime" if EMBEDDED
196 default y
197 depends on !XIP_KERNEL && MMU
198 depends on !ARCH_REALVIEW || !SPARSEMEM
199 help
200 Patch phys-to-virt and virt-to-phys translation functions at
201 boot and module load time according to the position of the
202 kernel in system memory.
204 This can only be used with non-XIP MMU kernels where the base
205 of physical memory is at a 16MB boundary.
207 Only disable this option if you know that you do not require
208 this feature (eg, building a kernel for a single machine) and
209 you need to shrink the kernel to the minimal size.
211 config NEED_MACH_GPIO_H
212 bool
213 help
214 Select this when mach/gpio.h is required to provide special
215 definitions for this platform. The need for mach/gpio.h should
216 be avoided when possible.
218 config NEED_MACH_IO_H
219 bool
220 help
221 Select this when mach/io.h is required to provide special
222 definitions for this platform. The need for mach/io.h should
223 be avoided when possible.
225 config NEED_MACH_MEMORY_H
226 bool
227 help
228 Select this when mach/memory.h is required to provide special
229 definitions for this platform. The need for mach/memory.h should
230 be avoided when possible.
232 config PHYS_OFFSET
233 hex "Physical address of main memory" if MMU
234 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
235 default DRAM_BASE if !MMU
236 help
237 Please provide the physical address corresponding to the
238 location of main memory in your system.
240 config GENERIC_BUG
241 def_bool y
242 depends on BUG
244 source "init/Kconfig"
246 source "kernel/Kconfig.freezer"
248 menu "System Type"
250 config MMU
251 bool "MMU-based Paged Memory Management Support"
252 default y
253 help
254 Select if you want MMU-based virtualised addressing space
255 support by paged memory management. If unsure, say 'Y'.
257 #
258 # The "ARM system type" choice list is ordered alphabetically by option
259 # text. Please add new entries in the option alphabetic order.
260 #
261 choice
262 prompt "ARM system type"
263 default ARCH_MULTIPLATFORM
265 config ARCH_MULTIPLATFORM
266 bool "Allow multiple platforms to be selected"
267 depends on MMU
268 select ARM_PATCH_PHYS_VIRT
269 select AUTO_ZRELADDR
270 select COMMON_CLK
271 select MULTI_IRQ_HANDLER
272 select SPARSE_IRQ
273 select USE_OF
275 config ARCH_INTEGRATOR
276 bool "ARM Ltd. Integrator family"
277 select ARCH_HAS_CPUFREQ
278 select ARM_AMBA
279 select COMMON_CLK
280 select COMMON_CLK_VERSATILE
281 select GENERIC_CLOCKEVENTS
282 select HAVE_TCM
283 select ICST
284 select MULTI_IRQ_HANDLER
285 select NEED_MACH_MEMORY_H
286 select PLAT_VERSATILE
287 select PLAT_VERSATILE_FPGA_IRQ
288 select SPARSE_IRQ
289 help
290 Support for ARM's Integrator platform.
292 config ARCH_REALVIEW
293 bool "ARM Ltd. RealView family"
294 select ARCH_WANT_OPTIONAL_GPIOLIB
295 select ARM_AMBA
296 select ARM_TIMER_SP804
297 select COMMON_CLK
298 select COMMON_CLK_VERSATILE
299 select GENERIC_CLOCKEVENTS
300 select GPIO_PL061 if GPIOLIB
301 select ICST
302 select NEED_MACH_MEMORY_H
303 select PLAT_VERSATILE
304 select PLAT_VERSATILE_CLCD
305 help
306 This enables support for ARM Ltd RealView boards.
308 config ARCH_VERSATILE
309 bool "ARM Ltd. Versatile family"
310 select ARCH_WANT_OPTIONAL_GPIOLIB
311 select ARM_AMBA
312 select ARM_TIMER_SP804
313 select ARM_VIC
314 select CLKDEV_LOOKUP
315 select GENERIC_CLOCKEVENTS
316 select HAVE_MACH_CLKDEV
317 select ICST
318 select PLAT_VERSATILE
319 select PLAT_VERSATILE_CLCD
320 select PLAT_VERSATILE_CLOCK
321 select PLAT_VERSATILE_FPGA_IRQ
322 help
323 This enables support for ARM Ltd Versatile board.
325 config ARCH_AT91
326 bool "Atmel AT91"
327 select ARCH_REQUIRE_GPIOLIB
328 select CLKDEV_LOOKUP
329 select HAVE_CLK
330 select IRQ_DOMAIN
331 select NEED_MACH_GPIO_H
332 select NEED_MACH_IO_H if PCCARD
333 help
334 This enables support for systems based on Atmel
335 AT91RM9200 and AT91SAM9* processors.
337 config ARCH_BCM2835
338 bool "Broadcom BCM2835 family"
339 select ARCH_WANT_OPTIONAL_GPIOLIB
340 select ARM_AMBA
341 select ARM_ERRATA_411920
342 select ARM_TIMER_SP804
343 select CLKDEV_LOOKUP
344 select COMMON_CLK
345 select CPU_V6
346 select GENERIC_CLOCKEVENTS
347 select MULTI_IRQ_HANDLER
348 select SPARSE_IRQ
349 select USE_OF
350 help
351 This enables support for the Broadcom BCM2835 SoC. This SoC is
352 use in the Raspberry Pi, and Roku 2 devices.
354 config ARCH_CNS3XXX
355 bool "Cavium Networks CNS3XXX family"
356 select ARM_GIC
357 select CPU_V6K
358 select GENERIC_CLOCKEVENTS
359 select MIGHT_HAVE_CACHE_L2X0
360 select MIGHT_HAVE_PCI
361 select PCI_DOMAINS if PCI
362 help
363 Support for Cavium Networks CNS3XXX platform.
365 config ARCH_CLPS711X
366 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
367 select ARCH_USES_GETTIMEOFFSET
368 select CLKDEV_LOOKUP
369 select COMMON_CLK
370 select CPU_ARM720T
371 select NEED_MACH_MEMORY_H
372 help
373 Support for Cirrus Logic 711x/721x/731x based boards.
375 config ARCH_GEMINI
376 bool "Cortina Systems Gemini"
377 select ARCH_REQUIRE_GPIOLIB
378 select ARCH_USES_GETTIMEOFFSET
379 select CPU_FA526
380 help
381 Support for the Cortina Systems Gemini family SoCs
383 config ARCH_SIRF
384 bool "CSR SiRF"
385 select ARCH_REQUIRE_GPIOLIB
386 select COMMON_CLK
387 select GENERIC_CLOCKEVENTS
388 select GENERIC_IRQ_CHIP
389 select MIGHT_HAVE_CACHE_L2X0
390 select NO_IOPORT
391 select PINCTRL
392 select PINCTRL_SIRF
393 select USE_OF
394 help
395 Support for CSR SiRFprimaII/Marco/Polo platforms
397 config ARCH_EBSA110
398 bool "EBSA-110"
399 select ARCH_USES_GETTIMEOFFSET
400 select CPU_SA110
401 select ISA
402 select NEED_MACH_IO_H
403 select NEED_MACH_MEMORY_H
404 select NO_IOPORT
405 help
406 This is an evaluation board for the StrongARM processor available
407 from Digital. It has limited hardware on-board, including an
408 Ethernet interface, two PCMCIA sockets, two serial ports and a
409 parallel port.
411 config ARCH_EP93XX
412 bool "EP93xx-based"
413 select ARCH_HAS_HOLES_MEMORYMODEL
414 select ARCH_REQUIRE_GPIOLIB
415 select ARCH_USES_GETTIMEOFFSET
416 select ARM_AMBA
417 select ARM_VIC
418 select CLKDEV_LOOKUP
419 select CPU_ARM920T
420 select NEED_MACH_MEMORY_H
421 help
422 This enables support for the Cirrus EP93xx series of CPUs.
424 config ARCH_FOOTBRIDGE
425 bool "FootBridge"
426 select CPU_SA110
427 select FOOTBRIDGE
428 select GENERIC_CLOCKEVENTS
429 select HAVE_IDE
430 select NEED_MACH_IO_H if !MMU
431 select NEED_MACH_MEMORY_H
432 help
433 Support for systems based on the DC21285 companion chip
434 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
436 config ARCH_MXC
437 bool "Freescale MXC/iMX-based"
438 select ARCH_REQUIRE_GPIOLIB
439 select CLKDEV_LOOKUP
440 select CLKSRC_MMIO
441 select GENERIC_CLOCKEVENTS
442 select GENERIC_IRQ_CHIP
443 select MULTI_IRQ_HANDLER
444 select SPARSE_IRQ
445 select USE_OF
446 help
447 Support for Freescale MXC/iMX-based family of processors
449 config ARCH_MXS
450 bool "Freescale MXS-based"
451 select ARCH_REQUIRE_GPIOLIB
452 select CLKDEV_LOOKUP
453 select CLKSRC_MMIO
454 select COMMON_CLK
455 select GENERIC_CLOCKEVENTS
456 select HAVE_CLK_PREPARE
457 select MULTI_IRQ_HANDLER
458 select PINCTRL
459 select SPARSE_IRQ
460 select USE_OF
461 help
462 Support for Freescale MXS-based family of processors
464 config ARCH_NETX
465 bool "Hilscher NetX based"
466 select ARM_VIC
467 select CLKSRC_MMIO
468 select CPU_ARM926T
469 select GENERIC_CLOCKEVENTS
470 help
471 This enables support for systems based on the Hilscher NetX Soc
473 config ARCH_H720X
474 bool "Hynix HMS720x-based"
475 select ARCH_USES_GETTIMEOFFSET
476 select CPU_ARM720T
477 select ISA_DMA_API
478 help
479 This enables support for systems based on the Hynix HMS720x
481 config ARCH_IOP13XX
482 bool "IOP13xx-based"
483 depends on MMU
484 select ARCH_SUPPORTS_MSI
485 select CPU_XSC3
486 select NEED_MACH_MEMORY_H
487 select NEED_RET_TO_USER
488 select PCI
489 select PLAT_IOP
490 select VMSPLIT_1G
491 help
492 Support for Intel's IOP13XX (XScale) family of processors.
494 config ARCH_IOP32X
495 bool "IOP32x-based"
496 depends on MMU
497 select ARCH_REQUIRE_GPIOLIB
498 select CPU_XSCALE
499 select NEED_MACH_GPIO_H
500 select NEED_RET_TO_USER
501 select PCI
502 select PLAT_IOP
503 help
504 Support for Intel's 80219 and IOP32X (XScale) family of
505 processors.
507 config ARCH_IOP33X
508 bool "IOP33x-based"
509 depends on MMU
510 select ARCH_REQUIRE_GPIOLIB
511 select CPU_XSCALE
512 select NEED_MACH_GPIO_H
513 select NEED_RET_TO_USER
514 select PCI
515 select PLAT_IOP
516 help
517 Support for Intel's IOP33X (XScale) family of processors.
519 config ARCH_IXP4XX
520 bool "IXP4xx-based"
521 depends on MMU
522 select ARCH_HAS_DMA_SET_COHERENT_MASK
523 select ARCH_REQUIRE_GPIOLIB
524 select CLKSRC_MMIO
525 select CPU_XSCALE
526 select DMABOUNCE if PCI
527 select GENERIC_CLOCKEVENTS
528 select MIGHT_HAVE_PCI
529 select NEED_MACH_IO_H
530 help
531 Support for Intel's IXP4XX (XScale) family of processors.
533 config ARCH_DOVE
534 bool "Marvell Dove"
535 select ARCH_REQUIRE_GPIOLIB
536 select CPU_V7
537 select GENERIC_CLOCKEVENTS
538 select MIGHT_HAVE_PCI
539 select PLAT_ORION_LEGACY
540 select USB_ARCH_HAS_EHCI
541 help
542 Support for the Marvell Dove SoC 88AP510
544 config ARCH_KIRKWOOD
545 bool "Marvell Kirkwood"
546 select ARCH_REQUIRE_GPIOLIB
547 select CPU_FEROCEON
548 select GENERIC_CLOCKEVENTS
549 select PCI
550 select PLAT_ORION_LEGACY
551 help
552 Support for the following Marvell Kirkwood series SoCs:
553 88F6180, 88F6192 and 88F6281.
555 config ARCH_MV78XX0
556 bool "Marvell MV78xx0"
557 select ARCH_REQUIRE_GPIOLIB
558 select CPU_FEROCEON
559 select GENERIC_CLOCKEVENTS
560 select PCI
561 select PLAT_ORION_LEGACY
562 help
563 Support for the following Marvell MV78xx0 series SoCs:
564 MV781x0, MV782x0.
566 config ARCH_ORION5X
567 bool "Marvell Orion"
568 depends on MMU
569 select ARCH_REQUIRE_GPIOLIB
570 select CPU_FEROCEON
571 select GENERIC_CLOCKEVENTS
572 select PCI
573 select PLAT_ORION_LEGACY
574 help
575 Support for the following Marvell Orion 5x series SoCs:
576 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
577 Orion-2 (5281), Orion-1-90 (6183).
579 config ARCH_MMP
580 bool "Marvell PXA168/910/MMP2"
581 depends on MMU
582 select ARCH_REQUIRE_GPIOLIB
583 select CLKDEV_LOOKUP
584 select GENERIC_ALLOCATOR
585 select GENERIC_CLOCKEVENTS
586 select GPIO_PXA
587 select IRQ_DOMAIN
588 select NEED_MACH_GPIO_H
589 select PLAT_PXA
590 select SPARSE_IRQ
591 help
592 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
594 config ARCH_KS8695
595 bool "Micrel/Kendin KS8695"
596 select ARCH_REQUIRE_GPIOLIB
597 select CLKSRC_MMIO
598 select CPU_ARM922T
599 select GENERIC_CLOCKEVENTS
600 select NEED_MACH_MEMORY_H
601 help
602 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
603 System-on-Chip devices.
605 config ARCH_W90X900
606 bool "Nuvoton W90X900 CPU"
607 select ARCH_REQUIRE_GPIOLIB
608 select CLKDEV_LOOKUP
609 select CLKSRC_MMIO
610 select CPU_ARM926T
611 select GENERIC_CLOCKEVENTS
612 help
613 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
614 At present, the w90x900 has been renamed nuc900, regarding
615 the ARM series product line, you can login the following
616 link address to know more.
618 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
619 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
621 config ARCH_LPC32XX
622 bool "NXP LPC32XX"
623 select ARCH_REQUIRE_GPIOLIB
624 select ARM_AMBA
625 select CLKDEV_LOOKUP
626 select CLKSRC_MMIO
627 select CPU_ARM926T
628 select GENERIC_CLOCKEVENTS
629 select HAVE_IDE
630 select HAVE_PWM
631 select USB_ARCH_HAS_OHCI
632 select USE_OF
633 help
634 Support for the NXP LPC32XX family of processors
636 config ARCH_TEGRA
637 bool "NVIDIA Tegra"
638 select ARCH_HAS_CPUFREQ
639 select CLKDEV_LOOKUP
640 select CLKSRC_MMIO
641 select COMMON_CLK
642 select GENERIC_CLOCKEVENTS
643 select GENERIC_GPIO
644 select HAVE_CLK
645 select HAVE_SMP
646 select MIGHT_HAVE_CACHE_L2X0
647 select USE_OF
648 help
649 This enables support for NVIDIA Tegra based systems (Tegra APX,
650 Tegra 6xx and Tegra 2 series).
652 config ARCH_PXA
653 bool "PXA2xx/PXA3xx-based"
654 depends on MMU
655 select ARCH_HAS_CPUFREQ
656 select ARCH_MTD_XIP
657 select ARCH_REQUIRE_GPIOLIB
658 select ARM_CPU_SUSPEND if PM
659 select AUTO_ZRELADDR
660 select CLKDEV_LOOKUP
661 select CLKSRC_MMIO
662 select GENERIC_CLOCKEVENTS
663 select GPIO_PXA
664 select HAVE_IDE
665 select MULTI_IRQ_HANDLER
666 select NEED_MACH_GPIO_H
667 select PLAT_PXA
668 select SPARSE_IRQ
669 help
670 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
672 config ARCH_MSM
673 bool "Qualcomm MSM"
674 select ARCH_REQUIRE_GPIOLIB
675 select CLKDEV_LOOKUP
676 select GENERIC_CLOCKEVENTS
677 select HAVE_CLK
678 help
679 Support for Qualcomm MSM/QSD based systems. This runs on the
680 apps processor of the MSM/QSD and depends on a shared memory
681 interface to the modem processor which runs the baseband
682 stack and controls some vital subsystems
683 (clock and power control, etc).
685 config ARCH_SHMOBILE
686 bool "Renesas SH-Mobile / R-Mobile"
687 select CLKDEV_LOOKUP
688 select GENERIC_CLOCKEVENTS
689 select HAVE_CLK
690 select HAVE_MACH_CLKDEV
691 select HAVE_SMP
692 select MIGHT_HAVE_CACHE_L2X0
693 select MULTI_IRQ_HANDLER
694 select NEED_MACH_MEMORY_H
695 select NO_IOPORT
696 select PM_GENERIC_DOMAINS if PM
697 select SPARSE_IRQ
698 help
699 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
701 config ARCH_RPC
702 bool "RiscPC"
703 select ARCH_ACORN
704 select ARCH_MAY_HAVE_PC_FDC
705 select ARCH_SPARSEMEM_ENABLE
706 select ARCH_USES_GETTIMEOFFSET
707 select FIQ
708 select HAVE_IDE
709 select HAVE_PATA_PLATFORM
710 select ISA_DMA_API
711 select NEED_MACH_IO_H
712 select NEED_MACH_MEMORY_H
713 select NO_IOPORT
714 help
715 On the Acorn Risc-PC, Linux can support the internal IDE disk and
716 CD-ROM interface, serial and parallel port, and the floppy drive.
718 config ARCH_SA1100
719 bool "SA1100-based"
720 select ARCH_HAS_CPUFREQ
721 select ARCH_MTD_XIP
722 select ARCH_REQUIRE_GPIOLIB
723 select ARCH_SPARSEMEM_ENABLE
724 select CLKDEV_LOOKUP
725 select CLKSRC_MMIO
726 select CPU_FREQ
727 select CPU_SA1100
728 select GENERIC_CLOCKEVENTS
729 select HAVE_IDE
730 select ISA
731 select NEED_MACH_GPIO_H
732 select NEED_MACH_MEMORY_H
733 select SPARSE_IRQ
734 help
735 Support for StrongARM 11x0 based boards.
737 config ARCH_S3C24XX
738 bool "Samsung S3C24XX SoCs"
739 select ARCH_HAS_CPUFREQ
740 select ARCH_USES_GETTIMEOFFSET
741 select CLKDEV_LOOKUP
742 select GENERIC_GPIO
743 select HAVE_CLK
744 select HAVE_S3C2410_I2C if I2C
745 select HAVE_S3C2410_WATCHDOG if WATCHDOG
746 select HAVE_S3C_RTC if RTC_CLASS
747 select NEED_MACH_GPIO_H
748 select NEED_MACH_IO_H
749 help
750 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
751 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
752 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
753 Samsung SMDK2410 development board (and derivatives).
755 config ARCH_S3C64XX
756 bool "Samsung S3C64XX"
757 select ARCH_HAS_CPUFREQ
758 select ARCH_REQUIRE_GPIOLIB
759 select ARCH_USES_GETTIMEOFFSET
760 select ARM_VIC
761 select CLKDEV_LOOKUP
762 select CPU_V6
763 select HAVE_CLK
764 select HAVE_S3C2410_I2C if I2C
765 select HAVE_S3C2410_WATCHDOG if WATCHDOG
766 select HAVE_TCM
767 select NEED_MACH_GPIO_H
768 select NO_IOPORT
769 select PLAT_SAMSUNG
770 select S3C_DEV_NAND
771 select S3C_GPIO_TRACK
772 select SAMSUNG_CLKSRC
773 select SAMSUNG_GPIOLIB_4BIT
774 select SAMSUNG_IRQ_VIC_TIMER
775 select USB_ARCH_HAS_OHCI
776 help
777 Samsung S3C64XX series based systems
779 config ARCH_S5P64X0
780 bool "Samsung S5P6440 S5P6450"
781 select CLKDEV_LOOKUP
782 select CLKSRC_MMIO
783 select CPU_V6
784 select GENERIC_CLOCKEVENTS
785 select GENERIC_GPIO
786 select HAVE_CLK
787 select HAVE_S3C2410_I2C if I2C
788 select HAVE_S3C2410_WATCHDOG if WATCHDOG
789 select HAVE_S3C_RTC if RTC_CLASS
790 select NEED_MACH_GPIO_H
791 help
792 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
793 SMDK6450.
795 config ARCH_S5PC100
796 bool "Samsung S5PC100"
797 select ARCH_USES_GETTIMEOFFSET
798 select CLKDEV_LOOKUP
799 select CPU_V7
800 select GENERIC_GPIO
801 select HAVE_CLK
802 select HAVE_S3C2410_I2C if I2C
803 select HAVE_S3C2410_WATCHDOG if WATCHDOG
804 select HAVE_S3C_RTC if RTC_CLASS
805 select NEED_MACH_GPIO_H
806 help
807 Samsung S5PC100 series based systems
809 config ARCH_S5PV210
810 bool "Samsung S5PV210/S5PC110"
811 select ARCH_HAS_CPUFREQ
812 select ARCH_HAS_HOLES_MEMORYMODEL
813 select ARCH_SPARSEMEM_ENABLE
814 select CLKDEV_LOOKUP
815 select CLKSRC_MMIO
816 select CPU_V7
817 select GENERIC_CLOCKEVENTS
818 select GENERIC_GPIO
819 select HAVE_CLK
820 select HAVE_S3C2410_I2C if I2C
821 select HAVE_S3C2410_WATCHDOG if WATCHDOG
822 select HAVE_S3C_RTC if RTC_CLASS
823 select NEED_MACH_GPIO_H
824 select NEED_MACH_MEMORY_H
825 help
826 Samsung S5PV210/S5PC110 series based systems
828 config ARCH_EXYNOS
829 bool "Samsung EXYNOS"
830 select ARCH_HAS_CPUFREQ
831 select ARCH_HAS_HOLES_MEMORYMODEL
832 select ARCH_SPARSEMEM_ENABLE
833 select CLKDEV_LOOKUP
834 select CPU_V7
835 select GENERIC_CLOCKEVENTS
836 select GENERIC_GPIO
837 select HAVE_CLK
838 select HAVE_S3C2410_I2C if I2C
839 select HAVE_S3C2410_WATCHDOG if WATCHDOG
840 select HAVE_S3C_RTC if RTC_CLASS
841 select NEED_MACH_GPIO_H
842 select NEED_MACH_MEMORY_H
843 help
844 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
846 config ARCH_SHARK
847 bool "Shark"
848 select ARCH_USES_GETTIMEOFFSET
849 select CPU_SA110
850 select ISA
851 select ISA_DMA
852 select NEED_MACH_MEMORY_H
853 select PCI
854 select ZONE_DMA
855 help
856 Support for the StrongARM based Digital DNARD machine, also known
857 as "Shark" (<http://www.shark-linux.de/shark.html>).
859 config ARCH_U300
860 bool "ST-Ericsson U300 Series"
861 depends on MMU
862 select ARCH_REQUIRE_GPIOLIB
863 select ARM_AMBA
864 select ARM_PATCH_PHYS_VIRT
865 select ARM_VIC
866 select CLKDEV_LOOKUP
867 select CLKSRC_MMIO
868 select COMMON_CLK
869 select CPU_ARM926T
870 select GENERIC_CLOCKEVENTS
871 select GENERIC_GPIO
872 select HAVE_TCM
873 select SPARSE_IRQ
874 help
875 Support for ST-Ericsson U300 series mobile platforms.
877 config ARCH_U8500
878 bool "ST-Ericsson U8500 Series"
879 depends on MMU
880 select ARCH_HAS_CPUFREQ
881 select ARCH_REQUIRE_GPIOLIB
882 select ARM_AMBA
883 select CLKDEV_LOOKUP
884 select CPU_V7
885 select GENERIC_CLOCKEVENTS
886 select HAVE_SMP
887 select MIGHT_HAVE_CACHE_L2X0
888 help
889 Support for ST-Ericsson's Ux500 architecture
891 config ARCH_NOMADIK
892 bool "STMicroelectronics Nomadik"
893 select ARCH_REQUIRE_GPIOLIB
894 select ARM_AMBA
895 select ARM_VIC
896 select COMMON_CLK
897 select CPU_ARM926T
898 select GENERIC_CLOCKEVENTS
899 select MIGHT_HAVE_CACHE_L2X0
900 select PINCTRL
901 select PINCTRL_STN8815
902 help
903 Support for the Nomadik platform by ST-Ericsson
905 config PLAT_SPEAR
906 bool "ST SPEAr"
907 select ARCH_REQUIRE_GPIOLIB
908 select ARM_AMBA
909 select CLKDEV_LOOKUP
910 select CLKSRC_MMIO
911 select COMMON_CLK
912 select GENERIC_CLOCKEVENTS
913 select HAVE_CLK
914 help
915 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
917 config ARCH_DAVINCI
918 bool "TI DaVinci"
919 select ARCH_HAS_HOLES_MEMORYMODEL
920 select ARCH_REQUIRE_GPIOLIB
921 select CLKDEV_LOOKUP
922 select GENERIC_ALLOCATOR
923 select GENERIC_CLOCKEVENTS
924 select GENERIC_IRQ_CHIP
925 select HAVE_IDE
926 select NEED_MACH_GPIO_H
927 select ZONE_DMA
928 help
929 Support for TI's DaVinci platform.
931 config ARCH_OMAP
932 bool "TI OMAP"
933 depends on MMU
934 select ARCH_HAS_CPUFREQ
935 select ARCH_HAS_HOLES_MEMORYMODEL
936 select ARCH_REQUIRE_GPIOLIB
937 select CLKSRC_MMIO
938 select GENERIC_CLOCKEVENTS
939 select HAVE_CLK
940 select NEED_MACH_GPIO_H
941 help
942 Support for TI's OMAP platform (OMAP1/2/3/4).
944 config ARCH_VT8500
945 bool "VIA/WonderMedia 85xx"
946 select ARCH_HAS_CPUFREQ
947 select ARCH_REQUIRE_GPIOLIB
948 select CLKDEV_LOOKUP
949 select COMMON_CLK
950 select CPU_ARM926T
951 select GENERIC_CLOCKEVENTS
952 select GENERIC_GPIO
953 select HAVE_CLK
954 select USE_OF
955 help
956 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
958 config ARCH_ZYNQ
959 bool "Xilinx Zynq ARM Cortex A9 Platform"
960 select ARM_AMBA
961 select ARM_GIC
962 select CLKDEV_LOOKUP
963 select CPU_V7
964 select GENERIC_CLOCKEVENTS
965 select ICST
966 select MIGHT_HAVE_CACHE_L2X0
967 select USE_OF
968 help
969 Support for Xilinx Zynq ARM Cortex A9 Platform
970 endchoice
972 menu "Multiple platform selection"
973 depends on ARCH_MULTIPLATFORM
975 comment "CPU Core family selection"
977 config ARCH_MULTI_V4
978 bool "ARMv4 based platforms (FA526, StrongARM)"
979 depends on !ARCH_MULTI_V6_V7
980 select ARCH_MULTI_V4_V5
982 config ARCH_MULTI_V4T
983 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
984 depends on !ARCH_MULTI_V6_V7
985 select ARCH_MULTI_V4_V5
987 config ARCH_MULTI_V5
988 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
989 depends on !ARCH_MULTI_V6_V7
990 select ARCH_MULTI_V4_V5
992 config ARCH_MULTI_V4_V5
993 bool
995 config ARCH_MULTI_V6
996 bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
997 select ARCH_MULTI_V6_V7
998 select CPU_V6
1000 config ARCH_MULTI_V7
1001 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
1002 default y
1003 select ARCH_MULTI_V6_V7
1004 select ARCH_VEXPRESS
1005 select CPU_V7
1007 config ARCH_MULTI_V6_V7
1008 bool
1010 config ARCH_MULTI_CPU_AUTO
1011 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1012 select ARCH_MULTI_V5
1014 endmenu
1016 #
1017 # This is sorted alphabetically by mach-* pathname. However, plat-*
1018 # Kconfigs may be included either alphabetically (according to the
1019 # plat- suffix) or along side the corresponding mach-* source.
1020 #
1021 source "arch/arm/mach-mvebu/Kconfig"
1023 source "arch/arm/mach-at91/Kconfig"
1025 source "arch/arm/mach-clps711x/Kconfig"
1027 source "arch/arm/mach-cns3xxx/Kconfig"
1029 source "arch/arm/mach-davinci/Kconfig"
1031 source "arch/arm/mach-dove/Kconfig"
1033 source "arch/arm/mach-ep93xx/Kconfig"
1035 source "arch/arm/mach-footbridge/Kconfig"
1037 source "arch/arm/mach-gemini/Kconfig"
1039 source "arch/arm/mach-h720x/Kconfig"
1041 source "arch/arm/mach-highbank/Kconfig"
1043 source "arch/arm/mach-integrator/Kconfig"
1045 source "arch/arm/mach-iop32x/Kconfig"
1047 source "arch/arm/mach-iop33x/Kconfig"
1049 source "arch/arm/mach-iop13xx/Kconfig"
1051 source "arch/arm/mach-ixp4xx/Kconfig"
1053 source "arch/arm/mach-kirkwood/Kconfig"
1055 source "arch/arm/mach-ks8695/Kconfig"
1057 source "arch/arm/mach-msm/Kconfig"
1059 source "arch/arm/mach-mv78xx0/Kconfig"
1061 source "arch/arm/plat-mxc/Kconfig"
1063 source "arch/arm/mach-mxs/Kconfig"
1065 source "arch/arm/mach-netx/Kconfig"
1067 source "arch/arm/mach-nomadik/Kconfig"
1068 source "arch/arm/plat-nomadik/Kconfig"
1070 source "arch/arm/plat-omap/Kconfig"
1072 source "arch/arm/mach-omap1/Kconfig"
1074 source "arch/arm/mach-omap2/Kconfig"
1076 source "arch/arm/mach-orion5x/Kconfig"
1078 source "arch/arm/mach-picoxcell/Kconfig"
1080 source "arch/arm/mach-pxa/Kconfig"
1081 source "arch/arm/plat-pxa/Kconfig"
1083 source "arch/arm/mach-mmp/Kconfig"
1085 source "arch/arm/mach-realview/Kconfig"
1087 source "arch/arm/mach-sa1100/Kconfig"
1089 source "arch/arm/plat-samsung/Kconfig"
1090 source "arch/arm/plat-s3c24xx/Kconfig"
1092 source "arch/arm/mach-socfpga/Kconfig"
1094 source "arch/arm/plat-spear/Kconfig"
1096 source "arch/arm/mach-s3c24xx/Kconfig"
1097 if ARCH_S3C24XX
1098 source "arch/arm/mach-s3c2412/Kconfig"
1099 source "arch/arm/mach-s3c2440/Kconfig"
1100 endif
1102 if ARCH_S3C64XX
1103 source "arch/arm/mach-s3c64xx/Kconfig"
1104 endif
1106 source "arch/arm/mach-s5p64x0/Kconfig"
1108 source "arch/arm/mach-s5pc100/Kconfig"
1110 source "arch/arm/mach-s5pv210/Kconfig"
1112 source "arch/arm/mach-exynos/Kconfig"
1114 source "arch/arm/mach-shmobile/Kconfig"
1116 source "arch/arm/mach-prima2/Kconfig"
1118 source "arch/arm/mach-tegra/Kconfig"
1120 source "arch/arm/mach-u300/Kconfig"
1122 source "arch/arm/mach-ux500/Kconfig"
1124 source "arch/arm/mach-versatile/Kconfig"
1126 source "arch/arm/mach-vexpress/Kconfig"
1127 source "arch/arm/plat-versatile/Kconfig"
1129 source "arch/arm/mach-w90x900/Kconfig"
1131 # Definitions to make life easier
1132 config ARCH_ACORN
1133 bool
1135 config PLAT_IOP
1136 bool
1137 select GENERIC_CLOCKEVENTS
1139 config PLAT_ORION
1140 bool
1141 select CLKSRC_MMIO
1142 select COMMON_CLK
1143 select GENERIC_IRQ_CHIP
1144 select IRQ_DOMAIN
1146 config PLAT_ORION_LEGACY
1147 bool
1148 select PLAT_ORION
1150 config PLAT_PXA
1151 bool
1153 config PLAT_VERSATILE
1154 bool
1156 config ARM_TIMER_SP804
1157 bool
1158 select CLKSRC_MMIO
1159 select HAVE_SCHED_CLOCK
1161 source arch/arm/mm/Kconfig
1163 config ARM_NR_BANKS
1164 int
1165 default 16 if ARCH_EP93XX
1166 default 8
1168 config IWMMXT
1169 bool "Enable iWMMXt support"
1170 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1171 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1172 help
1173 Enable support for iWMMXt context switching at run time if
1174 running on a CPU that supports it.
1176 config XSCALE_PMU
1177 bool
1178 depends on CPU_XSCALE
1179 default y
1181 config MULTI_IRQ_HANDLER
1182 bool
1183 help
1184 Allow each machine to specify it's own IRQ handler at run time.
1186 if !MMU
1187 source "arch/arm/Kconfig-nommu"
1188 endif
1190 config ARM_ERRATA_326103
1191 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1192 depends on CPU_V6
1193 help
1194 Executing a SWP instruction to read-only memory does not set bit 11
1195 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1196 treat the access as a read, preventing a COW from occurring and
1197 causing the faulting task to livelock.
1199 config ARM_ERRATA_411920
1200 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1201 depends on CPU_V6 || CPU_V6K
1202 help
1203 Invalidation of the Instruction Cache operation can
1204 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1205 It does not affect the MPCore. This option enables the ARM Ltd.
1206 recommended workaround.
1208 config ARM_ERRATA_430973
1209 bool "ARM errata: Stale prediction on replaced interworking branch"
1210 depends on CPU_V7
1211 help
1212 This option enables the workaround for the 430973 Cortex-A8
1213 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1214 interworking branch is replaced with another code sequence at the
1215 same virtual address, whether due to self-modifying code or virtual
1216 to physical address re-mapping, Cortex-A8 does not recover from the
1217 stale interworking branch prediction. This results in Cortex-A8
1218 executing the new code sequence in the incorrect ARM or Thumb state.
1219 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1220 and also flushes the branch target cache at every context switch.
1221 Note that setting specific bits in the ACTLR register may not be
1222 available in non-secure mode.
1224 config ARM_ERRATA_458693
1225 bool "ARM errata: Processor deadlock when a false hazard is created"
1226 depends on CPU_V7
1227 help
1228 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1229 erratum. For very specific sequences of memory operations, it is
1230 possible for a hazard condition intended for a cache line to instead
1231 be incorrectly associated with a different cache line. This false
1232 hazard might then cause a processor deadlock. The workaround enables
1233 the L1 caching of the NEON accesses and disables the PLD instruction
1234 in the ACTLR register. Note that setting specific bits in the ACTLR
1235 register may not be available in non-secure mode.
1237 config ARM_ERRATA_460075
1238 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1239 depends on CPU_V7
1240 help
1241 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1242 erratum. Any asynchronous access to the L2 cache may encounter a
1243 situation in which recent store transactions to the L2 cache are lost
1244 and overwritten with stale memory contents from external memory. The
1245 workaround disables the write-allocate mode for the L2 cache via the
1246 ACTLR register. Note that setting specific bits in the ACTLR register
1247 may not be available in non-secure mode.
1249 config ARM_ERRATA_742230
1250 bool "ARM errata: DMB operation may be faulty"
1251 depends on CPU_V7 && SMP
1252 help
1253 This option enables the workaround for the 742230 Cortex-A9
1254 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1255 between two write operations may not ensure the correct visibility
1256 ordering of the two writes. This workaround sets a specific bit in
1257 the diagnostic register of the Cortex-A9 which causes the DMB
1258 instruction to behave as a DSB, ensuring the correct behaviour of
1259 the two writes.
1261 config ARM_ERRATA_742231
1262 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1263 depends on CPU_V7 && SMP
1264 help
1265 This option enables the workaround for the 742231 Cortex-A9
1266 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1267 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1268 accessing some data located in the same cache line, may get corrupted
1269 data due to bad handling of the address hazard when the line gets
1270 replaced from one of the CPUs at the same time as another CPU is
1271 accessing it. This workaround sets specific bits in the diagnostic
1272 register of the Cortex-A9 which reduces the linefill issuing
1273 capabilities of the processor.
1275 config PL310_ERRATA_588369
1276 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1277 depends on CACHE_L2X0
1278 help
1279 The PL310 L2 cache controller implements three types of Clean &
1280 Invalidate maintenance operations: by Physical Address
1281 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1282 They are architecturally defined to behave as the execution of a
1283 clean operation followed immediately by an invalidate operation,
1284 both performing to the same memory location. This functionality
1285 is not correctly implemented in PL310 as clean lines are not
1286 invalidated as a result of these operations.
1288 config ARM_ERRATA_720789
1289 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1290 depends on CPU_V7
1291 help
1292 This option enables the workaround for the 720789 Cortex-A9 (prior to
1293 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1294 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1295 As a consequence of this erratum, some TLB entries which should be
1296 invalidated are not, resulting in an incoherency in the system page
1297 tables. The workaround changes the TLB flushing routines to invalidate
1298 entries regardless of the ASID.
1300 config PL310_ERRATA_727915
1301 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1302 depends on CACHE_L2X0
1303 help
1304 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1305 operation (offset 0x7FC). This operation runs in background so that
1306 PL310 can handle normal accesses while it is in progress. Under very
1307 rare circumstances, due to this erratum, write data can be lost when
1308 PL310 treats a cacheable write transaction during a Clean &
1309 Invalidate by Way operation.
1311 config ARM_ERRATA_743622
1312 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1313 depends on CPU_V7
1314 help
1315 This option enables the workaround for the 743622 Cortex-A9
1316 (r2p*) erratum. Under very rare conditions, a faulty
1317 optimisation in the Cortex-A9 Store Buffer may lead to data
1318 corruption. This workaround sets a specific bit in the diagnostic
1319 register of the Cortex-A9 which disables the Store Buffer
1320 optimisation, preventing the defect from occurring. This has no
1321 visible impact on the overall performance or power consumption of the
1322 processor.
1324 config ARM_ERRATA_751472
1325 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1326 depends on CPU_V7
1327 help
1328 This option enables the workaround for the 751472 Cortex-A9 (prior
1329 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1330 completion of a following broadcasted operation if the second
1331 operation is received by a CPU before the ICIALLUIS has completed,
1332 potentially leading to corrupted entries in the cache or TLB.
1334 config PL310_ERRATA_753970
1335 bool "PL310 errata: cache sync operation may be faulty"
1336 depends on CACHE_PL310
1337 help
1338 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1340 Under some condition the effect of cache sync operation on
1341 the store buffer still remains when the operation completes.
1342 This means that the store buffer is always asked to drain and
1343 this prevents it from merging any further writes. The workaround
1344 is to replace the normal offset of cache sync operation (0x730)
1345 by another offset targeting an unmapped PL310 register 0x740.
1346 This has the same effect as the cache sync operation: store buffer
1347 drain and waiting for all buffers empty.
1349 config ARM_ERRATA_754322
1350 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1351 depends on CPU_V7
1352 help
1353 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1354 r3p*) erratum. A speculative memory access may cause a page table walk
1355 which starts prior to an ASID switch but completes afterwards. This
1356 can populate the micro-TLB with a stale entry which may be hit with
1357 the new ASID. This workaround places two dsb instructions in the mm
1358 switching code so that no page table walks can cross the ASID switch.
1360 config ARM_ERRATA_754327
1361 bool "ARM errata: no automatic Store Buffer drain"
1362 depends on CPU_V7 && SMP
1363 help
1364 This option enables the workaround for the 754327 Cortex-A9 (prior to
1365 r2p0) erratum. The Store Buffer does not have any automatic draining
1366 mechanism and therefore a livelock may occur if an external agent
1367 continuously polls a memory location waiting to observe an update.
1368 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1369 written polling loops from denying visibility of updates to memory.
1371 config ARM_ERRATA_364296
1372 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1373 depends on CPU_V6 && !SMP
1374 help
1375 This options enables the workaround for the 364296 ARM1136
1376 r0p2 erratum (possible cache data corruption with
1377 hit-under-miss enabled). It sets the undocumented bit 31 in
1378 the auxiliary control register and the FI bit in the control
1379 register, thus disabling hit-under-miss without putting the
1380 processor into full low interrupt latency mode. ARM11MPCore
1381 is not affected.
1383 config ARM_ERRATA_764369
1384 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1385 depends on CPU_V7 && SMP
1386 help
1387 This option enables the workaround for erratum 764369
1388 affecting Cortex-A9 MPCore with two or more processors (all
1389 current revisions). Under certain timing circumstances, a data
1390 cache line maintenance operation by MVA targeting an Inner
1391 Shareable memory region may fail to proceed up to either the
1392 Point of Coherency or to the Point of Unification of the
1393 system. This workaround adds a DSB instruction before the
1394 relevant cache maintenance functions and sets a specific bit
1395 in the diagnostic control register of the SCU.
1397 config PL310_ERRATA_769419
1398 bool "PL310 errata: no automatic Store Buffer drain"
1399 depends on CACHE_L2X0
1400 help
1401 On revisions of the PL310 prior to r3p2, the Store Buffer does
1402 not automatically drain. This can cause normal, non-cacheable
1403 writes to be retained when the memory system is idle, leading
1404 to suboptimal I/O performance for drivers using coherent DMA.
1405 This option adds a write barrier to the cpu_idle loop so that,
1406 on systems with an outer cache, the store buffer is drained
1407 explicitly.
1409 config ARM_ERRATA_775420
1410 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1411 depends on CPU_V7
1412 help
1413 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1414 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1415 operation aborts with MMU exception, it might cause the processor
1416 to deadlock. This workaround puts DSB before executing ISB if
1417 an abort may occur on cache maintenance.
1419 endmenu
1421 source "arch/arm/common/Kconfig"
1423 menu "Bus support"
1425 config ARM_AMBA
1426 bool
1428 config ISA
1429 bool
1430 help
1431 Find out whether you have ISA slots on your motherboard. ISA is the
1432 name of a bus system, i.e. the way the CPU talks to the other stuff
1433 inside your box. Other bus systems are PCI, EISA, MicroChannel
1434 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1435 newer boards don't support it. If you have ISA, say Y, otherwise N.
1437 # Select ISA DMA controller support
1438 config ISA_DMA
1439 bool
1440 select ISA_DMA_API
1442 # Select ISA DMA interface
1443 config ISA_DMA_API
1444 bool
1446 config PCI
1447 bool "PCI support" if MIGHT_HAVE_PCI
1448 help
1449 Find out whether you have a PCI motherboard. PCI is the name of a
1450 bus system, i.e. the way the CPU talks to the other stuff inside
1451 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1452 VESA. If you have PCI, say Y, otherwise N.
1454 config PCI_DOMAINS
1455 bool
1456 depends on PCI
1458 config PCI_NANOENGINE
1459 bool "BSE nanoEngine PCI support"
1460 depends on SA1100_NANOENGINE
1461 help
1462 Enable PCI on the BSE nanoEngine board.
1464 config PCI_SYSCALL
1465 def_bool PCI
1467 # Select the host bridge type
1468 config PCI_HOST_VIA82C505
1469 bool
1470 depends on PCI && ARCH_SHARK
1471 default y
1473 config PCI_HOST_ITE8152
1474 bool
1475 depends on PCI && MACH_ARMCORE
1476 default y
1477 select DMABOUNCE
1479 source "drivers/pci/Kconfig"
1481 source "drivers/pcmcia/Kconfig"
1483 endmenu
1485 menu "Kernel Features"
1487 config HAVE_SMP
1488 bool
1489 help
1490 This option should be selected by machines which have an SMP-
1491 capable CPU.
1493 The only effect of this option is to make the SMP-related
1494 options available to the user for configuration.
1496 config SMP
1497 bool "Symmetric Multi-Processing"
1498 depends on CPU_V6K || CPU_V7
1499 depends on GENERIC_CLOCKEVENTS
1500 depends on HAVE_SMP
1501 depends on MMU
1502 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1503 select USE_GENERIC_SMP_HELPERS
1504 help
1505 This enables support for systems with more than one CPU. If you have
1506 a system with only one CPU, like most personal computers, say N. If
1507 you have a system with more than one CPU, say Y.
1509 If you say N here, the kernel will run on single and multiprocessor
1510 machines, but will use only one CPU of a multiprocessor machine. If
1511 you say Y here, the kernel will run on many, but not all, single
1512 processor machines. On a single processor machine, the kernel will
1513 run faster if you say N here.
1515 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1516 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1517 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1519 If you don't know what to do here, say N.
1521 config SMP_ON_UP
1522 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1523 depends on EXPERIMENTAL
1524 depends on SMP && !XIP_KERNEL
1525 default y
1526 help
1527 SMP kernels contain instructions which fail on non-SMP processors.
1528 Enabling this option allows the kernel to modify itself to make
1529 these instructions safe. Disabling it allows about 1K of space
1530 savings.
1532 If you don't know what to do here, say Y.
1534 config ARM_CPU_TOPOLOGY
1535 bool "Support cpu topology definition"
1536 depends on SMP && CPU_V7
1537 default y
1538 help
1539 Support ARM cpu topology definition. The MPIDR register defines
1540 affinity between processors which is then used to describe the cpu
1541 topology of an ARM System.
1543 config SCHED_MC
1544 bool "Multi-core scheduler support"
1545 depends on ARM_CPU_TOPOLOGY
1546 help
1547 Multi-core scheduler support improves the CPU scheduler's decision
1548 making when dealing with multi-core CPU chips at a cost of slightly
1549 increased overhead in some places. If unsure say N here.
1551 config SCHED_SMT
1552 bool "SMT scheduler support"
1553 depends on ARM_CPU_TOPOLOGY
1554 help
1555 Improves the CPU scheduler's decision making when dealing with
1556 MultiThreading at a cost of slightly increased overhead in some
1557 places. If unsure say N here.
1559 config HAVE_ARM_SCU
1560 bool
1561 help
1562 This option enables support for the ARM system coherency unit
1564 config ARM_ARCH_TIMER
1565 bool "Architected timer support"
1566 depends on CPU_V7
1567 help
1568 This option enables support for the ARM architected timer
1570 config HAVE_ARM_TWD
1571 bool
1572 depends on SMP
1573 help
1574 This options enables support for the ARM timer and watchdog unit
1576 choice
1577 prompt "Memory split"
1578 default VMSPLIT_3G
1579 help
1580 Select the desired split between kernel and user memory.
1582 If you are not absolutely sure what you are doing, leave this
1583 option alone!
1585 config VMSPLIT_3G
1586 bool "3G/1G user/kernel split"
1587 config VMSPLIT_2G
1588 bool "2G/2G user/kernel split"
1589 config VMSPLIT_1G
1590 bool "1G/3G user/kernel split"
1591 endchoice
1593 config PAGE_OFFSET
1594 hex
1595 default 0x40000000 if VMSPLIT_1G
1596 default 0x80000000 if VMSPLIT_2G
1597 default 0xC0000000
1599 config NR_CPUS
1600 int "Maximum number of CPUs (2-32)"
1601 range 2 32
1602 depends on SMP
1603 default "4"
1605 config HOTPLUG_CPU
1606 bool "Support for hot-pluggable CPUs"
1607 depends on SMP && HOTPLUG
1608 help
1609 Say Y here to experiment with turning CPUs off and on. CPUs
1610 can be controlled through /sys/devices/system/cpu.
1612 config LOCAL_TIMERS
1613 bool "Use local timer interrupts"
1614 depends on SMP
1615 default y
1616 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1617 help
1618 Enable support for local timers on SMP platforms, rather then the
1619 legacy IPI broadcast method. Local timers allows the system
1620 accounting to be spread across the timer interval, preventing a
1621 "thundering herd" at every timer tick.
1623 config ARCH_NR_GPIO
1624 int
1625 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1626 default 355 if ARCH_U8500
1627 default 264 if MACH_H4700
1628 default 512 if SOC_OMAP5
1629 default 288 if ARCH_VT8500
1630 default 0
1631 help
1632 Maximum number of GPIOs in the system.
1634 If unsure, leave the default value.
1636 source kernel/Kconfig.preempt
1638 config HZ
1639 int
1640 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1641 ARCH_S5PV210 || ARCH_EXYNOS4
1642 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1643 default AT91_TIMER_HZ if ARCH_AT91
1644 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1645 default 100
1647 config THUMB2_KERNEL
1648 bool "Compile the kernel in Thumb-2 mode"
1649 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1650 select AEABI
1651 select ARM_ASM_UNIFIED
1652 select ARM_UNWIND
1653 help
1654 By enabling this option, the kernel will be compiled in
1655 Thumb-2 mode. A compiler/assembler that understand the unified
1656 ARM-Thumb syntax is needed.
1658 If unsure, say N.
1660 config THUMB2_AVOID_R_ARM_THM_JUMP11
1661 bool "Work around buggy Thumb-2 short branch relocations in gas"
1662 depends on THUMB2_KERNEL && MODULES
1663 default y
1664 help
1665 Various binutils versions can resolve Thumb-2 branches to
1666 locally-defined, preemptible global symbols as short-range "b.n"
1667 branch instructions.
1669 This is a problem, because there's no guarantee the final
1670 destination of the symbol, or any candidate locations for a
1671 trampoline, are within range of the branch. For this reason, the
1672 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1673 relocation in modules at all, and it makes little sense to add
1674 support.
1676 The symptom is that the kernel fails with an "unsupported
1677 relocation" error when loading some modules.
1679 Until fixed tools are available, passing
1680 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1681 code which hits this problem, at the cost of a bit of extra runtime
1682 stack usage in some cases.
1684 The problem is described in more detail at:
1685 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1687 Only Thumb-2 kernels are affected.
1689 Unless you are sure your tools don't have this problem, say Y.
1691 config ARM_ASM_UNIFIED
1692 bool
1694 config AEABI
1695 bool "Use the ARM EABI to compile the kernel"
1696 help
1697 This option allows for the kernel to be compiled using the latest
1698 ARM ABI (aka EABI). This is only useful if you are using a user
1699 space environment that is also compiled with EABI.
1701 Since there are major incompatibilities between the legacy ABI and
1702 EABI, especially with regard to structure member alignment, this
1703 option also changes the kernel syscall calling convention to
1704 disambiguate both ABIs and allow for backward compatibility support
1705 (selected with CONFIG_OABI_COMPAT).
1707 To use this you need GCC version 4.0.0 or later.
1709 config OABI_COMPAT
1710 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1711 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1712 default y
1713 help
1714 This option preserves the old syscall interface along with the
1715 new (ARM EABI) one. It also provides a compatibility layer to
1716 intercept syscalls that have structure arguments which layout
1717 in memory differs between the legacy ABI and the new ARM EABI
1718 (only for non "thumb" binaries). This option adds a tiny
1719 overhead to all syscalls and produces a slightly larger kernel.
1720 If you know you'll be using only pure EABI user space then you
1721 can say N here. If this option is not selected and you attempt
1722 to execute a legacy ABI binary then the result will be
1723 UNPREDICTABLE (in fact it can be predicted that it won't work
1724 at all). If in doubt say Y.
1726 config ARCH_HAS_HOLES_MEMORYMODEL
1727 bool
1729 config ARCH_SPARSEMEM_ENABLE
1730 bool
1732 config ARCH_SPARSEMEM_DEFAULT
1733 def_bool ARCH_SPARSEMEM_ENABLE
1735 config ARCH_SELECT_MEMORY_MODEL
1736 def_bool ARCH_SPARSEMEM_ENABLE
1738 config HAVE_ARCH_PFN_VALID
1739 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1741 config HIGHMEM
1742 bool "High Memory Support"
1743 depends on MMU
1744 help
1745 The address space of ARM processors is only 4 Gigabytes large
1746 and it has to accommodate user address space, kernel address
1747 space as well as some memory mapped IO. That means that, if you
1748 have a large amount of physical memory and/or IO, not all of the
1749 memory can be "permanently mapped" by the kernel. The physical
1750 memory that is not permanently mapped is called "high memory".
1752 Depending on the selected kernel/user memory split, minimum
1753 vmalloc space and actual amount of RAM, you may not need this
1754 option which should result in a slightly faster kernel.
1756 If unsure, say n.
1758 config HIGHPTE
1759 bool "Allocate 2nd-level pagetables from highmem"
1760 depends on HIGHMEM
1762 config HW_PERF_EVENTS
1763 bool "Enable hardware performance counter support for perf events"
1764 depends on PERF_EVENTS
1765 default y
1766 help
1767 Enable hardware performance counter support for perf events. If
1768 disabled, perf events will use software events only.
1770 source "mm/Kconfig"
1772 config FORCE_MAX_ZONEORDER
1773 int "Maximum zone order" if ARCH_SHMOBILE
1774 range 11 64 if ARCH_SHMOBILE
1775 default "12" if SOC_AM33XX
1776 default "9" if SA1111
1777 default "11"
1778 help
1779 The kernel memory allocator divides physically contiguous memory
1780 blocks into "zones", where each zone is a power of two number of
1781 pages. This option selects the largest power of two that the kernel
1782 keeps in the memory allocator. If you need to allocate very large
1783 blocks of physically contiguous memory, then you may need to
1784 increase this value.
1786 This config option is actually maximum order plus one. For example,
1787 a value of 11 means that the largest free memory block is 2^10 pages.
1789 config ALIGNMENT_TRAP
1790 bool
1791 depends on CPU_CP15_MMU
1792 default y if !ARCH_EBSA110
1793 select HAVE_PROC_CPU if PROC_FS
1794 help
1795 ARM processors cannot fetch/store information which is not
1796 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1797 address divisible by 4. On 32-bit ARM processors, these non-aligned
1798 fetch/store instructions will be emulated in software if you say
1799 here, which has a severe performance impact. This is necessary for
1800 correct operation of some network protocols. With an IP-only
1801 configuration it is safe to say N, otherwise say Y.
1803 config UACCESS_WITH_MEMCPY
1804 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1805 depends on MMU
1806 default y if CPU_FEROCEON
1807 help
1808 Implement faster copy_to_user and clear_user methods for CPU
1809 cores where a 8-word STM instruction give significantly higher
1810 memory write throughput than a sequence of individual 32bit stores.
1812 A possible side effect is a slight increase in scheduling latency
1813 between threads sharing the same address space if they invoke
1814 such copy operations with large buffers.
1816 However, if the CPU data cache is using a write-allocate mode,
1817 this option is unlikely to provide any performance gain.
1819 config SECCOMP
1820 bool
1821 prompt "Enable seccomp to safely compute untrusted bytecode"
1822 ---help---
1823 This kernel feature is useful for number crunching applications
1824 that may need to compute untrusted bytecode during their
1825 execution. By using pipes or other transports made available to
1826 the process as file descriptors supporting the read/write
1827 syscalls, it's possible to isolate those applications in
1828 their own address space using seccomp. Once seccomp is
1829 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1830 and the task is only allowed to execute a few safe syscalls
1831 defined by each seccomp mode.
1833 config CC_STACKPROTECTOR
1834 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1835 depends on EXPERIMENTAL
1836 help
1837 This option turns on the -fstack-protector GCC feature. This
1838 feature puts, at the beginning of functions, a canary value on
1839 the stack just before the return address, and validates
1840 the value just before actually returning. Stack based buffer
1841 overflows (that need to overwrite this return address) now also
1842 overwrite the canary, which gets detected and the attack is then
1843 neutralized via a kernel panic.
1844 This feature requires gcc version 4.2 or above.
1846 config XEN_DOM0
1847 def_bool y
1848 depends on XEN
1850 config XEN
1851 bool "Xen guest support on ARM (EXPERIMENTAL)"
1852 depends on EXPERIMENTAL && ARM && OF
1853 help
1854 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1856 endmenu
1858 menu "Boot options"
1860 config USE_OF
1861 bool "Flattened Device Tree support"
1862 select IRQ_DOMAIN
1863 select OF
1864 select OF_EARLY_FLATTREE
1865 help
1866 Include support for flattened device tree machine descriptions.
1868 config ATAGS
1869 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1870 default y
1871 help
1872 This is the traditional way of passing data to the kernel at boot
1873 time. If you are solely relying on the flattened device tree (or
1874 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1875 to remove ATAGS support from your kernel binary. If unsure,
1876 leave this to y.
1878 config DEPRECATED_PARAM_STRUCT
1879 bool "Provide old way to pass kernel parameters"
1880 depends on ATAGS
1881 help
1882 This was deprecated in 2001 and announced to live on for 5 years.
1883 Some old boot loaders still use this way.
1885 # Compressed boot loader in ROM. Yes, we really want to ask about
1886 # TEXT and BSS so we preserve their values in the config files.
1887 config ZBOOT_ROM_TEXT
1888 hex "Compressed ROM boot loader base address"
1889 default "0"
1890 help
1891 The physical address at which the ROM-able zImage is to be
1892 placed in the target. Platforms which normally make use of
1893 ROM-able zImage formats normally set this to a suitable
1894 value in their defconfig file.
1896 If ZBOOT_ROM is not enabled, this has no effect.
1898 config ZBOOT_ROM_BSS
1899 hex "Compressed ROM boot loader BSS address"
1900 default "0"
1901 help
1902 The base address of an area of read/write memory in the target
1903 for the ROM-able zImage which must be available while the
1904 decompressor is running. It must be large enough to hold the
1905 entire decompressed kernel plus an additional 128 KiB.
1906 Platforms which normally make use of ROM-able zImage formats
1907 normally set this to a suitable value in their defconfig file.
1909 If ZBOOT_ROM is not enabled, this has no effect.
1911 config ZBOOT_ROM
1912 bool "Compressed boot loader in ROM/flash"
1913 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1914 help
1915 Say Y here if you intend to execute your compressed kernel image
1916 (zImage) directly from ROM or flash. If unsure, say N.
1918 choice
1919 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1920 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1921 default ZBOOT_ROM_NONE
1922 help
1923 Include experimental SD/MMC loading code in the ROM-able zImage.
1924 With this enabled it is possible to write the ROM-able zImage
1925 kernel image to an MMC or SD card and boot the kernel straight
1926 from the reset vector. At reset the processor Mask ROM will load
1927 the first part of the ROM-able zImage which in turn loads the
1928 rest the kernel image to RAM.
1930 config ZBOOT_ROM_NONE
1931 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1932 help
1933 Do not load image from SD or MMC
1935 config ZBOOT_ROM_MMCIF
1936 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1937 help
1938 Load image from MMCIF hardware block.
1940 config ZBOOT_ROM_SH_MOBILE_SDHI
1941 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1942 help
1943 Load image from SDHI hardware block
1945 endchoice
1947 config ARM_APPENDED_DTB
1948 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1949 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1950 help
1951 With this option, the boot code will look for a device tree binary
1952 (DTB) appended to zImage
1953 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1955 This is meant as a backward compatibility convenience for those
1956 systems with a bootloader that can't be upgraded to accommodate
1957 the documented boot protocol using a device tree.
1959 Beware that there is very little in terms of protection against
1960 this option being confused by leftover garbage in memory that might
1961 look like a DTB header after a reboot if no actual DTB is appended
1962 to zImage. Do not leave this option active in a production kernel
1963 if you don't intend to always append a DTB. Proper passing of the
1964 location into r2 of a bootloader provided DTB is always preferable
1965 to this option.
1967 config ARM_ATAG_DTB_COMPAT
1968 bool "Supplement the appended DTB with traditional ATAG information"
1969 depends on ARM_APPENDED_DTB
1970 help
1971 Some old bootloaders can't be updated to a DTB capable one, yet
1972 they provide ATAGs with memory configuration, the ramdisk address,
1973 the kernel cmdline string, etc. Such information is dynamically
1974 provided by the bootloader and can't always be stored in a static
1975 DTB. To allow a device tree enabled kernel to be used with such
1976 bootloaders, this option allows zImage to extract the information
1977 from the ATAG list and store it at run time into the appended DTB.
1979 choice
1980 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1981 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1983 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1984 bool "Use bootloader kernel arguments if available"
1985 help
1986 Uses the command-line options passed by the boot loader instead of
1987 the device tree bootargs property. If the boot loader doesn't provide
1988 any, the device tree bootargs property will be used.
1990 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1991 bool "Extend with bootloader kernel arguments"
1992 help
1993 The command-line arguments provided by the boot loader will be
1994 appended to the the device tree bootargs property.
1996 endchoice
1998 config CMDLINE
1999 string "Default kernel command string"
2000 default ""
2001 help
2002 On some architectures (EBSA110 and CATS), there is currently no way
2003 for the boot loader to pass arguments to the kernel. For these
2004 architectures, you should supply some command-line options at build
2005 time by entering them here. As a minimum, you should specify the
2006 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2008 choice
2009 prompt "Kernel command line type" if CMDLINE != ""
2010 default CMDLINE_FROM_BOOTLOADER
2011 depends on ATAGS
2013 config CMDLINE_FROM_BOOTLOADER
2014 bool "Use bootloader kernel arguments if available"
2015 help
2016 Uses the command-line options passed by the boot loader. If
2017 the boot loader doesn't provide any, the default kernel command
2018 string provided in CMDLINE will be used.
2020 config CMDLINE_EXTEND
2021 bool "Extend bootloader kernel arguments"
2022 help
2023 The command-line arguments provided by the boot loader will be
2024 appended to the default kernel command string.
2026 config CMDLINE_FORCE
2027 bool "Always use the default kernel command string"
2028 help
2029 Always use the default kernel command string, even if the boot
2030 loader passes other arguments to the kernel.
2031 This is useful if you cannot or don't want to change the
2032 command-line options your boot loader passes to the kernel.
2033 endchoice
2035 config XIP_KERNEL
2036 bool "Kernel Execute-In-Place from ROM"
2037 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2038 help
2039 Execute-In-Place allows the kernel to run from non-volatile storage
2040 directly addressable by the CPU, such as NOR flash. This saves RAM
2041 space since the text section of the kernel is not loaded from flash
2042 to RAM. Read-write sections, such as the data section and stack,
2043 are still copied to RAM. The XIP kernel is not compressed since
2044 it has to run directly from flash, so it will take more space to
2045 store it. The flash address used to link the kernel object files,
2046 and for storing it, is configuration dependent. Therefore, if you
2047 say Y here, you must know the proper physical address where to
2048 store the kernel image depending on your own flash memory usage.
2050 Also note that the make target becomes "make xipImage" rather than
2051 "make zImage" or "make Image". The final kernel binary to put in
2052 ROM memory will be arch/arm/boot/xipImage.
2054 If unsure, say N.
2056 config XIP_PHYS_ADDR
2057 hex "XIP Kernel Physical Location"
2058 depends on XIP_KERNEL
2059 default "0x00080000"
2060 help
2061 This is the physical address in your flash memory the kernel will
2062 be linked for and stored to. This address is dependent on your
2063 own flash usage.
2065 config KEXEC
2066 bool "Kexec system call (EXPERIMENTAL)"
2067 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2068 help
2069 kexec is a system call that implements the ability to shutdown your
2070 current kernel, and to start another kernel. It is like a reboot
2071 but it is independent of the system firmware. And like a reboot
2072 you can start any kernel with it, not just Linux.
2074 It is an ongoing process to be certain the hardware in a machine
2075 is properly shutdown, so do not be surprised if this code does not
2076 initially work for you. It may help to enable device hotplugging
2077 support.
2079 config ATAGS_PROC
2080 bool "Export atags in procfs"
2081 depends on ATAGS && KEXEC
2082 default y
2083 help
2084 Should the atags used to boot the kernel be exported in an "atags"
2085 file in procfs. Useful with kexec.
2087 config CRASH_DUMP
2088 bool "Build kdump crash kernel (EXPERIMENTAL)"
2089 depends on EXPERIMENTAL
2090 help
2091 Generate crash dump after being started by kexec. This should
2092 be normally only set in special crash dump kernels which are
2093 loaded in the main kernel with kexec-tools into a specially
2094 reserved region and then later executed after a crash by
2095 kdump/kexec. The crash dump kernel must be compiled to a
2096 memory address not used by the main kernel
2098 For more details see Documentation/kdump/kdump.txt
2100 config AUTO_ZRELADDR
2101 bool "Auto calculation of the decompressed kernel image address"
2102 depends on !ZBOOT_ROM && !ARCH_U300
2103 help
2104 ZRELADDR is the physical address where the decompressed kernel
2105 image will be placed. If AUTO_ZRELADDR is selected, the address
2106 will be determined at run-time by masking the current IP with
2107 0xf8000000. This assumes the zImage being placed in the first 128MB
2108 from start of memory.
2110 endmenu
2112 menu "CPU Power Management"
2114 if ARCH_HAS_CPUFREQ
2116 source "drivers/cpufreq/Kconfig"
2118 config CPU_FREQ_IMX
2119 tristate "CPUfreq driver for i.MX CPUs"
2120 depends on ARCH_MXC && CPU_FREQ
2121 select CPU_FREQ_TABLE
2122 help
2123 This enables the CPUfreq driver for i.MX CPUs.
2125 config CPU_FREQ_SA1100
2126 bool
2128 config CPU_FREQ_SA1110
2129 bool
2131 config CPU_FREQ_INTEGRATOR
2132 tristate "CPUfreq driver for ARM Integrator CPUs"
2133 depends on ARCH_INTEGRATOR && CPU_FREQ
2134 default y
2135 help
2136 This enables the CPUfreq driver for ARM Integrator CPUs.
2138 For details, take a look at <file:Documentation/cpu-freq>.
2140 If in doubt, say Y.
2142 config CPU_FREQ_PXA
2143 bool
2144 depends on CPU_FREQ && ARCH_PXA && PXA25x
2145 default y
2146 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2147 select CPU_FREQ_TABLE
2149 config CPU_FREQ_S3C
2150 bool
2151 help
2152 Internal configuration node for common cpufreq on Samsung SoC
2154 config CPU_FREQ_S3C24XX
2155 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2156 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2157 select CPU_FREQ_S3C
2158 help
2159 This enables the CPUfreq driver for the Samsung S3C24XX family
2160 of CPUs.
2162 For details, take a look at <file:Documentation/cpu-freq>.
2164 If in doubt, say N.
2166 config CPU_FREQ_S3C24XX_PLL
2167 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2168 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2169 help
2170 Compile in support for changing the PLL frequency from the
2171 S3C24XX series CPUfreq driver. The PLL takes time to settle
2172 after a frequency change, so by default it is not enabled.
2174 This also means that the PLL tables for the selected CPU(s) will
2175 be built which may increase the size of the kernel image.
2177 config CPU_FREQ_S3C24XX_DEBUG
2178 bool "Debug CPUfreq Samsung driver core"
2179 depends on CPU_FREQ_S3C24XX
2180 help
2181 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2183 config CPU_FREQ_S3C24XX_IODEBUG
2184 bool "Debug CPUfreq Samsung driver IO timing"
2185 depends on CPU_FREQ_S3C24XX
2186 help
2187 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2189 config CPU_FREQ_S3C24XX_DEBUGFS
2190 bool "Export debugfs for CPUFreq"
2191 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2192 help
2193 Export status information via debugfs.
2195 endif
2197 source "drivers/cpuidle/Kconfig"
2199 endmenu
2201 menu "Floating point emulation"
2203 comment "At least one emulation must be selected"
2205 config FPE_NWFPE
2206 bool "NWFPE math emulation"
2207 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2208 ---help---
2209 Say Y to include the NWFPE floating point emulator in the kernel.
2210 This is necessary to run most binaries. Linux does not currently
2211 support floating point hardware so you need to say Y here even if
2212 your machine has an FPA or floating point co-processor podule.
2214 You may say N here if you are going to load the Acorn FPEmulator
2215 early in the bootup.
2217 config FPE_NWFPE_XP
2218 bool "Support extended precision"
2219 depends on FPE_NWFPE
2220 help
2221 Say Y to include 80-bit support in the kernel floating-point
2222 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2223 Note that gcc does not generate 80-bit operations by default,
2224 so in most cases this option only enlarges the size of the
2225 floating point emulator without any good reason.
2227 You almost surely want to say N here.
2229 config FPE_FASTFPE
2230 bool "FastFPE math emulation (EXPERIMENTAL)"
2231 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2232 ---help---
2233 Say Y here to include the FAST floating point emulator in the kernel.
2234 This is an experimental much faster emulator which now also has full
2235 precision for the mantissa. It does not support any exceptions.
2236 It is very simple, and approximately 3-6 times faster than NWFPE.
2238 It should be sufficient for most programs. It may be not suitable
2239 for scientific calculations, but you have to check this for yourself.
2240 If you do not feel you need a faster FP emulation you should better
2241 choose NWFPE.
2243 config VFP
2244 bool "VFP-format floating point maths"
2245 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2246 help
2247 Say Y to include VFP support code in the kernel. This is needed
2248 if your hardware includes a VFP unit.
2250 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2251 release notes and additional status information.
2253 Say N if your target does not have VFP hardware.
2255 config VFPv3
2256 bool
2257 depends on VFP
2258 default y if CPU_V7
2260 config NEON
2261 bool "Advanced SIMD (NEON) Extension support"
2262 depends on VFPv3 && CPU_V7
2263 help
2264 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2265 Extension.
2267 endmenu
2269 menu "Userspace binary formats"
2271 source "fs/Kconfig.binfmt"
2273 config ARTHUR
2274 tristate "RISC OS personality"
2275 depends on !AEABI
2276 help
2277 Say Y here to include the kernel code necessary if you want to run
2278 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2279 experimental; if this sounds frightening, say N and sleep in peace.
2280 You can also say M here to compile this support as a module (which
2281 will be called arthur).
2283 endmenu
2285 menu "Power management options"
2287 source "kernel/power/Kconfig"
2289 config ARCH_SUSPEND_POSSIBLE
2290 depends on !ARCH_S5PC100
2291 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2292 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2293 def_bool y
2295 config ARM_CPU_SUSPEND
2296 def_bool PM_SLEEP
2298 endmenu
2300 source "net/Kconfig"
2302 source "drivers/Kconfig"
2304 source "fs/Kconfig"
2306 source "arch/arm/Kconfig.debug"
2308 source "security/Kconfig"
2310 source "crypto/Kconfig"
2312 source "lib/Kconfig"